TWI721225B - 封裝結構及其製造方法 - Google Patents

封裝結構及其製造方法 Download PDF

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TWI721225B
TWI721225B TW106136664A TW106136664A TWI721225B TW I721225 B TWI721225 B TW I721225B TW 106136664 A TW106136664 A TW 106136664A TW 106136664 A TW106136664 A TW 106136664A TW I721225 B TWI721225 B TW I721225B
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Taiwan
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layer
die
rewiring
integrated fan
hole
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TW106136664A
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TW201916305A (zh
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戴志軒
陳志華
蔡豪益
黃育智
劉家宏
郭婷婷
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台灣積體電路製造股份有限公司
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
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Abstract

本揭露提供一種封裝結構及其製造方法。所述封裝結構包括晶粒、重佈線結構、集成扇出型穿孔以及第一連接件。重佈線結構與晶粒連接且包括多條重佈線。集成扇出型穿孔位於晶粒側邊且穿過重佈線結構。第一連接件與集成扇出型穿孔電性接觸，且與晶粒電性連接。集成扇出型穿孔與重佈線結構的重佈線電性接觸。

Description

封裝結構及其製造方法
本揭露實施例是關於一種封裝結構。
隨著各種電子元件(例如是電晶體、二極體、電阻、電容等)的積集度持續地增加，半導體工業經歷了快速成長。大體而言，積集度的增加是來自於最小特徵尺寸(feature size)不斷地縮減，以允許更多的較小元件整合到一給定區域內。較小的電子元件需要面積比以往的封裝更小的較小封裝。半導體元件的其中一部分較小型的封裝包括有四面扁平封裝(quad flat packages，QFPs)、引腳柵格陣列(pin grid array，PGA)封裝、球狀柵格陣列(ball grid array，BGA)封裝等等。
目前，整合扇出型封裝由於其緊密度而趨於熱門。
在本發明的一些實施例中，一種封裝結構包括晶粒、重佈線結構、集成扇出型穿孔及第一連接件。重佈線結構與晶粒連接且包括多個重佈線。集成扇出型穿孔位於晶粒側邊且穿過重佈 線層結構。第一連接件與集成扇出型穿孔電性接觸，且與晶粒電性連接。集成扇出型穿孔與重佈線層結構的重佈線層電性接觸。
在本發明的另一些實施例中，一種封裝結構包括晶粒、重佈線結構、集成扇出型穿孔以及連接件。重佈線結構與晶粒連接。集成扇出型穿孔位於晶粒側邊且穿過重佈線結構。連接件與集成扇出型穿孔電性接觸，且與晶粒電性連接。
在本發明的一些實施例中，一種製造封裝結構的方法包括：在第一介電層上形成重佈線結構；將晶粒貼附於重佈線結構上。在晶粒側邊形成集成扇出型穿孔。集成扇出型穿孔穿過重佈線結構。形成連接件，與集成扇出型穿孔電性接觸。
10:載板
11:離型層
12:介電層
13、13a、13b、22、22a、22b、38、38a、122、122a、122b: 晶種層
14、23、39:圖案化的罩幕層
15、41、62:導電層
16、25、37、40、45a、45b、145a:開口
17:重佈線層
17a、17b、117a:重佈線
18、18’、118:間隙
19:介電層/第二介電層
19b、24:頂表面
20、120:凹槽
20a:第一凹槽
20b:第二凹槽
21、44、144:重佈線結構
26、126:導電柱
27、127:集成扇出型穿孔
27a:第一嵌入部
27b:第二嵌入部
27c、127b:凸出部
28:黏著膜
29、71:基底
30、74、75:接墊
31、33:鈍化層
32、46a、46b、146a、63:連接件
34:晶粒
35、77:封裝體
36:介電層/第一介電層
42:重佈線層/第一重佈線層
42a:通孔
42b:導電線路
43:介電層/第二介電層
47:側壁
48:底部填充層
50a、50b、70:封裝結構
60:介電層/第三介電層
61:重佈線層/第二重佈線層
72:晶粒
73:結合導線
127a:嵌入部
W0、W11:寬度
W1、W12:頂面寬度
W2:底面寬度
α:頂角
圖1A至圖1L是說明根據本揭露第一實施例的形成封裝結構的方法的示意性剖視圖。
圖2A至圖2C是說明根據本揭露第二實施例的形成封裝結構的方法的示意性剖視圖。
圖3A至圖3F是說明根據本揭露一些實施例的形成封裝結構的方法的示意性剖視圖。
以下公開內容提供用於實現所提供主題的不同特徵的許多不同的實施例或實例。以下闡述元件及配置的具體實例以簡 化本公開內容。當然，這些僅為實例而非用以限制。舉例來說，以下說明中將第二特徵形成於第一特徵“之上”或第一特徵“上”可包括第二特徵與第一特徵被形成為直接接觸的實施例，且也可包括第二特徵與第一特徵之間可形成有附加特徵使得所述第二特徵與所述第一特徵可能不直接接觸的實施例。另外，本公開內容可能在各種實例中重複使用元件符號及/或字母。這種重複是出於簡潔及清楚的目的，而不表示所論述的各種實施例及/或配置本身之間的關係。
另外，為易於說明，本文中可能使用例如“在...之下(beneath)”、“在...下面(below)”、“下部的(lower)”、“在...上(on)”、“在...上方(above)”、“上部的(upper)”等空間相對性用語來闡述圖中所示的一個元件或特徵與另一(其他)元件或特徵的關係。除了附圖中所繪示的定向之外，所述空間相對性用語意欲涵蓋元件在使用或操作中的不同定向。設備可具有其他定向(旋轉90度或其他定向)，且本文中所用的空間相對性用語可同樣相應地進行解釋。
以下揭露也可包括其他特徵及製程。舉例來說，可包括測試結構，以對三維(three dimensional，3D)封裝或三維積體電路(three dimensional integrated circuit，3DIC)裝置進行驗證測試。所述測試結構可包括例如在重佈線路層中或在基底上形成的測試接墊(test pad)，所述測試接墊能夠測試三維封裝或三維積體電路、使用探針及/或探針卡(probe card)等。可對中間結構以及最終結構進行驗證測試。另外，可將本文中所公開的結構及方法與包括對已知良好晶粒進行中間驗證的測試方法結合使用，以 提高良率並降低成本。
圖1A至圖1L是說明根據本揭露第一實施例的形成封裝結構的方法的示意性剖視圖。
請參照圖1A，提供載板10。載板10可為玻璃載板、陶瓷載板或類似載板。以例如是旋轉塗布(spin coating)法在載板10上形成離型層11。在一些實施例中，離型層11可由例如紫外(Ultra-Violet，UV)膠、光/熱轉換(Light-to-Heat Conversion，LTHC)材料、環氧樹脂類的熱離型材料等聚合物類的材料形成。離型層11可在光熱作用下分解，以使載板10從將在後續步驟中形成的上覆結構脫離。
在離型層11上形成介電層12(或稱為第一介電層)。介電層12可為單層結構或多層結構。在一些實施例中，介電層12的材料包括無機介電材料、有機介電材料或其組合。無機介電材料包括：氮化物(例如氮化矽)、氧化物(氧化矽)、氮氧化物(例如氮氧化矽)、磷矽酸鹽玻璃(phosphosilicate glass，PSG)、硼矽酸鹽玻璃(borosilicate glass，BSG)、摻雜有硼的磷矽酸鹽玻璃(boron-doped phosphosilicate glass，BPSG)、或其類似物或其組合。有機介電材料包括聚合物，所述聚合物可為感光性材料，例如聚苯並惡唑(polybenzoxazole，PBO)、聚醯亞胺(polyimide，PI)、苯並環丁烯(benzocyclobutene，BCB)、味之素構成膜(ajinomoto buildup film，ABF)、阻銲膜(solder resist film，SR)、或其類似物、或其組合。介電層12例如是藉由旋轉塗布法、疊層法、沉積法等合適的製作技術形成。
請繼續參照圖1A，以例如是物理氣相沉積(physical vapor deposition，PVD)的方式在介電層12上形成晶種層13。在一些實施例中，物理氣相沉積(包括濺鍍沉積)、氣相沉積或其它合適的方法。晶種層13可為包含銅、鋁、鈦、其合金、或其多層組合的金屬晶種層。在一些實施例中，晶種層13包括第一金屬層(例如，鈦層(圖中未示出))以及位於第一金屬層之上的第二金屬層(例如，銅層(圖中未示出))。在一些實施例中，此晶種層13為共形層(conformal layer)。也就是說，晶種層13具有沿著上面形成有晶種層13的區域延伸的實質上相等的厚度。
之後，在晶種層13上形成圖案化的罩幕層14。圖案化的罩幕層14具有多個開口16。所述多個開口16暴露出部分晶種層13。圖案化的罩幕層14例如為光阻。圖案化的罩幕層14例如是藉由以下步驟形成：首先在晶種層13上形成光阻層；並接著對光阻層進行曝光及顯影製程。
請繼續參照圖1A，以例如是電鍍或無電電鍍的方式，在開口16暴露出的晶種層13上形成導電層15。導電層15例如是由銅或其他合適的金屬形成。
請參照圖1A及圖1B，接著移除圖案化的罩幕層14，以使得未被導電層15覆蓋的晶種層13暴露出來。移除的方式例如是乾式剝除(dry strip)法、濕式剝除(wet strip)法或其組合。在一些實施例中，接著利用導電層15做為罩幕來移除未被導電層15覆蓋的晶種層13，從而形成晶種層13a。在一些實施例中，晶種層13a可用作導電層15的阻障層或黏著層。所述移除方法包括蝕刻製程，例如乾蝕刻、濕蝕刻或其組合。
請參照圖1B，晶種層13a與導電層15形成重佈線 (redistribution line，RDL)層17。在一些實施例中，重佈線層17包括多條導電線路(conductive trace)，所述多條導電線路在介電層12上延伸且彼此連接。在另一些實施例中，重佈線層17具有多層結構且包括多個通孔(via)以及彼此連接的多條導電線路。在一些實施例中，重佈線層17包括重佈線17a及重佈線17b。具體來說，重佈線17a位於重佈線17b的兩側。重佈線17a及重佈線17b的數量可根據產品設計來進行調整。在重佈線17a與重佈線17b之間存在多個間隙18及18’。在一些實施例中，間隙18存在於相鄰的兩條重佈線17a之間，且間隙18的寬度W0的範圍為40μm至500μm。間隙18’存在於相鄰的兩條重佈線17b之間或相鄰的重佈線17a與重佈線17b之間。在一些實施例中，間隙18’的寬度大於間隙18的寬度W0。
請繼續參照圖1B，在介電層12及重佈線層17上形成介電層19(或者稱為第二介電層)。介電層19填充在間隙18及18’中，覆蓋介電層12、重佈線層17的側壁47以及重佈線層17的頂表面24。介電層19可為單層結構或多層結構。在一些實施例中，介電層19的材料包括無機介電材料、有機介電材料或其組合。無機介電材料包括：氮化物(例如氮化矽)、氧化物(例如氧化矽)、氮氧化物(例如氮氧化矽)、磷矽酸鹽玻璃、硼矽酸鹽玻璃、摻雜有硼的磷矽酸鹽玻璃、其類似物或其組合。有機介電材料包括聚合物，所述聚合物可為感光性材料，例如是聚苯並惡唑、聚醯亞胺、苯並環丁烯、味之素構成膜、阻銲膜、其類似物或其組合。介電層19的材料與介電層12的材料可相同或不同。介電層19例如是藉由旋轉塗布法、疊層法、沉積法等合適的製作技術 形成。在一些實施例中，重佈線層17與介電層19形成重佈線結構21。
請參照圖1B及圖1C，之後，移除位於間隙18上方的部分介電層19以及位於間隙18中的介電層19，以形成多個凹槽20。移除的方式例如是曝光及顯影製程、雷射鑽孔製程、微影及蝕刻製程或其組合。凹槽20穿過重佈線結構21，暴露出兩條相鄰的重佈線17a的部分頂表面24和側壁47以及介電層12的部分頂表面。
在一些實施例中，凹槽20包括在空間上彼此連通的第一凹槽20a及第二凹槽20b。第一凹槽20a位於第二凹槽20b之上，即，第一凹槽20a與第二凹槽20b是交疊的。第一凹槽20a的寬度大於第二凹槽20b的寬度。第一凹槽20a位於兩條相鄰的重佈線17a之上，暴露出重佈線17a的部分頂表面24。第二凹槽20b位於兩條相鄰的重佈線17a之間，暴露出重佈線17a的側壁47以及介電層12的頂表面。
在一些實施例中，凹槽20具有階梯形狀，凹槽20的剖面形狀為T型或類似漏斗狀，但本發明並非僅限於此。第一凹槽20a的側壁(即，介電層19的側壁)與介電層19的頂表面19b形成頂角α。頂角α的角度範圍為100°至140°。
請參照圖1C至圖1D，接著在重佈線結構21上及介電層12上形成晶種層22。晶種層22的材料及形成方法與圖1A所示晶種層13的材料及形成方法實質上相同，於此不再贅述。晶種層22覆蓋介電層19的頂表面19b以及凹槽20的底表面及側壁。在一些實施例中，晶種層22與重佈線17a的部分頂表面24、重佈 線17a的側壁47以及介電層12的部分頂表面接觸。晶種層22的底表面與重佈線17a的晶種層13a的底表面實質上齊平。
請參照圖1D，在晶種層22上形成圖案化的罩幕層23。圖案化的罩幕層23具有多個開口25。開口25暴露出位於凹槽20中的晶種層22以及覆蓋介電層19的頂角α的晶種層22。
請繼續參照圖1D，在圖案化的罩幕層23的開口25暴露出的晶種層22上形成多個導電柱26。導電柱26設置在凹槽20中，且凸出於介電層19的頂表面19b。導電柱26可為銅柱或任意其他適合的金屬柱。用語“銅柱”是指銅凸出部、銅穿孔、厚銅接墊及/或含銅凸出部。全文中，用語“銅”旨在包括實質上純的元素銅、含有不可避免的雜質的銅、或含有微量的例如鉭、銦、錫、鋅、錳、鉻、鈦、鍺、鍶、鉑、鎂、鋁或鋯等元素的銅合金等。導電柱26是例如藉由電鍍形成。
請參照圖1D及圖1E，接著移除圖案化的罩幕層23，以使得未被導電柱26覆蓋的晶種層22暴露出來。接著利用導電柱26做為罩幕，以移除未被導電柱26覆蓋的晶種層22，從而形成晶種層22a。在一些實施例中，晶種層22a可用作導電柱26的阻障層或黏著層。所述移除方法包括蝕刻製程，例如乾蝕刻、濕蝕刻或其組合。
請參照圖1E，晶種層22a及其上覆的導電柱26形成多個集成扇出型穿孔(through integrated fan-out via，TIV)27。集成扇出型穿孔27的數目並非僅限於圖1E所示的數目，而是可根據需要進行調整。集成扇出型穿孔27設置在凹槽20中，且凸出於介電層19的頂表面19b。集成扇出型穿孔27穿過重佈線結構 21，且與介電層12接觸。換句話說，集成扇出型穿孔27與重佈線結構21嚙合。另外，集成扇出型穿孔27與兩條相鄰的重佈線17a的部分頂表面24以及側壁47電性接觸。
請繼續參照圖1E，在一些實施例中，集成扇出型穿孔27的末端(即，集成扇出型穿孔27的底部)具有階梯形狀，且與重佈線結構21嚙合。具體來說，導電柱26的一個末端及晶種層22a具有階梯形狀。導電柱26的部分側壁及底部被晶種層22a覆蓋。集成扇出型穿孔27的另一個末端(即，導電柱26的另一個末端)是平坦的。集成扇出型穿孔27自下而上包括彼此電性接觸的第一嵌入部27a、第二嵌入部27b及凸出部27c。第一嵌入部27a及第二嵌入部27b位於凹槽20中。凸出部27c位於重佈線結構21之上，凸出於介電層19的頂表面19b。
具體來說，第一嵌入部27a位於兩條相鄰的重佈線17a之間且與重佈線17a的側壁47電性接觸。第一嵌入部27a的頂表面與重佈線17a的頂表面24實質上齊平；第一嵌入部27a的底表面與重佈線17a的底表面實質上齊平且與介電層12接觸。第二嵌入部27b位於第一嵌入部27a以及兩條相鄰的重佈線17a上，以與兩條相鄰的重佈線17a的部分頂表面24電性接觸。在一些實施例中，第一嵌入部27a的剖面形狀是正方形或矩形；第二嵌入部27b的剖面形狀是倒梯形或矩形。第一嵌入部27a與第二嵌入部27b整體的剖面形狀為T型或類似漏斗狀。在一些實施例中，第二嵌入部27b的底面寬度W2等於或大於第一嵌入部27a的頂面寬度W1，以使得集成扇出型穿孔的底部具有階梯形狀。在一些示例性實施例中，第二嵌入部27b的底面寬度W2的範圍為50μm至 510μm；第一嵌入部37a的頂面寬度W1實質上等於間隙18(圖1B所示)的寬度W0，且其範圍為40μm至500μm。
凸出部27c位於第二嵌入部27b上。在一些實施例中，凸出部27c覆蓋第二嵌入部27b的頂表面以及部分介電層19的頂表面19b。也就是說，介電層19的頂角α被集成扇出型穿孔27覆蓋，但本發明並非僅限於此。在另一些實施例中，凸出部27c僅覆蓋第二嵌入部27b的頂表面，而不覆蓋介電層19的頂表面19b(圖中未示出)。在一些實施例中，凸出部27c的剖面形狀是矩形或梯形，但本發明並非僅限於此。
請參照圖1F，藉由黏著膜28(例如，晶粒貼合膜(die attach film，DAF))將晶粒(die)34貼附於介電層19，並將晶粒34設置在集成扇出型穿孔27之間。晶粒34包括基底29、多個接墊30、鈍化層31、多個連接件32及鈍化層33。接墊30可為內連結構(圖中未示出)的一部分，且與形成在基底29上的積體電路裝置(圖中未示出)電性連接。鈍化層31形成在基底29之上且覆蓋接墊30的一部分。接墊30的一部分被鈍化層31暴露出且做為晶粒34的外部連接。連接件32形成在未被鈍化層31覆蓋的接墊30上，且與未被鈍化層31覆蓋的接墊30電性連接。連接件32包括銲料凸塊、金凸塊、銅凸塊、銅柱等。鈍化層33形成在鈍化層31之上及連接件32的側邊，以覆蓋連接件32的側壁。鈍化層31及33分別包含絕緣材料，例如氧化矽、氮化矽、聚合物或其組合。在一些實施例中，鈍化層33的的頂表面與連接件32的頂表面實質上齊平。
在一些實施例中，晶粒34例如是從晶圓(wafer)切割 下來的多個晶粒中的一個。晶粒34可為特定應用積體電路(application-specific integrated circuit，ASIC)晶片、類比晶片(analog chip)、感測晶片(sensor chip)、無線射頻晶片(wireless and radio frequency chip)、電壓調節器晶片(voltage regulator chip)或記憶體晶片(memory chip)。圖1F所示晶粒34的數目僅用於例示說明，且本發明並非僅限於此。在一些實施例中，在介電層19上可安裝兩個或更多個晶粒34，所述兩個或更多個晶粒34可為相同類型的晶粒或不同類型的晶粒。在另一些實施例中，將包括以陣列形式排列的多個晶粒34的晶圓(圖中未示出)安裝到介電層19上，且晶粒34被集成扇出型穿孔27環繞。
接著在載板10上形成封裝體35，以囊封(encapsulate)晶粒34的側壁以及集成扇出型穿孔27的凸出部27c。在一些實施例中，封裝體35包含模塑化合物(molding compound)、模塑底部填充料(molding underfill)、樹脂(例如環氧樹脂)、其組合或類似物。在另一些實施例中，封裝體35包括可容易地藉由曝光及顯影製程被圖案化的感光性材料，例如聚苯並惡唑、聚醯亞胺、苯並環丁烯、其組合或類似物。在替代實施例中，封裝體35包含氮化物(例如氮化矽)、氧化物(例如氧化矽)、磷矽酸鹽玻璃、硼矽酸鹽玻璃、摻雜硼的磷矽酸鹽玻璃、其組合或類似物。封裝體35是藉由以下步驟形成：藉由例如旋轉塗布法、疊層法、沉積法或類似的製程等合適的製造技術，在載板10之上形成封裝材料層。封裝材料層囊封晶粒34的頂表面及側壁以及集成扇出型穿孔27的凸出部27c的頂表面及側壁。之後，進行研磨或拋光製程，以移除部分封裝材料層，使得連接件32的頂表面及集成扇出型穿 孔27的頂表面暴露出來。在一些實施例中，連接件32的頂表面、集成扇出型穿孔27的頂表面以及封裝體35的頂表面實質上共面。
請參照圖1G，在晶粒34、集成扇出型穿孔27以及封裝體35上形成第一介電層36。第一介電層36可為單層結構或多層結構。第一介電層36具有多個開口37，開口37暴露出部分集成扇出型穿孔27以及晶粒34的部分連接件32。第一介電層36的材料與介電層12及介電層19的材料相似。第一介電層36藉由以下步驟形成：首先形成第一介電材料層(圖中未示出)，以覆蓋晶粒34、封裝體35及集成扇出型穿孔27。之後，移除位於集成扇出型穿孔27上以及位於連接件32上的部分介電材料層，以形成具有開口37的第一介電層36。移除的方式例如是曝光及顯影製程、雷射鑽孔製程、微影及蝕刻製程或其組合。
請繼續參照圖1G，在第一介電層36上形成晶種層38，且晶種層38填充於開口37中，以覆蓋開口37的底表面及側壁。晶種層38在開口37的底部處與集成扇出型穿孔27及連接件32電性接觸。晶種層38的材料及形成方法與圖1A所示晶種層13的材料及形成方法相似。
請參照圖1H，在晶種層38上形成圖案化的罩幕層39。圖案化的罩幕層39具有多個開口40。開口40暴露出開口37中的晶種層38以及第一介電層36上的部分晶種層38。接著，在開口40暴露出的晶種層38上形成導電層41。導電層41填充到開口37中，且凸出於第一介電層36的頂表面，並覆蓋第一介電層36的部分頂表面。
請參照圖1H及圖1I，接著移除圖案化的罩幕層39，以 使得未被導電層41覆蓋的晶種層38暴露出來。接著利用導電層41做為罩幕，以移除未被導電層41覆蓋的晶種層38，從而形成晶種層38a。所述移除方法包括蝕刻製程，例如，乾蝕刻、濕蝕刻或其組合。
請參照圖1I，晶種層38a與導電層41形成重佈線層42。在一些實施例中，重佈線層42與集成扇出型穿孔27以及晶粒34的連接件32接觸並電性連接。在一些實施例中，重佈線層42包括多個通孔42a及多條導電線路42b。通孔42a穿過第一介電層36，而與集成扇出型穿孔27及連接件32接觸。導電線路42b在第一介電層36上延伸，且與通孔42a連接。之後，在重佈線層42上形成第二介電層43，以覆蓋重佈線層42的頂表面及側壁。第二介電層43的材料及形成方法與介電層12的材料及形成方法相似，於此不再贅述。
第一介電層36、重佈線層42以及第二介電層43形成重佈線結構44。重佈線結構44的重佈線層42的層數並非僅限於圖1I所示，而是可根據需要進行調整。重佈線結構44可具有一層或多層重佈線層42。在重佈線結構44具有多於一層重佈線層42的一些實施例中，重佈線結構44包括多個堆疊的介電層36及43，以及重佈線層42(圖中未示出)。重佈線結構44的多層結構的形成方法例如是在形成第二介電層43之後，重複進行上述圖1G至圖1I的製程，以形成多層重佈線層42。
請繼續參照圖1I，重佈線結構44是設置在晶粒34的前側(靠近連接件32的一側，即，靠近晶粒34的主動表面的一側)，重佈線結構21是設置在晶粒34的背側(與前側相對的一側)。 因此，在一些實施例中，重佈線結構21被稱為背側重佈線結構，而重佈線結構44被稱為前側重佈線結構。
請參照圖1I及圖1J，將在圖1I中形成的結構翻轉，使離型層11在光熱作用下分解，且接著將載板10從載板10的上覆結構脫離。
請繼續參照圖1J及圖1K，移除部分介電層12、部分晶種層13a以及集成扇出型穿孔27頂部的晶種層22a，以形成多個開口45a。開口45a穿過重佈線結構21的介電層12以及重佈線17a的晶種層13a。另外，移除位於重佈線17b上的部分介電層12及其下方的晶種層13a，以形成多個開口45b。開口45b穿過介電層12以及重佈線17b的晶種層13a。所述移除方法例如是包括雷射鑽孔製程。重佈線層17的晶種層13b以及集成扇出型穿孔27的晶種層22b留下來。導電柱26的部分側壁被晶種層22b覆蓋。導電柱26與介電層19被位於兩者之間的晶種層22b隔開。開口45a的底部暴露出集成扇出型穿孔27的晶種層22b及導電柱26，以及重佈線17a的導電層15的部分頂表面。開口45a的側壁暴露出重佈線17a的晶種層13b以及介電層12。開口45a的寬度可進行調整，只要開口45a的底部至少暴露出部分導電柱26即可。開口45b的底部暴露出重佈線17b的導電層15。開口45b的側壁暴露出介電層12以及重佈線17b的晶種層13b。在一些晶種層13(圖1A所示)與晶種層22(圖1D所示)形成為同一厚度的實施例中，導電柱26的頂表面及晶種層22b的頂表面與導電層15的頂表面(與晶種層13b接觸的表面)實質上共面，但本發明並非僅限於此。
請參照圖1K及圖1L，分別在集成扇出型穿孔27上及重佈線17b上形成多個連接件46a及46b。連接件46a及46b又可稱為導電端子。在一些實施例中，連接件46a及46b可覆蓋介電層12的部分頂表面。在另一些實施例中，連接件46a及46b可不覆蓋介電層12的頂表面。連接件46a與46b可同時形成或先後形成。連接件46a填充於開口45a中，且穿過介電層12以及重佈線17a的晶種層13b。連接件46a的底部與集成扇出型穿孔27的導電柱26及晶種層22b以及重佈線17a的導電層15電性接觸。連接件46a的側壁與重佈線17a的晶種層13b以及介電層12接觸。連接件46b填充於開口45b中，以使得連接件46b的底部與重佈線17b的導電層15電性接觸；而連接件46b的側壁與重佈線17b的晶種層13b以及介電層12接觸。連接件46a及46b的材料包括銅、鋁、無鉛合金(例如，金、錫、銀、鋁或銅合金)或者鉛合金(例如，鉛錫合金)。在一些實施例中，連接件46a及46b分別藉由植球製程(ball mounting process)形成。在另一些實施例中，可進行印刷步驟以將銲料(solder paste)印刷到開口45a及45b中，之後對銲料進行回銲，以形成連接件46a及46b。或者，將銲球滴入開口45a及45b中，並接著進行回銲製程，以形成連接件46a及46b。在一些實施例中，更包括在形成連接件46a及46b之前，形成球下金屬(under-ball metallurgy，UBM)層(圖中未示出)。球下金屬層填充於開口45a及45b中，覆蓋開口45a及45b的底部及側壁以及部分介電層12。
請繼續參照圖1L，至此，封裝結構50a即已完成。封裝結構50a包括晶粒34、重佈線結構21、集成扇出型穿孔27、重佈 線結構44以及連接件46a及46b。集成扇出型穿孔27穿過重佈線結構21，且與連接件46a電性接觸。之後，封裝結構50a可藉由連接件46a及46b連接到其他封裝元件，例如印刷電路板(printed circuit board，PCB)、軟性印刷電路板或類似物。在前述製程中將包括多個晶粒34的晶圓形成在載板10上的一些實施例中，在連接到其他封裝元件之前，可藉由晶粒切割製程(die-saw process)將封裝結構(圖中未示出)單體化，以形成多個相同的如圖1L所示的封裝結構50a。
圖2A至圖2C是說明根據本揭露第二實施例的形成封裝結構的方法的示意性剖視圖。第二實施例與第一實施例的不同之處在於，進一步形成了連接件63，以與晶粒34上的重佈線結構144連接，並形成疊層封裝(package-on-package，POP)裝置。詳細說明如下。
請參照圖1I及圖2A，在一些實施例中，重佈線結構144包括交替堆疊的多個重佈線層42/61以及介電層36/43/60，且重佈線層42被稱為第一重佈線層42。在一些實施例中，在如圖1I所示形成第一介電層36、第一重佈線層42及第二介電層43之後，進行與圖1G至圖1I中所述製程相似的製程，從而形成第二重佈線層61及第三介電層60。第二重佈線層61穿過第二介電層43，以與第一重佈線層42連接。第二重佈線層61及第三介電層60的材料、形成方法及結構特性與第一重佈線層42及第二介電層43的材料、形成方法及結構特性相似，於此不再贅述。
之後，形成導電層62，其穿過第三介電層60，與第二重佈線層61連接。在一些實施例中，導電層62被稱為球下金屬 (UBM)層。導電層62的材料包括金屬或金屬合金。導電層62例如是銅、錫、其合金或其組合。導電層62例如是藉由物理氣相沉積或電鍍形成。
請繼續參照圖2A，將多個連接件(也稱為導電球)63置於導電層62上。連接件63的材料包括銅、鋁、無鉛合金(例如，金、錫、銀、鋁或銅合金)或者鉛合金(例如，鉛錫合金)。在一些實施例中，連接件63是藉由植球製程被置於導電層62上。連接件63藉由導電層62及重佈線結構144與連接件32電性連接。
請參照圖2A及圖2B，接著進行與圖1J至圖1L中所述製程相似的製程，將圖2A中所形成的結構翻轉，使離型層11分解，且接著將載板10從其上覆結構脫離。
請參照圖2B，形成多個開口45a及45b。之後，形成多個連接件46a。連接件46a穿過介電層12以及重佈線17a的晶種層13b，與集成扇出型穿孔27及重佈線17a電性接觸。形成多個連接件46b。連接件46b穿過介電層12，與重佈線17b電性接觸。連接件46a與46b可同時形成或先後形成。開口45a及45b以及連接件46a及46b的形成方法及結構特性與第一實施例中的開口45a及45b以及連接件46a及46b的形成方法及結構特性實質上相同，於此不再贅述。
至此，封裝結構50b即已完成。在一些實施例中，封裝結構50b可進一步電耦合至封裝結構70，以形成疊層封裝裝置，但本發明並非僅限於此。
請參照圖2C，在一些實施例中，封裝結構70具有基底71以及安裝在基底71的一個表面(例如，頂表面)上的晶粒72。 結合導線(bonding wires)73可用於提供晶粒72與位於基底71的相同頂表面的接墊74(例如，結合接墊(bonding pads))之間的電性連接。集成扇出型穿孔(圖中未示出)可用於提供接墊74與位於基底71相對表面(例如，底表面)上的接墊75(例如，結合接墊)之間的電性連接。連接件46a及46b連接接墊75，並與封裝結構50b電性連接。在上述結構上方形成封裝體77，以保護上述構件不受環境及外部污染物的影響。
之後，形成底部填充層(under-fill layer)48，填充於封裝結構50b與封裝結構70之間，並環繞連接件46a及46b。在一些實施例中，底部填充層48包括模塑化合物(例如，環氧樹脂)，且可藉由點膠(dispensing)、注射(injecting)及/或噴射(spraying)技術形成。
圖3A至圖3F是說明根據本揭露一些實施例的形成封裝結構的方法的示意性剖視圖。
在前述實施例中，如圖1L及圖2B所示，集成扇出型穿孔27穿過重佈線結構21以與連接件46a電性接觸，且集成扇出型穿孔27及連接件46a也與重佈線17a的導電層15以及晶種層13b電性接觸。請參照圖3A至圖3F，在一些實施例中，可存在一些集成扇出型穿孔127，其未與重佈線117a接觸，而是與重佈線117a之間透過介電層19隔開，且連接件46a也不與重佈線117a接觸。為簡潔起見，圖3A至圖3E僅示出重佈線117a、集成扇出型穿孔127、封裝體35及連接件146a。
請參照圖1B、圖3A及圖3B，重佈線結構21更包括重佈線117a，且間隙118存在於相鄰兩條重佈線117a之間。移除位 於間隙118內的部分介電層19，以形成穿過介電層19的凹槽120。凹槽120位於相鄰的兩條重佈線117a之間。在一些實施例中，凹槽120的底部暴露出介電層12的部分頂表面。由於間隙118中的介電層19是被部分地移除，因而凹槽120並未暴露出重佈線117a。在一些實施例中，凹槽120的剖面形狀可為倒梯形、正方形、矩形或其他任意形狀，只要重佈線117a的表面被介電層19覆蓋即可。之後，在介電層19上形成晶種層122。
請參照圖3B至圖3D，進行與圖1D至圖1E中所述製程相似的製程，以形成集成扇出型穿孔127。集成扇出型穿孔127包括導電柱126及晶種層122a，其材料及形成方法與集成扇出型穿孔27的材料及形成方法實質上相同，於此不再贅述。集成扇出型穿孔127穿過重佈線結構21且與介電層12接觸。集成扇出型穿孔127與前述實施例的集成扇出型穿孔27的不同之處在於，集成扇出型穿孔127未與重佈線117a電性接觸，而是與重佈線117a之間藉由介電層19隔開。在一些實施例中，集成扇出型穿孔127包括嵌入部127a及凸出部127b。嵌入部127a位於凹槽120中，且嵌入部127a的頂表面與介電層19的頂表面19b實質上齊平。在一些實施例中，嵌入部127a的剖面形狀可為倒梯形、正方形或矩形，但本發明並非僅限於此。在一些嵌入部127a具有倒梯形剖面形狀的實施例中，嵌入部127a的頂面寬度W12小於圖3A所示間隙118的寬度W11。凸出部127b位於嵌入部127a上，且凸出於介電層19的頂表面19b。凸出部127b的其他結構特性與圖1E所示集成扇出型穿孔27相似。
請參照圖1J、圖3D及圖3E，在載板10脫離之後，移 除部分介電層以及覆蓋導電柱126頂表面的晶種層122a，從而形成穿過介電層12的開口145a，且留下集成扇出型穿孔127的晶種層122b。嵌入部127a的部分側壁被晶種層122b覆蓋，嵌入部127a的頂表面被開口145a暴露出來。開口145a的寬度可進行調整，只要開口145a的底部至少暴露出部分導電柱126即可。
導電柱126與介電層19被位於兩者之間的晶種層122b隔開。在一些實施例中，晶種層122b的剖面形狀是L型或線形的，但本發明並非僅限於此。
在一些實施例中，開口145a的剖面形狀例如是倒梯形或矩形，但本發明並非僅限於此。開口145a的底部暴露出集成扇出型穿孔127的導電柱126以及晶種層122b。在一些實施例中，導電柱126的頂表面及晶種層122b的頂表面與重佈線117a的導電層15實質上共面。請參照圖3F，在集成扇出型穿孔127上形成連接件146a。連接件146a可被稱為導電端子。連接件146a穿過介電層12，且連接件146a的底部與集成扇出型穿孔127的導電柱126及晶種層122b電性接觸。連接件146a與重佈線117a被位於兩者之間的介電層19隔開。
在本發明的一些實施例中，集成扇出型穿孔被設置成穿過重佈線結構，以與連接件接觸並電性連接，由此可避免由晶種層或阻障層或者黏著層造成的集成扇出型穿孔與重佈線結構之間裂開的問題(open issue)。另一方面，由於晶種層是被部分移除，因此仍有部分晶種層設置在集成扇出型穿孔的導電柱與介電層之間，因而也可避免分層(delamination)問題。
根據本發明的一些實施例，提供一種封裝結構，其包括 晶粒、重佈線結構、集成扇出型穿孔及第一連接件。重佈線結構與晶粒連接且包括多個重佈線。集成扇出型穿孔位於晶粒側邊且穿過重佈線層結構。第一連接件與集成扇出型穿孔電性接觸，且與晶粒電性連接。集成扇出型穿孔與重佈線結構的重佈線電性接觸。
在上述封裝結構中，集成扇出型穿孔包括第一晶種層及導電柱，且導電柱與第一連接件電性接觸。
在上述封裝結構中，導電柱的部分側壁被第一晶種層覆蓋。
在上述封裝結構中，集成扇出型穿孔的末端具有階梯形狀。
在上述封裝結構中，第一晶種層及所述導電柱的末端具有階梯形狀。
在上述封裝結構中，重佈線包括第二晶種層及導電層。
在上述封裝結構中，第一連接件的底表面與集成扇出型穿孔的第一晶種層及導電柱以及重佈線的導電層電性接觸，第一連接件的側壁與重佈線的第二晶種層電性接觸。
在上述封裝結構中，更包括設置在晶粒上的第二連接件，其中第二連接件穿過重佈線中的一者的第二晶種層，且與重佈線中的所述一者的導電層接觸。
根據本發明的替代實施例，提供一種封裝結構，其包括晶粒、重佈線結構、集成扇出型穿孔以及連接件。重佈線結構與晶粒連接。集成扇出型穿孔位於晶粒側邊且穿過重佈線結構。連接件與集成扇出型穿孔電性接觸，且與晶粒電性連接。
在上述封裝結構中，重佈線結構包括介電層及多條重佈線，且集成扇出型穿孔與重佈線被位於兩者之間的介電層隔開。
在上述封裝結構中，集成扇出型穿孔包括晶種層及導電柱，其中導電柱的部分側壁被晶種層覆蓋。
在上述封裝結構中，連接件與集成扇出型穿孔的導電柱電性接觸。
在上述封裝結構中，連接件與重佈線被重佈線結構的介電層隔開。
在上述封裝結構中，集成扇出型穿孔包括嵌入部及凸出部，其中嵌入部設置在重佈線之間，凸出部位於所述晶粒側邊且位於封裝體中。
根據本發明的一些實施例，提供一種製造封裝結構的方法。對所述方法闡述如下。在第一介電層上形成重佈線結構。將晶粒貼附於重佈線結構上。在晶粒側邊形成集成扇出型穿孔。集成扇出型穿孔穿透重佈線結構。形成連接件，與集成扇出型穿孔電性接觸。
在上述製造封裝結構的方法中，形成重佈線結構包括：在第一介電層上形成多條重佈線，以及在所述重佈線上形成第二介電層。在形成集成扇出型穿孔之前，移除部分第二介電層，以形成穿過重佈線結構的凹槽，其中凹槽的底部暴露出第一介電層，且集成扇出型穿孔形成於凹槽中並凸出於第二介電層的頂表面。
在上述製造封裝結構的方法中，凹槽進一步暴露出重佈線的側壁以及重佈線的部分頂表面，使得集成扇出型穿孔與重佈 線的側壁及重佈線的部分頂表面電性接觸。
在上述製造封裝結構的方法中，凹槽被形成為具有階梯形狀。
在上述製造封裝結構的方法中，凹槽沒有暴露出重佈線，使得集成扇出型穿孔與重佈線被位於集成扇出型穿孔與重佈線之間的第二介電層隔開。
在上述製造封裝結構的方法中，形成集成扇出型穿孔包括形成晶種層以及在所述晶種層上形成導電柱，以及在形成第一連接件之前，移除集成扇出型穿孔的部分晶種層，使得第一連接件與集成扇出型穿孔的導電柱及晶種層接觸。
以上概述了數個實施例的特徵，使本領域具有通常知識者可更佳瞭解本揭露的態樣。本領域具有通常知識者應理解，其可輕易地使用本揭露做為設計或修改其他製程與結構的依據，以實行本文所介紹的實施例的相同目的及/或達到相同優點。本領域具有通常知識者還應理解，這種等效的配置並不悖離本揭露的精神與範疇，且本領域具有通常知識者在不悖離本揭露的精神與範疇的情況下可對本文做出各種改變、置換以及變更。
12:介電層
13b、22b、38a:晶種層
15、41:導電層
17a、17b:重佈線
19:介電層/第二介電層
21、44:重佈線結構
26:導電柱
27:集成扇出型穿孔
32、46a、46b:連接件
34:晶粒
35:封裝體
36:介電層/第一介電層
42:重佈線層/第一重佈線層
43:介電層/第二介電層
50a:封裝結構

Claims (10)

  1. 一種封裝結構，包括：晶粒；重佈線結構，與所述晶粒連接，其中所述重佈線結構包括多條重佈線；集成扇出型穿孔，位於所述晶粒側邊且穿過所述重佈線結構；以及第一連接件，與所述集成扇出型穿孔電性接觸，且與所述晶粒電性連接，其中所述集成扇出型穿孔與所述重佈線結構的所述多條重佈線電性接觸，其中所述集成扇出型穿孔包括第一晶種層及導電柱，且所述第一連接件的底面與所述集成扇出型穿孔的所述第一晶種層及所述導電柱物理接觸，其中所述多條重佈線包括第二晶種層及導電層，其中所述第一連接件的所述底面還與所述多條重佈線的所述導電層電性接觸，且所述第一連接件的側壁與所述多條重佈線的所述第二晶種層電性接觸。
  2. 如請求項1所述的封裝結構，其中所述導電柱的部分側壁被所述第一晶種層覆蓋。
  3. 如請求項1所述的封裝結構，其中所述集成扇出型穿孔的與所述第一連接件接觸的頂面低於所述多條重佈線的頂面。
  4. 如請求項1所述的封裝結構，其中所述集成扇出型穿孔的與所述第一連接件接觸的頂面與所述導電層的頂面齊平，且低於所述第二晶種層的頂面。
  5. 一種封裝結構，包括：晶粒；重佈線結構，連接至所述晶粒；集成扇出型穿孔，位於所述晶粒側邊且穿過所述重佈線結構；以及連接件，與所述集成扇出型穿孔的頂面電性接觸，且與所述晶粒電性連接，其中所述集成扇出型穿孔的與所述連接件接觸的所述頂面低於所述重佈線結構的重佈線層的頂面。
  6. 如請求項5所述的封裝結構，其中所述集成扇出型穿孔包括嵌入部及凸出部，所述嵌入部設置在所述重佈線結構的所述重佈線層的所述多條重佈線之間，所述凸出部位于所述晶粒側邊的封裝體中。
  7. 一種封裝結構的製造方法，包括：在第一介電層上形成重佈線結構；將晶粒貼附於所述重佈線結構上；在所述晶粒側邊形成集成扇出型穿孔，所述集成扇出型穿孔穿透所述重佈線結構；以及形成連接件，以與所述集成扇出型穿孔的頂面電性接觸且與所述晶粒電性連接， 其中所述集成扇出型穿孔的與所述連接件接觸的所述頂面低於所述重佈線結構的重佈線層的頂面，且所述重佈線結構與所述晶粒連接。
  8. 一種封裝結構，包括：晶粒；重佈線結構，設置于所述晶粒上並與所述晶粒電性連接；集成扇出型穿孔，位於所述晶粒側邊且延伸至接觸所述重佈線結構的重佈線層的底面與側壁；以及導電端子，通過所述重佈線結構及所述集成扇出型穿孔與所述晶粒電性連接。
  9. 一種封裝結構，包括：晶粒；重佈線結構，電性連接至所述晶粒，其中所述重佈線結構包括重佈線層，所述重佈線層具有第一晶種層與導電層，所述第一晶種層位於所述導電層上；以及集成扇出型穿孔，位於所述晶粒的側邊並延伸至所述重佈線結構中，所述集成扇出型穿孔包括第二晶種層及導電柱，所述第二晶種層位於所述導電柱上，其中所述集成扇出型穿孔的頂面與所述重佈線層的所述導電層的頂面齊平。
  10. 一種封裝結構的製造方法，包括：形成重佈線結構，其中所述重佈線結構包括嵌置於介電層中的重佈線層，其中所述重佈線層包括第一晶種層及導電層； 將晶粒貼附於所述重佈線結構；形成集成扇出型穿孔，所述集成扇出型穿孔位於所述晶粒側邊且延伸至所述重佈線結構中，所述集成扇出型穿孔包括第二晶種層及導電柱；移除所述第一晶種層的一部分及所述第二晶種層的一部分，以暴露出所述導電層的一部分及所述導電柱的一部分；以及形成導電端子，以與所述導電層的所述一部分及所述導電柱的所述一部分接觸。
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