CN109524378A - 封装结构 - Google Patents

封装结构 Download PDF

Info

Publication number
CN109524378A
CN109524378A CN201711017344.3A CN201711017344A CN109524378A CN 109524378 A CN109524378 A CN 109524378A CN 201711017344 A CN201711017344 A CN 201711017344A CN 109524378 A CN109524378 A CN 109524378A
Authority
CN
China
Prior art keywords
layer
dielectric layer
connector
integrated fan
rewiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201711017344.3A
Other languages
English (en)
Other versions
CN109524378B (zh
Inventor
戴志轩
陈志华
蔡豪益
黄育智
刘家宏
郭婷婷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN109524378A publication Critical patent/CN109524378A/zh
Application granted granted Critical
Publication of CN109524378B publication Critical patent/CN109524378B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68372—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to support a device or wafer when forming electrical connections thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02379—Fan-out arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/82001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/82005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/83005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83101—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06568—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices decreasing in size, e.g. pyramidical stack
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06596—Structural arrangements for testing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1035—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1041—Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

本揭露提供一种封装结构。所述封装结构包括管芯、重布线结构、集成扇出型穿孔以及第一连接件。重布线结构与管芯连接且包括多条重布线。集成扇出型穿孔位于管芯侧边且穿过重布线结构。第一连接件与集成扇出型穿孔电性接触，且与管芯电性连接。集成扇出型穿孔与重布线层结构的重布线电性接触。

Description

封装结构
技术领域
本揭露实施例涉及一种封装结构。
背景技术
随着各种电子元件(例如，晶体管、二极管、电阻器、电容器等)的集成密度持续地增加，半导体行业经历了快速成长。在很大程度上，集成密度的增加来自于最小特征尺寸(minimum feature size)的不断减小，以允许更多较小的组件能够集成到给定区域中。这些较小的电子元件需要比以往的封装更小的较小封装。半导体元件的一些较小型的封装包括四面扁平封装(quad flat package，QFP)、引脚阵列(pin grid array，PGA)封装、球阵列(ball grid array，BGA)封装等等。
当前，集成扇出型封装因其紧密度而趋于热门。
发明内容
在本发明的一些实施例中，一种封装结构包括管芯、重布线结构、集成扇出型穿孔及第一连接件。重布线结构与管芯连接且包括多个重布线。集成扇出型穿孔位于管芯侧边且穿过重布线层结构。第一连接件与集成扇出型穿孔电性接触，且与管芯电性连接。集成扇出型穿孔与重布线层结构的重布线层电性接触。
在本发明的另一些实施例中，一种封装结构包括管芯、重布线结构、集成扇出型穿孔以及连接件。重布线结构与管芯连接。集成扇出型穿孔位于管芯侧边且穿过重布线结构。连接件与集成扇出型穿孔电性接触，且与管芯电性连接。
在本发明的一些实施例中，一种制造封装结构的方法包括：在第一介电层上形成重布线结构；将管芯贴附于重布线结构上。在管芯侧边形成集成扇出型穿孔。集成扇出型穿孔穿过重布线结构。形成连接件，与集成扇出型穿孔电性接触。
附图说明
图1A至图1L是说明根据本揭露第一实施例的形成封装结构的方法的示意性剖视图。
图2A至图2C是说明根据本揭露第二实施例的形成封装结构的方法的示意性剖视图。
图3A至图3F是说明根据本揭露一些实施例的形成封装结构的方法的示意性剖视图。
附图标号说明：
10：载板
11：离型层
12：介电层
13、13a、13b、22、22a、22b、38、38a、122、122a、122b：晶种层
14、23、39：图案化的掩模层
15、41、62：导电层
16、25、37、40、45a、45b、145a：开口
17：重布线层
17a、17b、117a：重布线
18、18’、118：间隙
19：介电层/第二介电层
19b、24：顶表面
20、120：凹槽
20a：第一凹槽
20b：第二凹槽
21、44、144：重布线结构
26、126：导电柱
27、127：集成扇出型穿孔
27a：第一嵌入部
27b：第二嵌入部
27c、127b：凸出部
28：黏着膜
29、71：衬底
30、74、75：接垫
31、33：钝化层
32、46a、46b、146a、63：连接件
34：管芯
35、77：封装体
36：介电层/第一介电层
42：重布线层/第一重布线层
42a：通孔
42b：导电线路
43：介电层/第二介电层
47：侧壁
48：底部填充层
50a、50b、70：封装结构
60：介电层/第三介电层
61：重布线层/第二重布线层
72：管芯
73：结合导线
127a：嵌入部
W0、W11：宽度
W1、W12：顶面宽度
W2：底面宽度
α：顶角
具体实施方式
以下公开内容提供用于实现所提供主题的不同特征的许多不同的实施例或实例。以下阐述组件及配置的具体实例以简化本公开内容。当然，这些仅为实例而非用以限制。举例来说，以下说明中将第二特征形成于第一特征“之上”或第一特征“上”可包括第二特征与第一特征被形成为直接接触的实施例，且也可包括第二特征与第一特征之间可形成有附加特征使得所述第二特征与所述第一特征可能不直接接触的实施例。另外，本公开内容可能在各种实例中重复使用元件符号及/或字母。这种重复是出于简洁及清楚的目的，而不表示所论述的各种实施例及/或配置本身之间的关系。
另外，为易于说明，本文中可能使用例如“在...之下(beneath)”、“在...下面(below)”、“下部的(lower)”、“在...上(on)”、“在...上方(above)”、“上部的(upper)”等空间相对性用语来阐述图中所示的一个元件或特征与另一(其他)元件或特征的关系。除了附图中所绘示的定向之外，所述空间相对性用语意欲涵盖元件在使用或操作中的不同定向。设备可具有其他定向(旋转90度或其他定向)，且本文中所用的空间相对性用语可同样相应地进行解释。
以下揭露也可包括其他特征及工艺。举例来说，可包括测试结构，以对三维(threedimensional，3D)封装或三维集成电路(three dimensional integrated circuit，3DIC)装置进行验证测试。所述测试结构可包括例如在重布线路层中或在衬底上形成的测试接垫(test pad)，所述测试接垫能够测试三维封装或三维集成电路、使用探针及/或探针卡(probe card)等。可对中间结构以及最终结构进行验证测试。另外，可将本文中所公开的结构及方法与包括对已知良好管芯进行中间验证的测试方法结合使用，以提高良率并降低成本。
图1A至图1L是说明根据本揭露第一实施例的形成封装结构的方法的示意性剖视图。
请参照图1A，提供载板10。载板10可为玻璃载板、陶瓷载板或类似载板。以例如是旋转涂布(spin coating)的方式在载板10上形成离型层11。在一些实施例中，离型层11可由例如紫外(Ultra-Violet，UV)胶、光/热转换(Light-to-Heat Conversion，LTHC)材料、环氧树脂类的热离型材料等聚合物类的材料形成。离型层11可在光热作用下分解，以使载板10从将在后续步骤中形成的上覆结构脱离。
在离型层11上形成介电层12(或称为第一介电层)。介电层12可为单层结构或多层结构。在一些实施例中，介电层12的材料包括无机介电材料、有机介电材料或其组合。无机介电材料包括：氮化物(例如氮化硅)、氧化物(氧化硅)、氮氧化物(例如氮氧化硅)、磷硅酸盐玻璃(phosphosilicate glass，PSG)、硼硅酸盐玻璃(borosilicate glass，BSG)、掺杂有硼的磷硅酸盐玻璃(boron-doped phosphosilicate glass，BPSG)、或其类似物或其组合。有机介电材料包括聚合物，所述聚合物可为感光性材料，例如聚苯并恶唑(polybenzoxazole，PBO)、聚酰亚胺(polyimide，PI)、苯并环丁烯(benzocyclobutene，BCB)、味之素构成膜(ajinomoto buildup film，ABF)、阻焊膜(solder resist film，SR)、或其类似物、或其组合。介电层12例如是通过旋转涂布法、叠层法、沉积法等合适的制作技术形成。
请继续参照图1A，以例如是物理气相沉积(physical vapor deposition，PVD)的方式在介电层12上形成晶种层13。在一些实施例中，物理气相沉积包括溅镀沉积、气相沉积或其它合适的方法。晶种层13可为包含铜、铝、钛、其合金、或其多层组合的金属晶种层。在一些实施例中，晶种层13包括第一金属层(例如，钛层(图中未示出))以及位于第一金属层之上的第二金属层(例如，铜层(图中未示出))。在一些实施例中，此晶种层13为共形层(conformal layer)。也就是说，晶种层13具有沿着上面形成有晶种层13的区域延伸的实质上相等的厚度。
之后，在晶种层13上形成图案化的掩模层14。图案化的掩模层14具有多个开口16。所述多个开口16暴露出部分晶种层13。图案化的掩模层14例如为光刻胶。图案化的掩模层14例如是通过以下步骤形成：首先在晶种层13上形成光刻胶层；并接着对光刻胶层进行曝光及显影工艺。
请继续参照图1A，以例如是电镀或无电电镀的方式，在开口16暴露出的晶种层13上形成导电层15。导电层15例如是由铜或其他合适的金属形成。
请参照图1A及图1B，接着移除图案化的掩模层14，以使得未被导电层15覆盖的晶种层13暴露出来。移除的方式例如是干式剥除(dry strip)法、湿式剥除(wet strip)法或其组合。在一些实施例中，接着利用导电层15作为掩模来移除未被导电层15覆盖的晶种层13，从而形成晶种层13a。在一些实施例中，晶种层13a可用作导电层15的障壁层或黏着层。所述移除方法包括刻蚀工艺，例如干刻蚀、湿刻蚀或其组合。
请参照图1B，晶种层13a与导电层15形成重布线(redistribution line，RDL)层17。在一些实施例中，重布线层17包括多条导电线路(conductive trace)，所述多条导电线路在介电层12上延伸且彼此连接。在另一些实施例中，重布线层17具有多层结构且包括多个通孔(via)以及彼此连接的多条导电线路。在一些实施例中，重布线层17包括重布线17a及重布线17b。具体来说，重布线17a位于重布线17b的两侧。重布线17a及重布线17b的数量可根据产品设计来进行调整。在重布线17a与重布线17b之间存在多个间隙18及18’。在一些实施例中，间隙18存在于相邻的两条重布线17a之间，且间隙18的宽度W0的范围为40μm至500μm。间隙18’存在于相邻的两条重布线17b之间或相邻的重布线17a与重布线17b之间。在一些实施例中，间隙18’的宽度大于间隙18的宽度W0。
请继续参照图1B，在介电层12及重布线层17上形成介电层19(或者称为第二介电层)。介电层19填充在间隙18及18’中，覆盖介电层12、重布线层17的侧壁47以及重布线层17的顶表面24。介电层19可为单层结构或多层结构。在一些实施例中，介电层19的材料包括无机介电材料、有机介电材料或其组合。无机介电材料包括：氮化物(例如氮化硅)、氧化物(例如氧化硅)、氮氧化物(例如氮氧化硅)、磷硅酸盐玻璃、硼硅酸盐玻璃、掺杂有硼的磷硅酸盐玻璃、其类似物或其组合。有机介电材料包括聚合物，所述聚合物可为感光性材料，例如是聚苯并恶唑、聚酰亚胺、苯并环丁烯、味之素构成膜、阻焊膜、其类似物或其组合。介电层19的材料与介电层12的材料可相同或不同。介电层19例如是通过旋转涂布法、叠层法、沉积法等合适的制作技术形成。在一些实施例中，重布线层17与介电层19形成重布线结构21。
请参照图1B及图1C，之后，移除位于间隙18上方的部分介电层19以及位于间隙18中的介电层19，以形成多个凹槽20。移除的方式例如是曝光及显影工艺、激光钻孔工艺、光刻及刻蚀工艺或其组合。凹槽20穿过重布线结构21，暴露出两条相邻的重布线17a的部分顶表面24和侧壁47，以及介电层12的部分顶表面。
在一些实施例中，凹槽20包括在空间上彼此连通的第一凹槽20a及第二凹槽20b。第一凹槽20a位于第二凹槽20b之上，即，第一凹槽20a与第二凹槽20b是交叠的。第一凹槽20a的宽度大于第二凹槽20b的宽度。第一凹槽20a位于两条相邻的重布线17a之上，暴露出重布线17a的部分顶表面24。第二凹槽20b位于两条相邻的重布线17a之间，暴露出重布线17a的侧壁47以及介电层12的顶表面。
在一些实施例中，凹槽20具有阶梯形状，凹槽20的横截面形状为T型或类似漏斗状，但本发明并非仅限于此。第一凹槽20a的侧壁(即，介电层19的侧壁)与介电层19的顶表面19b形成顶角α。顶角α的角度范围为100°至140°。
请参照图1C至图1D，接着在重布线结构21上及介电层12上形成晶种层22。晶种层22的材料及形成方法与图1A所示晶种层13的材料及形成方法实质上相同，将不再对其予以赘述。晶种层22覆盖介电层19的顶表面19b，以及凹槽20的底表面及侧壁。在一些实施例中，晶种层22与重布线17a的部分顶表面24、重布线17a的侧壁47以及介电层12的部分顶表面接触。晶种层22的底表面与重布线17a的晶种层13a的底表面实质上齐平。
请参照图1D，在晶种层22上形成图案化的掩模层23。图案化的掩模层23具有多个开口25。开口25暴露出位于凹槽20中的晶种层22以及覆盖介电层19的顶角α的晶种层22。
请继续参照图1D，在图案化的掩模层23的开口25暴露出的晶种层22上形成多个导电柱26。导电柱26设置在凹槽20中，且凸出于介电层19的顶表面19b。导电柱26可为铜柱或任意其他适合的金属柱。用语“铜柱”是指铜凸出部、铜穿孔、厚铜接垫及/或含铜凸出部。全文中，用语“铜”旨在包括实质上纯的元素铜、含有不可避免的杂质的铜、或含有微量的例如钽、铟、锡、锌、锰、铬、钛、锗、锶、铂、镁、铝或锆等元素的铜合金等。导电柱26是例如通过电镀形成。
请参照图1D及图1E，接着移除图案化的掩模层23，以使得未被导电柱26覆盖的晶种层22暴露出来。接着利用导电柱26作为掩模，以移除未被导电柱26覆盖的晶种层22，从而形成晶种层22a。在一些实施例中，晶种层22a可用作导电柱26的障壁层或黏着层。所述移除方法包括刻蚀工艺，例如干刻蚀、湿刻蚀或其组合。
请参照图1E，晶种层22a及其上覆的导电柱26形成多个集成扇出型穿孔(throughintegrated fan-out via，TIV)27。集成扇出型穿孔27的数目并非仅限于图1E所示的数目，而是可根据需要进行调整。集成扇出型穿孔27设置在凹槽20中，且凸出于介电层19的顶表面19b。集成扇出型穿孔27穿过重布线结构21，且与介电层12接触。换句话说，集成扇出型穿孔27与重布线结构21啮合。另外，集成扇出型穿孔27与两条相邻的重布线17a的部分顶表面24以及侧壁47电性接触。
请继续参照图1E，在一些实施例中，集成扇出型穿孔27的末端(即，集成扇出型穿孔27的底部)具有阶梯形状，且与重布线结构21啮合。具体来说，导电柱26的一个末端及晶种层22a具有阶梯形状。导电柱26的部分侧壁及底部被晶种层22a覆盖。集成扇出型穿孔27的另一个末端(即，导电柱26的另一个末端)是平坦的。集成扇出型穿孔27自下而上包括彼此电性接触的第一嵌入部27a、第二嵌入部27b及凸出部27c。第一嵌入部27a及第二嵌入部27b位于凹槽20中。凸出部27c位于重布线结构21之上，凸出于介电层19的顶表面19b。
具体来说，第一嵌入部27a位于两条相邻的重布线17a之间且与重布线17a的侧壁47电性接触。第一嵌入部27a的顶表面与重布线17a的顶表面24实质上齐平；第一嵌入部27a的底表面与重布线17a的底表面实质上齐平且与介电层12接触。第二嵌入部27b位于第一嵌入部27a上以及两条相邻的重布线17a上，以与两条相邻的重布线17a的部分顶表面24电性接触。在一些实施例中，第一嵌入部27a的横截面形状是正方形或矩形。第二嵌入部27b的横截面形状是倒梯形或矩形。第一嵌入部27a与第二嵌入部27b整体的横截面形状为T型或类似漏斗状。在一些实施例中，第二嵌入部27b的底面宽度W2等于或大于第一嵌入部27a的顶面宽度W1，以使得集成扇出型穿孔的底部具有阶梯形状。在一些示例性实施例中，第二嵌入部27b的底面宽度W2的范围为50μm至510μm，第一嵌入部37a的顶面宽度W1实质上等于间隙18(图1B所示)的宽度W0，且其范围为40μm至500μm。
凸出部27c位于第二嵌入部27b上。在一些实施例中，凸出部27c覆盖第二嵌入部27b的顶表面以及部分介电层19的顶表面19b。也就是说，介电层19的顶角α被集成扇出型穿孔27覆盖，但本发明并非仅限于此。在另一些实施例中，凸出部27c仅覆盖第二嵌入部27b的顶表面而不覆盖介电层19的顶表面19b(图中未示出)。在一些实施例中，凸出部27c的横截面形状是矩形或梯形，但本发明并非仅限于此。
请参照图1F，通过黏着膜28(例如，管芯贴合膜(die attach film，DAF))将管芯(die)34贴附于介电层19，并将管芯34设置在集成扇出型穿孔27之间。管芯34包括衬底29、多个接垫30、钝化层31、多个连接件32及钝化层33。接垫30可为内连结构(图中未示出)的一部分，且与形成在衬底29上的集成电路装置(图中未示出)电性连接。钝化层31形成在衬底29之上，且覆盖接垫30的一部分。接垫30的一部分被钝化层31暴露出且作为管芯34的外部连接。连接件32形成在未被钝化层31覆盖的接垫30上，且与未被钝化层31覆盖的接垫30电性连接。连接件32包括焊料凸块、金凸块、铜凸块、铜柱等。钝化层33形成在钝化层31之上及连接件32的侧边，以覆盖连接件32的侧壁。钝化层31及33分别包含绝缘材料，例如氧化硅、氮化硅、聚合物或其组合。在一些实施例中，钝化层33的的顶表面与连接件32的顶表面实质上齐平。
在一些实施例中，管芯34例如是从晶片(wafer)切割下来的多个管芯中的一个。管芯34可为专用集成电路(application-specific integrated circuit，ASIC)芯片、模拟芯片(analog chip)、传感器芯片(sensor chip)、无线射频芯片(wireless and radiofrequency chip)、电压调节器芯片(voltage regulator chip)或存储器芯片(memorychip)。图1F所示管芯34的数目仅用于例示说明，且本发明并非仅限于此。在一些实施例中，在介电层19上可安装两个或更多个管芯34，所述两个或更多个管芯34可为相同类型的管芯或不同类型的管芯。在另一些实施例中，将包括以阵列形式排列的多个管芯34的晶片(图中未示出)安装到介电层19上，且管芯34被集成扇出型穿孔27环绕。
接着在载板10上形成封装体35，以囊封(encapsulate)管芯34的侧壁以及集成扇出型穿孔27的凸出部27c。在一些实施例中，封装体35包含模塑化合物(moldingcompound)、模塑底部填充料(molding underfill)、树脂(例如环氧树脂)、其组合或类似物。在另一些实施例中，封装体35包括可容易地通过曝光及显影工艺被图案化的感光性材料，例如聚苯并恶唑、聚酰亚胺、苯并环丁烯、其组合或类似物。在替代实施例中，封装体35包含氮化物(例如氮化硅)、氧化物(例如氧化硅)、磷硅酸盐玻璃、硼硅酸盐玻璃、掺杂硼的磷硅酸盐玻璃、其组合或类似物。封装体35是通过以下步骤形成：通过例如旋转涂布法、叠层法、沉积法或类似的工艺等合适的制作技术，在载板10之上形成封装材料层。封装材料层囊封管芯34的顶表面及侧壁以及集成扇出型穿孔27的凸出部27c的顶表面及侧壁。之后，进行研磨或抛光工艺，以移除部分封装材料层，使得连接件32的顶表面及集成扇出型穿孔27的顶表面暴露出来。在一些实施例中，连接件32的顶表面、集成扇出型穿孔27的顶表面以及封装体35的顶表面实质上共面。
请参照图1G，在管芯34、集成扇出型穿孔27以及封装体35上形成第一介电层36。第一介电层36可为单层结构或多层结构。第一介电层36具有多个开口37，开口37暴露出部分集成扇出型穿孔27以及管芯34的部分连接件32。第一介电层36的材料与介电层12及介电层19的材料相似。第一介电层36通过以下步骤形成：首先形成第一介电材料层(图中未示出)，以覆盖管芯34、封装体35及集成扇出型穿孔27。之后，移除位于集成扇出型穿孔27上以及位于连接件32上的部分介电材料层，以形成具有开口37的第一介电层36。移除的方式例如是曝光及显影工艺、激光钻孔工艺、光刻及刻蚀工艺或其组合。
请继续参照图1G，在第一介电层36上形成晶种层38，且晶种层38填充于开口37中，以覆盖开口37的底表面及侧壁。晶种层38在开口37的底部处与集成扇出型穿孔27及连接件32电性接触。晶种层38的材料及形成方法与图1A所示晶种层13的材料及形成方法相似。
请参照图1H，在晶种层38上形成图案化的掩模层39。图案化的掩模层39具有多个开口40，开口40暴露出开口37中的晶种层38以及第一介电层36上的部分晶种层38。接着，在开口40暴露出的晶种层38上形成导电层41。导电层41填充到开口37中，且凸出于第一介电层36的顶表面，并覆盖第一介电层36的部分顶表面。
请参照图1H及图1I，接着移除图案化的掩模层39，以使得未被导电层41覆盖的晶种层38暴露出来。接着利用导电层41作为掩模，以移除未被导电层41覆盖的晶种层38，从而形成晶种层38a。所述移除方法包括刻蚀工艺，例如，干刻蚀、湿刻蚀或其组合。
请参照图1I，晶种层38a与导电层41形成重布线层42。在一些实施例中，重布线层42与集成扇出型穿孔27以及管芯34的连接件32接触并电性连接。在一些实施例中，重布线层42包括多个通孔42a及多条导电线路42b。通孔42a穿过第一介电层36，与集成扇出型穿孔27及连接件32接触。导电线路42b在第一介电层36上延伸，且与通孔42a连接。之后，在重布线层42上形成第二介电层43，以覆盖重布线层42的顶表面及侧壁。第二介电层43的材料及形成方法与介电层12的材料及形成方法相似，将不再对其予以赘述。
第一介电层36、重布线层42以及第二介电层43形成重布线结构44。重布线结构44的重布线层42的层数并非仅限于图1I所示，而是可根据需要进行调整。重布线结构44可具有一层或多层重布线层42。在重布线结构44具有多于一层重布线层42的一些实施例中，重布线结构44包括多个堆叠的介电层36及43，以及重布线层42(图中未示出)。重布线结构44的多层结构的形成方法例如是在形成第二介电层43之后，重复进行上述图1G至图1I的工艺，以形成多层重布线层42。
请继续参照图1I，重布线结构44是设置在管芯34的前侧(靠近连接件32的一侧，即，靠近管芯34的有源表面的一侧)，重布线结构21是设置在管芯34的背侧(与前侧相对的一侧)。因此，在一些实施例中，重布线结构21被称为背侧重布线结构，而重布线结构44被称为前侧重布线结构。
请参照图1I及图1J，将在图1I中形成的结构翻转，使离型层11在光热作用下分解，且接着将载板10从载板10的上覆结构脱离。
请继续参照图1J及图1K，移除部分介电层12、部分晶种层13a以及集成扇出型穿孔27顶部的晶种层22a，以形成多个开口45a。开口45a穿过重布线结构21的介电层12以及重布线17a的晶种层13a。另外，移除位于重布线17b上的部分介电层12及其下方的晶种层13a，以形成多个开口45b。开口45b穿过介电层12以及重布线17b的晶种层13a。所述移除方法例如是包括激光钻孔工艺。重布线层17的晶种层13b以及集成扇出型穿孔27的晶种层22b留下来。导电柱26的部分侧壁被晶种层22b覆盖。导电柱26与介电层19被位于两者之间的晶种层22b隔开。开口45a的底部暴露出集成扇出型穿孔27的晶种层22b及导电柱26，以及重布线17a的导电层15的部分顶表面。开口45a的侧壁暴露出重布线17a的晶种层13b以及介电层12。开口45a的宽度可进行调整，只要开口45a的底部至少暴露出部分导电柱26即可。开口45b的底部暴露出重布线17b的导电层15。开口45b的侧壁暴露出介电层12以及重布线17b的晶种层13b。在一些晶种层13(图1A所示)与晶种层22(图1D所示)形成为同一厚度的实施例中，导电柱26的顶表面及晶种层22b的顶表面与导电层15的顶表面(与晶种层13b接触的表面)实质上共面，但本发明并非仅限于此。
请参照图1K及图1L，分别在集成扇出型穿孔27上及重布线17b上形成多个连接件46a及46b。连接件46a及46b又可称为导电端子。在一些实施例中，连接件46a及46b可覆盖介电层12的部分顶表面。在另一些实施例中，连接件46a及46b可不覆盖介电层12的顶表面。连接件46a与46b可同时形成或先后形成。连接件46a填充于开口45a中，且穿过介电层12以及重布线17a的晶种层13b。连接件46a的底部与集成扇出型穿孔27的导电柱26及晶种层22b，以及重布线17a的导电层15电性接触。连接件46a的侧壁与重布线17a的晶种层13b以及介电层12接触。连接件46b填充于开口45b中，以使得连接件46b的底部与重布线17b的导电层15电性接触；而连接件46b的侧壁与重布线17b的晶种层13b以及介电层12接触。连接件46a及46b的材料包括铜、铝、无铅合金(例如，金、锡、银、铝或铜合金)或者铅合金(例如，铅锡合金)。在一些实施例中，连接件46a及46b分别通过植球工艺(ball mounting process)形成。在另一些实施例中，可进行印刷步骤以将焊料(solder paste)印刷到开口45a及45b中，之后对焊料进行回焊，以形成连接件46a及46b。或者，将焊球滴入开口45a及45b中，并接着进行回焊工艺，以形成连接件46a及46b。在一些实施例中，更包括在形成连接件46a及46b之前，形成球下金属(under-ball metallurgy，UBM)层(图中未示出)。球下金属层填充于开口45a及45b中，覆盖开口45a及45b的底部及侧壁以及部分介电层12。
请继续参照图1L，至此，封装结构50a即已完成。封装结构50a包括管芯34、重布线结构21、集成扇出型穿孔27、重布线结构44以及连接件46a及46b。集成扇出型穿孔27穿过重布线结构21，且与连接件46a电性接触。之后，封装结构50a可通过连接件46a及46b连接到其他封装组件，例如印刷电路板(printed circuit board，PCB)、柔性印刷电路板或类似物。在前述工艺中将包括多个管芯34的晶片形成在载板10上的一些实施例中，在连接到其他封装组件之前，可通过管芯切割工艺(die-saw process)将封装结构(图中未示出)单体化，以形成多个相同的如图1L所示的封装结构50a。
图2A至图2C是说明根据本揭露第二实施例的形成封装结构的方法的示意性剖视图。第二实施例与第一实施例的不同之处在于，进一步形成了连接件63，以与管芯34上的重布线结构144连接，并形成叠层封装(package-on-package，POP)装置。详细说明如下。
请参照图1I及图2A，在一些实施例中，重布线结构144包括交替堆叠的多个重布线层42/61以及介电层36/43/60，且重布线层42被称为第一重布线层42。在一些实施例中，在如图1I所示形成第一介电层36、第一重布线层42、及第二介电层43之后，进行与图1G至图1I中所述工艺相似的工艺，从而形成第二重布线层61及第三介电层60。第二重布线层61穿过第二介电层43，以与第一重布线层42连接。第二重布线层61及第三介电层60的材料、形成方法及结构特性与第一重布线层42及第二介电层43的材料、形成方法及结构特性相似，将不再对其予以赘述。
之后，形成导电层62，其穿过第三介电层60，与第二重布线层61连接。在一些实施例中，导电层62被称为球下金属(UBM)层。导电层62的材料包括金属或金属合金。导电层62例如是铜、锡、其合金或其组合。导电层62例如是通过物理气相沉积或电镀形成。
请继续参照图2A，将多个连接件(也称为导电球)63置于导电层62上。连接件63的材料包括铜、铝、无铅合金(例如，金、锡、银、铝或铜合金)或者铅合金(例如，铅锡合金)。在一些实施例中，连接件63是通过植球工艺被置于导电层62上。连接件63通过导电层62及重布线结构144与连接件32电性连接。
请参照图2A及图2B，接着进行与图1J至图1L中所述工艺相似的工艺，将图2A中所形成的结构翻转，使离型层11分解，且接着将载板10从其上覆结构脱离。
请参照图2B，形成多个开口45a及45b。之后，形成多个连接件46a。连接件46a穿过介电层12以及重布线17a的晶种层13b，与集成扇出型穿孔27及重布线17a电性接触。形成多个连接件46b。连接件46b穿过介电层12，与重布线17b电性接触。连接件46a与46b可同时形成或先后形成。开口45a及45b以及连接件46a及46b的形成方法及结构特性与第一实施例中的开口45a及45b以及连接件46a及46b的形成方法及结构特性实质上相同，将不再对其予以赘述。
至此，封装结构50b即已完成。在一些实施例中，封装结构50b可进一步电耦合至封装结构70，以形成叠层封装装置，但本发明并非仅限于此。
请参照图2C，在一些实施例中，封装结构70具有衬底71以及安装在衬底71的一个表面(例如，顶表面)上的管芯72。结合导线(bonding wires)73可用于提供管芯72与位于衬底71的相同顶表面的接垫74(例如，结合接垫(bonding pads))之间的电性连接。集成扇出型穿孔(图中未示出)可用于提供接垫74与位于衬底71相对表面(例如，底表面)上的接垫75(例如，结合接垫)之间的电性连接。连接件46a及46b连接接垫75，并与封装结构50b电性连接。在上述结构上方形成封装体77，以保护上述构件不受环境及外部污染物的影响。
之后，形成底部填充层(under-fill layer)48，填充于封装结构50b与封装结构70之间，并环绕连接件46a及46b。在一些实施例中，底部填充层48包括模塑化合物(例如，环氧树脂)，且可通过点胶(dispensing)、注射(injecting)及/或喷射(spraying)技术形成。
图3A至图3F是说明根据本揭露一些实施例的形成封装结构的方法的示意性剖视图。
在前述实施例中，如图1L及图2B所示，集成扇出型穿孔27穿过重布线结构21以与连接件46a电性接触，且集成扇出型穿孔27及连接件46a也与重布线17a的导电层15以及晶种层13b电性接触。请参照图3A至图3F，在一些实施例中，可存在一些集成扇出型穿孔127，其未与重布线117a接触，而是与重布线117a之间通过介电层19隔开，且连接件46a也不与重布线117a接触。为简洁起见，图3A至图3E仅示出重布线117a、集成扇出型穿孔127、封装体35及连接件146a。
请参照图1B、图3A及图3B，重布线结构21还包括重布线117a，且间隙118存在于相邻两条重布线117a之间。移除位于间隙118内的部分介电层19，从而形成穿过介电层19的凹槽120。凹槽120位于相邻的两条重布线117a之间。在一些实施例中，凹槽120的底部暴露出介电层12的部分顶表面。由于间隙118中的介电层19是被部分地移除，因而凹槽120并未暴露出重布线117a。在一些实施例中，凹槽120的横截面形状可为倒梯形、正方形、矩形或其他任意形状，只要重布线117a的表面被介电层19覆盖即可。之后，在介电层19上形成晶种层122。
请参照图3B至图3D，进行与图1D至图1E中所述工艺相似的工艺，以形成集成扇出型穿孔127。集成扇出型穿孔127包括导电柱126及晶种层122a，其材料及形成方法与集成扇出型穿孔27的材料及形成方法实质上相同，将不再对其予以赘述。集成扇出型穿孔127穿过重布线结构21且与介电层12接触。集成扇出型穿孔127与前述实施例的集成扇出型穿孔27的不同之处在于，集成扇出型穿孔127不与重布线117a电性接触，而是与重布线117a之间通过介电层19隔开。在一些实施例中，集成扇出型穿孔127包括嵌入部127a及凸出部127b。嵌入部127a位于凹槽120中，且嵌入部127a的顶表面与介电层19的顶表面19b实质上齐平。在一些实施例中，嵌入部127a的横截面形状可为倒梯形、正方形或矩形，但本发明并非仅限于此。在一些嵌入部127a具有倒梯形横截面形状的实施例中，嵌入部127a的顶面宽度W12小于图3A所示间隙118的宽度W11。凸出部127b位于嵌入部127a上，且凸出于介电层19的顶表面19b。凸出部127b的其他结构特性与图1E所示集成扇出型穿孔27相似。
请参照图1J、图3D及图3E，在载板10脱离之后，移除部分介电层以及覆盖导电柱126顶表面的晶种层122a，从而形成穿过介电层12的开口145a，且留下集成扇出型穿孔127的晶种层122b。嵌入部127a的部分侧壁被晶种层122b覆盖，嵌入部127a的顶表面被开口145a暴露出来。开口145a的宽度可进行调整，只要开口145a的底部至少暴露出部分导电柱126即可。
导电柱126与介电层19被位于两者之间的晶种层122b隔开。在一些实施例中，晶种层122b的横截面形状是L型或线形的，但本发明并非仅限于此。
在一些实施例中，开口145a的横截面形状例如是倒梯形或矩形，但本发明并非仅限于此。开口145a的底部暴露出集成扇出型穿孔127的导电柱126以及晶种层122b。在一些实施例中，导电柱126的顶表面及晶种层122b的顶表面与重布线117a的导电层15实质上共面。请参照图3F，在集成扇出型穿孔127上形成连接件146a。连接件146a可被称为导电端子。连接件146a穿过介电层12，且连接件146a的底部与集成扇出型穿孔127的导电柱126及晶种层122b电性接触。连接件146a与重布线117a被位于两者之间的介电层19隔开。
在本发明的一些实施例中，集成扇出型穿孔被设置成穿过重布线结构，以与连接件接触并电性连接，由此可避免由晶种层或障壁层或者黏着层造成的集成扇出型穿孔与重布线结构之间裂开的问题(open issue)。另一方面，由于晶种层是被部分移除，因此仍有部分晶种层设置在集成扇出型穿孔的导电柱与介电层之间，因而也可避免分层(delamination)问题。
根据本发明的一些实施例，提供一种封装结构，其包括管芯、重布线结构、集成扇出型穿孔及第一连接件。重布线结构与管芯连接且包括多个重布线。集成扇出型穿孔位于管芯侧边且穿过重布线结构。第一连接件与集成扇出型穿孔电性接触，且与管芯电性连接。集成扇出型穿孔与重布线结构的重布线电性接触。
在上述封装结构中，集成扇出型穿孔包括第一晶种层及导电柱，且导电柱与第一连接件电性接触。
在上述封装结构中，导电柱的部分侧壁被第一晶种层覆盖。
在上述封装结构中，集成扇出型穿孔的末端具有阶梯形状。
在上述封装结构中，第一晶种层及所述导电柱的末端具有阶梯形状。
在上述封装结构中，重布线包括第二晶种层及导电层。
在上述封装结构中，第一连接件的底表面与集成扇出型穿孔的第一晶种层及导电柱以及重布线的导电层电性接触，第一连接件的侧壁与重布线的第二晶种层电性接触。
在上述封装结构中，进一步包括设置在管芯上的第二连接件，其中第二连接件穿过重布线中的一者的第二晶种层，且与重布线中的所述一者的导电层接触。
根据本发明的替代实施例，提供一种封装结构，其包括管芯、重布线结构、集成扇出型穿孔以及连接件。重布线结构与管芯连接。集成扇出型穿孔位于管芯侧边且穿过重布线结构。连接件与集成扇出型穿孔电性接触，且与管芯电性连接。
在上述封装结构中，重布线结构包括介电层及多条重布线，且集成扇出型穿孔与重布线被位于两者之间的介电层隔开。
在上述封装结构中，集成扇出型穿孔包括晶种层及导电柱，其中导电柱的部分侧壁被晶种层覆盖。
在上述封装结构中，连接件与集成扇出型穿孔的导电柱电性接触。
在上述封装结构中，连接件与重布线被重布线结构的介电层隔开。
在上述封装结构中，集成扇出型穿孔包括嵌入部及凸出部，其中嵌入部设置在重布线之间，凸出部位于所述管芯侧边且位于封装体中。
根据本发明的一些实施例，提供一种制造封装结构的方法。对所述方法阐述如下。在第一介电层上形成重布线结构。将管芯贴附于重布线结构上。在管芯侧边形成集成扇出型穿孔。集成扇出型穿孔穿透重布线结构。形成连接件，与集成扇出型穿孔电性接触。
在上述制造封装结构的方法中，形成重布线结构包括：在第一介电层上形成多条重布线，以及在所述重布线上形成第二介电层。在形成集成扇出型穿孔之前，移除部分第二介电层，以形成穿过重布线结构的凹槽，其中凹槽的底部暴露出第一介电层，且集成扇出型穿孔形成于凹槽中并凸出于第二介电层的顶表面。
在上述制造封装结构的方法中，凹槽进一步暴露出重布线的侧壁以及重布线的部分顶表面，使得集成扇出型穿孔与重布线的侧壁及重布线的部分顶表面电性接触。
在上述制造封装结构的方法中，凹槽被形成为具有阶梯形状。
在上述制造封装结构的方法中，凹槽没有暴露出重布线，使得集成扇出型穿孔与重布线被位于集成扇出型穿孔与重布线之间的第二介电层隔开。
在上述制造封装结构的方法中，形成集成扇出型穿孔包括形成晶种层以及在所述晶种层上形成导电柱，以及在形成第一连接件之前，移除集成扇出型穿孔的部分晶种层，使得第一连接件与集成扇出型穿孔的导电柱及晶种层接触。
以上概述了若干实施例的特征，以使本领域技术人员可更好地理解本揭露的各个方面。本领域技术人员应理解，其可容易地使用本揭露作为设计或修改其他工艺及结构的依据，来实现与本文中所介绍的实施例相同的目的及/或达到相同的优点。本领领域技术人员还应理解，这些等效的配置并不悖离本揭露的精神及范畴，且本领域技术人员在不悖离本揭露的精神及范畴的情况下可对本文作出各种改变、置换及变更。

Claims (1)

1.一种封装结构，其特征在于，包括：
管芯；
重布线结构，与所述管芯连接，其中所述重布线结构包括多条重布线；
集成扇出型穿孔，位于所述管芯侧边且穿过所述重布线结构；以及
第一连接件，与所述集成扇出型穿孔电性接触，且与所述管芯电性连接，
其中所述集成扇出型穿孔与所述重布线结构的所述重布线电性接触。
CN201711017344.3A 2017-09-18 2017-10-26 封装结构及其制造方法 Active CN109524378B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15/706,783 US10510631B2 (en) 2017-09-18 2017-09-18 Fan out package structure and method of manufacturing the same
US15/706,783 2017-09-18

Publications (2)

Publication Number Publication Date
CN109524378A true CN109524378A (zh) 2019-03-26
CN109524378B CN109524378B (zh) 2023-05-23

Family

ID=65721111

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201711017344.3A Active CN109524378B (zh) 2017-09-18 2017-10-26 封装结构及其制造方法

Country Status (3)

Country Link
US (3) US10510631B2 (zh)
CN (1) CN109524378B (zh)
TW (1) TWI721225B (zh)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10269773B1 (en) * 2017-09-29 2019-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages and methods of forming the same
US10573573B2 (en) * 2018-03-20 2020-02-25 Taiwan Semiconductor Manufacturing Co., Ltd. Package and package-on-package structure having elliptical conductive columns
US11139247B2 (en) * 2019-03-14 2021-10-05 Advanced Semiconductor Engineering, Inc. Interconnection structure, semiconductor package and method of manufacturing the same
US10886223B2 (en) * 2019-06-03 2021-01-05 Advanced Semiconductor Engineering, Inc. Semiconductor package
US11189484B2 (en) * 2019-12-20 2021-11-30 Micron Technology, Inc. Semiconductor nitridation passivation
US11462418B2 (en) * 2020-01-17 2022-10-04 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit package and method
DE102021107672A1 (de) * 2020-04-07 2021-10-07 Mediatek Inc. Halbleiter-package-struktur
US11670596B2 (en) 2020-04-07 2023-06-06 Mediatek Inc. Semiconductor package structure
TWI742991B (zh) * 2021-01-20 2021-10-11 啟耀光電股份有限公司 基板結構與電子裝置
CN113347799A (zh) * 2021-06-04 2021-09-03 珠海中京电子电路有限公司 MiniLED板的制备方法
US11967547B2 (en) * 2021-08-26 2024-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Solder resist structure to mitigate solder bridge risk

Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20090010442A (ko) * 2007-07-23 2009-01-30 주식회사 동부하이텍 시스템 인 패키지 및 그 제조 방법
US20100072588A1 (en) * 2008-09-25 2010-03-25 Wen-Kun Yang Substrate structure with die embedded inside and dual build-up layers over both side surfaces and method of the same
US20140131858A1 (en) * 2012-11-14 2014-05-15 Taiwan Semiconductor Manufacturing Company, Ltd. Warpage Control of Semiconductor Die Package
US20140211438A1 (en) * 2013-01-25 2014-07-31 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and Apparatus for Transmission Lines in Packages
CN104134641A (zh) * 2013-05-03 2014-11-05 矽品精密工业股份有限公司 半导体封装件及其制法
US20150303174A1 (en) * 2014-04-17 2015-10-22 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-Out Stacked System in Package (SIP) and the Methods of Making the Same
TW201545305A (zh) * 2014-05-29 2015-12-01 台灣積體電路製造股份有限公司 用於封裝的對準標記設計
CN106469661A (zh) * 2015-08-21 2017-03-01 台湾积体电路制造股份有限公司 封装结构及其形成方法
CN106876363A (zh) * 2017-03-13 2017-06-20 江苏长电科技股份有限公司 3d连接的扇出型封装结构及其工艺方法
CN107104058A (zh) * 2017-06-21 2017-08-29 中芯长电半导体（江阴）有限公司 扇出型单裸片封装结构及其制备方法
CN107408547A (zh) * 2015-03-03 2017-11-28 苹果公司 扇出型系统级封装件及其形成方法

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8106504B2 (en) * 2008-09-25 2012-01-31 King Dragon International Inc. Stacking package structure with chip embedded inside and die having through silicon via and method of the same
US9048233B2 (en) 2010-05-26 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Package systems having interposers
US8797057B2 (en) 2011-02-11 2014-08-05 Taiwan Semiconductor Manufacturing Company, Ltd. Testing of semiconductor chips with microbumps
US8466544B2 (en) * 2011-02-25 2013-06-18 Stats Chippac, Ltd. Semiconductor device and method of forming interposer and opposing build-up interconnect structure with connecting conductive TMV for electrical interconnect of Fo-WLCSP
US9000584B2 (en) 2011-12-28 2015-04-07 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor device with a molding compound and a method of forming the same
US9111949B2 (en) 2012-04-09 2015-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus of wafer level package for heterogeneous integration technology
US20130307153A1 (en) 2012-05-18 2013-11-21 International Business Machines Corporation Interconnect with titanium-oxide diffusion barrier
KR101971279B1 (ko) * 2012-08-30 2019-04-22 에스케이하이닉스 주식회사 범프 구조물 및 그 형성 방법
US9263511B2 (en) 2013-02-11 2016-02-16 Taiwan Semiconductor Manufacturing Co., Ltd. Package with metal-insulator-metal capacitor and method of manufacturing the same
US9048222B2 (en) 2013-03-06 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating interconnect structure for package-on-package devices
US9368460B2 (en) 2013-03-15 2016-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out interconnect structure and method for forming same
US9252065B2 (en) * 2013-11-22 2016-02-02 Taiwan Semiconductor Manufacturing Co., Ltd. Mechanisms for forming package structure
US9281254B2 (en) 2014-02-13 2016-03-08 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming integrated circuit package
US9496189B2 (en) 2014-06-13 2016-11-15 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked semiconductor devices and methods of forming same
US9449914B2 (en) * 2014-07-17 2016-09-20 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked integrated circuits with redistribution lines
US9793243B2 (en) * 2014-08-13 2017-10-17 Taiwan Semiconductor Manufacturing Company, Ltd. Buffer layer(s) on a stacked structure having a via
US10325853B2 (en) * 2014-12-03 2019-06-18 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming semiconductor packages having through package vias

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20090010442A (ko) * 2007-07-23 2009-01-30 주식회사 동부하이텍 시스템 인 패키지 및 그 제조 방법
US20100072588A1 (en) * 2008-09-25 2010-03-25 Wen-Kun Yang Substrate structure with die embedded inside and dual build-up layers over both side surfaces and method of the same
US20140131858A1 (en) * 2012-11-14 2014-05-15 Taiwan Semiconductor Manufacturing Company, Ltd. Warpage Control of Semiconductor Die Package
US20140211438A1 (en) * 2013-01-25 2014-07-31 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and Apparatus for Transmission Lines in Packages
CN104134641A (zh) * 2013-05-03 2014-11-05 矽品精密工业股份有限公司 半导体封装件及其制法
US20150303174A1 (en) * 2014-04-17 2015-10-22 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-Out Stacked System in Package (SIP) and the Methods of Making the Same
TW201545305A (zh) * 2014-05-29 2015-12-01 台灣積體電路製造股份有限公司 用於封裝的對準標記設計
CN107408547A (zh) * 2015-03-03 2017-11-28 苹果公司 扇出型系统级封装件及其形成方法
CN106469661A (zh) * 2015-08-21 2017-03-01 台湾积体电路制造股份有限公司 封装结构及其形成方法
CN106876363A (zh) * 2017-03-13 2017-06-20 江苏长电科技股份有限公司 3d连接的扇出型封装结构及其工艺方法
CN107104058A (zh) * 2017-06-21 2017-08-29 中芯长电半导体（江阴）有限公司 扇出型单裸片封装结构及其制备方法

Also Published As

Publication number Publication date
US20190088564A1 (en) 2019-03-21
US10510631B2 (en) 2019-12-17
US11309225B2 (en) 2022-04-19
CN109524378B (zh) 2023-05-23
TWI721225B (zh) 2021-03-11
US20220238406A1 (en) 2022-07-28
TW201916305A (zh) 2019-04-16
US20200118900A1 (en) 2020-04-16

Similar Documents

Publication Publication Date Title
CN109524378A (zh) 封装结构
US11955459B2 (en) Package structure
CN109309073B (zh) 封装结构及其形成方法
KR101803612B1 (ko) 3ｄ 패키지 구조 및 그 형성 방법
US8502376B2 (en) Wirebondless wafer level package with plated bumps and interconnects
US9059186B2 (en) Embedded semiconductor die package and method of making the same using metal frame carrier
US20200118993A1 (en) Semiconductor package and method of manufacturing the semiconductor package
KR20180106791A (ko) 반도체 장치 및 그 제조 방법
US10290610B2 (en) PoP device and method of forming the same
US20200006274A1 (en) Semiconductor package and manufacturing method thereof
US10790212B2 (en) Method of manufacturing package structure
KR101496996B1 (ko) 반도체 패키지
CN109585410A (zh) 封装结构
KR20210015648A (ko) 반도체 디바이스 및 반도체 디바이스의 제조 방법
US11398455B2 (en) Semiconductor devices and related methods
US11961775B2 (en) Semiconductor devices and related methods
KR20220034698A (ko) 반도체 디바이스 및 관련 방법
CN114420574A (zh) 一种柔性封装构件及其形成方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant