TW201906126A - 半導體裝置 - Google Patents

半導體裝置 Download PDF

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Publication number
TW201906126A
TW201906126A TW106142596A TW106142596A TW201906126A TW 201906126 A TW201906126 A TW 201906126A TW 106142596 A TW106142596 A TW 106142596A TW 106142596 A TW106142596 A TW 106142596A TW 201906126 A TW201906126 A TW 201906126A
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Taiwan
Prior art keywords
conductive
recess
bump
sacrificial layer
layer
Prior art date
Application number
TW106142596A
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English (en)
Inventor
吳勝郁
陳清暉
李明機
吳凱第
郭建鴻
王肇儀
黃宏麟
王子中
邱俊貿
Original Assignee
台灣積體電路製造股份有限公司
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Publication of TW201906126A publication Critical patent/TW201906126A/zh

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Abstract

一種半導體裝置包括半導體基板。墊區域(pad region)設置於半導體基板上。微凸塊設置於墊區域上。微凸塊(micro bump)具有在墊區域上之第一部分及在第一部分上之第二部分。第一部分與第二部分具有不同寬度。第一部分具有第一寬度並且第二部分具有第二寬度。第一寬度大於或小於第二寬度。微凸塊包括鎳及金。半導體裝置亦包括覆蓋墊區域之一部分的鈍化層。

Description

半導體裝置
本發明實施例係關於半導體元件，更具體關於具有凸塊的半導體元件。
現代積體電路係由數以百萬計主動及/或被動裝置(諸如電晶體及電容器)構成。此等裝置最初彼此隔離，但隨後互連在一起以形成功能電路(functional circuits)。一般互連結構包括橫向互連(諸如金屬線(接線))及垂直互連(諸如通孔及接觸)。互連越來越決定現代積體電路之效能及密度之限制。在互連結構之頂部，凸塊形成並且暴露在對應晶片的表面上。電性連接經由凸塊構成，以連接晶片與另一元件。
根據本揭露的一態樣，半導體裝置包含半導體基板、導電墊、導電凸塊、導電帽以及至少一個鈍化層。導電墊位於半導體基板上方。導電凸塊位於導電墊上方。導電帽位於導電凸塊上方，其中導電凸塊與導電帽的組合具有階梯側壁輪廓。鈍化層位於導電基板上方，並且圍繞導電凸塊。
10‧‧‧半導體基板
12‧‧‧導電區域
14‧‧‧鈍化層
16‧‧‧第一犧牲層
17a‧‧‧第一凹陷
17b‧‧‧第一凹陷
17c‧‧‧第一凹陷
17d‧‧‧第一凹陷
17e‧‧‧第一凹陷
17f‧‧‧第一凹陷
19a‧‧‧第二凹陷
19b‧‧‧第二凹陷
19c‧‧‧第二凹陷
19d‧‧‧第二凹陷
19e‧‧‧第二凹陷
19f‧‧‧第二凹陷
20a‧‧‧微凸塊
20c‧‧‧微凸塊
20d‧‧‧微凸塊
20e‧‧‧微凸塊
20f‧‧‧微凸塊
21‧‧‧第三凹陷
22‧‧‧導電凸塊
22a‧‧‧底部
22b‧‧‧頂部
24‧‧‧導電帽
26‧‧‧第二犧牲層
60‧‧‧基板
62‧‧‧導電墊
64‧‧‧鈍化層
66‧‧‧第一犧牲層
67‧‧‧開口
70‧‧‧微凸塊
70'‧‧‧微凸塊
72‧‧‧導電凸塊
74‧‧‧阻障層
74a‧‧‧阻障層
76‧‧‧導電帽
77‧‧‧第二犧牲層
77a‧‧‧開口
78‧‧‧黏著膜
100‧‧‧方法
110‧‧‧操作
120‧‧‧操作
130‧‧‧操作
140‧‧‧操作
150‧‧‧操作
160‧‧‧操作
600‧‧‧方法
610‧‧‧操作
620‧‧‧操作
630‧‧‧操作
640‧‧‧操作
650‧‧‧操作
660‧‧‧操作
當結合隨附圖式閱讀時，自以下詳細描述將很好地理解本揭露之態樣。應注意，根據工業中的標準實務，各特徵並非按比例繪製。事實上，出於論述清晰之目的，可任意增加或減小各特徵之尺寸。
第1圖係繪示根據本揭示之一些實施例的製造半導體裝置之方法的流程圖；第2圖至第8圖係根據本揭示之一些實施例的於凸塊形成製程中之各個階段的半導體裝置之一部分的橫截面圖；第9圖及第10圖係根據本揭示之一些實施例的於凸塊形成製程之中間階段的半導體裝置之一部分的橫截面圖；第11圖至第20圖係根據本揭示之一些實施例的於凸塊形成製程之中間階段的半導體裝置之一部分的橫截面圖；第21圖至第27圖係根據本揭示之一些實施例的於凸塊形成製程之中間階段的半導體裝置之一部分的橫截面圖；第28圖至第34圖係根據本揭示之一些實施例的於凸塊形成製程之中間階段的半導體裝置之一部分的橫截面圖；第35圖係繪示根據本揭示之一些實施例的製造半導體裝置之方法的流程圖；第36圖至第43圖係根據本揭示之一些實施例的於凸塊形成製程之各個階段的半導體裝置之一部分的橫截面圖；以及 第44圖係根據本揭示之一些實施例的於凸塊形成製程之各個階段的半導體裝置之一部分的橫截面圖。
以下揭示提供了許多不同實施例或實例，以便實施所提供標的之不同特徵。下文描述組件及排列之特定實例以簡化本揭示。當然，此些實例僅為示例且並不意欲為限制性。例如，以下描述中在第二特徵上方或第二特徵上形成第一特徵可包括以直接接觸形成第一特徵及第二特徵的實施例，且亦可包括可在第一特徵與第二特徵之間形成額外特徵以使得第一特徵及第二特徵可不處於直接接觸的實施例。另外，本揭示可在各實例中重複元件符號及/或字母。此重複係出於簡明性及清晰之目的並且本身並不指示所論述之各實施例及/或配置之間的關係。
進一步地，為了便於描述，本文可使用空間相對性術語(諸如「之下」、「下方」、「下部」、「上方」、「上部」及類似者)來描述諸圖中所圖示之一個元件或特徵與另一元件或特徵之關係。除了諸圖所描繪之定向外，空間相對性術語意欲包含使用或操作中裝置之不同定向。設備可經其他方式定向(旋轉90度或處於其他定向)且因此可類似解讀本文所使用之空間相對性描述詞。
參考第1圖，根據本揭示之一些實施例的製造半導體裝置之方法100的流程圖。方法開始於操作110，其中犧牲層在半導體基板上形成。方法繼續至操作120，其中第 一凹陷在犧牲層中形成。隨後，進行操作130。圖案化犧牲層以形成第二凹陷。方法繼續至操作140，其中導電凸塊在第一凹陷及第二凹陷內形成。方法繼續至操作150，其中導電帽在導電凸塊上形成。方法繼續至操作160，其中移除犧牲層。
第2圖至第8圖係根據本揭示之一些實施例的於凸塊形成製程之各個階段的半導體裝置之一部分的橫截面圖。
參考第2圖至第8圖，用於凸塊製造之例示性半導體基板10用在半導體裝置製造中，而且積體電路可在其中及/或其上形成。半導體基板10定義為包括半導體材料之任何構造，諸如主體矽(bulk silicon)、半導體晶圓、絕緣體上矽(silicon-on-insulator,SOI)基板、鍺矽基板或類似者。亦可使用包括第Ⅲ族、第Ⅳ族、及第V族元素之其他半導體材料。基板10可進一步包含複數個隔離特徵(未圖示)，諸如淺溝槽隔離(shallow trench isolation,STI)特徵、矽局部氧化(local oxidation of silicon,LOCOS)特徵或類似者。隔離特徵可限定並隔離各個微電子元件(未圖示)。可在半導體基板10中形成的各個微電子元件之實例，包括電晶體(例如，金氧半場效電晶體(metal oxide semiconductor field effect transistors,MOSFET)、互補式金氧半場效電晶體(complementary metal oxide semiconductor,CMOS)、雙極接面電晶體(bipolar junction transistors,BJT)、高壓電晶體、高頻電晶體、p 通道及/或n通道場效電晶體(PFET/NFET)等)、電阻器、二極體、電容器、感應器、熔斷器、或其他適宜元件。進行各種製程(包括沉積、蝕刻、植入、光微影、退火、或其他適宜製程)以形成各種微電子元件。互連微電子元件以形成積體電路裝置，諸如邏輯裝置、記憶體裝置(例如，靜態隨機存取記憶體(static random access memory,SRAM))、射頻(radio frequency,RF)裝置、輸入/輸出(I/O)裝置、晶片上系統(system-on-chip,SoC)裝置、其組合、或其他適宜類型之裝置。
基板10進一步包括層間介電層及覆蓋積體電路之金屬化結構。層間介電層包括低k介電材料、未摻雜之矽酸鹽玻璃(un-doped silicate glass,USG)、氧化矽、氮化矽、氮氧化矽、或其他適宜材料。低k介電材料之介電常數(k值)可小於約3.9或小於約2.8。在金屬化結構中之金屬線可由銅、銅合金或類似者形成。
参考第2圖，導電區域12及至少一個鈍化層14在半導體基板10上方形成。導電區域12係在層間介電層上方形成之金屬化層。若需要的話，導電區域12係導電路徑之一部分並且具有使用平坦化製程(諸如化學機械研磨(CMP))處理的暴露表面。用於導電區域12之適宜材料可包括但不限於，例如銅、鋁、銅合金或其他導電材料，但其亦可由其他材料形成或包括其他材料，諸如銀、金、鎳、鎢、其合金、其多層、或類似者。導電區域12具有在約1μm與約10μm之間變化的寬度(直徑)。術語「寬度」指其終點 位於表面上之最長直線。在一些實施例中，導電區域12係為導電墊12，此導電墊可用於結合製程中將對應晶片中的積體電路連接至外部特徵。鈍化層14在基板10上形成，進而覆蓋導電墊12。在一些實施例中，鈍化層14包括一或多個非有機層，諸如未摻雜之矽酸鹽玻璃(USG)、氮化矽、氮氧化矽、氧化矽、碳化矽、氧化鋁、其組合、其多層、或類似者，但亦可使用其他介電材料。鈍化層14具有朝向導電墊12凹陷之下陷。鈍化層14在導電墊12之任一側面上較厚，並且鈍化層14之厚度朝向導電墊12急劇減小。鈍化層14之下陷疊加在導電墊12上方。
參考第3圖，第一犧牲層16形成在鈍化層14上。第一犧牲層16可由氧化物材料(諸如高縱橫比製程(high aspect ratio process,HARP)氧化物)形成，但其亦可由其他適宜材料形成。
參考第4圖，第一犧牲層16隨後圖案化以形成第一凹陷17a，藉由例如暴露、顯影及蝕刻，使得第一凹陷17a疊加在導電墊12上方。第一凹陷17a具有小於導電墊12之寬度的第一直徑。第一凹陷17a之位置排列在鈍化層14之下陷上方。第一凹陷17a疊加導電墊12。圖案化之第一犧牲層16在不暴露其下之組件的情況下覆蓋鈍化層14之完整頂表面及側壁。
參考第5圖，圖案化第一犧牲層16及鈍化層14。進行涉及光微影及蝕刻之第二圖案化製程以圖案化第一犧牲層16以形成第二凹陷19a。第二凹陷19a穿過第一凹 陷17a之底部並且進一步穿過鈍化層14以暴露下面導電墊12之一部分。第一犧牲層16之第二凹陷19a具有與第一凹陷17a之第一直徑相比較小之寬度(直徑)。第一犧牲層16之側壁向內突出以產生較狹窄之第二凹陷19a。第一凹陷17a及第二凹陷19a之寬度不同，使得形成階梯狀配置。形成不具有相同寬度的開口結構(包括第一凹陷17a及第二凹陷19a)。第一凹陷17a及第二凹陷19a可實質上同心，而在第一凹陷17a與第二凹陷19a之間的寬度差異足夠呈現出兩階之間的階梯。階梯之階面落到第一犧牲層16之第一凹陷17a上。
參考第6圖，導電凸塊22形成在第一凹陷17a及第二凹陷19a內的導電墊12之暴露之部分上方。導電凸塊22由例如鎳、鎳合金、其組合或類似者製成。導電凸塊22可藉由無電(E-less)電鍍製程或類似者形成。導電凸塊22具有底部22a及頂部22b。底部22a填充在第二凹陷19a中，且頂部22b係在第一凹陷17a內之導電凸塊22。底部22a在導電墊12上方。頂部22b在底部22a上方。頂部22b之厚度不超過第一凹陷17a之深度。頂部22b之頂表面低於第一犧牲層16之頂表面。鈍化層14圍繞導電凸塊22。導電凸塊22類似具有頸部(底部22a)及帽部(頂部22b)的酒塞或蘑菇。導電凸塊22之寬度分別繼承了第一凹陷17a及第二凹陷19a之寬度。底部22a具有與頂部22b相比較小之寬度。底部22b之外邊界底表面落到第一犧牲層16之第一凹陷17a上。頂部22b相對於底部22a橫向突出。
參考第7圖，導電帽24形成在導電凸塊22上方。導電帽24填充在第一凹陷17a之一部分中並且具有與導電凸塊22之頂部22b相似之寬度。導電帽24之形成方法可包括無電電鍍方法或類似者。導電帽24可包括金(Au)、銀、鈀(Pd)、鎳鈀金(NiPdAu)、鎳金(NiAu)或其他適宜材料或合金。半導體裝置之微凸塊20a包括導電凸塊22及導電帽24。微凸塊20a非直柱，但於不同部分具有不同寬度。例如，微凸塊20a具有狹窄頸部(底部22a)及較寬頭部(頂部22b及導電帽24)。微凸塊20a之側壁表面呈現出具有與頂部22b及導電帽24相比較狹窄之底部22a的階梯狀輪廓。
仍參看第7圖，導電墊12及導電帽24之雜質控制對接觸電阻具有關鍵影響。鈍化層14及第一犧牲層16非金屬材料。當導電凸塊22及導電帽24填充在第一凹陷17a及第二凹陷19a中時，在非金屬材料(亦即，鈍化層14及第一犧牲層16)與金屬材料(亦即，導電凸塊22及導電帽24)之間的黏著力係不良的。不良的黏著力導致間隙形成。此等間隙可能形成於界面處(例如，頂部22b與第一犧牲層16接觸處)。因為形成具有不同寬度之微凸塊20a，間隙因此以鋸齒型方式蜿蜒。
當形成導電帽24時，導電帽24可沿著朝向導電墊12之間隙產生。擴散路徑可在導電墊12與導電帽24之間鋪砌。鋸齒型路徑抑制了導電帽24之非預期的拉伸。導電凸塊22之階梯側壁表面產生至導電帽24的較長(若非不可實現的)路徑。在隨後熱製程(例如，退火)中，在導電墊 12與導電帽24之間的材料交換較不可能發生。例如，當導電墊12由銅(Cu)製成並且導電帽24由金(Au)製成時，金之一部分可擠入導電凸塊22與第一犧牲層16(及鈍化層14)之間的狹窄間隙。由於源自不同導電凸塊22寬度的階梯之急轉彎，此擴散路徑可截斷。在隨後熱製程期間，來自導電墊12之銅不能穿過斷開擴散路徑移動至導電帽24。則保護導電帽24不被外來材料污染。在銅污染之情形中，銅的較快速的氧化速率會導致對於金及其對應體之負面影響。當其對應體結合至導電帽時，被污染之導電帽將具有較高的接觸電阻。
參考第8圖，移除第一犧牲層16。因此，暴露出鈍化層14，且微凸塊20a之導電帽24在鈍化層14上方突出。導電帽24之頂表面位於高於鈍化層14之頂表面的位置。導電帽24係與其對應體之結合點。導電凸塊22之頂部22b與鈍化層14間隔開，且底部22a之一部分上升到鈍化層14之下陷上方。在一些實施例中，微凸塊20a具有第一部分及第二部分。第一部分係導電凸塊22之底部22a，而第二部分係頂部22b及導電帽24。第一部分與第二部分具有不同寬度，並且因此產生具有階梯側壁輪廓之微凸塊20a。
第8圖所示之結構可經附接至另一基板。基板可為顯示裝置之玻璃或其他適宜基板。微凸塊20a穿過例如金屬層，並接觸基板上的接觸墊及/或導電跡線。金屬層可包括具有低熔點之金屬，諸如銦、銦合金或類似者。使用包括 晶片佈置及熱壓縮結合之例示性耦接製程，在兩個基板之間形成金屬接合結構。
參考第9圖，在替代實施例中，在沉積第3圖所示之第一犧牲層16之後，圖案化第一犧牲層16以形成第一凹陷17b。第一凹陷17b穿過第一犧牲層16及鈍化層14。第一凹陷17b暴露出導電墊12之一部分。導電凸塊22之底部22a形成在第一凹陷17b內之導電墊12的暴露之部分上方。與第4圖所示之方法不同，首先形成導電凸塊22之一部分。
參考第10圖，第一犧牲層16經歷第二圖案化製程以形成第二凹陷19b。第二凹陷19b具有與第一凹陷17b相比較大之寬度。第二凹陷19b由第一犧牲層16之側壁及底部22a之頂表面界定。如第6圖所示，在形成第二凹陷19b之後，頂部22b隨後形成在底部22a上方。接下來，導電帽24在與先前所述相似的第7圖所示之頂部22b上形成。
參考第11圖，在替代實施例中，在沉積第3圖所示之第一犧牲層16之後，圖案化第一犧牲層16以形成第一凹陷17c。第一凹陷17c穿過第一犧牲層16及鈍化層14。第一凹陷17c暴露出導電墊12之一部分。
參考第12圖，導電凸塊22形成在第一凹陷17c內之導電墊12的暴露之部分上方。導電凸塊22之頂表面低於第一凹陷17c之開口。導電凸塊22具有在第一凹陷17c中橫跨第一犧牲層16與鈍化層14之間的界面的厚度。導電凸塊22具有與第一凹陷17c相同之寬度。
參考第13圖，第二犧牲層26保形形成在第一犧牲層16及導電凸塊22上。第二犧牲層26覆蓋第一犧牲層16之頂表面及側壁。第二犧牲層26亦覆蓋第一凹陷17c(第12圖所示)中之導電凸塊22。第一凹陷17c(第12圖所示)之輪廓藉由第二犧牲層26部分再現，但是具有較狹窄之開口，因為第二犧牲層26具有佔據第一凹陷17c(第12圖所示)之體積的厚度以產生具有不同寬度之第二凹陷19c。例如，若第一凹陷17c(第12圖所示)具有約7μm之寬度。在沉積第二犧牲層26之後，第二凹陷19c具有約4μm之寬度，因為第二犧牲層26佔據第一凹陷17c(第12圖所示)之體積。
參考第14圖，移除第二犧牲層26之底部。第二犧牲層26之底部位於導電凸塊22之頂表面上。導電凸塊22之頂表面之一部分藉由移除第二犧牲層26之底部而暴露出。如第14圖所示，因為保留了在第一犧牲層16之側壁上的第二犧牲層26，導電凸塊22之頂表面之剩餘部分被第二犧牲層26覆蓋。隨後，導電帽24形成在導電凸塊22上之第二凹陷19c中。導電帽24具有與第二凹陷19c相同但小於導電凸塊22之寬度的寬度。
參考第15圖，移除第一犧牲層16及第二犧性層26以形成微凸塊20c。導電凸塊22具有實質上相同之寬度。導電凸塊22具有超過鈍化層14之下陷之底表面的高度。因為導電凸塊22具有歸因於第一凹陷17c(第11圖所示)及第二凹陷19c(第13圖所示)的與導電帽24不同之寬度，階梯側壁表面於導電帽24與導電凸塊22接觸的位準處產生。導 電帽24具有與導電凸塊22相比較小之寬度。導電凸塊22之一部分從導電帽24暴露出。導電凸塊22之頂表面形成在平面圖中圍繞導電帽24之環。在一些實施例中，微凸塊20c具有第一部分及第二部分。第一部分係導電凸塊22，而第二部分係導電帽24。第一部分與第二部分具有不同寬度，並且因此產生具有階梯側壁輪廓之微凸塊20c。
參考第16圖，在替代實施例中，圖案化第一犧牲層16以形成第一凹陷17d。第一凹陷17d疊加在導電墊12上方。當暴露出下面鈍化層14時，第一凹陷17d的圖案化製程終止。第一凹陷17d具有小於導電墊12之寬度的第一直徑。
參考第17圖，圖案化鈍化層14。進行涉及光微影及蝕刻之第二圖案化製程以圖案化鈍化層14，形成第二凹陷19d。第二凹陷19d穿過鈍化層14以暴露下面之導電墊12之一部分。鈍化層14之第二凹陷19d具有與第一凹陷17d之第一直徑相比較小之寬度(直徑)。鈍化層14之側壁向內突出以產生較狹窄之第二凹陷19d。第一凹陷17d與第二凹陷19d之寬度不同，以形成階梯狀配置。與第5圖所示之結構不同，階梯之階面落到鈍化層14之第二凹陷19d上。第二凹陷19d與第一凹陷17d相比較淺。
參考第18圖，導電凸塊22形成在第一凹陷17d及第二凹陷19d內之導電墊12的暴露部分上方形成。導電凸塊22具有底部22a及頂部22b。底部22a填充在第二凹陷19d中，而頂部22b指第一凹陷17d內之導電凸塊22。底部22a 具有與頂部22b相比較小之寬度。此外，底部22a與頂部22b相比較薄。頂部22b之外邊界底表面落到鈍化層14上。頂部22b與鈍化層14相比較厚並且與此鈍化層接觸。
參考第19圖，導電帽24形成在導電凸塊22上。導電帽24填充在第一凹陷17d之一部分中並且具有與導電凸塊22之頂部22b相似之寬度。
參考第20圖，移除第一犧牲層16以形成微凸塊20d。微凸塊20a(第8圖所示)與微凸塊20d之間的差異源自導電凸塊22的底部22a與頂部22b之比例。如第20圖所示，底部22a與頂部22b相比較薄並且由鈍化層14封閉。頂部22b黏附至鈍化層14之頂表面。在一些實施例中，微凸塊20d具有第一部分及第二部分。第一部分指導電凸塊22之底部22a，並且第二部分指頂部22b及導電帽24。第一部分與第二部分具有不同寬度，並且由此產生具有階梯側壁輪廓之微凸塊20d。
參考第21圖，在替代實施例中，在沉積第3圖所示之第一犧牲層16之後，圖案化第一犧牲層16以形成第一凹陷17e。第一凹陷17e穿過第一犧牲層16及鈍化層14。第一凹陷17e暴露出導電墊12之一部分。
參考第22圖，導電凸塊22之底部22a形成在第一凹陷17e內之導電墊12的暴露之部分上方。底部22a之頂表面低於第一凹陷17e之開口。導電凸塊22具有在第一凹陷17c中橫跨第一犧牲層16與鈍化層14之間的界面的厚度。底部22a具有與第一凹陷17e相同之寬度。
參考第23圖，第二犧牲層26保形形成在第一犧牲層16及底部22a上。第二犧牲層26覆蓋第一犧牲層16之頂表面及側壁。第二犧牲層26亦覆蓋第一凹陷17e(第22圖所示)中之底部22a。第一凹陷17e(第22圖所示)之輪廓藉由第二犧牲層26部分再現，但其具有較狹窄之開口，因為第二犧牲層26具有佔據第一凹陷17e(第22圖所示)之體積的厚度以產生具有不同寬度之第二凹陷19e。
參考第24圖，移除第二犧牲層26之底部。第二犧牲層26之底部位於底部22a之頂表面上。底部22a之頂表面之一部分藉由移除第二犧牲層26之底部而暴露出。因為保留了在第一犧牲層16之側壁上的第二犧牲層26，底部22a之頂表面之剩餘部分由第二犧牲層26覆蓋，如第24圖所示。
參看第25圖，隨後導電凸塊22之頂部22b形成在第二凹陷19e中。頂部22b具有與第二凹陷19e相同之寬度，而頂部22b具有與底部22a相比較小之寬度。從平面圖來看，底部22a形成環繞頂部22b之環。導電凸塊22具有階梯狀配置，並且階面落到底部22b上。
參考第26圖，導電帽24形成在導電凸塊22之頂部22b上的第二凹陷19e中。導電帽24具有與第二凹陷19e相同但小於底部22a之寬度的寬度。
參考第27圖，移除第一犧牲層16及第二犧牲層26以形成微凸塊20e。微凸塊20e具有寬腰(底部22a)及較狹窄主體(頂部22b及導電帽24)。階梯產生於頂部22b與底部22a之界面處。微凸塊20e可被看作倒置之蘑菇，其 具有與導電墊12接觸之帽(底部22a)及向外指之莖(頂部22b及導電帽24)。在一些實施例中，微凸塊20e具有第一部分及第二部分。第一部分係導電凸塊22之底部22a，而第二部分指頂部22b及導電帽24。第一部分與第二部分具有不同寬度，並且由此產生具有階梯側壁輪廓之微凸塊20e。
參考第28圖，在替代實施例中，圖案化第一犧牲層16以形成第一凹陷17f。第一凹陷17f具有小於導電墊12之寬度的第一直徑。第一凹陷17f之形成不暴露出其下面之鈍化層14。
參考第29圖，圖案化第一犧牲層16及鈍化層14。進行涉及光微影及蝕刻之第二圖案化製程以圖案化第一犧牲層16以形成第二凹陷19f。第二凹陷19f穿過第一凹陷17f之底部並且進一步穿過鈍化層14以暴露出下面導電墊12之一部分。第一犧牲層16之第二凹陷19f具有與第一凹陷17f之第一直徑相比較小之寬度(直徑)。第一犧牲層16之側壁向內突出以產生較狹窄之第二凹陷19f。第一凹陷17f與第二凹陷19f之寬度不同，使得形成階梯狀配置。
參考第30圖，導電凸塊22形成在第一凹陷17f及第二凹陷19f內之導電墊12的暴露之部分上方。導電凸塊22具有底部22a及頂部22b。底部22a填充在第二凹陷19f中，而頂部22b指在第一凹陷17f內之導電凸塊22。頂部22b之頂表面低於第一犧牲層16之頂表面。
參考第31圖，第二犧牲層26保形形成在第一犧牲層16及導電凸塊22上。第二犧牲層26覆蓋第一犧牲層16 之頂表面及側壁。第二犧牲層26亦覆蓋第一凹陷17f(第30圖所示)中之頂部22b。第一凹陷17f(第30圖所示)之輪廓藉由第二犧牲層26部分再現，但其具有較狹窄之開口，因為第二犧牲層26具有佔據第一凹陷17f(第30圖所示)之體積的厚度，以產生具有與第一凹陷17f(第30圖所示)不同之寬度的第三凹陷21。在一些實施例中，第三凹陷21具有與第二凹陷19f(第30圖所示)實質上相同之寬度。在一些實施例中，第一凹陷17f(第30圖所示)、第二凹陷19f(第30圖所示)及第三凹陷21之寬度彼此不同。第三凹陷21不具有與第一凹陷17f(第30圖所示)相同之寬度。
參考第32圖，移除第二犧牲層26之底部。第二犧牲層26之底部位於導電凸塊22之頂部22b之頂表面上。底部22a之頂表面之一部分藉由移除第二犧牲層26之底部而暴露出。因為保留了在第一犧牲層16之側壁上的第二犧牲層26，頂部22b之頂表面之剩餘部分藉由第二犧牲層26覆蓋，如第33圖所示。
參考第33圖，導電帽24形成在導電凸塊22之頂部22b上的第三凹陷21中。
參考第34圖，移除第一犧牲層16及第二犧牲層26以形成微凸塊20f。微凸塊20f具有多階梯配置。導電凸塊22保持其蘑菇狀配置，其中底部22a具有與頂部22b相比較小之寬度。此外，導電帽24具有與頂部22b相比較小之寬度。如第34圖所示，微凸塊20f中間較寬並且任一末端較窄。在一些實施例中，導電帽24可具有與導電凸塊22之底 部22a相似之寬度。在一些實施例中，底部22a、頂部22b及導電帽24具有不同寬度。微凸塊20f之側壁表面呈鋸齒型配置。一個階梯形成在導電帽24與頂部22b之間，並且另一階梯形成在頂部22b與底部22a之間。在導電帽24與導電墊12之間的擴散路徑甚至更為錯綜複雜，這意味著較少的外來材料污染。在一些實施例中，微凸塊20f具有第一部分、第二部分及第三部分。第一部分係導電凸塊22之底部22a，第二部分係導電凸塊22之頂部22b，並且第三部分係導電帽24。微凸塊22f之第一、第二及第三部分具有變化的寬度。第二部分具有分別與第一部分及第三部分相比較大之寬度。
參考第35圖，其係根據本揭示之一些實施例的製造半導體裝置之方法600的流程圖。方法開始於操作610，其中犧牲層形成在半導體基板上方。方法繼續至操作620，其中開口形成在犧牲層中以暴露出在半導體基板上方之導電墊之一部分。隨後，進行操作630。導電凸塊形成在開口中。方法繼續至操作640，其中阻障層形成在開口之側壁上及導電凸塊之頂表面上。方法繼續至操作650，其中在阻障層介於導電凸塊與導電帽之間的情況下導電帽形成在開口中。方法繼續至操作660，其中移除第一犧牲層。
第36圖至第43圖係根據本揭示之一些實施例的於凸塊形成製程中之各個階段的半導體裝置之一部分的橫截面圖。
參考第36圖，在製造半導體裝置中半導體基板60用於凸塊製造，而積體電路可在其中及/或其上形成。導 電墊62、至少一個鈍化層64、及第一犧牲層66在基板60上方形成。本文不重複與先前所述之彼等相似之元件以避免贅述。第36圖亦描繪了圖案化鈍化層64及第一犧牲層66以形成開口67，進而暴露出導電墊62之一部分。導電凸塊72填充在開口67中並且覆蓋導電墊62的暴露部分。
參考第37圖，阻障層74a在第一犧牲層66上及導電凸塊72上方之開口67中形成。形成阻障層74a以覆蓋第一犧牲層66之開口67之側壁及底部(導電凸塊72之頂表面)。阻障層74a不與鈍化層64接觸。阻障層74a可由鈷、鈦、其組合、或類似者形成。形成方法包括物理氣相沉積(physical vapor deposition,PVD)、濺鍍、或類似者。
參考第38圖，移除阻障層74a之一部分。阻障層74a可藉由CMP或其他適宜方法移除。在移除之後，移除在第一犧牲層66之表面上的阻障層74a。剩餘的阻障層74係在開口67之側壁及底部上。
參考第39圖，導電帽76填充在阻障層74上方之開口67中。導電帽76包括與導電帽24(第7圖所示)相似之材料，而且其形成方法包括無電電鍍或類似者。阻障層74類似接收導電帽76之碗。導電帽76略微超過阻障層74之邊緣，使得導電帽76之底部由阻障層74纏繞在周圍，而導電帽76之小的頂部在阻障層74上方突出。導電凸塊72、導電帽76、及阻障層74包括不同材料。導電帽76之頂表面不與第一犧牲層66及阻障層74之邊緣平齊。導電帽76之頂表面位於高於鈍化層64之頂表面的位置處。
參考第40圖，第二犧牲層77在第一犧牲層66上方形成。第二犧牲層77可包括四乙氧基矽烷(tetraethoxysilane,TEOS)或類似者。由於突出之導電帽76，當第二犧牲層77在第一犧牲層66上形成時，突出之導電帽76導致第二犧牲層77於界面處內縮。
參考第41圖，圖案化第二犧牲層77以形成開口77a。開口77a暴露出導電帽76之頂表面並且具有與導電凸塊72之寬度相似之寬度。
參考第42圖，黏著膜78在第二犧牲層77上形成並且填充在開口77a中。黏著膜78包括多種材料，例如，雙苯并環丁烯(bisbenzocyclobutene,BCB)、聚醯亞胺(polyimide,PI)、聚苯并惡唑(polybenzoxazole,PBO)、雙馬來醯亞胺三嗪(bismaleimidetriazne,BT)或類似者。黏著膜78展現與導電帽76相比對載體晶圓的較強黏著親和性。
參考第43圖，第二犧牲層77及第一犧牲層66藉由例如稀釋之氫氟酸(diluted hydrofluoric acid,DHF)處理或氣相氫氟酸(vapor hydrofluoric acid,VHF)處理適宜時間來移除。在一些實施例中，半導體基板60經歷薄化製程，而且載體晶圓(未圖示)可附接至黏著膜78。由於對載體晶圓具有較高黏著親和性，黏著膜78確保裝置晶圓(微凸塊70)在薄化期間具備來自載體晶圓的充分支撐。當微凸塊70將與其對應體結合時，移除黏著膜78連同載體晶圓。
參考第44圖，在替代實施例中，在形成第40圖所示之導電帽76之後，移除第一犧牲層66以形成微凸塊70’。在微凸塊70’與微凸塊70(第44圖所示)之間的差異源自後處理(post processing)。微凸塊70’獨立於黏著膜78，因此省略了形成第二犧牲層及黏著膜之步驟。
第44圖所示之結構可經附接至另一基板。基板可係顯示裝置之玻璃或其他適宜基板。連接結構102穿過例如金屬層接觸基板上的接觸墊及/或導電跡線。金屬層可包括具有低熔點之金屬，諸如銦、銦合金、或類似者。使用包括晶片佈置及熱壓縮結合之例示性耦接製程，在兩個基板之間形成金屬接合結構。
微凸塊之階梯側壁表面在導電帽與墊區域之間產生旋繞之擴散路徑。歸因於雜質必須移動過之蜿蜒路徑，擴散路徑通常被截斷。在導電帽與另一基板之焊接層之間的導電接合因此更為可靠並且具有均勻高度。
在一些實施例中，一種半導體裝置包括半導體基板。導電墊經設置在半導體基板上方。導電凸塊經設置在導電墊上方。導電帽經設置在導電凸塊上方。導電凸塊及導電帽之組合具有階梯側壁輪廓。至少一個鈍化層經設置在半導體基板上方並且圍繞導電凸塊。
在一些實施例中，導電凸塊具有在導電墊上方之底部及在底部上方之頂部，並且頂部與底部具有不同寬度。
在一些實施例中，導電凸塊具有在導電墊上方之底部及在該底部上方之頂部，底部具有第一寬度，頂部具有第二寬度，且第一寬度小於第二寬度。
在一些實施例中，頂部與至少一個鈍化層間隔開。
在一些實施例中，頂部之底表面落到至少一個鈍化層上。
在一些實施例中，導電帽具有第三寬度，並且第三寬度小於第二寬度。
在一些實施例中，導電凸塊之頂表面之一部分在導電帽上方突出。
在一些實施例中，導電凸塊具有在導電墊上方之底部及在底部上方之頂部，底部具有第一寬度，頂部具有第二寬度，且第一寬度大於第二寬度。
在一些實施例中，導電帽之頂表面位於高於該至少一個鈍化層之頂表面的位置處。
在一些實施例中，一種半導體裝置包括半導體基板。導電墊經設置在半導體基板上方。導電凸塊經設置在導電墊上方。導電帽經設置在導電凸塊上方。阻障層纏繞在導電帽之底部周圍。至少一個鈍化層經設置在半導體基板上方並且圍繞導電凸塊。
在一些實施例中，導電帽之頂部在阻障層之邊緣上方突出。
在一些實施例中，導電凸塊及導電帽包含不同材料。
在一些實施例中，導電帽與阻障層包含不同材料。
在一些實施例中，阻障層包含鈦、鈷或其組合。
在一些實施例中，導電帽之頂表面位於高於至少一個鈍化層之頂表面的位置處。
在一些實施例中，一種製造半導體裝置之方法包括在半導體基板上方形成第一犧牲層。接下來，第一開口在第一犧牲層中形成以暴露出在半導體基板上方之導電墊。隨後，導電凸塊在第一開口中形成。隨後，阻障層在第一開口之側壁上及導電凸塊之頂表面上形成。之後，在阻障層介於導電凸塊與導電帽之間的情況下，導電帽在第一開口中形成。隨後移除第一犧牲層。
在一些實施例中，形成該阻障層包括：在第一犧牲層之頂表面上及第一開口中形成阻障層；以及移除在第一犧牲層之頂表面上的阻障層之部分。
在一些實施例中，第一犧牲層之頂表面上的阻障層之部分藉由化學機械平坦化移除。
在一些實施例中，製造半導體裝置之方法進一步包括：在第一開口中形成導電帽之後，在第一犧牲層上方形成第二犧牲層；在第二犧牲層中形成第二開口，進而暴露導電帽之頂表面；在第二犧牲層上及第二開口中形成黏著膜；以及移除第二犧牲層。
在一些實施例中，阻障層包含鈦、鈷或其組合。
上文概述若干實施例之特徵，使得熟習此項技術者可更好地理解本揭示之態樣。熟習此項技術者應瞭解，可輕易使用本揭示作為設計或修改其他製程及結構的基礎，以便實施本文所介紹之實施例的相同目的及/或實現相同優勢。熟習此項技術者亦應認識到，此類等效結構並未脫離本揭示之精神及範疇，且可在不脫離本揭示之精神及範疇的情況下產生本文的各種變化、替代及更改。

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  1. 一種半導體裝置，包含：一半導體基板；一導電墊，位於該半導體基板上方；一導電凸塊，位於該導電墊上方；一導電帽，位於該導電凸塊上方，其中該導電凸塊與該導電帽之一組合具有一階梯側壁輪廓；以及至少一個鈍化層，位於該導電基板上方並且圍繞該導電凸塊。
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