TWI721564B - 半導體結構及其製作方法 - Google Patents

半導體結構及其製作方法 Download PDF

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TWI721564B
TWI721564B TW108133566A TW108133566A TWI721564B TW I721564 B TWI721564 B TW I721564B TW 108133566 A TW108133566 A TW 108133566A TW 108133566 A TW108133566 A TW 108133566A TW I721564 B TWI721564 B TW I721564B
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Taiwan
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bonding
hole
dummy
effective
die
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TW108133566A
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TW202046482A (zh
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陳憲偉
陳潔
陳明發
楊慶榮
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台灣積體電路製造股份有限公司
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Abstract

本發明實施例公開半導體封裝及形成所述半導體封裝的方法。所述方法中的一者包括以下步驟。提供第一晶粒，其中所述第一晶粒包括第一基底、第一內連結構以及第一焊墊，所述第一內連結構位於所述第一基底之上，所述第一焊墊設置在所述第一內連結構之上且電性連接到所述第一內連結構。在所述第一晶粒之上形成第一結合介電層以覆蓋所述第一晶粒。使用單鑲嵌製程形成穿透所述第一結合介電層的第一結合通孔以電性連接所述第一內連結構。

Description

半導體結構及其製作方法
本發明實施例是有關於一種半導體結構及其製作方法。
近年來，由於各種電子元件(例如，電晶體、二極體、電阻器、電容器等)的積體密度持續提高，半導體行業已經歷快速成長。在很大程度上，積體密度的這種提高歸因於最小特徵尺寸(minimum feature size)的連續減小，這使得更多元件能夠集成到給定區域中。
這些較小的電子元件也需要與先前的封裝相比佔據較小面積的較小的封裝。半導體封裝的一些類型包括方形扁平封裝(quad flat pack，QFP)、針格柵陣列(pin grid array，PGA)、球柵陣列(ball grid array，BGA)、覆晶(flip chip，FC)、三維積體電路(three dimensional integrated circuit，3DIC)、晶圓級封裝(wafer level package，WLP)及疊層封裝(package on package，PoP)裝置。一些3DIC是通過在半導體晶圓級的晶片之上放置晶片製備而成。3DIC提供提高的積體密度及其他優點(例如，較快 的速度及較高的頻寬)，這是由於堆疊晶片之間的內連線的長度減小。然而，對於3DIC技術而言，存在許多要應對的挑戰。
本發明實施例的一種製造半導體結構的方法包括以下步驟。提供第一晶粒，其中所述第一晶粒包括第一基底、第一內連結構以及第一焊墊(pad)，所述第一內連結構位於所述第一基底之上，所述第一焊墊設置在所述第一內連結構之上且電性連接到所述第一內連結構。在所述第一晶粒之上形成第一結合介電層(bonding dielectric layer)以覆蓋所述第一晶粒。使用單鑲嵌製程形成穿透所述第一結合介電層的第一結合通孔(bonding via)以電性連接所述第一內連結構。
本發明實施例的一種製造半導體結構的方法包括以下步驟。形成第一晶粒，其中所述第一晶粒包括第一基底、第一內連結構及第一有效(active)焊墊，所述第一內連結構位於所述第一基底之上，所述第一有效焊墊設置在所述第一內連結構之上且電性連接到所述第一內連結構。在所述第一晶粒之上形成第一結合介電層以覆蓋所述第一晶粒。使用單次移除製程形成分別穿透所述結合介電層的通孔洞(via hole)及至少一個虛設通孔洞(dummy via hole)。在所述通孔洞及所述至少一個虛設通孔洞中分別形成第一有效結合通孔及至少一個第一虛設結合通孔，其中所述第一有效結合通孔電性連接到所述第一內連結構，且所述至少一個第一 虛設結合通孔是電性浮置的。
本發明實施例的一種半導體結構且所述半導體結構包括第一晶粒以及第二晶粒。所述第一晶粒包括位於所述第一晶粒上的第一結合介電層及位於所述第一結合介電層中的第一有效結合通孔。所述第二晶粒包括位於所述第二晶粒上的第二結合介電層及位於所述第二結合介電層中的第二有效結合通孔。通過將所述第一有效結合通孔與所述第二有效結合通孔結合在一起以及將所述第一結合介電層與所述第二結合介電層結合在一起來對所述第一晶粒與所述第二晶粒進行結合。所述第一有效結合通孔穿透所述第一結合介電層，且所述第一有效結合通孔具有從所述第一有效結合通孔的頂部到底部的連續傾斜的側壁。
10、10A、10B、10C、10D:三維積體電路(3DIC)結構
15:混合結合結構
100、200:半導體結構
101、201:晶粒
102、202:半導體基底
104、204:裝置層
106、206:內連結構
108、208:絕緣材料
110、210:金屬特徵
112、212:鈍化層
114、214:有效焊墊
115、215:結合結構
116、216:結合介電層
118:通孔洞
120、120a、120b:有效結合通孔
122、136、222、236:阻障層
124、138、224、238:金屬層
130、230:虛設特徵
132:虛設通孔洞
134、234:虛設結合通孔
140、240:虛設焊墊
220、220a、220b:有效結合通孔
BCD:底部寬度
D1、D2、D3、D4:距離
M:罩幕層
OP、OP1、OP2:開口
SW:側壁
TCD:寬度
θ:夾角
結合附圖閱讀以下詳細說明，會最好地理解本公開的各個方面。應注意，根據本行業中的標準慣例，各種特徵並非按比例繪製。事實上，為論述清晰起見，可任意增大或減小各種特徵的臨界尺寸。
圖1A到圖1E是根據本公開一些實施例的形成三維積體電路(3DIC)結構的方法的剖視圖。
圖2是根據本公開一些實施例的3DIC結構的剖視圖。
圖3是根據本公開一些實施例的3DIC結構的剖視圖。
圖4A到圖4E是根據本公開一些實施例的形成3DIC結構的方法的剖視圖。
圖5是示出圖4D所示結構的俯視圖。
圖6A是根據本公開一些實施例的3DIC結構的剖視圖且圖6B是3DIC結構中的第一結合通孔、第一虛設結合通孔、第一焊墊及第一虛設焊墊的俯視圖。
以下公開內容提供用於實施所提供主題的不同特徵的許多不同的實施例或實例。以下闡述元件及排列的具體實例以簡化本公開。當然，這些僅為實例而不旨在進行限制。舉例來說，以下說明中將第二特徵形成在第一特徵“之上”或第一特徵“上”可包括其中第二特徵與第一特徵被形成為直接接觸的實施例，且也可包括其中第二特徵與第一特徵之間可形成有附加特徵、以使得所述第二特徵與所述第一特徵可能不直接接觸的實施例。另外，本公開可在各種實例中重複使用參考編號和/或字母。這種重複使用是出於簡潔及清晰的目的，而不是自身表示所論述的各種實施例和/或配置之間的關係。
此外，為易於說明，本文中可能使用例如“在...之下(beneath)”、“在...下面(below)”、“下部的(lower)”、“在...上(on)”、“在...之上(over)”、“上覆在...之上(overlying)”、“在...上方(above)”、“上部的(upper)”等空間相對性用語來闡述圖 中所示的一個元件或特徵與另一(其他)元件或特徵的關係。所述空間相對性用語旨在除圖中所繪示的取向外還囊括裝置在使用或操作中的不同取向。裝置可具有其他取向(旋轉90度或其他取向)，且本文中所用的空間相對性描述語可同樣相應地進行解釋。
另外，為易於說明，本文中可能使用例如“第一(first)”、“第二(second)”、“第三(third)”、“第四(fourth)”等用語來闡述圖中所示相似的或不同的元件或特徵，且可根據所述說明的存在的次序或上下文來互換地使用所述用語。
也可包括其他特徵及製程。舉例來說，可包括測試結構以說明對三維封裝或3DIC裝置進行驗證測試。所述測試結構可例如包括在重佈線層中或在基底上形成的測試焊墊(test pad)，以便能夠對三維封裝或3DIC進行測試、對探針和/或探針卡(probe card)進行使用等。可對中間結構以及最終結構執行驗證測試。另外，可將本文中所公開的結構及方法與包括對已知良好晶粒進行中間驗證的測試方法結合使用，以提高良率並降低成本。
圖1A到圖1E是根據本公開一些實施例的形成三維積體電路(3DIC)結構的方法的剖視圖。
參照圖1A，提供第一晶粒101。舉例來說，第一晶粒101包括第一半導體基底102、第一裝置層104、第一內連結構106、第一鈍化層112及第一有效焊墊114。在一些實施例中，第一晶粒101可為半導體晶粒、半導體晶片、半導體晶圓的晶粒或其組合。舉例來說，第一晶粒101可為應用專用積體電路 (application-specific integrated circuit，ASIC)晶片、類比晶片、感測器晶片、無線與射頻晶片、電壓調節器晶片或記憶體晶片。
在一些實施例中，第一半導體基底102可包含矽或其他半導體材料。作為另外一種選擇，或另外地，第一半導體基底102可包含其他元素半導體材料，例如鍺。在一些實施例中，第一半導體基底102是由化合物半導體(例如碳化矽、砷化鎵、砷化銦或磷化銦)製成的。在一些實施例中，第一半導體基底102是由合金半導體(例如矽鍺、碳化矽鍺、磷化鎵砷或磷化鎵銦)製成的。在一些實施例中，第一半導體基底102包括磊晶層。舉例來說，第一半導體基底102具有上覆在塊狀半導體上的磊晶層。
在一些實施例中，第一裝置層104以前段(front-end-of-line，FEOL)製程形成在第一半導體基底102之上。第一裝置層104包括各種各樣的裝置。在一些實施例中，裝置包括主動元件、被動元件或其組合。所述裝置的功能可包括記憶體、處理器、感測器、放大器、功率分配(power distribution)、輸入和/或輸出電路系統等。在一些實施例中，裝置可包括積體電路裝置。舉例來說，裝置為電晶體、電容器、電阻器、二極體、光電二極體、熔絲裝置(fuse device)或其他相似的裝置。在一些實施例中，第一裝置層104包括閘極結構、源極及汲極區以及隔離結構(例如，淺溝槽隔離(shallow trench isolation，STI)結構(圖中未示出))。在第一裝置層104中，可形成各種N型金屬氧化物半導體(N-type metal-oxide semiconductor，NMOS)裝置和/或P 型金屬氧化物半導體(P-type metal-oxide semiconductor，PMOS)裝置(例如電晶體或記憶體等)，且可將所述裝置內連在一起以執行一種或多種功能。
參照圖1A，第一內連結構106形成在第一裝置層104之上。詳細來說，第一內連結構106包括第一絕緣材料108及多個第一金屬特徵110。第一金屬特徵110形成在第一絕緣材料108中且電性連接到第一裝置層104。第一金屬特徵110的一部分(例如最頂部第一金屬特徵110)被第一絕緣材料108暴露出。在一些實施例中，第一絕緣材料108包括層間介電(inner-layer dielectric，ILD)層以及至少一個金屬間介電(inter-metal dielectric，IMD)層。ILD層設置在第一裝置層104之上且IMD設置在ILD層之上。在一些實施例中，第一絕緣材料108包含氧化矽、氮氧化矽、氮化矽、低介電常數(低-k)材料或其組合。在一些實施例中，第一絕緣材料108可為單層或多層。在一些實施例中，第一金屬特徵110包括插塞及金屬線。插塞可包括形成在ILD層中的接觸件以及形成在IMD層中的通孔。接觸件形成在第一裝置層104與最底部金屬線之間，且與第一裝置層104及最底部金屬線連接。通孔形成在兩條金屬線之間，且與所述兩條金屬線連接。第一金屬特徵110可由鎢(W)、銅(Cu)、銅合金、鋁(Al)、鋁合金或其組合製成。在一些替代實施例中，可在第一金屬特徵110與第一絕緣材料108之間形成阻障層(圖中未示出)以防止第一金屬特徵110的材料遷移到或擴散到第一裝置層104。舉例來說，阻障層 的材料包括鉭、氮化鉭、鈦、氮化鈦、鈷鎢(cobalt-tungsten，CoW)或其組合。在一些實施例中，與第一內連結構106相鄰的第一金屬特徵110的厚度小於與第一結合結構115(如圖1D所示)相鄰的第一金屬特徵110的厚度。舉例來說，直接連接到第一裝置層104的第一金屬特徵110的厚度小於直接連接到第一有效焊墊114的第一金屬特徵110的厚度。然而，本發明並非僅限於此。
參照圖1A，第一鈍化層112形成在第一內連結構106之上。在一些實施例中，第一鈍化層112的材料包括氧化矽、氮化矽、苯並環丁烯(benzocyclobutene，BCB)聚合物、聚醯亞胺(polyimide，PI)、聚苯並惡唑(polybenzoxazole，PBO)或其組合且可通過合適的製程(例如旋轉塗布、化學氣相沉積(chemical vapor deposition，CVD)等)形成。在一些實施例中，第一鈍化層112可為單層結構、雙層結構或多層結構。
參照圖1A，第一有效焊墊114形成在第一內連結構106之上且電性連接到第一內連結構106。在本文中，當將元件闡述為“有效”時，元件是功能性的且電性連接到晶粒的其他元件。在一些實施例中，第一有效焊墊114進一步延伸到第一鈍化層112中，從而電性連接到第一金屬特徵110。第一有效焊墊114與第一金屬特徵110可具有相同或不同的材料。在一些實施例中，第一有效焊墊114的材料可包括金屬材料，例如鋁、銅、鎳、金、銀、鎢或其組合。第一有效焊墊114可通過以下步驟形成：形成通孔洞以暴露出第一金屬特徵110；通過合適的製程(例如電化學鍍敷 製程、CVD、原子層沉積(atomic layer deposition，ALD)、PVD等)沉積金屬材料層以填充開口並覆蓋第一鈍化層112；以及接著對金屬材料層進行圖案化。在一些實施例中，舉例來說，第一有效焊墊114的厚度可介於1μm到3μm的範圍內。
參照圖1B，在第一晶粒101的正面之上形成第一結合介電層116。第一結合介電層116設置在第一鈍化層112之上以覆蓋第一有效焊墊114。在一些實施例中，第一結合介電層116覆蓋第一有效焊墊114的頂表面及側壁。在一些實施例中，第一結合介電層116包含氧化矽、氮化矽、聚合物或其組合。第一結合介電層116通過合適的製程(例如旋轉塗布、CVD等)形成。在一些實施例中，第一結合介電層116的厚度可介於2μm到8μm的範圍內。
參照圖1C及圖1D，在第一結合介電層116中形成通孔洞118，且在通孔洞118中形成第一有效結合通孔120。在一些實施例中，第一有效結合通孔120是通過單鑲嵌製程形成的。首先，如圖1C所示，在第一結合介電層116上形成罩幕層M，且罩幕層M具有開口OP以暴露出第一結合介電層116的一部分。接著，使用罩幕層M作為罩幕，通過單次移除製程(例如乾蝕刻製程或濕蝕刻製程)移除第一結合介電層116及第一鈍化層112的一些部分，從而暴露出第一金屬特徵110。在一些實施例中，第一結合介電層116與第一鈍化層112可相對於單次移除製程中使用的蝕刻劑具有相似的蝕刻選擇性。另外，第一鈍化層112及第一結合介 電層116的蝕刻選擇性與第一金屬特徵110的蝕刻選擇性不同。因此，在單次移除製程期間，可使用第一金屬特徵110的頂表面作為蝕刻停止層。因此，通孔洞118穿透第一鈍化層112及第一結合介電層116並在第一金屬特徵110的頂表面上停止。接著，移除罩幕層M。在一些實施例中，通孔洞118通過單個製程一體成形(integrally formed)，且僅需要一個罩幕。因此，形成通孔洞118的成本可降低。
在一些實施例中，通孔洞118的整個側壁SW連續傾斜且未形成有轉折點(turning point)或臺階(step)。因此，通孔洞118可具有實質上平滑的側壁SW。在一些實施例中，舉例來說，側壁SW可相對於通孔洞118的底部及第一絕緣材料108的頂表面漸縮。在一些實施例中，舉例來說，側壁SW與第一絕緣材料108的頂表面之間的夾角θ可介於85度到89.9度的範圍內。在一些實施例中，舉例來說，通孔洞118的頂部寬度TCD與底部寬度BCD之間的差可小於頂部寬度TCD的5%。舉例來說，通孔洞118的寬度TCD可介於2μm到10μm的範圍內。在一些替代實施例中，側壁SW實質上垂直於通孔洞118的底部及第一絕緣材料108的頂表面，且因此通孔洞118可從頂部到底部具有實質上恒定的寬度。
接著，如圖1D所示，第一有效結合通孔120形成在通孔洞118中以電性連接第一內連結構106的第一金屬特徵110。在一些實施例中，舉例來說，第一有效結合通孔120包括阻障層122 及金屬層124。阻障層122設置在通孔洞118的側壁SW及底部上，且金屬層124設置在阻障層122上並填充到通孔洞118中。舉例來說，阻障層122可包含鈦(Ti)、鉭(Ta)、氮化鈦(TiN)、氮化鉭(TaN)或其組合，且金屬層124可包含鎢(W)、銅(Cu)、銅合金、鋁(Al)、鋁合金或其組合。在一些實施例中，第一有效結合通孔120可如下所述形成。首先，在第一結合介電層116的表面以及通孔洞118的側壁SW及底部上形成阻障材料。在一些實施例中，阻障材料可通過合適的製程(例如化學氣相沉積方法、濺射方法或鍍敷方法)形成。接著，在阻障材料上形成導電材料並將導電材料填充到上面具有阻障材料的通孔洞118中。導電材料可通過合適的製程(例如電化學鍍敷製程、CVD、原子層沉積(ALD)、PVD等)形成。之後，通過平坦化製程(例如化學機械拋光(chemical mechanical polish，CMP)製程)移除通孔洞118外的阻障材料以及導電材料，且因此在通孔洞118中形成第一有效結合通孔120。
在一些實施例中，第一有效結合通孔120設置在第一有效焊墊114旁邊並與第一有效焊墊114隔開，且第一有效結合通孔120與第一有效焊墊114電性隔離。在一些實施例中，第一有效結合通孔120形成為通孔，且第一有效結合通孔120穿透第一鈍化層112及第一結合介電層116以電性連接第一內連結構106的第一金屬特徵110。在一些實施例中，第一有效結合通孔120直接設置在第一內連結構106的最頂部第一金屬特徵110上並接觸 第一內連結構106的最頂部第一金屬特徵110。舉例來說，第一有效結合通孔120的頂表面與第一結合介電層116的頂表面實質上齊平，且第一有效結合通孔120的底表面與第一鈍化層112的底表面及第一絕緣材料108的頂表面實質上齊平。在一些實施例中，舉例來說，阻障層122的頂表面及金屬層124的頂表面與第一結合介電層116的頂表面實質上共面，且阻障層122的底表面與第一鈍化層112的底表面以及第一絕緣材料108的頂表面實質上共面。第一有效結合通孔120的高度可實質上相同於第一鈍化層112及第一結合介電層116的總厚度(例如2μm到8μm)。
第一有效結合通孔120具有與通孔洞118實質上相同的輪廓。詳細來說，第一有效結合通孔120的整個側壁SW連續傾斜且未形成有轉折點或臺階。也就是說，第一有效結合通孔120的整個側壁SW實質上是平滑的。在一些實施例中，舉例來說，第一有效結合通孔120的側壁SW可相對於第一有效結合通孔120的底部及第一絕緣材料108的頂表面漸縮。在一些實施例中，舉例來說，側壁SW與第一絕緣材料108的頂表面之間的夾角θ可介於85度到89.9度的範圍內。在一些實施例中，舉例來說，第一有效結合通孔120的頂部寬度TCD與底部寬度BCD之間的差可小於頂部寬度TCD的5%。舉例來說，第一有效結合通孔120的頂部寬度TCD可介於2μm到10μm的範圍內。在一些替代實施例中，側壁SW實質上垂直於第一有效結合通孔120的底部及第一絕緣材料108的頂表面，且因此第一有效結合通孔120可具有 從頂部到頂部實質上恒定的寬度。
在第一結合介電層116中形成第一有效結合通孔120之後，形成第一結合結構115。在一些實施例中，如圖1D所示，完成第一半導體結構100，第一半導體結構100包括第一晶粒101以及第一晶粒101之上的第一結合結構115。
參照圖1E，提供第二半導體結構200。詳細來說，第二半導體結構200包括第二晶粒201以及設置在第二晶粒201的正面之上的第二結合結構215。在一些實施例中，第二半導體結構200可包括半導體晶粒、半導體晶片、半導體晶圓或其組合。舉例來說，第二晶粒201可為應用專用積體電路(ASIC)晶片、類比晶片、感測器晶片、無線與射頻晶片、電壓調節器晶片或記憶體晶片。第二晶粒201與第一晶粒101可為相同類型的晶粒或不同類型的晶粒。
在一些實施例中，第二晶粒201與第一晶粒101相似。也就是說，第二晶粒201包括第二半導體基底202、第二裝置層204、第二內連結構206、第二鈍化層212及第二有效焊墊214，第二內連結構206包括第二絕緣材料208及多個第二金屬特徵210。第二晶粒201的配置、材料及形成方法與第一晶粒101的配置、材料及形成方法相似。因此，此處省略其細節。圖1E所示第一晶粒101與第二晶粒201具有相同的尺寸。本文中的用語“尺寸”是指寬度、長度或面積。舉例來說，如圖1E所示，第二晶粒201的寬度等於第一晶粒101的寬度。然而，本發明的實施例並非僅 限於此。在其他實施例中，第一晶粒101的尺寸不同於第二晶粒201的尺寸。舉例來說，第一晶粒101可為晶圓，第二晶粒201可為晶粒且作為晶圓上晶片(chip-on-wafer，CoW)結構設置在晶圓之上。
在一些實施例中，第二結合結構215與第一結合結構115相似。也就是說，第二結合結構215包括第二結合介電層216以及位於第二結合介電層216中的第二有效結合通孔220，且第二有效結合通孔220可具有阻障層222及金屬層224。第二結合結構215的配置、材料及形成方法與第一結合結構115的配置、材料及形成方法相似。因此，此處省略其細節。圖1E所示第一有效結合通孔120與第二有效結合通孔220具有相同的尺寸。舉例來說，如圖1E所示，第二有效結合通孔220的寬度等於第一有效結合通孔120的寬度。然而，本發明的實施例並非僅限於此。在其他實施例中，第一有效結合通孔120的尺寸不同於第二有效結合通孔220的尺寸。另外，在一些替代實施例中，第二結合結構215可不同於第一結合結構115。
參照圖1E，將第二半導體結構200進一步上下翻轉並安裝到第一半導體結構100上。也就是說，第一晶粒101與第二晶粒201通過第一結合結構115及第二結合結構215面對面地結合在一起以形成三維積體電路(3DIC)結構10(或被稱為晶粒堆疊結構)。然而，本發明的實施例並非僅限於此。在其他實施例中，第一晶粒101與第二晶粒201可面對背地結合在一起。
在一些實施例中，在將第一晶粒101結合到第二晶粒201之前，將第一結合結構115與第二結合結構215對齊，以使第一有效結合通孔120可結合到第二有效結合通孔220，且第一結合介電層116可結合到第二結合介電層216。在一些實施例中，第一結合結構115與第二結合結構215的對齊可使用光學感測方法實現。在實現對齊之後，通過混合結合(hybrid bonding)將第一結合結構115與第二結合結構215結合在一起以形成混合結合結構15。
第一結合結構115與第二結合結構215通過施加壓力及熱量而混合結合在一起。應注意，混合結合涉及至少兩種類型的結合，所述至少兩種類型的結合包括金屬到金屬結合以及非金屬到非金屬結合(例如，介電質到介電質結合或熔融結合)。如圖1E所示，混合結合結構15包括通過金屬到金屬結合而結合在一起的第一有效結合通孔120與第二有效結合通孔220以及通過非金屬到非金屬結合而結合在一起的第一結合介電層116與第二結合介電層216。
圖2是根據本公開一些實施例的3DIC結構的剖視圖。圖2所示3DIC結構與圖1E所示3DIC結構相似，由此使用相同的參考編號來指代相同及類似的部件，且在本文中將省略其詳細說明。圖1E與圖2所示3DIC結構之間的差異在於結合通孔的位置。舉例來說，在圖1E所示實施例中，結合通孔(例如第一有效結合通孔120及第二有效結合通孔220)被設計成直接電性連接到內連 結構(例如第一內連結構106及第二內連結構206)。然而，在圖2所示實施例中，在3DIC結構10A中，第一有效結合通孔120設置在第一有效焊墊114上且電性連接到第一有效焊墊114，且通過第一有效焊墊114進一步電性連接到內連結構106。在一些實施例中，第一有效結合通孔120穿透第一有效焊墊114之上的第一結合介電層116且直接接觸第一有效焊墊114。第一有效結合通孔120的高度可介於1μm到5μm的範圍內。第一有效結合通孔120可通過單鑲嵌方法形成。舉例來說，在第一結合介電層116中形成通孔洞以暴露出第一有效焊墊114的一部分。接著，在通孔洞中形成第一有效結合通孔120以電性連接第一有效焊墊114。在一些實施例中，第二半導體結構200與第一半導體結構100相似。然而，本發明並非僅限於此。
在一些替代實施例中，如圖3所示，在3DIC結構10B中，第一結合結構115可包括位於第一結合介電層116中的多個第一有效結合通孔120a、120b。第一有效結合通孔120a可設置在第一內連結構106的第一金屬特徵110上且直接接觸第一內連結構106的第一金屬特徵110。第一有效結合通孔120b可設置在第一有效焊墊114上且直接接觸第一有效焊墊114。在一些實施例中，第一有效結合通孔120a從頂部到底部的高度大於第一有效結合通孔120b從頂部到底部的高度。第一有效結合通孔120a、120b的頂表面與第一結合介電層116的頂表面實質上齊平。在一些實施例中，第一有效結合通孔120a與第一有效結合通孔120b可利 用同一罩幕使用單鑲嵌方法同時形成。在單鑲嵌方法期間，使用第一有效焊墊114與第一金屬特徵110作為蝕刻停止層。在一些實施例中，第二結合結構215可與第一結合結構115相似。也就是說，第二結合結構215可包括位於第二結合介電層216中的多個第二有效結合通孔220a、220b。舉例來說，第二有效結合通孔220a可設置在第二內連結構206的第二金屬特徵210上且直接接觸第二內連結構206的第二金屬特徵210，且第二有效結合通孔220b可設置在第二有效焊墊214上且直接接觸第二有效焊墊214。在結合之後，第一有效結合通孔120a、120b可分別結合到第二有效結合通孔220a、220b。然而，本發明並非僅限於此。
圖4A到圖4E是根據本公開一些實施例的形成3DIC結構的方法的剖視圖。圖5是示出圖4D所示結構的俯視圖，其中省略了第一結合介電層116。圖4A到圖4E所示步驟與圖1A到圖1E所示步驟相似，由此使用相同的參考編號來指代相同及類似的部件，且在本文中將省略其詳細說明。圖4A到圖4E所示步驟與圖1A到圖1E所示步驟之間的差異在於虛設元件的形成且在以下進行闡述。
參照圖4A，提供第一晶粒101。在一些實施例中，舉例來說，第一晶粒101包括第一半導體基底102、第一裝置層104、第一內連結構106、多個第一虛設特徵130、第一鈍化層112及第一有效焊墊114。在一些實施例中，第一虛設特徵130形成在第一內連結構106的第一金屬特徵110旁邊。在本文中，當將元件闡 述為“虛設的”時，元件是電性浮置的或與其他元件電性隔離的。舉例來說，如圖4A所示，第一虛設特徵130是電性浮置的。
在一些實施例中，第一虛設特徵130與最頂部第一金屬特徵110處於實質上相同的水準高度。也就是說，第一虛設特徵130的頂部及最頂部第一金屬特徵110的頂部與第一絕緣材料108的頂表面實質上共面。在一些實施例中，第一虛設特徵130的材料與第一金屬特徵110的材料可為相同的。在一些替代實施例中，第一虛設特徵130的材料可與第一金屬特徵110的材料不同。在一些實施例中，第一虛設特徵130與第一金屬特徵110使用同一罩幕同時形成。在一些替代實施例中，第一虛設特徵130與第一金屬特徵110相繼形成。在一些實施例中，舉例來說，第一虛設特徵130的寬度可小於最頂部第一金屬特徵110的寬度。然而，在一些替代實施例中，第一虛設特徵130的寬度可實質上相同於或大於最頂部第一金屬特徵110的寬度。
在一些實施例中，如圖5所示，多個第一虛設特徵130及最頂部第一金屬特徵110可形成陣列，且舉例來說，多個第一虛設特徵130環繞最頂部第一金屬特徵110。也就是說，最頂部第一金屬特徵110可設置在由多個第一虛設特徵130及最頂部第一金屬特徵110所排列而成的陣列的中心處。在一些實施例中，在一方向(例如，x方向或y方向)上，第一虛設特徵130與最頂部第一金屬特徵110之間的距離D1可小於第一虛設特徵130之間的距離D2。然而，本發明並非僅限於此。在一些實施例中，舉例來 說，前述距離D1可介於3μm到10μm的範圍內。
參照圖4B，在第一晶粒101之上形成第一結合介電層116。接著，在第一結合介電層116之上形成罩幕層M，且罩幕層M包括多個開口OP1、OP2。開口OP1、OP2暴露出第一結合介電層116。在一些實施例中，開口OP1對應於最頂部第一金屬特徵110設置，且開口OP2對應於第一虛設特徵130設置。
參照圖4C，在第一結合介電層116及第一鈍化層112中形成通孔洞118及多個虛設通孔洞132。在一些實施例中，使用罩幕層M作為罩幕來移除由開口OP1、OP2暴露出的第一結合介電層116及第一鈍化層112的一些部分，從而形成通孔洞118及虛設通孔洞132。換句話說，通孔洞118與虛設通孔洞132可使用同一罩幕及單次移除製程同時形成。由於最頂部第一金屬特徵110及第一虛設特徵130的蝕刻選擇性相似且不同於第一結合介電層116及第一鈍化層112的蝕刻選擇性，因此移除製程可在最頂部第一金屬特徵110及第一虛設特徵130的頂部處停止。接著，移除罩幕層M。在一些實施例中，舉例來說，通孔洞118暴露出最頂部第一金屬特徵110，且虛設通孔洞132分別暴露出第一虛設特徵130。在一些實施例中，與前述實施例中所述的通孔洞118相似，虛設通孔洞132的整個側壁SW連續傾斜且未形成有轉折點或臺階。因此，虛設通孔洞132可具有實質上平滑的側壁SW。在一些實施例中，舉例來說，虛設通孔洞132的側壁SW可相對於虛設通孔洞132的底部及第一鈍化層112的底表面漸縮。在一些實施 例中，舉例來說，虛設通孔洞132的寬度可小於通孔洞118的寬度。然而，在一些替代實施例中，虛設通孔洞132的寬度可實質上相同於或大於通孔洞118的寬度。
參照圖4D，在通孔洞118及虛設通孔洞132中分別形成第一有效結合通孔120及多個第一虛設結合通孔134。在一些實施例中，第一虛設結合通孔134可與第一有效結合通孔120同時形成，且因此第一虛設結合通孔134可具有與第一有效結合通孔120相似的、實質上相同的或相同的配置。舉例來說，在一些實施例中，第一有效結合通孔120可具有阻障層122及金屬層124，且第一虛設結合通孔134可具有阻障層136及金屬層138。在一些實施例中，形成第一有效結合通孔120及第一虛設結合通孔134的方法可包括以下步驟。首先，在第一結合介電層116、通孔洞118及虛設通孔洞132的暴露出的表面之上形成阻障材料。接著，在阻障材料的頂表面之上形成金屬材料且金屬材料填充到通孔洞118及虛設通孔洞132中。之後，通過平坦化製程(例如CMP製程)移除通孔洞118及虛設通孔洞132外的阻障材料以及導電材料，且在通孔洞118及虛設通孔洞132中分別形成第一有效結合通孔120及第一虛設結合通孔134。在一些實施例中，第一有效結合通孔120與第一虛設結合通孔134利用同一罩幕來通過單鑲嵌製程形成。在一些實施例中，與前述實施例中所述的第一有效結合通孔120相似，第一虛設結合通孔134的整個側壁SW連續傾斜且未形成有轉折點或臺階。因此，第一虛設結合通孔134可具有實 質上平滑的側壁SW。在一些實施例中，舉例來說，第一虛設結合通孔134的側壁SW可相對於通孔洞118的底部及第一鈍化層112的底表面漸縮。
在一些實施例中，如圖4D及圖5所示，第一有效結合通孔120設置在第一內連結構106的最頂部第一金屬特徵110上且電性連接到第一內連結構106的最頂部第一金屬特徵110，且第一虛設結合通孔134分別設置在第一虛設特徵130上且與第一內連結構106電性隔離。在一些實施例中，第一虛設結合通孔134可電性連接到電性浮置的第一虛設特徵130。在一些實施例中，舉例來說，第一虛設結合通孔134的寬度可小於第一有效結合通孔120的寬度。然而，在一些替代實施例中，第一虛設結合通孔134的寬度可實質上相同於或大於第一有效結合通孔120的寬度。
在一些實施例中，如圖5所示，多個第一虛設結合通孔134及第一有效結合通孔120可配置成陣列，且舉例來說，多個第一虛設結合通孔134環繞第一有效結合通孔120。也就是說，第一有效結合通孔120可設置在由多個第一虛設結合通孔134及第一有效結合通孔120所排列而成的陣列的中心處。在一些實施例中，在一方向(例如，x方向或y方向)上，第一虛設結合通孔134與第一有效結合通孔120之間的距離D3可小於第一虛設結合通孔134之間的距離D4。然而，本發明並非僅限於此。在一些實施例中，舉例來說，前述距離D3可介於1μm到8μm的範圍內。在一些實施例中，通過將第一虛設結合通孔134設計在第一有效結合 通孔120旁邊，可減小在形成第一有效結合通孔120期間平坦化製程的負載效應。
在第一結合介電層116中形成第一有效結合通孔120及第一虛設結合通孔134之後，形成第一結合結構115。在一些實施例中，如圖4D所示，完成第一半導體結構100，第一半導體結構100包括第一晶粒101及第一結合結構115。
參照圖4E，提供第二半導體結構200並將第二半導體結構200結合到圖4D所示第一半導體結構100。在一些實施例中，第二半導體結構200包括第二晶粒201及第二結合結構215。在一些實施例中，第二晶粒201可與第一晶粒101相似，且第二結合結構215可與第一結合結構115相似。舉例來說，第二虛設結合通孔234分別設置在第二虛設特徵230上且電性連接到第二虛設特徵230，且第二有效結合通孔220設置在最頂部第二金屬特徵210上且電性連接到最頂部第二金屬特徵210。在一些實施例中，第二虛設結合通孔234可具有阻障層236及金屬層238。
在一些實施例中，通過混合結合將第一晶粒101與第二晶粒201結合在一起以形成3DIC結構10C。在一些實施例中，如圖4E所示，混合結合結構15包括通過金屬到金屬結合而結合在一起的第一有效結合通孔120與第二有效結合通孔220及第一虛設結合通孔134與第二虛設結合通孔234以及通過非金屬到非金屬結合而結合在一起的第一結合介電層116與第二結合介電層216。
圖6A是根據本公開一些實施例的3DIC結構的剖視圖，且圖6B是3DIC結構中的第一結合通孔、第一虛設結合通孔、第一焊墊以及第一虛設焊墊的俯視圖。圖6A及圖6B所示3DIC結構與圖4E及圖5所示3DIC結構相似，由此使用相同的參考編號來指代相同及類似的部件，且在本文中將省略其詳細說明。圖6A及圖6B所示3DIC結構與圖4E及圖5所示3DIC結構之間的差異在於結合通孔的位置及虛設焊墊的形成。舉例來說，在圖4E及圖5所示實施例中，結合通孔(例如第一有效結合通孔120及第二有效結合通孔220)及虛設結合通孔(例如第一虛設結合通孔134及第二虛設結合通孔234)被設計成電性連接到內連結構(例如第一內連結構106及第二內連結構206)及虛設特徵(例如第一虛設特徵130及第二虛設特徵230)。然而，在圖6A及圖6B所示實施例中，在3DIC結構10D中，第一半導體結構100還包括位於第一有效焊墊114旁邊的多個第一虛設焊墊140。第一有效焊墊114電性連接到第一內連結構106，而第一虛設焊墊140是電性浮置的且與第一晶粒101隔離。在一些實施例中，第一虛設焊墊140與第一有效焊墊114處於實質上相同的水準高度。也就是說，第一虛設焊墊140的頂部與第一有效焊墊114的頂部彼此實質上共面。在一些替代實施例中，可省略虛設特徵130。
在一些實施例中，第一有效結合通孔120設置在第一有效焊墊114上且電性連接到第一有效焊墊114，且第一虛設結合通孔134分別設置在第一虛設焊墊140上且與第一晶粒101電性隔 離。在一些實施例中，第一虛設焊墊140的材料可包括金屬材料，例如鋁、銅、鎳、金、銀、鎢或其組合。在一些實施例中，第一虛設焊墊140的材料可相對於在第一有效結合通孔120及第一虛設結合通孔134的通孔洞的形成過程中使用的蝕刻劑具有與第一有效焊墊114的材料相似的蝕刻選擇性。在一些實施例中，第一虛設焊墊140與第一有效焊墊114同時形成。在一些替代實施例中，第一虛設焊墊140與第一有效焊墊114相繼形成。在一些實施例中，舉例來說，第一虛設焊墊140的寬度可小於第一有效焊墊114的寬度。然而，在一些替代實施例中，第一虛設焊墊140的寬度可實質上相同於或大於第一有效焊墊114的寬度。
在一些實施例中，如圖6B所示，多個第一虛設焊墊140及第一有效焊墊114可配置成陣列，且舉例來說，多個第一虛設焊墊140環繞第一有效焊墊114。也就是說，第一有效焊墊114可設置在由多個第一虛設焊墊140及第一有效焊墊114所排列而成的陣列的中心中。在一些實施例中，第一虛設焊墊140與第一有效焊墊114之間的距離可實質上小於第一虛設焊墊140之間的距離。然而，本發明並非僅限於此。在一些實施例中，舉例來說，第一虛設焊墊140與第一有效焊墊114之間的距離可介於1μm到8μm的範圍內。在一些實施例中，第二半導體結構200與第一半導體結構100相似。也就是說，第二半導體結構200上具有多個第二虛設焊墊240及多個第二虛設結合通孔234。然而，本發明並非僅限於此。在一些實施例中，如圖6A所示，混合結合結構15 包括通過金屬到金屬結合而結合在一起的第一有效結合通孔120與第二有效結合通孔220及第一虛設結合通孔134與第二虛設結合通孔234以及通過非金屬到非金屬結合而結合在一起的第一結合介電層116與第二結合介電層216。
在一些實施例中，穿透結合介電層的結合通孔通過單鑲嵌方法形成。換句話說，用於結合通孔的通孔洞僅利用一個罩幕而通過單次移除製程形成。因此，與上面包括結合通孔及結合焊墊的傳統的導電結合結構相比，不需要用於形成結合焊墊的製程及罩幕。因此，簡化了形成結合結構的製程並降低了形成結合結構的成本。另外，在一些實施例中，為改善製程控制，可在結合通孔旁邊形成多個虛設結合通孔。此外，可在虛設結合通孔下面形成多個虛設元件(例如虛設特徵或虛設焊墊)，且在形成虛設結合通孔期間使用所述多個虛設元件作為蝕刻停止層。在一些實施例中，虛設結合通孔可使用同一罩幕與結合通孔同時形成，且因此時間及成本不會顯著增加。
根據一些實施例，一種製造半導體結構的方法包括以下步驟。提供第一晶粒，其中所述第一晶粒包括第一基底、第一內連結構以及第一焊墊，所述第一內連結構位於所述第一基底之上，所述第一焊墊設置在所述第一內連結構之上且電性連接到所述第一內連結構。在所述第一晶粒之上形成第一結合介電層以覆蓋所述第一晶粒。使用單鑲嵌製程形成穿透所述第一結合介電層的第一結合通孔以電性連接所述第一內連結構。
根據一些實施例，其中形成所述第一結合通孔包括：在所述第一結合介電層之上形成罩幕層，其中所述罩幕層具有開口以暴露出所述第一結合介電層的一部分；使用所述罩幕層作為罩幕來部分地移除所述第一結合介電層，以形成通孔洞；移除所述罩幕層；在所述通孔洞中形成導電材料；以及移除所述通孔洞外的所述導電材料。
根據一些實施例，其中所述第一結合通孔直接接觸所述第一內連結構。
根據一些實施例，其中所述第一結合通孔直接接觸所述第一焊墊。
根據一些實施例，其中所述第一結合通孔未形成有轉折點。
根據一些實施例，還包括：提供第二晶粒，其中所述第二晶粒上具有第二結合通孔及第二結合介電層；以及通過將所述第一結合通孔與所述第二結合通孔結合在一起以及將所述第一結合介電層與所述第二結合介電層結合在一起來對所述第一晶粒與所述第二晶粒進行結合。
根據一些實施例，一種製造半導體結構的方法包括以下步驟。形成第一晶粒，其中所述第一晶粒包括第一基底、第一內連結構及第一有效焊墊，所述第一內連結構位於所述第一基底之上，所述第一有效焊墊設置在所述第一內連結構之上且電性連接到所述第一內連結構。在所述第一晶粒之上形成第一結合介電層 以覆蓋所述第一晶粒。使用單次移除製程形成分別穿透所述結合介電層的通孔洞及至少一個虛設通孔洞。在所述通孔洞及所述至少一個虛設通孔洞中分別形成第一有效結合通孔及至少一個第一虛設結合通孔，其中所述第一有效結合通孔電性連接到所述第一內連結構，且所述至少一個第一虛設結合通孔是電性浮置的。
根據一些實施例，其中形成所述通孔洞及所述至少一個虛設通孔洞還包括：在所述第一結合介電層之上形成罩幕層，其中所述罩幕層具有多個開口以暴露出所述第一結合介電層的一些部分；以及使用所述罩幕層作為罩幕，通過所述單次移除製程部分地移除所述第一結合介電層以同時形成所述通孔洞及所述至少一個虛設通孔洞。
根據一些實施例，其中所述第一有效結合通孔與所述至少一個第一虛設結合通孔是同時形成的。
根據一些實施例，其中所述通孔洞暴露出所述第一內連結構。
根據一些實施例，還包括：形成至少一個第一虛設特徵，所述至少一個第一虛設特徵設置在所述第一內連結構旁邊且與所述第一內連結構電性隔離，其中所述至少一個第一虛設結合通孔連接到所述至少一個第一虛設特徵。
根據一些實施例，其中所述通孔洞暴露出所述第一有效焊墊。
根據一些實施例，還包括形成至少一個第一虛設焊墊， 所述至少一個第一虛設焊墊設置在所述第一有效焊墊旁邊且與所述第一內連結構電性隔離，其中所述至少一個虛設通孔洞暴露出所述至少一個第一虛設焊墊。
根據一些實施例，還包括：提供第二晶粒；在所述第二晶粒之上形成第二有效結合通孔、至少一個第二虛設結合通孔及第二結合介電層，其中所述第二有效結合通孔電性連接到所述第二晶粒，且所述至少一個第二虛設結合通孔是電性浮置的；以及通過將所述第一有效結合通孔與所述第二有效結合通孔結合在一起、將所述至少一個第一虛設結合通孔與所述至少一個第二虛設結合通孔結合在一起以及將所述第一結合介電層與所述第二結合介電層結合在一起來對所述第一晶粒與所述第二晶粒進行結合。
根據一些實施例，提供一種半導體結構且所述半導體結構包括第一晶粒以及第二晶粒。所述第一晶粒包括位於所述第一晶粒上的第一結合介電層及位於所述第一結合介電層中的第一有效結合通孔。所述第二晶粒包括位於所述第二晶粒上的第二結合介電層及位於所述第二結合介電層中的第二有效結合通孔。通過將所述第一有效結合通孔與所述第二有效結合通孔結合在一起以及將所述第一結合介電層與所述第二結合介電層結合在一起來對所述第一晶粒與所述第二晶粒進行結合。所述第一有效結合通孔穿透所述第一結合介電層，且所述第一有效結合通孔具有從所述第一有效結合通孔的頂部到底部的連續傾斜的側壁。
根據一些實施例，其中所述連續傾斜的側壁不具有轉折 點。
根據一些實施例，其中所述第一有效結合通孔設置在所述第一晶粒的第一焊墊上且接觸所述第一晶粒的所述第一焊墊，並且所述第一焊墊設置在所述第一晶粒的第一內連結構之上且電性連接到所述第一晶粒的所述第一內連結構。
根據一些實施例，其中所述第一有效結合通孔設置在所述第一晶粒的第一內連結構上且接觸所述第一晶粒的所述第一內連結構。
根據一些實施例，還包括位於所述第一有效結合通孔旁邊的至少一個第一虛設結合通孔以及位於所述第二有效結合通孔旁邊的至少一個第二虛設結合通孔，其中所述至少一個第一虛設結合通孔設置在所述第一結合介電層中且是電性浮置的，並且所述至少一個第二虛設結合通孔設置在所述第二結合介電層中且是電性浮置的。
根據一些實施例，其中所述至少一個第一虛設結合通孔結合到所述至少一個第二虛設結合通孔。
以上概述了若干實施例的特徵，以使所屬領域中的技術人員可更好地理解本公開的各個方面。所屬領域中的技術人員應知，他們可容易地使用本公開作為設計或修改其他製程及結構的基礎來施行與本文中所介紹的實施例相同的目的和/或實現與本文中所介紹的實施例相同的優點。所屬領域中的技術人員還應認識到，這些等效構造並不背離本公開的精神及範圍，而且他們可在 不背離本公開的精神及範圍的條件下對其作出各種改變、代替及變更。
10：三維積體電路（3DIC）結構 15：混合結合結構 100、200：半導體結構 101、201：晶粒 102、202：半導體基底 104、204：裝置層 106、206：內連結構 108、208：絕緣材料 110、210：金屬特徵 112、212：鈍化層 114、214：有效焊墊 115、215：結合結構 116、216：結合介電層 120、220：有效結合通孔 122、222：阻障層 124、224：金屬層

Claims (10)

  1. 一種製造半導體結構的方法，包括：提供第一晶粒，其中所述第一晶粒包括第一基底、第一內連結構以及第一焊墊，所述第一內連結構位於所述第一基底之上，所述第一焊墊設置在所述第一內連結構之上且電性連接到所述第一內連結構；在所述第一晶粒之上形成第一結合介電層，以覆蓋所述第一晶粒；以及使用單鑲嵌製程形成穿透所述第一結合介電層的第一有效結合通孔，以電性連接所述第一內連結構；以及在所述第一結合介電層中形成多個第一虛設結合通孔，其中所述第一虛設結合通孔環繞所述第一有效結合通孔且電性浮置。
  2. 如申請專利範圍第1項所述的方法，其中形成所述第一有效結合通孔包括：在所述第一結合介電層之上形成罩幕層，其中所述罩幕層具有開口以暴露出所述第一結合介電層的一部分；使用所述罩幕層作為罩幕來部分地移除所述第一結合介電層，以形成通孔洞；移除所述罩幕層；在所述通孔洞中形成導電材料；以及移除所述通孔洞外的所述導電材料。
  3. 如申請專利範圍第1項所述的方法，其中所述第一有效結合通孔直接接觸所述第一內連結構。
  4. 如申請專利範圍第1項所述的方法，其中所述第一有效結合通孔直接接觸所述第一焊墊。
  5. 如申請專利範圍第1項所述的方法，其中所述第一有效結合通孔未形成有轉折點。
  6. 如申請專利範圍第1項所述的方法，還包括：提供第二晶粒，其中所述第二晶粒上具有第二結合通孔及第二結合介電層；以及通過將所述第一有效結合通孔與所述第二結合通孔結合在一起以及將所述第一結合介電層與所述第二結合介電層結合在一起來對所述第一晶粒與所述第二晶粒進行結合。
  7. 一種製造半導體結構的方法，包括：提供第一晶粒，其中所述第一晶粒包括第一基底、第一內連結構及第一有效焊墊，所述第一內連結構位於所述第一基底之上，所述第一有效焊墊設置在所述第一內連結構之上且電性連接到所述第一內連結構；形成多個第一虛設焊墊，所述第一虛設焊墊設置在所述第一有效焊墊旁邊且與所述第一內連結構電性隔離；在所述第一晶粒之上形成第一結合介電層，以覆蓋所述第一晶粒； 使用單次移除製程形成分別穿透所述第一結合介電層的通孔洞及多個虛設通孔洞，其中所述通孔洞暴露所述第一有效焊墊，且所述虛設通孔洞暴露出所述第一虛設焊墊；在所述通孔洞及所述虛設通孔洞中分別形成第一有效結合通孔及多個第一虛設結合通孔，其中所述第一有效結合通孔電性連接到所述第一內連結構，且所述第一虛設結合通孔是電性浮置的，其中所述第一虛設結合通孔環繞所述第一有效結合通孔。
  8. 如申請專利範圍第7項所述的方法，其中形成所述通孔洞及所述虛設通孔洞還包括：在所述第一結合介電層之上形成罩幕層，其中所述罩幕層具有多個開口以暴露出所述第一結合介電層的一些部分；以及使用所述罩幕層作為罩幕，通過所述單次移除製程部分地移除所述第一結合介電層以同時形成所述通孔洞及所述虛設通孔洞。
  9. 如申請專利範圍第7項所述的方法，其中所述第一有效結合通孔與所述第一虛設結合通孔是同時形成的。
  10. 一種半導體結構，包括：第一晶粒，包括第一內連結構、第一有效焊墊、多個第一虛設焊墊以及位於所述第一晶粒上的第一結合介電層以及位於所述第一結合介電層中的第一有效結合通孔及第一虛設結合通孔，其中所述第一有效結合通孔藉由所述第一有效焊墊與所述第一內連結構電性連接，所述第一虛設結合通孔與所述第一虛設焊墊電性 連接並與所述第一內連結構電性隔離，所述第一虛設結合通孔環繞所述第一有效結合通孔，所述第一虛設焊墊環繞所述第一有效結合通孔。
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