TW201533868A - 半導體裝置與接合半導體裝置的方法 - Google Patents

半導體裝置與接合半導體裝置的方法 Download PDF

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TW201533868A
TW201533868A TW103144819A TW103144819A TW201533868A TW 201533868 A TW201533868 A TW 201533868A TW 103144819 A TW103144819 A TW 103144819A TW 103144819 A TW103144819 A TW 103144819A TW 201533868 A TW201533868 A TW 201533868A
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layer
protective layer
barrier layer
sub
semiconductor device
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TW103144819A
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TWI569389B (zh
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Ping-Yin Liu
Hsun-Chung Kuang
Cheng-Tai Hsiao
Xin-hua HUANG
Lan-Lin Chao
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Taiwan Semiconductor Mfg Co Ltd
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Abstract

一種半導體裝置與其製備方法。在部分實施方式中，一或多個保護層形成於一第一基板上。接著形成凹陷於保護層中，再形成一或多個導電墊於凹陷中。一或多個阻障層位於保護層與導電墊之間。其中，第一基板的導電墊對準第二基板的導電墊，且第一基板以直接接合方式與第二基板接合。

Description

晶圓接合結構與其製備方法
本發明是有關一種晶圓接合結構，與製備此晶圓接合結構的方法。
半導體製造業正面臨持續的挑戰，以符合摩爾定律(Moore’s Law)。半導體製造業持續努力以增加元件密度、線路密度與操作頻率，並使特徵尺寸(例如，主動元件與被動元件的尺寸)、內連線路的寬度與厚度、以及功率消耗不斷縮減。相對於習用的封裝體，應用中此些較小的電子元件亦需形成較小的封裝體，以縮減面積。
三維立體封裝(three dimensional integrated circuits,3DICs)是最近發展中的半導體封裝技術，其係以多個半導體晶片相互堆疊，例如：堆疊式封裝(package on package)或系統級封裝(system in package)技術。形成三維立體封裝的方法包含接合二或多個半導體晶圓，而主動電路，例如：邏輯、記憶體、處理器等位於不同的半導體晶圓中。常使用的接合技術包含直接接合、化學活化接合、電漿活化接合、陽極接合、共晶接合、玻璃介質接合、附著接合、 熱壓接合、反應性接合、或其他合適的接合方式。在二個半導體晶圓接合後，半導體晶圓之間的介面能提供導電路徑予堆疊的半導體晶圓。
使用堆疊的半導體元件之好處在於，其可達到 較高的元件密度。此外，堆疊的半導體元件可具有到較小的形狀因素(form factor)與高成本效益，並提高性能及達到更低的功耗。
本發明之一態樣係提供一種半導體裝置，包含一第一基板，且一第一介電層位於第一基板上；一第一保護層覆蓋第一介電層，且第一保護層具有一第一凹陷；一第一阻障層覆蓋第一凹陷的側壁；以及一第一外部接觸墊位於第一凹陷中，第一阻障層位於第一外部接觸墊與第一保護層之間。
根據本發明一或多個實施方式，第一保護層包含一第一子保護層，包含未摻雜矽玻璃；一第二子保護層，包含氮化矽；一第三子保護層，包含未摻雜矽玻璃；以及一第四子保護層，包含氮氧化矽。
根據本發明一或多個實施方式，第一阻障層包含一第一子阻障層，包含氮化鉭；以及一第二子阻障層，包含鈷、鎳或鐵。
本發明之另一態樣係提供一種半導體裝置，包含一第一結構，以及一第二結構直接接合至第一結構。第一結構包含一第一基板；一第一保護層位於第一基板上；複數個 第一導電墊位於第一保護層中；以及一第一阻障層位於此些第一導電墊與第一保護層之間，且第一阻障層包含一第一子阻障層與一第二子阻障層。第二結構則包含一第二基板；一第二保護層位於第二基板上；複數個第二導電墊位於第二保護層中；以及一第二阻障層位於此些第二導電墊與第二保護層之間，且第二阻障層包含一第三子阻障層與一第四子阻障層。第一結構接合至第二結構，以令使此些第一導電墊與此些第二導電墊對應排列。
根據本發明一或多個實施方式，第一阻障層與 此些第一導電墊之間的一還原電位差介於約-1伏特至約+1伏特之間。
本發明之另一態樣係提供一種接合半導體裝置的 方法，包含下列步驟。先提供一第一基板，並形成一第一保護層於第一基板上。接著，形成一第一凹陷於第一保護層中，更形成一第一阻障層於第一凹陷中。最後形成一第一導電墊於第一保護層的第一凹陷中，以令使第一阻障層位於第一導電墊與第一保護層之間。
根據本發明一或多個實施方式，接合半導體裝 置的方法，更包含下列步驟。先提供一第二基板，並形成第二保護層於第二基板上。接著，形成一第二凹陷於第二保護層中，更形成一第二阻障層於第二凹陷中。最後形成一第二導電墊於第二保護層的第二凹陷中，以令使第二阻障層位於第二導電墊與第二保護層之間。
根據本發明一或多個實施方式，更使用一介電 質-介電質直接接合方式接合第一介電層與第二介電層。
根據本發明一或多個實施方式，更使用一金屬-金屬直接接合方式接合第一導電墊與第二導電墊。
根據本發明一或多個實施方式，更進行退火，其中退火的溫度介於250℃至約400℃之間，而退火的時間介於約0.5小時至約4小時之間。
100‧‧‧第一晶圓
101‧‧‧基板
103‧‧‧元件
105‧‧‧層間介電層
107‧‧‧金屬層
1071‧‧‧金屬層
109‧‧‧保護層
111‧‧‧第一保護層
113‧‧‧第二保護層
115‧‧‧第三保護層
117‧‧‧第四保護層
119‧‧‧第一開口
201‧‧‧第一阻障層
301‧‧‧金屬層
203‧‧‧第一子阻障層
205‧‧‧第二子阻障層
401‧‧‧第一接合墊
403‧‧‧第二接合墊
405‧‧‧第一孔洞
500‧‧‧第二晶圓
501‧‧‧第三接合墊
503‧‧‧第四接合墊
601‧‧‧內金屬介電層
603‧‧‧第二開口
605‧‧‧導電元件
701‧‧‧第二阻障層
703‧‧‧第三子阻障層
705‧‧‧第四子阻障層
801‧‧‧金屬材料
901‧‧‧內連線結構
903‧‧‧金屬線
905‧‧‧連通柱
907‧‧‧第二孔洞
1001-1009‧‧‧步驟
為讓本發明之上述和其他目的、特徵、優點與實施例能更明顯易懂，在閱讀下述的說明書時請參照所附圖式。值得注意的是，根據業界的標準做法，各種特徵並非按比例繪製。事實上為清楚說明，此些特徵的尺寸可任意放大或縮小。
第1-5圖繪示本發明之部分實施方式中，晶圓接合製程在各個階段的剖面圖；第6-9圖繪示本發明之部分實施方式中，金屬層的形成方法在各個階段的剖面圖；以及第10圖為本發明之部分實施方式中，晶圓接合方法的流程圖。
下述揭露內容提供許多不同的實施例或範例，用於實施本發明的不同特徵。元件與排列的具體實例方式描述如下以簡化本揭露內容。這些當然僅為示例，並且不用於限制本 揭露內容。例如，說明書中所述第一特徵形成於第二特徵上可包含第一特徵與第二特徵直接接觸的實施例，或亦可包含其他特徵形成於第一與第二特徵之間的實施例，從而使得第一與第二特徵可未直接接觸。此外，本揭露內容可在各種示例中重複元件符號。重複的目的是為了簡化和清楚說明，並不代表討論的各種實施例和/或配置之間的關係。
此外，相對詞彙，如『下』或『底部』與『上』 或『頂部』，用來描述文中在附圖中所示的一元件與另一元件之關係。相對詞彙是用來描述裝置在附圖中所描述之外的不同方位是可以被理解的。例如，如果一附圖中的裝置被翻轉，元件將會被描述原為位於其它元件之『下』側將被定向為位於其他元件之『上』側。例示性的詞彙『下』，根據附圖的特定方位可以包含『下』和『上』兩種方位。同樣地，如果一附圖中的裝置被翻轉，元件將會被描述原為位於其它元件之『下方』或『之下』將被定向為位於其他元件上之『上方』。例示性的詞彙『下方』或『之下』，可以包含『上方』和『上方』兩種方位。
接著將以實施例詳細說明本揭露內容之特定範 圍，即一種晶圓接合方法。此後，請參照附圖以理解本揭露內容的各種實施方式。
請先參閱第1圖，第1圖繪示一第一晶圓100的 局部剖面圖。第一晶圓100可包含一基板101、元件103位於基板101上、一層間介電(interlayer dielectric,ILD)層105位於元件103上、一或多層金屬層107位於層間介電 層105上，以及一保護層109位於金屬層107上。基板101可包含摻雜或非摻雜的塊狀矽基板，或為絕緣層覆矽基板(silicon-on-insulator,SOI)的活性層。通常絕緣層覆矽基板具有一半導體材料層，包含矽、鍺、矽化鍺、絕緣層覆矽、絕緣層覆矽化鍺(silicon germanium on insulator,SGOI)、或上述之組合。亦可使用其他合適的基板，例如多層基板、梯度基板或混合定向基板。
第1圖所示的元件103可為一單晶體。然而，元 件103可包含各種主動元件或被動元件，例如：電晶體、二極體、電容、電阻、電感或其他合適的元件，以符合第一晶圓100設計所需的結構和功能需求。元件103可以任何合適的方法形成於基板101的表面上或表面中，或者形成於覆蓋在基板101上的介電層中。所屬領域具有通常知識者應理解上述實例僅用於說明目的，以進一步解釋說明性實施例的應用方式，並不意味著以任何方式限定本揭露內容。
層間介電層105形成於基板101與元件103 上，其係用於隔離元件103與金屬層107。層間介電層105可包含二氧化矽、低介電常數(low-K)材料(指介電常數低於二氧化矽的材料)，例如：氮氧化矽、磷矽酸鹽玻璃(phosphosilicate glass,PSG)、硼磷矽酸鹽玻璃(borophosphosilicate glass,BPSG)、氟矽玻璃(fluorinated silicate glass,FSG)、碳化矽玻璃(organosilicate glasses,OSG)、碳摻雜玻璃(SiOxCy)、旋塗式玻璃(Spin-On-Glass)、旋塗式高分子 (Spin-On-Polymers)、碳矽化物材料、上述的化合物、上述的複合物、上述之組合、或其他合適的材料。並使用合適的方法沉積此些材料，例如旋塗、化學氣相沉積(CVD)、電漿加強化學氣相沉積(plasma-enhanced CVD,PECVD)、或其他合適的方式。此外，亦可使用上述材料的多孔洞形態。上述提供的材料與製程係用於示例，亦可使用其他的材料與製程。
金屬層107形成於層間介電層105上，其連接至 元件103並形成功能性電路。雖然第1圖繪示單層金屬層107，但金屬層107可以交替的介電材料與導電材料形成多層結構，且能以任何合適的方式形成金屬層107(例如：沉積、金屬鑲嵌法、雙層金屬鑲嵌法等)。金屬層107的層數可視第一晶圓100的設計而定。
值得注意的是，一或多個蝕刻終止層(未繪示) 可位於相鄰層間，舉例來說，位於層間介電層105與基板101之間。在形成穿孔或/及導電接觸時，蝕刻終止層通常用於停止蝕刻製程。蝕刻終止層係以介電材料製成，並具有與相鄰層(在蝕刻終止層上的層間介電層105與在蝕刻終止層下的基板101)不同的蝕刻選擇比。在本發明之部分實施例中，蝕刻終止層之材質可為氮化矽、氮碳化矽、氧碳化矽、氮化碳、上述之組合、或任何合適的材料。且可使用化學氣相沉積(CVD)或電漿加強化學氣相沉積技術沉積蝕刻終止層。
保護層109形成於第一晶圓100上。保護層109 可為單層或多層結構，包含二氧化矽、未摻雜的矽玻璃(undoped silicon glass,USG)、氮氧化矽、磷矽酸鹽玻璃、氮化矽、上述的化合物、上述的複合物、上述之組合、或其他合適的材料。可以任何合適的方式沉積此些材料，例如旋塗、化學氣相沉積(CVD)、電漿加強化學氣相沉積(plasma-enhanced CVD,PECVD)、或其他合適的方式。 此些材料與製程係用於示例，亦可使用其他的材料與製程。
在本發明之部分實施例中，保護層109可為一 複合結構，包含未摻雜的矽玻璃構成的一第一保護層111、由氮化矽構成的一第二保護層113、由未摻雜的矽玻璃構成的一第三保護層115、以及由氮氧化矽構成的一第四保護層117。上述的任何一層均亦可作為蝕刻終止層。所屬領域具有通常知識者應理解上述實例僅用於說明目的，而保護層109的層數以及使用的材料可視第一晶圓100的規格而變化。
微影蝕刻技術可用於圖案化保護層109。通常 形成一光阻層(未繪示)於保護層109上，接著紫外光或準分子雷射(excimer laser)通過一光罩(未繪示)以曝光光阻層，其中光罩上具有預定圖案。然後進行烘烤與固化操作，並視使用的正型光阻或負型光阻而定，以顯影劑移除光阻層的曝光區或非曝光區。藉此，形成一圖案於光阻層，其係用於形成複數個第一開口119於保護層109中。此處所述用於形成多個第一開口119之特定圖案僅用於說明目的，應理解可視第一晶圓100的設計需求來形成其他圖案。
請繼續參閱第1圖，蝕刻保護層109，舉例來 說，使用非等向性乾蝕刻製程移除保護層109的暴露部分，而蝕刻後形成複數個第一開口119於保護層109中。多種蝕刻製程均可用於蝕刻保護層109的各層。接著，搭配使用一灰化製程與一濕清洗製程以移除光阻層。舉例來說，在上述的實施方式中，保護層109包含未摻雜的矽玻璃構成的一第一保護層111、由氮化矽構成的一第二保護層113、由未摻雜的矽玻璃構成的一第三保護層115、以及由氮氧化矽構成的一第四保護層117，蝕刻製程可包含使用六氟化硫(SF6)電漿進行的反應性離子蝕刻製程。
更詳細的說，此些第一開口119在後續製程中 會形成接合墊(bonding pad)，且此些接合墊包含合適的金屬材料。接合墊的形成方式包含使用合適的沉積製程來形成晶種層(seed layer)與阻障層，或電鍍製程來形成塊狀金屬。此些接合墊在後續製程中用於接合不同的晶圓，並作為接合的晶圓上元件之間的金屬接觸(metallic contact)。
第2圖繪示形成一第一阻障層201於保護層109 的第一開口119的步驟。第一阻障層201在後續製程中形成導電材料於第一開口119時，能防止導電材料擴散進入保護層109中，減少金屬中毒(metallic poisoning)的機會。形成的第一阻障層201可為單層結構或多層結構，其可包含鈦、氮化鈦、鉭、氮化鉭、鈷、或其他合適的材料。且可使用化學氣相沉積、物理氣相沉積、或其他合適的方法來形成阻障層。
在本發明之部分實施例中，第一阻障層201可 包含一第一子阻障層203與一第二子阻障層205。在本發明之其他部分實施例中，第一子阻障層203係以氮化鉭構成，且第一子阻障層203的一第一厚度小於約500埃，例如250埃。第二子阻障層205係以鈷構成，且第二子阻障層205的一第二厚度小於約100埃。所屬領域具有通常知識者應理解的是，說明書中列舉的尺寸係對應至特定的技術節點(technology node)，而此些尺寸可隨著技術節點的縮放而增減。在本發明之部分實施例中，第一子阻障層203係以氮化鉭構成，而第二子阻障層205鎳構成。在本發明之其他部分實施例中，第一子阻障層203係以氮化鉭構成，而第二子阻障層205係以鐵構成。
請繼續參閱第3圖，沉積一金屬層301填充至保 護層109的第一開口119，以形成接合墊。金屬層301可包含銅、銀、金、鎢、鋁、或其他合適的材料，且可使用用化學氣相沉積、物理氣相沉積、電漿加強化學氣相沉積、電鍍、或其他合適的方式來沉積金屬層301。
請接著參閱第4圖，利用化學機械研磨來移除保護層109之上表面上多餘的第一阻障層201與金屬層301。在化學機械研磨製程中，係搭配使用高腐蝕性的化學物，例如酸與鹼，與小磨料顆粒，以將多餘的材料分別以化學與機械方式移除。殘留於第一開口119中的金屬材料形成第一接合墊401與第二接合墊403。
接著，清潔與活化第一晶圓100的表面，以準 備進行第一晶圓100的接合。表面清潔係用於移除第一晶圓100表面的化學機械研磨漿與原生氧化層。表面清潔製程可直接與不直接接觸第一晶圓的表面，例如低溫清潔、機械式擦拭與洗滌(mechanical wiping and scrubbing)、氣體，電漿或液體蝕刻、超音波震盪與清潔、雷射清潔、或其他合適的方式。接著，可以去離子水清洗第一晶圓100，並使用旋轉乾燥器或異丙醇乾燥器來乾燥第一晶圓100。在本發明之其他實施例中，可使用RCA清潔技術或其他合適的方式來清潔第一晶圓100。
表面活化係用以準備進行第一晶圓100的接 合。可使用任何合適的方式進行表面活化製程，例如電漿蝕刻或濕蝕刻，以移除在晶圓清洗製程後形成於第一晶圓100表面的原生氧化物。在本發明之部分實施例中，接合墊可包含銅，並使用檸檬酸移除接合墊表面的氧化銅。接著，以去離子水清洗第一晶圓100，並使用旋轉乾燥器或異丙醇乾燥器來乾燥第一晶圓100。
請繼續參閱第4圖。如第4圖所示，複數個第一 孔洞405形成於第一接合墊401與第二接合墊403中，且此些第一孔洞405位於接合墊與第一阻障層201的介面。在化學機械研磨、晶圓清洗、晶圓活化製程時，接合墊產生電化侵蝕(galvanic corrosion)而形成此些第一孔洞405。為減少此些第一孔洞405的尺寸，第一子阻障層203、第二子阻障層205與接合墊選用的材質使第一阻障層201與接合墊之間的一還原電位差介於約-1伏特至約+1伏特之間。在本發 明之部分實施例中，第一孔洞405的尺寸小於約500埃。
請參閱第5圖，第一晶圓100接合至一第二晶圓 500。在本發明之部分實施例中，繪示的第二晶圓500之結構與第一晶圓100相似。然而，所屬領域具有通常知識者應理解上述實例僅用於說明目的，以進一步解釋說明性實施例的應用方式，並不意味著以任何方式限定本揭露內容。在本發明之其他部分實施例中，第二晶圓500可包含與第一晶圓100不同的元件與電路。在本發明之其他部分實施例中，第一晶圓100係以互補式金屬氧化物半導體(complementary metal oxide semiconductor,CMOS)製程製備，而第二晶圓500係以微機電系統(micro electrical mechanical system,MEMS)製程製備。
在本發明之部分實施例中，第一晶圓100可以 任何方式與第二晶圓500接合，例如：直接接合製程，如金屬-金屬接合(銅-銅接合)、介電質-介電質接合(氧化物-氧化物接合)、金屬-介電質接合(銅-氧化物接合)、混合接合(同時使用金屬-金屬接合與介電質-介電質接合)、上述的組合、或其他合適的接合方式。舉例來說，第一晶圓100可使用混合接合方式與第二晶圓500接合，其中第一晶圓100中的第一接合墊401與第二接合墊403係分別對準第二晶圓500中的第三接合墊501與第四接合墊503。接著，將第一晶圓100與第二晶圓500的表面置於室溫、常壓與大氣環境物理接觸，使第一接合墊401與第三接合墊501，以及第二接合墊403與第四接合墊503以金屬-金屬直接接合方式進 行接合。同時，第一晶圓100與第二晶圓500中的保護層亦以介電質-介電質直接接合方式進行接合。之後，可選擇性的進行退火以增加第一晶圓100與第二晶圓500之間的接合強度。在本發明之部分實施例中，退火的溫度介於250℃至約400℃之間，而退火的時間介於約0.5小時至約4小時之間。
值得注意的是，上述的實施方式為晶圓級 (wafer-level)接合，以接合第一晶圓100與第二晶圓500，接著再切割成複數個分離的晶片。但此接合步驟亦可用於晶片-晶片(die-to-die level)接合，或晶片-晶圓(die-to-wafer)接合。
請繼續參閱第5圖，在本發明之部分實施例中， 第一接合墊401、第二接合墊403、第三接合墊501與第四接合墊503可具有雙重功能性(dual functionality)。舉例來說，第一接合墊401與第三接合墊501可提供第一晶圓100與第二晶圓500之間的機械接合與電性連接。其中，形成的第一接合墊401電性接觸至第一晶圓100的金屬層107，而形成的第三接合墊501電性接觸至第二晶圓500的金屬層。接合的第一接合墊401第三接合墊501堤供電通道(electrical pathway)於第一晶圓100的元件103以及第二晶圓的元件之間。在本發明之部分實施例中，如前所述減少第一孔洞405的尺寸，此將提升第一接合墊401第三接合墊501之間電性連接的品質，同時也提升第一晶圓100與第二晶圓500之間電性連接的品質。
在本發明之部分實施例中，第二接合墊403可 作為虛擬接合墊，其不提供第一晶圓100與第二晶圓500之間的電性連接，只作為第一晶圓100與第二晶圓500之間的機械接合。舉例來說，形成的第二接合墊403可具有一或多個介電層位於第二接合墊403與金屬層107之間，因此第二接合墊403可與第一晶圓100的元件103電性絕緣。無論第四接合墊503與第二晶圓500的金屬層是否具有電通道，第二接合墊403與第四接合墊503的接合並無電性連接作用，而只作為第一晶圓100與第二晶圓500之間的機械接合。在本發明之部分實施例中，虛擬接合墊可用於減少製程中的不利影響。舉例來說，虛擬接合墊可增加化學機械研磨製程的效率，並減少金屬凹陷與介電質剝落所帶來的影響。
所屬領域具有通常知識者應理解上述形成接合 墊的方法亦可用於形成金屬線與連通柱(via)中的金屬層，以及金屬線與連通柱中的重佈局線路層。
第6-9圖為第一晶圓100在製程各個階段的剖 面圖，以繪示本發明之部分實施方式中金屬層107的形成方法。在第6-9圖中，與第1-5圖相同的元件均具有相同的元件符號。相應地，第6-9圖繪示本發明之部分實施方式中，形成一內連線結構於第1圖所示的其中一金屬層107中的步驟。為了更清楚的說明本揭露內容，第6-9圖繪示形成一內連線結構於一第一金屬層1071的步驟。其他實施方式亦可形成上述的內連線結構於其他金屬層中。在本發明之部分實施方式中，更詳細地說，可使用鑲嵌方法、雙鑲嵌方法、或 其他合適的方式來形成內連線結構。
請參閱第6圖，在本發明之部分實施例中，第一 金屬層1071中的一內金屬介電層(inter-metal dielectric,IMD)601之材質與層間介電層105相似，並可使用與形成層間介電層105相似的方法來形成內金屬介電層601。微影蝕刻技術可用以圖案化第一金屬層1071的內金屬介電層601。通常形成一光阻層(未繪示)於內金屬介電層601上，接著紫外光或準分子雷射(excimer laser)通過一光罩(未繪示)以曝光光阻層，其中光罩上具有預定圖案。進行烘烤與固化操作，並視使用的正型光阻或負型光阻，以顯影劑移除光阻層的曝光區或非曝光區。藉此，光阻層具有一圖案，其係用於形成第二開口603於內金屬介電層601中。此處所述用以形成第二開口603的特定圖案僅用於說明目的，應理解可視第一晶圓100的設計需求來形成其他圖案。
接著蝕刻內金屬介電層601。舉例來說，使用 非等向性乾蝕刻製程移除內金屬介電層601的暴露部分，以暴露層間介電層105中的導電元件605之至少一部分。蝕刻後更形成第二開口603於內金屬介電層601中。在本發明之部分實施例中，一或多種蝕刻製程均可用於圖案化內金屬介電層601，且可形成一或多層蝕刻終止層(未繪示)於內金屬介電層601中以協助圖案化製程。接著搭配使用一灰化製程與一濕清洗製程以移除光阻層。
請參閱第7圖，第7圖形成一第二阻障層701於 內金屬介電層601的第二開口603。第二阻障層701在後續 製程中形成導電材料於第二開口603時，能防止導電材料擴散進入內金屬介電層601中，減少金屬中毒(metallic poisoning)的機會。形成的第二阻障層701可為單層結構或多層結構，其可包含，例如：鈦、氮化鈦、鉭、氮化鉭、鈷、或其他合適的材料。且可使用化學氣相沉積、物理氣相沉積、或其他合適的方法來形成第二阻障層701。
舉例來說，第二阻障層701可為一複合結構， 如第7圖所示包含一第三子阻障層703與一第四子阻障層705。在本發明之其他部分實施例中，第三子阻障層703係以氮化鉭構成，且第三子阻障層703的一第一厚度小於500埃，例如250埃。第四子阻障層705係以鈷構成，且第四子阻障層705的一第二厚度小於100埃。所屬領域具有通常知識者應理解的是，說明書中列舉的尺寸係對應至特定的技術節點，而此些尺寸可隨著技術節點的縮放而增減。
請繼續參閱第8圖，第8圖繪示沉積一金屬材料 801以填充至內金屬介電層601的第二開口603的步驟，以形成內連線結構。金屬材料801可包含銅、銀、金、鎢、鋁、或其他合適的材料，且可使用用化學氣相沉積、物理氣相沉積、電漿加強化學氣相沉積、電鍍、或其他合適的方式來沉積金屬材料801。
請接著參閱第9圖，利用化學機械研磨移除保護層109之上表面上多餘的第二阻障層701與金屬材料801。在化學機械研磨製程中，係搭配使用高腐蝕性的化學物，例如酸與鹼、以及小磨料顆粒，將多餘的材料分別以化學與機 械方式移除。殘留於第二開口603中的金屬材料801形一成內連線結構901。在本發明之部分實施例中，內連線結構901可包含一金屬線903與一連通柱905。此處所述的內連線結構901僅用於說明目的，可視第一金屬層1071的規格形成具有不同設計的一或多個內連線結構於內金屬介電層601中。舉例來說，在本發明之部分實施例中，內連線結構901可包含一連通柱，而在本發明之其他部分實施例中，內連線結構901可包含一金屬線。
請繼續參閱第9圖。如第9圖所示，複數個第二 孔洞907形成於金屬線903與第二阻障層701的介面。在化學機械研磨、晶圓清洗、晶圓活化製程時，接合墊產生電化侵蝕(galvanic corrosion)而形成此些第二孔洞907。為減少此些第二孔洞907的尺寸，第三子阻障層703、第四子阻障層705與內連線結構901選用的材質使第二阻障層701與內連線結構901之間的一還原電位差介於約-1伏特至約+1伏特之間。在本發明之部分實施例中，第二孔洞907的尺寸小於500埃。
第10圖繪示依據本發明之部分實施方式中，晶圓接合方法的流程圖。晶圓接合方法先進行步驟1001，如第1圖所示，形成一或多個保護層於第一晶圓上。繼續參閱步驟1003，如第1圖所示，形成一或多個開口於保護層中。接著請參閱步驟1005，並同時參閱第2圖，形成一或多個阻障層於此些開口中。接著進行步驟1007，如第3圖與第4圖所示，沉積金屬材料於此些開口中，以形成接合墊。最後進 行步驟1009，如第5圖所示，接合第一晶圓與第二晶圓。
在本發明之部份實施例中，一種半導體裝置， 包含一第一介電層位於第一基板上，一第一保護層覆蓋第一介電層，且第一保護層具有一第一凹陷。半導體裝置更包含一第一阻障層覆蓋第一凹陷的側壁，以及一第一外部接觸墊位於第一凹陷中，第一阻障層位於第一外部接觸墊與第一保護層之間。
在本發明之其他部份實施例中，一種半導體裝 置，包含一第一結構。第一結構包含一第一基板，一第一保護層位於第一基板上，複數個第一導電墊位於第一保護層中，以及一第一阻障層位於此些第一導電墊與第一保護層之間，且第一阻障層包含一第一子阻障層與一第二子阻障層。 半導體結構更包含一第二結構直接接合至第一結構。第二結構則包含一第二基板，一第二保護層位於第二基板上，複數個第二導電墊位於第二保護層中，以及一第二阻障層位於此些第二導電墊與第二保護層之間，且第二阻障層包含一第三子阻障層與一第四子阻障層。第一結構接合至第二結構，以令使此些第一導電墊與此些第二導電墊對應排列。
在本發明之其他部份實施例中，一種接合半導 體裝置的方法，包含下列步驟。先提供一第一基板，並形成一第一保護層於第一基板上。接著，形成一第一凹陷於第一保護層中，更形成一第一阻障層於第一凹陷中。最後形成一第一導電墊於第一保護層的第一凹陷中，以令使第一阻障層位於第一導電墊與第一保護層之間。
雖然本發明已以實施方式揭露如上，然其並非用以限定本發明，任何熟習此技藝者，在不脫離本發明之精神和範圍內，當可作各種之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
100‧‧‧第一晶圓
101‧‧‧基板
103‧‧‧元件
105‧‧‧層間介電層
107‧‧‧金屬層
109‧‧‧保護層
111‧‧‧第一保護層
113‧‧‧第二保護層
115‧‧‧第三保護層
117‧‧‧第四保護層
203‧‧‧第一子阻障層
205‧‧‧第二子阻障層
401‧‧‧第一接合墊
403‧‧‧第二接合墊
405‧‧‧第一孔洞
500‧‧‧第二晶圓
501‧‧‧第三接合墊
503‧‧‧第四接合墊

Claims (20)

  1. 一種半導體裝置，包含：一第一基板，且一第一介電層位於該第一基板上；一第一保護層覆蓋該第一介電層，且該第一保護層具有一第一凹陷；一第一阻障層覆蓋該第一凹陷的側壁；以及一第一外部接觸墊位於該第一凹陷中，該第一阻障層位於該第一外部接觸墊與該第一保護層之間。
  2. 如請求項1所述之半導體裝置，其中該第一保護層包含：一第一子保護層，包含未摻雜矽玻璃；一第二子保護層，包含氮化矽；一第三子保護層，包含未摻雜矽玻璃；以及一第四子保護層，包含氮氧化矽。
  3. 如請求項1所述之半導體裝置，其中該第一阻障層包含：一第一子阻障層，包含氮化鉭；以及一第二子阻障層，包含鈷、鎳或鐵。
  4. 如請求項1所述之半導體裝置，其中該第一阻障層延伸至該第一凹陷的一底部。
  5. 如請求項1所述之半導體裝置，其中該第 一外部接觸墊包含複數個孔洞，且該些孔洞小於500埃。
  6. 如請求項1所述之半導體裝置，更包含：一第二基板，且一第二介電層位於該第二基板上；一第二保護層覆蓋該第二介電層，且該第二保護層具有一第二凹陷；一第二阻障層覆蓋該第二凹陷的側壁；以及一第二外部接觸墊位於該第一凹陷中，該第二阻障層位於該第二外部接觸墊與該第二保護層之間。
  7. 如請求項6所述之半導體裝置，其中該第一外部接觸墊係以金屬-金屬直接接合方式與該第二外部接觸墊接合，而該第一介電層係以介電質-介電質直接接合方式與該第二介電層接合。
  8. 一種半導體裝置，包含：一第一結構，包含：一第一基板；一第一介電層位於該第一基板上；複數個第一導電墊位於該第一保護層中；以及一第一阻障層位於該些第一導電墊與該第一保護層之間，且該第一阻障層包含一第一子阻障層與一第二子阻障層；以及一第二結構直接接合至該第一結構，該第二結構包含：一第二基板； 一第二介電層位於該第二基板上；複數個第二導電墊位於該第二保護層中；以及一第二阻障層位於該些第二導電墊與該第二保護層之間，且該第二阻障層包含一第三子阻障層與一第四子阻障層，其中該第一結構接合至該第二結構，以令使該些第一導電墊與該些第二導電墊對應排列。
  9. 如請求項8所述之半導體裝置，其中該第一保護層包含：一第一子保護層，包含未摻雜矽玻璃；一第二子保護層，包含氮化矽；一第三子保護層，包含未摻雜矽玻璃；以及一第四子保護層，包含氮氧化矽。
  10. 如請求項8所述之半導體裝置，中該第一阻障層包含：一第一子阻障層，包含氮化鉭；以及一第二子阻障層，包含鈷、鎳或鐵。
  11. 如請求項8所述之半導體裝置，其中該些第一導電墊包含銅。
  12. 如請求項8所述之半導體裝置，其中該第一阻障層與該些第一導電墊之間的一還原電位差介於約 -1伏特至約+1伏特之間。
  13. 如請求項8所述之半導體裝置，其中該第一接觸墊包含複數個孔洞，且該些孔洞小於500埃。
  14. 如請求項8所述之半導體裝置，其中該些第一接觸墊的一第一上表面與該第一保護層的一第二上表面為同平面。
  15. 一種接合半導體裝置的方法，包含：提供一第一基板形成一第一保護層於該第一基板上；形成一第一凹陷於該第一保護層中；形成一第一阻障層於該第一凹陷中；以及形成一第一導電墊於該第一保護層的該第一凹陷中，以令使該第一阻障層位於該第一導電墊與該第一保護層之間。
  16. 如請求項15所述之接合半導體裝置的方法，其中形成該第一阻障層包含形成一第一子阻障層與一第二子阻障層於該第一保護層的該第一凹陷中。
  17. 如請求項15所述之接合半導體裝置的方法，更包含：提供一第二基板 形成一第二保護層於該第二基板上；形成一第二凹陷於該第二保護層中；形成一第二阻障層於該第二凹陷中；以及形成一第二導電墊於該第二保護層的該第二凹陷中，以令使該第二阻障層位於該第二導電墊與該第二保護層之間。
  18. 如請求項17所述之接合半導體裝置的方法，更包含使用一介電質-介電質直接接合方式接合該第一介電層與該第二介電層。
  19. 如請求項18所述之接合半導體裝置的方法，更包含使用一金屬-金屬直接接合方式接合該第一導電墊與該第二導電墊。
  20. 如請求項18所述之接合半導體裝置的方法，更包含進行退火，其中退火的溫度介於250℃至約400℃之間，而退火的時間介於約0.5小時至約4小時之間。
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