TWI429046B - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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TWI429046B
TWI429046B TW098115797A TW98115797A TWI429046B TW I429046 B TWI429046 B TW I429046B TW 098115797 A TW098115797 A TW 098115797A TW 98115797 A TW98115797 A TW 98115797A TW I429046 B TWI429046 B TW I429046B
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semiconductor substrate
semiconductor device
layer
forming
fabricating
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TW098115797A
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TW201027698A (en
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Hung Pin Chang
Kuo Ching Hsu
Chen Shien Chen
Wen Chih Chiou
Chen Hua Yu
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Taiwan Semiconductor Mfg
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Description

半導體裝置及其製造方法
本發明係有關於積體電路，且特別是有關於一種堆疊晶粒之隔離結構。
自從發明積體電路以來，由於各種電子元件(例如電晶體，二極體，電阻，電容等)的積集度持續不斷的改良，半導體產業已經經歷了快速的成長。此種積集度的改良使得最小特徵尺寸不斷減少，讓元件可以整合在一個特定區域。
上述積集度的改善在本質上是二維(平面)的性質，因為積體電路所佔用的體積基本上是在半導體晶圓的表面。雖然微影技術的進步已使得二維積體電路的製作得到相當大的改良，但在二維上可達到的密度有其物理上的限制。其中一個限制便是製作這些元件所需之最小尺寸。而且當需要將更多元件放置在同一晶片上時，所需要的設計也越複雜。為了更進一步增加電路密度，業界提出了所謂的”三維(3D)積體電路”。在典型的三維(3D)積體電路製程中係將兩個晶粒互相接合並與基底上之接觸墊形成電性連接。例如，可將兩個晶粒的頂部互相接合，然後將堆疊的晶粒接合至一載板，並以焊線將每一晶粒之接合墊電性連接至載板之接合墊。
矽穿孔(TSV；Through-Silicon Via)技術為近來發展的重點。一般來說，TSV技術是將基板蝕刻出一垂直孔洞，並在孔洞中填入導電材料，如銅。將基板的背面薄化後露出TSV，並在TSV上直接設置焊球以提供電性接觸。之後，在焊球放置另一晶粒即可形成堆疊晶粒封裝。
由於基板經過了薄化，於基板電路面進行的介電製程並未形成於背面，於是基板背面是在缺乏保護的情況下，把焊球放置在暴露的TSV，使得表面的潤濕性不足，焊球和基板之間無法形成良好的電性連接。此外，該結構限制了接合面的機械強度並限制了I/O引腳總數。
因此，業界亟須一種接合TSV的改良結構與方法。
本發明提供一種半導體裝置，包括：一半導體基底，其具有相對之電路側與背側；複數個矽穿孔，延伸進入半導體基底，且每一矽穿孔具有一突出部，突出於半導體基底之背側；一隔離層，位於半導體基底之背側且介於相鄰之矽穿孔之間，隔離層未延伸超過每一矽穿孔之突出部的頂端；以及，一導電元件，位於每一矽穿孔之突出部上。
本發明亦提供一種半導體裝置的製造方法，包括：提供一半導體基底，其具有一矽穿孔從一電路側延伸進入半導體基底；薄化半導體基底之背側，使矽穿孔突出於半導體基底之背側；形成一隔離層於半導體基底之背側與矽穿孔上；薄化隔離層以露出矽穿孔；以及，形成一導電元件於矽穿孔上。
本發明另提供一種半導體裝置的製造方法，包括：提供一半導體基底，其具有相對之第一側與第二側，半導體基底具有一矽穿孔從第一側部分延伸進入半導體基底；露出矽穿孔，使矽穿孔至少一部分突出於半導體基底之第二側；形成一介電層於半導體基底之第二側；形成一圖案化罩幕於介電層上，並露出矽穿孔上之介電層；以及，去除矽穿孔上之介電層。
為讓本發明之上述和其他目的、特徵、和優點能更明顯易懂，下文特舉出較佳實施例，並配合所附圖式，作詳細說明如下：
第1~5圖繪示一種具有隔離結構之晶粒的製作方法，其可用於三維(3D)積體電路或堆疊晶粒結構。在以下的實施例與圖示中，類似的元件將以類似的標號表示。
第1圖顯示一半導體基底110，其上形成有電路112。半導體基底110例如可包括：摻雜或未摻雜之矽塊材(bulk Si)、或絕緣層上半導體(SOI；semiconductor-on-insulator)之主動層。一般而言，SOI基底包含一層半導體材料(例如矽)設置於一絕緣層上，例如埋藏氧化層(buried oxide layer)或氧化矽層。該絕緣層設置於一基底上，通常為矽基底或玻璃基底。此外，亦可使用多層基底、梯度(gradient)基底等其他基底。
半導體基底110上的電路112可以是具有特定用途的任何電路。在一實施例中，電路112包括基底上的數個電子元件，且其上具有一或多個介電層。介電層之間可形成金屬層以作為電子元件之間的電性連接。電子元件亦可形成在一或多個介電層之中。
舉例而言，電路112可包括各種N型金氧半(NMOS)電晶體、P型金氧半(PMOS)電晶體、電容、電阻、二極體、光二極體、熔絲等互相連接之元件以進行一或多種功能。這些功能可包括：記憶體結構、運算結構、感應器、放大器、配電系統、輸入/輸出電路等。此技術領域人士當可了解，上述提到的例子只是作為舉例之用，而非用來限定本發明之用途，因此，本發明亦可使用其他的電路。
第1圖所示更包括一蝕刻停止層114與一內層介電層(ILD)116。蝕刻停止層114所使用之介電材質較佳與底下的半導體基底110及上方的內層介電層116具有不同的蝕刻選擇率。在一實施例中，蝕刻停止層114可為SiN、SiCN、SiCO、CN、或前述之組合，其可利用化學氣相沉積法(CVD；Chemical Vapor Deposition)或電漿加強化學氣相沉積法(PECVD)等技術沉積。
內層介電層116可由氧化矽或低介電常數材料，例如磷矽玻璃(PSG)、硼磷矽玻璃(BPSG)、氟矽玻璃(FSG)、SiOx Cy 、旋塗式玻璃(Spin-On-Glass)、旋塗式高分子(Spin-On-Polymer)、碳化矽材料、前述之化合物、複合物、或組合所形成，其形成方式例如是旋轉塗佈、CVD、PECVD等各種習知技術。應注意的是，蝕刻停止層114與內層介電層116可各自包含數層介電層，且相鄰的介電層之間可形成或不形成蝕刻停止層。
接觸插塞118形成於內層介電層116中以提供電性接觸至電路112。接觸插塞118例如可用以下方式形成：首先，於內層介電層116上形成一光阻材料並利用微影技術將之圖案化，露出內層介電層116中欲形成接觸插塞的部分。接著以蝕刻製程，例如非等向性乾蝕刻，在內層介電層116中形成開口。之後，較佳在開口中順應性地形成擴散阻障層及/或黏著層(未顯示)後，填入導電材料。擴散阻障層較佳包括TaN、Ta、TiN、Ti、CoW、或前述之組合。導電材料較佳包括銅、鎢、鋁、銀、或前述之組合。如此，便可形成第1圖中之接觸插塞118。
於內層介電層116上形成一或多層金屬問介電層(IMD)120以及相關之金屬化層(未顯示)，使電路之間能相互連通並提供外界之電性連接。金屬間介電層120較佳是由低介電常數材料所形成，例如氟矽玻璃(FSG)，其可由PECVD或高密度電漿CVD(HDP-CVD)等方式形成。金屬間介電層120中可包含類似於蝕刻停止層114之蝕刻停止層。頂層金屬接觸(top metal contact)122形成在最上層的金屬間介電層120上以提供外界之電性連接。
第1圖更顯示矽穿孔(through-silicon via)124。矽穿孔124可由適當方式形成，例如可在形成內層介電層116之前，以蝕刻、銑切(milling)、雷射等一或多種技術，形成穿入基底110的開口。開口中較佳形成襯層126作為隔離，然後再填入導電材料124。襯層126較佳包括氮化矽、氧化物、聚合物、或前述之組合。導電材料124可包括銅、鎢、鋁、銀、或前述之組合。如此，便可形成矽穿孔124。此外，亦可使用導電擴散阻障層等其他材料，例如TaN、Ta、TiN、Ti、CoW、或前述之組合。
應注意的是，雖然圖中所示之矽穿孔124是由基底110之上表面向下延伸，但在其他實施例中也可能是其他型態。例如，矽穿孔124可從內層介電層116或金屬間介電層120之上表面向下延伸。在一實施例中，係於接觸插塞118形成後，利用蝕刻、銑切、雷射等方式形成穿入基底110的開口，然後依照前述方式形成襯層與導電材料即可形成矽穿孔124。
頂層金屬接觸122上形成有導電凸塊128，例如Cu、W、CuSn、AuSn、InAu、PbSn等金屬凸塊。載板130藉由粘著劑(adhesive)132貼附於金屬間介電層120的上表面。載板130可以在後續的製程中提供機械上與結構上的暫時支撐，以減少或避免對半導體基底110的傷害。
載板130例如可包括：玻璃、氧化矽、氧化鋁等。在一實施例中，可利用粘結劑132將載板130粘附到金屬間介電層120(或保護層)之上表面。粘結劑132可以任何適當的粘結劑例如紫外光(UV)膠，其經過紫外光照射後會喪失黏性。載板130的較佳厚度可從數密爾(mil)到數拾密爾(mil)的範圍。
第2圖顯示在基底110背面進行薄化製程以露出矽穿孔124/襯層126。薄化製程可使用機械磨削(Mechanical Grinding)、化學機械研磨、蝕刻製程、或前述之組合。例如，可先利用磨削或化學機械研磨露出矽穿孔124，然後再以濕蝕刻或乾蝕刻對半導體基底110進行凹蝕(recessing)，使矽穿孔124與襯層126突出於基底110表面，如第2圖所示，其中所用之濕蝕刻或乾蝕刻對於襯層126材料與基底110材料具有高蝕刻選擇比。在一實施例中，當矽穿孔124為銅，而襯層126為氧化物時，可以使用HBr/O2 、HBr/Cl2 /O2 、SF6 /Cl2 、SF6 電漿等乾蝕刻製程對半導體基底110進行凹蝕。矽穿孔124與襯層126露出的部分較佳約從次微米到數微米。
第3圖顯示在基底110背面(或基底表面之原生氧化層)形成隔離層310。在較佳實施例中，隔離層310為介電材料，例如SiN、氧化物、SiC、SiON、聚合物等，可利用旋轉塗佈、印刷、CVD等製程形成。較佳者，隔離層310可利用低溫製程形成，例如低於250℃之PECVD製程，如此可避免粘著劑劣化以確保整個製程中的機械強度。
形成隔離層310後，視其形成的方式而定，可能需要進行平坦化製程。有些沉積方式(如旋轉塗佈)可形成一平坦的表面，但有些沉積方式(如CVD)會形成順應性(conformal)的表面，因此需要再進行磨削或化學機械研磨等平坦製程以得到如第3圖所示之平坦表面。
第3圖顯示以薄化製程將矽穿孔124再次露出。薄化製程可使用機械磨削、化學機械研磨、蝕刻製程、或前述之組合。例如，可先利用磨削或化學機械研磨露出矽穿孔124，然後再以濕蝕刻或乾蝕刻對隔離層310進行凹蝕，使矽穿孔124突出於隔離層310表面，如第4圖所示，其中所用之濕蝕刻或乾蝕刻對矽穿孔124材料與襯層126、隔離層310材料具有高蝕刻選擇比。在一實施例中，當矽穿孔124為銅時，可以使用乾蝕刻製程或氫氟酸之濕蝕刻製程對隔離層310進行凹蝕。但在其他實施例中亦可使用其他材料與蝕刻方式。矽穿孔124露出的部分較佳約從次微米到數微米。第4圖亦顯示襯層126在上述隔離層310的凹蝕步驟中被一併去除。
第5圖顯示在露出的矽穿孔124上形成連接元件510。連接元件510可以是任何適當的導電材料，如Cu、Ni、Sn、Au、Ag等，且可用任何適當的方式形成，包括蒸鍍、電鍍、印刷、噴射(jetting)沉積、焊柱凸點(stud bump)技術、直接放置(direct placement)等方式。
之後可視實際需要進行各種後段製程(BEOL；back-end-of-line)。例如，可去除載板130、形成封膠(encapsulant)、晶粒切割(singulation)、晶圓級或晶粒級堆疊等製程。應注意的是，本發明之實施例可以應用在各種情況，例如晶粒對晶粒接合、晶圓對晶圓接合、或晶粒對晶圓接合等。
第6-11圖顯示本發明於晶粒上形成隔離結構的另一實施例，其適用於堆疊晶粒結構。第6-11圖之起始步驟具有如第2圖所示之結構，其中相似的元件符號代表相似的元件。
第6圖顯示在基底110背面(或基底表面之原生氧化層)形成隔離層610。在一較佳實施例中，隔離層610為一層順應性(conformal)的介電材料，例如SiN、氧化物、SiC、SiON、聚合物等，較佳者，隔離層610可利用低溫製程形成，例如低於250℃之PECVD製程，如此可避免粘著劑劣化以確保整個製程中的機械強度。隔離層610的厚度較佳數千埃()。應注意的是，隔離層610的厚度小於矽穿孔124突出基板110的高度。
第7圖顯示在隔離層610上形成罩幕層710，第8圖顯示進行回蝕刻製程以露出位於矽穿孔124上的隔離層610。在一實施例中，罩幕層710包括一光阻材料，但其他與底下隔離層610及襯層126具有高蝕刻選擇性的材料也可使用。上述的回蝕刻製程例如可使用乾蝕刻。
之後，如第9圖所示，以乾蝕刻或濕蝕刻製程去除矽穿孔124上的隔離層610與襯層126以露出矽穿孔124。上述乾蝕刻或濕蝕刻對於罩幕層710、矽穿孔124材料與隔離層610、襯層126材料具有高蝕刻選擇性。在一實施例中，當矽穿孔124為銅時，可以使用乾蝕刻製程或氫氟酸之濕蝕刻製程以露出矽穿孔124。但在其他實施例中亦可使用其他材料與蝕刻方式。
第10圖顯示罩幕層710的去除。在一實施例中，當罩幕層710為光阻時，可使用電漿灰化或濕式剝除製程將罩幕層710去除。電漿灰化製程條件較佳例如：氧氣流量約1000-2000sccm、壓力約300-600mTorr、功率約500-2000瓦、溫度約80-200℃。進行電漿灰化後，可視需要將晶圓浸在一溶劑中進行清潔並去除任何殘留的光阻材料。
第11圖顯示在露出的矽穿孔124上形成連接元件1110。連接元件1110可以是任何適當的導電材料，如Cu、Ni、Sn、Au、Ag等，且可用任何適當的方式形成，包括蒸鍍、電鍍、印刷、噴射(jetting)沉積、焊柱凸點(stud bump)技術、直接放置(direct placement)等方式。
之後可視實際需要進行各種後段製程(BEOL；back-end-of-line)。例如，可去除載板130、形成封膠(encapsulant)、晶粒切割(singulation)、晶圓級或晶粒級堆疊等製程。應注意的是，本發明之實施例可以應用在各種情況，例如晶粒對晶粒接合、晶圓對晶圓接合、或晶粒對晶圓接合等。
第12-16圖顯示本發明於晶粒上形成隔離結構的又一實施例，其適用於堆疊晶粒結構。第12-16圖之起始步驟具有如第4圖所示之結構，其中相似的元件符號代表相似的元件。
請參照第12圖，在隔離層310與矽穿孔124露出的表面上沉積一順應性的晶種層1210。晶種層1210為一導電薄膜，其可幫助後續形成較厚的膜層。在一實施例中，晶種層1210可利用CVD或物理氣相沈積法(PVD；Physical Vapor Deposition)形成例如Cu、Ti、Ta、TiN、TaN等薄導電層。例如，可利用PVD形成Ti阻障層，再以PVD形成Cu晶種層。
第13圖顯示在晶種層1210上形成一圖案化罩幕1310。圖案化罩幕1310較佳包括圖案化光阻、硬罩幕等。在一較佳實施例中，係沉積一光阻材料並將之圖案化而在矽穿孔124上形成開口1312。
之後，如第14圖所示，在開口1312中形成導電接墊(conductive pad)1410。導電接墊1410例如可利用電鍍、無電電鍍等方式形成。在一實施例中，可將晶圓浸入電鍍液中進行電鍍製程，其中晶圓表面電性連接至外部直流電源供應器之負極，以使晶圓在電鍍過程中作為陰極(cathode)，而固態導電陽極(anode)，例如銅陽極，亦浸入電鍍液中並連接至電源供應器之正極。來自陽極之原子溶入電鍍液中然後到達陰極(晶圓)，如此可在晶圓露出的導電區域上(例如開口1312)進行電鍍。
第15圖顯示將圖案化罩幕1310去除。在一實施例中，當罩幕層1310為光阻時，可使用電漿灰化或濕式剝除製程將罩幕層1310去除。
第16圖顯示將露出之晶種層1210去除。晶種層1210例如可利用濕蝕刻製程加以去除。
之後可視實際需要進行各種後段製程(BEOL；back-end-of-line)。例如，可去除載板130、形成封膠(encapsulant)、晶粒切割(singulation)、晶圓級或晶粒級堆疊等製程。應注意的是，本發明之實施例可以應用在各種情況，例如晶粒對晶粒接合、晶圓對晶圓接合、或晶粒對晶圓接合等。
第17-21圖顯示本發明於晶粒上形成隔離結構的再一實施例，其適用於堆疊晶粒結構。第17-21圖之起始步驟具有如第10圖所示之結構，其中相似的元件符號代表相似的元件。
請參照第17圖，在隔離層610與矽穿孔124露出的表面上沉積一順應性的晶種層1710。晶種層1710為一導電薄膜，其可幫助後續形成較厚的膜層且可包括一阻障層。晶種層1710的形成方式與材質類似於第12圖的晶種層1210。
第18圖顯示在晶種層1710上形成一圖案化罩幕1810。圖案化罩幕1310較佳包括圖案化光阻、硬罩幕等。在一較佳實施例中，係沉積一光阻材料並將之圖案化而在矽穿孔124上形成開口1812。
之後，在開口1812中形成導電接墊1910。導電接墊1910例如可利用電鍍、無電電鍍等方式形成，如第14圖之導電接墊1410。
第20圖顯示將圖案化罩幕1810去除。在一實施例中，當罩幕層1810為光阻時，可使用電漿灰化或濕式剝除製程將罩幕層1810去除。進行電漿灰化後，可視需要將晶圓浸在一溶劑中進行清潔並去除任何殘留的光阻材料。
第21圖顯示將露出之晶種層1710去除。晶種層1710例如可利用濕蝕刻製程加以去除。
之後可視實際需要進行各種後段製程(BEOL；back-end-of-line)。例如，可去除載板130、形成封膠(encapsulant)、晶粒切割(singulation)、晶圓級或晶粒級堆疊等製程。應注意的是，本發明之實施例可以應用在各種情況，例如晶粒對晶粒接合、晶圓對晶圓接合、或晶粒對晶圓接合等。
由以上實施例可知，本發明提供一種隔離結構，其圍繞露出之矽穿孔，因此提供一較大之濕潤表面，使焊球和基板之間可形成良好的電性連接。如此一來，可增加焊球的密度。此外，隔離層亦可增加接合界面的機械強度。
雖然本發明已以數個較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作任意之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
110．．．基底
112．．．電路
114．．．蝕刻停止層
116．．．內層介電層
118．．．接觸插塞
120．．．金屬間介電層
122．．．頂層金屬接觸
124．．．矽穿孔
126．．．襯層
128．．．導電凸塊
130．．．載板
132．．．粘著劑
310、610．．．隔離層
510、1110．．．連接元件
710．．．罩幕層
1210、1710．．．晶種層
1310．．．圖案化罩幕
1312、1712．．．開口
1410、1910．．．導電接墊
第1-5圖顯示本發明於晶粒上形成隔離結構的實施例。
第6-11圖顯示本發明於晶粒上形成隔離結構的另一實施例。
第12-16圖顯示本發明於晶粒上形成隔離結構的又一實施例。
第17-21圖顯示本發明於晶粒上形成隔離結構的再一實施例。
110．．．基底
112．．．電路
114．．．蝕刻停止層
116．．．內層介電層
118．．．接觸插塞
120．．．金屬間介電層
122．．．頂層金屬接觸
124．．．矽穿孔
126．．．襯層
128．．．導電凸塊
130．．．載板
132．．．粘著劑
310．．．隔離層
510．．．連接元件

Claims (19)

  1. 一種半導體裝置，包括：一半導體基底，其具有相對之電路側與背側；多個導電凸塊，位於該半導體基底之電路側；複數個矽穿孔，延伸進入該半導體基底，且每一矽穿孔具有一突出部，突出於該半導體基底之背側；一隔離層，位於該半導體基底之背側且介於相鄰之矽穿孔之間，該隔離層未延伸超過每一矽穿孔之突出部的頂端；以及一導電元件，位於每一矽穿孔之突出部上。
  2. 如申請專利範圍第1項所述之半導體裝置，其中導電元件包括：一導電晶種層於每一矽穿孔之突出部上；以及，一導電接墊於該導電晶種層上。
  3. 如申請專利範圍第2項所述之半導體裝置，其中該導電晶種層延伸至部分之隔離層上。
  4. 如申請專利範圍第2項所述之半導體裝置，其中該導電接墊包含銅。
  5. 如申請專利範圍第1項所述之半導體裝置，其中該隔離層延伸至每一矽穿孔之突出部的側壁。
  6. 如申請專利範圍第1項所述之半導體裝置，其中該導電元件包含焊球。
  7. 一種半導體裝置的製造方法，包括：提供一半導體基底，其具有相對之一電路側與一背側，該半導體基底具有多個導電凸塊於該電路側、與一矽穿孔從該電路側延伸進入該半導體基底； 薄化該半導體基底之背側，使該矽穿孔突出於該半導體基底之背側；形成一隔離層於該半導體基底之背側與該矽穿孔上；薄化該隔離層以露出該矽穿孔；以及形成一導電元件於該矽穿孔上。
  8. 如申請專利範圍第7項所述之半導體裝置的製造方法，其中形成該導電元件的步驟包括：形成一焊球於該矽穿孔上。
  9. 如申請專利範圍第7項所述之半導體裝置的製造方法，其中形成該導電元件的步驟包括：形成一晶種層於該矽穿孔上；以及，形成一金屬接墊於該晶種層上。
  10. 如申請專利範圍第7項所述之半導體裝置的製造方法，其中該半導體基底與該矽穿孔之間更包括一襯層，且更包括去除該矽穿孔上之該襯層。
  11. 如申請專利範圍第10項所述之半導體裝置的製造方法，其中去除該襯層之步驟是於該隔離層形成後進行。
  12. 如申請專利範圍第10項所述之半導體裝置的製造方法，其中該隔離層具有一平坦表面。
  13. 一種半導體裝置的製造方法，包括：提供一半導體基底，其具有相對之第一側與第二側，其中該第一側為一電路側而該第二側為一背側，且其中該半導體基底具有多個導電凸塊於該第一側、與一矽穿孔從第一側部分延伸進入該半導體基底； 露出該矽穿孔，使該矽穿孔至少一部分突出於該半導體基底之第二側；形成一介電層於該半導體基底之第二側；形成一圖案化罩幕於該介電層上，並露出該矽穿孔上之該介電層；以及去除該矽穿孔上之該介電層。
  14. 如申請專利範圍第13項所述之半導體裝置的製造方法，更包括形成一導電元件於該矽穿孔上。
  15. 如申請專利範圍第14項所述之半導體裝置的製造方法，其中該導電元件包括焊球。
  16. 如申請專利範圍第13項所述之半導體裝置的製造方法，其中於去除該介電層之後更包括：去除該圖案化罩幕。
  17. 如申請專利範圍第13項所述之半導體裝置的製造方法，其中該半導體基底與該矽穿孔之間更包括一襯層。
  18. 如申請專利範圍第17項所述之半導體裝置的製造方法，其中於形成該圖案化罩幕之後更包括：去除該襯層。
  19. 如申請專利範圍第17項所述之半導體裝置的製造方法，其中該襯層延伸至該矽穿孔之突出部分的側壁。
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US20100171197A1 (en) 2010-07-08
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