TWI399827B - 堆疊晶粒的形成方法 - Google Patents

堆疊晶粒的形成方法 Download PDF

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Publication number
TWI399827B
TWI399827B TW098124613A TW98124613A TWI399827B TW I399827 B TWI399827 B TW I399827B TW 098124613 A TW098124613 A TW 098124613A TW 98124613 A TW98124613 A TW 98124613A TW I399827 B TWI399827 B TW I399827B
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Taiwan
Prior art keywords
wafer
semiconductor
forming
bonding
semiconductor wafer
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TW098124613A
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English (en)
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TW201023299A (en
Inventor
Mingfa Chen
Chenshien Chen
Wenchih Chiou
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Taiwan Semiconductor Mfg
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Publication of TW201023299A publication Critical patent/TW201023299A/zh
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Publication of TWI399827B publication Critical patent/TWI399827B/zh

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    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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Description

堆疊晶粒的形成方法
本發明是有關於一種積體電路的製造方法，且特別是有關於一種形成具有一或多個穿矽介層窗之堆疊晶粒的方法。
一般來說，積體電路的操作速度會受到晶片上分離最遠且可彼此通訊的元件之間的距離的影響。三維結構的佈局電路已經被證實可以有效地降低晶片上元件間的通訊路徑長度，其所提供的層間垂直距離遠小於各層晶片寬度。因此，藉由垂直的堆疊電路層，通常可增加整體晶片的速度。已經運用一種透過晶圓鍵合的方式來進行這樣的堆疊。
晶圓鍵合就是將兩個或多個上面已經形成積體電路的半導體晶圓結合在一起。晶圓通常係藉由外氧化層的直接結合、或者藉由加入黏著劑至層間介電層(ILD)的方式來加以結合。接合的結果產生了一個三維的晶圓堆疊，此晶圓堆疊後續將被切割成獨立的堆疊晶粒，其中每一個堆疊晶粒都具有數層積體電路。除了三維結構電路系統通常具有的增加速度的優點之外，晶圓堆疊還具有其它潛在利益，包含改善形成因素、低成本以及透過系統晶片(system-on-chip；SOC)解決方案所獲得之較大的積集度。為了使得各種元件可整合到每個堆疊晶粒內，提供電性連接，以提供垂直層間的導體。通常製造穿矽介層窗時係藉由提供填滿導體材料之介層窗，其中這些介層窗徹底穿過層，以接觸及連接其它結合層的TSVs以及導體。
在一個現存的TSV形成製程中，在形成互補型金氧半導體(CMOS)裝置於晶圓基板上之後，或者甚至在上層金屬化製程後，形成TSVs。CMOS製程或金屬化製程後，再形成TSVs的一個缺點，就是由於蝕刻與設計的限制，介層窗的密度通常較低。蝕刻穿過金屬化層通常不會造成凹槽，而可提供特別密集的TSV。此外，再次因為製程蝕刻通過金屬化及接觸區域，介層窗的設計受限於金屬化層與接觸區域的已存結構。因此，設計者通常將必須將TSV網狀系統設計於已存的金屬層與接觸線路的週遭。這些受限的設計與密度可能造成連接、接觸以及可靠性的問題。
現存TSV的形成製程的另一個限制為，在晶圓基板中可形成之TSVs的有限深度。由於金屬化層的現存結構，一般用來形成TSV開口於晶圓基板的蝕刻製程係在晶圓基板中進行至一有限深度，其中此有限深度遠小於基板的厚度。例如，電漿蝕刻製程通常可用以形成深度介於實質25微米(micron)至實質50微米的TSV開口，相較於一般矽晶圓基板的厚度則有實質700微米。一般利用背面研磨的方式來薄化晶圓基板的厚度至小於100微米，並露出TSVs，以連接堆疊晶粒。然而，這樣的實施方式可能降低晶圓基板之機械強度，其中此晶圓基板係作為形成於其上之積體電路的固體基礎。此外，過度薄化的晶圓基板常會破損，因此嚴重的影響了整體IC產品的良率。
本發明之較佳實施例在金屬化處理前形成TSVs，因而通常可解決或避免上述這些或其他問題的發生，且可獲得技術優勢。可製作出具有更大高寬比且更深入晶圓基板中的TSVs。此方法大致上降低了晶圓基板在晶圓背磨製程中被過度薄化的風險，其中晶圓背磨製程一般是用來露出及製作出TSVs的電性接觸。藉由提供更深的TSVs與接合墊，每個晶圓及晶粒可直接接合在這些TSVs與另一晶圓上的接合墊之間。
依據本發明之一較佳實施例，提出一種形成堆疊積體電路半導體晶粒的方法，包含下列步驟。形成一或複數個個凹槽於第一半導體晶圓中，利用導體材料填充所述的凹槽，以形成一或複數個穿矽介層窗於所述的第一半導體晶圓中。形成一或複數個接合接觸於所述的第一半導體晶圓的正面上，將所述的第一半導體晶圓的正面貼附到晶圓載體上，並暴露出所述的第一半導體晶圓的背面。薄化所述第一半導體晶圓的背面，直到所述的穿矽介層窗暴露出且稍微突出於此背面。對齊及接合所述的穿矽介層窗與在第二半導體晶粒上之一或複數個接合表面上的一或複數個接合接觸。
依據本發明之另一較佳實施例，提出一種形成堆疊積體電路半導體晶粒的方法，包含下列步驟。提供第一半導體晶圓，其中此半導體晶圓具有一或複數個穿矽介層窗形成於基板中。貼附所述第一半導體晶圓的正表面至晶圓載體，並暴露出所述第一半導體晶圓的背面。薄化所述第一半導體晶圓的背面，直到所述穿矽介層窗暴露出且稍微突出於此背面。形成一或多個第一接合接觸於此第一半導體晶圓薄化過的背面上的金屬化絕緣層中。將所述的第一接合接觸電性耦接到所述的穿矽介層窗。提供具有一或複數個第二接合接觸的第二半導體工件，其中第二接合接觸設於此第二半導體工件的接合表面上。對齊及接合第一半導體晶圓上的所述第一接合接觸至第二半導體工件上之對應的第二接合接觸。
較佳實施例的應用與實施將在以下詳細揭露。然而，可以理解的是，本發明提供許多可供應用的創新概念，這些創新概念可在各種特定背景中加以體現。所討論之特定實施例僅係用以舉例說明製造與應用本發明之特定方式，並不用以限制本發明之範圍。
現請參照第1A圖，其繪示晶圓10的剖面圖。晶圓10包含基板100以及製作在基板100上的裝置101A、101B及101C，其中基板100之材料一般為矽(Si)，但亦可為砷化鎵(GaAs)、磷化鎵砷(GaAsP)、磷化銦(InP)、砷化鎵鋁(GaAlAs)、磷化銦鎵(InGaP)及其類似物。在第1B圖中，絕緣層(有時也稱為層間介電層或ILD層)102沉積於晶圓10的基板100上。上述絕緣材料包含，例如二氧化矽以及磷矽玻璃(phosphosilicate glass；PSG)。如第1C圖所示般，在晶圓10上進行蝕刻，以製造出穿矽介層窗凹槽103與104以及接觸開口111A、111B及111C於層間介電層102中。為了要防止任何導體材料溶入晶圓10之電路系統的任何主動部分中，以共形層(Conformal layer)的方式沉積介電襯105，例如氮化矽(Silicon Nitride)，於晶圓10上，包含介層窗凹槽103及104。在一較佳實施例中，介層窗凹槽103及104之尺寸(例如直徑)的範圍均係從實質5微米至實質50微米，且高寬比的範圍從實質12：1至實質3：1。
如第1D圖所示，形成一層導體材料，即導體106，於晶圓10之上。此導體材料可包含各種材料，例如銅、鎢、鋁、金、銀及其類似物。導體106填充TSV介層窗凹槽103及104，以及接觸開口111A、111B與111C。利用蝕刻、化學機械研磨法(CMP)及類似方法移除導體106的多餘部分後，此時晶圓10包含位於層間介電層102中的接觸118A、118B及118C以及穿矽介層窗(TSVs)107與108，其中TSVs 107與108同時形成於基板100與層間介電層102中，如第1E圖所示。
在另一實施例中，接觸118A、118B及118C可在製作TSVs 107及108之前形成。在另一及/或替代實施例中，接觸118A、118B及118C可形成在TSVs 107及108形成之後。
接著，請參照第1F圖，藉由應用在積體電路製造製程中的一般後段製作流程，於晶圓10上沉積且圖案化第一互連層(M1層)，而形成第一互連線路120A、120B與120C以及接觸墊124與125，其中第一互連線路120A至120C分別透過接觸118A至118C而耦接於裝置101A至101C，且接觸墊124與125分別耦接於穿矽介層窗107、108。沉積第一金屬間介電層200至晶圓10上。接著，利用現存技術，例如雙鑲嵌(dual damascene)製程，在晶圓10上沉積且圖案化第二互連層(M2層)，而形成互連線路210。利用類似的方法，形成互連線路310於第三互連層(M3層)中，且覆蓋於第二互連層中的互連線路210上方，其中互連線路310與互連線路210由第二金屬間介電層300所分隔。晶圓10上之互連結構的製程，可繼續在上方之互連層中進行，直到製作出晶圓10中各種裝置及特徵之間的所需交互連接。用來作為各互連層中之互連線路的導體材料可包含各種材料，例如銅、鎢、鋁、金、銀及其類似物。值得注意的是，介層窗通常是用來將穿矽介層窗107及108透過接觸墊124及125，而耦接至上層互連層(M2層與上方層)中的互連線路。例如，接觸墊124以及互連線路210是藉由介層窗via1a而以直接連接的方式進行耦接，其中介層窗via1a係形成於穿矽介層窗107上且對齊穿矽介層窗107。又例如，接觸墊125延伸通過一重佈M1特徵138，其中重佈M1特徵138透過介層窗via1b而耦接於互連線路210。在此例子中，介層窗via1b並非形成於穿矽介層窗108上，也非對齊於穿矽介層窗108。本發明之各種實施例並不受限於穿矽介層窗接觸墊與上層互連層中之互連線路間僅為直接連接的型態。亦值得注意的一點是，介層窗係用來連接各互連層中的互連線路，但為了簡化圖式，而未繪示於第1F圖中。之後，沉積隔離層345(有時也稱為鈍化層)於晶圓10上，其中隔離層345可提供晶圓10中的裝置及互連線路機械或化學上的保護。
如第1G圖所示，經由沉積介電層339，來形成接合接觸410、411及412，其中介電層339可使晶圓10中的裝置及互連線路與連接至晶圓10的任何晶圓中的任何其他電路系統或裝置之間絕緣。在介電層339中蝕刻出凹槽，沉積導體材料於這些凹槽中，以形成接合接觸410、411及412。移除或蝕刻構成介電層339的絕緣材料，至暴露出接合接觸410、411及412，使得接合接觸410、411及412稍稍地高於介電層339的頂端。接合接觸410、411及412可透過絕緣層345中的介層窗347而電性耦接至互連線路310。
應注意的是，如第1G圖所示，接合接觸410、411及412相對於下方頂端互連層中之互連線路310的位置並未受到限制。然而，接合接觸410、411及412與互連線路310間的連接應存在其它方式，例如重佈層350(第2圖)、導體線路或相似結構。本發明之各實施例並未限制接合接觸與頂端互連層中的互連線路之間只能直接連接。
如第1H圖所示，塗佈黏著劑450於晶圓10，以將晶圓10接合至晶圓載體500。載體500通常是用以在後續基板100背面的薄化製程中，提供機械支撐。在一較佳實施例中，載體500可為玻璃基板，或具有厚度介於實質500微米至實質1000微米的裸矽晶圓。
第1I圖係繪示根據本發明之一實施例之晶圓10的剖面圖。為了要提供介層窗107及108在背面的接觸點，將晶圓10翻面，並由背面對基板100進行薄化，且藉由如蝕刻、化學機械研磨法或類似的方法，來移除基板100的一部分，以暴露出介層窗107及108的接觸點。為了要完成上述步驟，將載體500固定於於晶圓薄化手柄式夾具(Wafer thinning handle jig)，晶圓薄化手柄式夾具接著將裝在晶圓薄化機構上。在移除基板100的這些部分中，介層窗107及108稍微地突出於基板100。於基板薄化製程後，晶圓10的厚度下降至實質25微米至實質250微米的範圍。
第1J圖繪示晶圓10堆疊且接合至晶圓11的剖面圖。晶圓11包含基板600、介電層624以及絕緣層626。基板600可包含一或多個預先形成的半導體元件，介電層624可用以隔離形成在不同互連層中的互連線路，而絕緣層626可用來限制任何一個晶圓上的各種元件間的干擾。在介層窗107與接合墊607、以及介層窗108與接合墊608處，將晶圓10及11對齊且結合在一起，以形成堆疊晶圓12。接合的媒介，例如銅、鎢、銅錫合金、金錫合金、銦金合金、鉛錫合金或其相似物，都可塗佈於預備接合的晶圓10及11上的接合接觸之間。
在另一較佳實施例中，在對基板100進行薄化製程後(第1I圖)，自晶圓10上將載體500拆下，並移除黏著劑450。如第1K圖所示，沉積金屬化絕緣層127於介層窗107及108之突出邊上的基板100背面上。金屬化絕緣層127包含具有一層襯墊材料的數層絕緣材料層，其中此襯墊材料層可防止在金屬化製程中所沉積之任何金屬滲入晶圓10中。接著，在金屬化絕緣層127中蝕刻出凹槽130及131。如第1L圖所示，金屬化製程形成了接合墊132及133。沉積金屬，例如銅、鎢、鋁或其相似物，於金屬化絕緣層127，接著藉由蝕刻法或化學機械研磨法來蝕刻或移除金屬的多餘部分，以形成接合墊132及133。經過上述製程處理的晶圓在第1L圖中標示為晶圓10’。
第1M圖繪示晶圓11堆疊且接合至晶圓10’的剖面圖。晶圓11包含基板600、介電層624以及絕緣層626。基板600可包含一或複數個個預先形成的半導體元件，介電層624可用以隔離形成在不同互連層中的互連線路，而絕緣層626可用來限制兩晶圓上各種元件間的干擾。在接合墊607與132以及接合墊608與133處，將晶圓10及11對齊且接合在一起，而形成堆疊晶圓13。接合媒介，例如銅、鎢、銅錫合金、金錫合金、銦金合金、鉛錫合金或其相似物，塗佈於預備接合的晶圓10’及11上的接合接觸之間。
應該注意的是，雖然晶圓10、10’及11係以形成堆疊晶圓結構的方式來予以說明，在此所用的特定晶圓並非用以在任何方面限制本發明的實施例。在實際應用上，晶圓10、10’及11的結構可能為晶圓或晶粒，因此堆疊後的結構可能具有晶粒結合晶粒的結構、晶粒結合晶圓的結構或晶圓結合晶圓的結構。
亦應該注意的是，任何數目的不同裝置、元件、連接件或其相似結構可整合於晶圓10、10’及11中。在此所可能例示出之特定元件或缺少的元件並非用以在任何方面限制本發明之實施例。
應進一步注意的是，僅繪示一定數目的主動元件，例如裝置101A至101C，以及介層窗，例如介層窗107及108，以利清楚說明。然而，在此技術領域中具有通常知識者將可了解到，在實際應用中，與積體電路及堆疊式晶粒有關之積體電路系統可能包含數百萬甚至數千萬或更多的主動元件，且這些互連結構在最上層之介電層中可能包含數十種甚至數百種導體。相同地，在此技術領域中具有通常知識者將理解到，在實際應用上，每一個堆疊晶粒包含數十個或更多的利用導電介層窗或導線的背面連接。又，較佳實施例中的堆疊晶粒結構可能包含數十個或甚至數百個以上用以與積體電路封裝產生電性連接的接合接觸，例如，儘管只有顯示出三個接合接觸410至412。
第3圖係繪示在覆晶球柵陣列結構中的積體電路封裝20的剖面圖，其中積體電路封裝20包含較佳實施例的堆疊晶粒，例如堆疊晶圓12(第1J圖)或13(第1M圖)中的堆疊晶粒。在堆疊晶圓12、13中的堆疊晶粒形成之後，通常以陣列形式排列大量的接合接觸，例如接合接觸410-412，於接合表面75上。接合表面75透過銲錫塊(例如銲錫球)55，而貼附於封裝基板50，進一步透過封裝導線65而與印刷電路板(未繪示)產生電性連接。值得注意的是，在較佳實施例中，也可以用其它積體電路封裝系統來封裝堆疊晶粒。在另一個例子中，堆疊晶粒可直接銲接至印刷電路板以。可能在此例示出的特定元件或缺少的元件並非用以在任何方面限制本發明之實施例。
應該注意的是，上述每一個例子所描述或圖示出的晶圓及晶粒，意欲提供可應用在本發明之各種實施例的介層窗、接觸墊以及接合墊的替代實施例。在本發明之其它或替代實施例中，可利用例示之選擇的任意組合。這些說明實施例並非用以限制本發明之各種其它及/或替代實施例的實施。
更應注意的是，在說明實施例中所描述之不同層可依據所需功能或製程之可利用性而包含各種不同的材料。金屬化接合墊的金屬可以是任何適合的金屬或合金，例如銅、鎢、鋁、鋁銅及其相似物。再者，按照不同介電層或絕緣層的所需用途及功能，可使用任何介電材料，例如二氧化矽、氮化矽、碳化矽、氮氧化矽及其相似物。本發明並非僅限於使用任何特定範圍的化合物及材料。
更應注意的是，說明實施例中的不同層與凹槽可利用各種已知的製程來沉積或形成。例如，氧化物、介電質或其它層等各種不同層的形成都可以經由化學氣相沉積法(CVD)、原子層沉積法(ALD)或類似方法來達成。再者，由晶圓上移除材料可經由乾蝕刻或濕蝕刻、化學機械研磨法(CMP)或類似方法來達成。本發明並不受限於任何單一方法。
第4圖係繪示實施本發明之一實施例之示範步驟的流程圖。在步驟400中，在半導體元件形成於晶圓中之前，先形成一或複數個凹槽於第一晶圓中。上述凹槽由晶圓正表面延伸至與晶圓背表面相隔一預定距離處。在步驟410中，將導體材料，例如銅、鎢、鋁或其相似物，沉積至上述凹槽中，其中導體材料形成複數個介層窗。在一較佳實施例中，介層窗之尺寸(例如直徑)介於實質15微米至實質35微米，且高寬比之範圍由實質2：1至實質3.3：1。在步驟420中，於晶圓上形成半導體元件(例如互補金屬氧化物半導體、或雙極性裝置或其相似裝置)。在步驟430中，層間介電層沉積於半導體元件與介層窗上之晶圓的正表面上，其中層間介電層是由一材料所組成，此材料例如為二氧化矽、氮化矽、碳化矽、氮氧化矽、或其相似物。在步驟440中，一或複數個接觸形成於層間介電層中，其中數個選定接觸電性連接至數個選定的穿矽介層窗。
第5圖係繪示實施本發明之一實施例之示範步驟流程圖。在步驟500中，形成複數個半導體元件(例如互補式金屬氧化物半導體元件)於第一半導體晶圓之正面上。在步驟510中，沉積層間介電層至半導體元件上之晶圓的正表面上，其中層間介電層是由一材料所組成，此材料例如為二氧化矽、磷矽酸鹽玻璃(phosphosilicate glass；PSG)、氮化矽、碳化矽、氮氧化矽或其相似物等材料所組成。在步驟520中，形成一或複數個凹槽至半導體晶圓中。這些凹槽延伸穿過層間介電層與晶圓之正表面至與晶圓之背表面相隔一預定距離處。在步驟530中，將導體材料，例如銅、鎢、鋁、或其相似物，沉積至凹槽中，以在晶圓中形成穿矽介層窗。在一較佳實施例中，穿矽介層窗之尺寸(例如直徑)的範圍介於實質15微米至實質35微米之間，且高寬比之範圍介於實質2：1至實質3.3：1之間。在步驟540中，形成一或複數個接觸於層間介電層中，其中數個選定接點電性連接至數個選定穿矽介層窗。
第6圖係繪示實施本發明一實施例的示範步驟流程圖。在步驟600中，在形成半導體元件於晶圓中之前(例如第4圖)，或者在形成半導體元件於晶圓之後，但在形成複數個互連線路於晶圓上以連接形成於晶圓中的半導體元件之前(例如第5圖)，在第一晶圓中形成一或複數個凹槽。這些凹槽自晶圓之正表面延伸至與晶圓之背表面相隔一預定距離處。在步驟610中，在凹槽中沉積導體材料，例如銅、鎢、鋁或其相似物，此導體材料形成複數個穿矽介層窗。在此實施例中，這些穿矽介層窗之尺寸(例如直徑)的範圍介於實質15微米至實質35微米之間，且高寬比之範圍介於實質2：1至實質3.3：1之間。在步驟620中，在沉積於晶圓正表面上的一層間介電層中，形成一或複數個接觸，其中數個選定接點電性連接至數個選定穿矽介層窗。在步驟630中，沉積一或複數層金屬間介電層至層間介電層與接觸上。形成複數條金屬線路至介電層中，以電性耦接半導體元件及穿矽介層窗。在步驟640中，形成一或複數個接合接觸於前述之一或複數層介電層中，其中所述接合接觸電性連接至數個選定之金屬線路及/或穿矽介層窗。在步驟650中，將前述之一或複數個接合接觸對齊堆疊式晶粒對晶圓結構或晶圓對晶圓結構中之第二晶粒或晶圓上的一或複數個接觸表面上的一或複數個接合接觸。將接合媒介，例如銅、鎢、銅錫合金、金錫合金、銦金合金、鉛錫合金或其相似物，塗佈於欲接合晶圓上的接合接觸之間。接著，可對堆疊式晶粒對晶圓結構或堆疊式晶圓對晶圓結構進行切割或封裝，其中藉由銲錫凸塊，前述之一或多個接合接觸接合於積體電路封裝，再透過封裝導線而電性連接至印刷電路板。
第7圖係繪示實施本發明之一實施例之示範步驟流程圖。在步驟700中，以黏著劑將第一晶圓之正表面貼附至載體，其中第一晶圓具有一或複數個穿矽介層窗。在步驟710中，移除第一晶圓背面上的基板材料的一部分，以暴露出穿矽介層窗之背面連接。在步驟720中，製作一或複數個背面接合接觸，此背面接合接觸電性連接至連接穿矽介層窗所暴露出之背面連接。在步驟730中，以與接合接觸電性相容的材料，例如銅、鎢、金、銅錫合金、銦金合金、鉛錫合金或其相似物，將第一晶圓的背面接合接觸與另一晶圓的接合接觸對齊且接合。
雖然本發明及其優點已詳細描述如上，然應該了解到的一點是，在不偏離后附申請專利範圍所界定之本發明的精神與範圍下，當可在此進行各種改變、取代以及修正。此外，本申請案之範圍並非限制在說明書所描述之製程、機械、製造、物質成分、手段、方法以及步驟的特定實施例中。任何在此技術領域中具有通常知識者，將可輕易從本發明之揭露中了解到，現存或日後所發展出之可與上述之對應的實施例執行實質相同之功能、或達到實質相同之結果的製程、機械、製造、物質成分、手段、方法或步驟，可依據本發明來加以應用。因此，所附之申請專利範圍係用以將這類製程、機械、製造、物質成分、手段、方法或步驟涵括在其範圍內。
10、10’、11、12、13．．．晶圓
100．．．基板
101A、101B、101C．．．裝置
102．．．層間介電層
103、104．．．穿矽介層窗凹槽
105．．．介電襯
106．．．導體
107、108．．．穿矽介層窗
118A、118B、118C．．．接觸
120A、120B、120C．．．第一互連線路
127．．．金屬化絕緣層
130、131．．．凹槽
124、125．．．接觸墊
200．．．第一金屬間介電層
132、133．．．接合墊
210．．．互連線路
300．．．第二金屬間介電層
310．．．互連線路
via1a、via1b．．．介層窗
339．．．介電層
345．．．隔離層
347．．．介層窗
350．．．重佈層
410、411、412．．．接合接觸
450．．．黏著劑
500．．．載體
600．．．基板
607、608．．．接合墊
624．．．介電層
626．．．絕緣層
20．．．積體電路封裝
為了更完整地了解本發明及其優點，現結合所附圖式而參照以上之描述，其中：
第1A至1M圖係繪示根據本發明一實施例之形成具有穿矽介層窗的晶圓的剖面圖。
第2圖係繪示根據本發明一實施例之具有形成於基板與介電層中之穿矽介層窗的晶圓的剖面圖。
第3圖係繪示根據本發明一實施例之具有形成於基板與介電層中之穿矽介層窗的晶圓的剖面圖。
第4圖係繪示一堆疊晶圓結構之剖面圖。
第5圖係繪示實施本發明之一實施例的示範步驟流程圖。
第6圖係繪示實施本發明之一實施例的示範步驟流程圖。
第7圖係繪示實施本發明之一實施例的示範步驟流程圖。
10’、11、13．．．晶圓
100．．．基板
101A、101B、101C．．．裝置
102．．．層間介電層
120A、120B、120C．．．第一互連線路
124、125．．．接觸墊
127．．．金屬化絕緣層
130、131．．．凹槽
132、133．．．接合墊
200．．．第一金屬間介電層
210．．．互連線路
300．．．第二金屬間介電層
310．．．互連線路
339．．．介電層
345．．．隔離層
347．．．介層窗
410、411、412．．．接合接觸
600．．．基板
607、608．．．接合墊
624．．．介電層
626．．．絕緣層

Claims (18)

  1. 一個形成堆疊積體電路半導體晶粒的方法，包含：形成一或複數個凹槽於一第一半導體晶圓中；以一導體材料填滿該或該些凹槽，以形成一或複數個穿矽介層窗於該第一半導體晶圓中；形成一或複數個半導體元件於該第一半導體晶圓中；形成一層間介電層於該第一半導體晶圓上；形成一或複數個接觸墊於該層間介電層中，該些接觸墊電性接觸於該或該些半導體元件；形成一金屬間介電層於該層間介電層上；形成複數個互連金屬線路於該金屬間介電層中，該些互連金屬線路電性分別連接至該或該些穿矽介層窗以及該或該些接觸墊；形成一上介電層於該金屬間介電層上；形成一或複數個接合接觸於該上介電層中，該或該些接合接觸電性耦接至該些互連金屬線路之一者或複數者；貼附該第一半導體晶圓之該正面至一載體，並暴露出該第一半導體晶圓之一背面；薄化該第一半導體晶圓之該背面直到該或該些穿矽介層窗暴露出且稍微突出於該第一半導體晶圓之該背面；以及對齊及接合該或該些穿矽介層窗與一第二半導體晶粒或晶圓上之一或複數個接合表面上的一或複數個接合接觸。
  2. 如請求項1所述之方法，其中該或該些凹槽具有一直徑範圍介於實質5微米至實質50微米、以及一高寬比範圍介於實質12：1至實質3：1。
  3. 如請求項1所述之方法，其中該或該些接觸墊藉由一重佈導體層耦接至該或該些穿矽介層窗。
  4. 如請求項1所述之方法，其中形成或該些凹槽的步驟是在形成該或該些半導體元件的步驟之前。
  5. 如請求項1所述之方法，其中形成該或該些凹槽的步驟是在形成該些互連金屬線路的步驟之前。
  6. 如請求項1所述之方法，其中用以形成該或該些穿矽介層窗之該導體材料是選自於銅、鎢、鋁、金、銀及其組成物所組成之群組之一。
  7. 如請求項1所述之方法，其中在該薄化步驟之後，該第一半導體晶圓具有一厚度範圍介於實質25微米至實質250微米。
  8. 如請求項1所述之方法，更包含：在該薄化步驟後，形成一金屬化絕緣層於該第一半導體晶圓之該背面上；以及 形成一或複數個第二接合墊於該金屬化絕緣層中，其中該或該些第二接合墊電性連接至該或該些穿矽介層窗且稍微突出於該金屬化絕緣層。
  9. 如請求項8所述之方法，其中該或該些第二接合墊是藉由一重佈導體層電性耦接到該或該些穿矽介層窗。
  10. 一種形成堆疊積體電路半導體晶粒的方法，包含：提供一第一半導體晶圓，該第一半導體晶圓具有一或複數個穿矽介層窗形成於一基板中；形成一或複數個半導體元件於該第一半導體晶圓中；形成一或複數個第二接合接觸於該第一半導體晶圓之該正面上，經由該第一半導體晶圓上的一金屬間介電層中的一或複數個互連金屬線路，該或該些第二接合接觸電性耦接至該或該些半導體元件以及該或該些穿矽介層窗；貼附該第一半導體晶圓之一正表面至一載體，並暴露出該第一半導體晶圓之一背面；薄化該第一半導體晶圓之該背面直到該或該些穿矽介層窗暴露出且稍微突出於該第一半導體晶圓之該背面；形成一或複數個第一接合接觸於該第一半導體晶圓薄化後之該背面上的一金屬化絕緣層中，該或該些第一接合接觸電性耦接至該或該些穿矽介層窗；提供一第二半導體工件，該第二半導體工件具有一或複數個第二接合接觸位於該第二半導體工件的一接合表面上；以及 對齊以及接合該第一半導體晶圓上的該或該些第一接合接觸與該第二半導體工件上之對應的一或複數個接合接觸。
  11. 如請求項10所述之方法，其中該第二半導體工件包含一半導體晶圓，以及其中該接合步驟產生一晶圓對晶圓接合結構。
  12. 如請求項10所述之方法，其中該第二半導體工件包含一半導體晶粒，且其中該接合步驟產生一晶粒對晶圓接合結構。
  13. 如請求項10所述之方法，其中該或該些穿矽介層窗具有一直徑範圍介於實質5微米至實質50微米、以及一高寬比範圍介於實質12：1至實質3：1。
  14. 如請求項10所述之方法，其中在該薄化步驟後，該第一半導體晶圓具有一厚度範圍介於實質25微米至實質250微米。
  15. 如請求項10所述之方法，其中用來形成一或多個穿矽介層窗的該導體材料是選自由銅、鎢、鋁、金、銀及其組成物所組成之群組之一。
  16. 如請求項10所述之方法，其中在形成該或該些穿矽介層窗之後，才進行形成該或該些半導體元件於該第一半導體晶圓中之步驟。
  17. 如請求項10所述之方法，其中形成該或該些半導體元件於該第一半導體晶圓中的步驟係在半導體元件形成該或該些互連金屬線路之步驟前。
  18. 如請求項10所述之方法，更包含：藉由在一覆晶積體電路封裝結構中之複數個凸塊，接合將該堆疊積體電路半導體晶粒上之該或該些第二接合接觸接合至一積體電路封裝基板。
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FR2946795B1 (fr) * 2009-06-12 2011-07-22 3D Plus Procede de positionnement des puces lors de la fabrication d'une plaque reconstituee
US8304863B2 (en) 2010-02-09 2012-11-06 International Business Machines Corporation Electromigration immune through-substrate vias
KR101107627B1 (ko) * 2010-02-22 2012-01-25 (주)실리콘화일 3차원 구조를 갖는 웨이퍼의 패드 형성 방법
US8674510B2 (en) * 2010-07-29 2014-03-18 Taiwan Semiconductor Manufacturing Company, Ltd. Three-dimensional integrated circuit structure having improved power and thermal management
US8435835B2 (en) 2010-09-02 2013-05-07 Stats Chippac, Ltd. Semiconductor device and method of forming base leads from base substrate as standoff for stacking semiconductor die
US9224647B2 (en) * 2010-09-24 2015-12-29 Stats Chippac, Ltd. Semiconductor device and method of forming TSV interposer with semiconductor die and build-up interconnect structure on opposing surfaces of the interposer
US8993377B2 (en) 2010-09-29 2015-03-31 Stats Chippac, Ltd. Semiconductor device and method of bonding different size semiconductor die at the wafer level
CN102024801B (zh) * 2010-10-12 2012-11-21 北京大学 超薄芯片垂直互联封装结构及其制造方法
KR101697573B1 (ko) * 2010-11-29 2017-01-19 삼성전자 주식회사 반도체 장치, 그 제조 방법, 및 상기 반도체 장치를 포함하는 반도체 패키지
TWI416679B (zh) * 2010-12-06 2013-11-21 Ind Tech Res Inst 半導體結構及其製造方法
US8354327B2 (en) * 2011-04-21 2013-01-15 Globalfoundries Singapore Pte Ltd Scheme for planarizing through-silicon vias
US9177893B2 (en) * 2011-05-17 2015-11-03 Infineon Technologies Ag Semiconductor component with a front side and a back side metallization layer and manufacturing method thereof
US8552567B2 (en) 2011-07-27 2013-10-08 Micron Technology, Inc. Semiconductor die assemblies, semiconductor devices including same, and methods of fabrication
US8937309B2 (en) 2011-08-08 2015-01-20 Micron Technology, Inc. Semiconductor die assemblies, semiconductor devices including same, and methods of fabrication
US8552548B1 (en) * 2011-11-29 2013-10-08 Amkor Technology, Inc. Conductive pad on protruding through electrode semiconductor device
FR2983638A1 (fr) * 2011-12-02 2013-06-07 St Microelectronics Sa Procede de formation d'un circuit integre
KR101918609B1 (ko) * 2012-01-11 2018-11-14 삼성전자 주식회사 집적회로 소자
CN103378015B (zh) * 2012-04-20 2016-04-27 南亚科技股份有限公司 半导体芯片与封装结构以及其形成方法
US20140147984A1 (en) * 2012-11-27 2014-05-29 United Microelectronics Corp. Semiconductor device and method of fabricating through silicon via structure
TWI492340B (zh) * 2012-12-12 2015-07-11 Ind Tech Res Inst 封裝結構及其製造方法
KR102038488B1 (ko) 2013-02-26 2019-10-30 삼성전자 주식회사 반도체 패키지의 제조 방법
US9406588B2 (en) 2013-11-11 2016-08-02 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor package and manufacturing method thereof
US9437572B2 (en) * 2013-12-18 2016-09-06 Taiwan Semiconductor Manufacturing Company, Ltd. Conductive pad structure for hybrid bonding and methods of forming same
US9431351B2 (en) 2014-10-17 2016-08-30 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor package and manufacturing method of the same
US9659863B2 (en) 2014-12-01 2017-05-23 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices, multi-die packages, and methods of manufacture thereof
US9502272B2 (en) 2014-12-29 2016-11-22 Taiwan Semiconductor Manufacturing Company, Ltd. Devices and methods of packaging semiconductor devices
US9601410B2 (en) 2015-01-07 2017-03-21 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
US10319701B2 (en) 2015-01-07 2019-06-11 Taiwan Semiconductor Manufacturing Company, Ltd. Bonded 3D integrated circuit (3DIC) structure
US9633958B2 (en) 2015-01-30 2017-04-25 Taiwan Semiconductor Manufacturing Company, Ltd. Bonding pad surface damage reduction in a formation of digital pattern generator
US10163709B2 (en) 2015-02-13 2018-12-25 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
US10497660B2 (en) 2015-02-26 2019-12-03 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structures, packaged semiconductor devices, and methods of packaging semiconductor devices
US9786519B2 (en) 2015-04-13 2017-10-10 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor devices and methods of packaging semiconductor devices
US9748212B2 (en) 2015-04-30 2017-08-29 Taiwan Semiconductor Manufacturing Company, Ltd. Shadow pad for post-passivation interconnect structures
US10340258B2 (en) 2015-04-30 2019-07-02 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structures, packaged semiconductor devices, and methods of packaging semiconductor devices
JP2016225471A (ja) * 2015-05-29 2016-12-28 株式会社東芝 半導体装置および半導体装置の製造方法
US9969614B2 (en) 2015-05-29 2018-05-15 Taiwan Semiconductor Manufacturing Company, Ltd. MEMS packages and methods of manufacture thereof
US9520385B1 (en) 2015-06-29 2016-12-13 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method for forming same
US10170444B2 (en) 2015-06-30 2019-01-01 Taiwan Semiconductor Manufacturing Company, Ltd. Packages for semiconductor devices, packaged semiconductor devices, and methods of packaging semiconductor devices
US9536865B1 (en) 2015-07-23 2017-01-03 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnection joints having variable volumes in package structures and methods of formation thereof
US9570431B1 (en) 2015-07-28 2017-02-14 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor wafer for integrated packages
US9570410B1 (en) 2015-07-31 2017-02-14 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming connector pad structures, interconnect structures, and structures thereof
US9691695B2 (en) 2015-08-31 2017-06-27 Taiwan Semiconductor Manufacturing Company, Ltd. Monolithic 3D integration inter-tier vias insertion scheme and associated layout structure
US10644229B2 (en) 2015-09-18 2020-05-05 Taiwan Semiconductor Manufacturing Company, Ltd. Magnetoresistive random access memory cell and fabricating the same
US10269682B2 (en) 2015-10-09 2019-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Cooling devices, packaged semiconductor devices, and methods of packaging semiconductor devices
US9659878B2 (en) 2015-10-20 2017-05-23 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer level shielding in multi-stacked fan out packages and methods of forming same
US10163856B2 (en) 2015-10-30 2018-12-25 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked integrated circuit structure and method of forming
US9691723B2 (en) 2015-10-30 2017-06-27 Taiwan Semiconductor Manufacturing Company, Ltd. Connector formation methods and packaged semiconductor devices
US9911623B2 (en) 2015-12-15 2018-03-06 Taiwan Semiconductor Manufacturing Company, Ltd. Via connection to a partially filled trench
US9589941B1 (en) 2016-01-15 2017-03-07 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-chip package system and methods of forming the same
US9773757B2 (en) 2016-01-19 2017-09-26 Taiwan Semiconductor Manufacturing Company, Ltd. Devices, packaged semiconductor devices, and semiconductor device packaging methods
US9741669B2 (en) 2016-01-26 2017-08-22 Taiwan Semiconductor Manufacturing Company, Ltd. Forming large chips through stitching
US10050018B2 (en) 2016-02-26 2018-08-14 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC structure and methods of forming
US9842829B2 (en) 2016-04-29 2017-12-12 Taiwan Semiconductor Manufacturing Co., Ltd. Chip package structure and method for forming the same
US10147704B2 (en) 2016-05-17 2018-12-04 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices and methods of manufacturing thereof
US9859258B2 (en) 2016-05-17 2018-01-02 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacture
US9793246B1 (en) 2016-05-31 2017-10-17 Taiwan Semiconductor Manufacturing Co., Ltd. Pop devices and methods of forming the same
US9881903B2 (en) 2016-05-31 2018-01-30 Taiwan Semiconductor Manufacturing Company, Ltd. Package-on-package structure with epoxy flux residue
US9875982B2 (en) 2016-06-01 2018-01-23 Taiwan Semiconductor Manufacturing Company Ltd Semiconductor device and manufacturing method thereof
US10050024B2 (en) 2016-06-17 2018-08-14 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor package and manufacturing method of the same
US10475769B2 (en) 2016-06-23 2019-11-12 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor package and manufacturing method of the same
US10229901B2 (en) 2016-06-27 2019-03-12 Taiwan Semiconductor Manufacturing Company, Ltd. Immersion interconnections for semiconductor devices and methods of manufacture thereof
US10115675B2 (en) 2016-06-28 2018-10-30 Taiwan Semiconductor Manufacturing Co., Ltd. Packaged semiconductor device and method of fabricating a packaged semiconductor device
US9941186B2 (en) 2016-06-30 2018-04-10 Taiwan Semiconductor Manufacturing Company Ltd. Method for manufacturing semiconductor structure
US10685911B2 (en) 2016-06-30 2020-06-16 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor package and manufacturing method of the same
US10163805B2 (en) 2016-07-01 2018-12-25 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and method for forming the same
US9966360B2 (en) 2016-07-05 2018-05-08 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package and manufacturing method thereof
US9893046B2 (en) 2016-07-08 2018-02-13 Taiwan Semiconductor Manufacturing Co., Ltd. Thinning process using metal-assisted chemical etching
US9875972B1 (en) 2016-07-14 2018-01-23 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device structure and method for forming the same
US9870975B1 (en) 2016-07-14 2018-01-16 Taiwan Semiconductor Manufacturing Co., Ltd. Chip package with thermal dissipation structure and method for forming the same
US10269732B2 (en) 2016-07-20 2019-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Info package with integrated antennas or inductors
US10332841B2 (en) 2016-07-20 2019-06-25 Taiwan Semiconductor Manufacturing Company, Ltd. System on integrated chips and methods of forming the same
US10157885B2 (en) 2016-07-29 2018-12-18 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure having magnetic bonding between substrates
US10720360B2 (en) 2016-07-29 2020-07-21 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor die singulation and structures formed thereby
US10120971B2 (en) 2016-08-30 2018-11-06 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package and layout method thereof
US10049981B2 (en) 2016-09-08 2018-08-14 Taiwan Semiconductor Manufacturing Company Ltd. Through via structure, semiconductor device and manufacturing method thereof
US11097942B2 (en) 2016-10-26 2021-08-24 Analog Devices, Inc. Through silicon via (TSV) formation in integrated circuits
US10170429B2 (en) 2016-11-28 2019-01-01 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming package structure including intermetallic compound
US10153320B2 (en) 2016-11-29 2018-12-11 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and method of forming the same
US10153218B2 (en) 2016-11-29 2018-12-11 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and manufacturing method thereof
TWI708358B (zh) * 2017-07-11 2020-10-21 聯華電子股份有限公司 半導體裝置及其製造方法
CN112164688B (zh) * 2017-07-21 2023-06-13 联华电子股份有限公司 芯片堆叠结构及管芯堆叠结构的制造方法
US10879183B2 (en) 2018-06-22 2020-12-29 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacture
US11172142B2 (en) 2018-09-25 2021-11-09 Taiwan Semiconductor Manufacturing Co., Ltd. Image sensor for sensing LED light with reduced flickering
US11201122B2 (en) 2018-09-27 2021-12-14 Taiwan Semiconductor Manufacturing Co., Ltd. Method of fabricating semiconductor device with reduced warpage and better trench filling performance
US11552019B2 (en) * 2019-03-12 2023-01-10 Intel Corporation Substrate patch reconstitution options
US11004829B2 (en) 2019-10-07 2021-05-11 Sandisk Technologies Llc Memory scaling semiconductor device
US11217560B2 (en) * 2019-10-28 2022-01-04 Nanya Technology Corporation Die assembly and method of manufacturing the same
US11133304B2 (en) 2019-11-27 2021-09-28 Taiwan Semiconductor Manufacturing Co., Ltd. Packaging scheme involving metal-insulator-metal capacitor
US20210296281A1 (en) * 2020-03-20 2021-09-23 Integrated Silicon Solution Inc. Wafer-bonding structure and method of forming thereof
US11276764B1 (en) * 2020-08-09 2022-03-15 Global Communication Semiconductors, Llc Method of making high frequency InGaP/GaAs HBTs
TWI839620B (zh) 2021-06-30 2024-04-21 立積電子股份有限公司 半導體裝置及形成半導體裝置之方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050136635A1 (en) * 2003-12-17 2005-06-23 Sergey Savastiouk Attachment of integrated circuit structures and other substrates to substrates with vias
TW200839915A (en) * 2007-03-19 2008-10-01 Taiwan Semiconductor Mfg Semiconductor die and package structure
TW200840041A (en) * 2003-12-30 2008-10-01 Fairchild Semiconductor Power semiconductor devices and methods of manufacture
TW200843061A (en) * 2007-04-27 2008-11-01 Taiwan Semiconductor Mfg Semiconductor package structure

Family Cites Families (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05211239A (ja) 1991-09-12 1993-08-20 Texas Instr Inc <Ti> 集積回路相互接続構造とそれを形成する方法
DE4314907C1 (de) 1993-05-05 1994-08-25 Siemens Ag Verfahren zur Herstellung von vertikal miteinander elektrisch leitend kontaktierten Halbleiterbauelementen
US5391917A (en) 1993-05-10 1995-02-21 International Business Machines Corporation Multiprocessor module packaging
US6882030B2 (en) 1996-10-29 2005-04-19 Tru-Si Technologies, Inc. Integrated circuit structures with a conductor formed in a through hole in a semiconductor substrate and protruding from a surface of the substrate
EP2270845A3 (en) 1996-10-29 2013-04-03 Invensas Corporation Integrated circuits and methods for their fabrication
US6037822A (en) 1997-09-30 2000-03-14 Intel Corporation Method and apparatus for distributing a clock on the silicon backside of an integrated circuit
US5998292A (en) 1997-11-12 1999-12-07 International Business Machines Corporation Method for making three dimensional circuit integration
US6274253B1 (en) * 1998-11-13 2001-08-14 Micron Technology, Inc. Processing methods for providing metal-comprising materials within high aspect ratio openings
JP3532788B2 (ja) 1999-04-13 2004-05-31 唯知 須賀 半導体装置及びその製造方法
US6322903B1 (en) 1999-12-06 2001-11-27 Tru-Si Technologies, Inc. Package of integrated circuits and vertical integration
US6444576B1 (en) 2000-06-16 2002-09-03 Chartered Semiconductor Manufacturing, Ltd. Three dimensional IC package module
US6599778B2 (en) 2001-12-19 2003-07-29 International Business Machines Corporation Chip and wafer integration process using vertical connections
EP1472730A4 (en) 2002-01-16 2010-04-14 Mann Alfred E Found Scient Res HOUSING FOR ELECTRONIC CIRCUITS WITH REDUCED SIZE
US6762076B2 (en) 2002-02-20 2004-07-13 Intel Corporation Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices
US6800930B2 (en) 2002-07-31 2004-10-05 Micron Technology, Inc. Semiconductor dice having back side redistribution layer accessed using through-silicon vias, and assemblies
US7030481B2 (en) 2002-12-09 2006-04-18 Internation Business Machines Corporation High density chip carrier with integrated passive devices
US6841883B1 (en) 2003-03-31 2005-01-11 Micron Technology, Inc. Multi-dice chip scale semiconductor components and wafer level methods of fabrication
US6924551B2 (en) 2003-05-28 2005-08-02 Intel Corporation Through silicon via, folded flex microelectronic package
US7111149B2 (en) 2003-07-07 2006-09-19 Intel Corporation Method and apparatus for generating a device ID for stacked devices
TWI251313B (en) 2003-09-26 2006-03-11 Seiko Epson Corp Intermediate chip module, semiconductor device, circuit board, and electronic device
US7335972B2 (en) 2003-11-13 2008-02-26 Sandia Corporation Heterogeneously integrated microsystem-on-a-chip
US7060601B2 (en) 2003-12-17 2006-06-13 Tru-Si Technologies, Inc. Packaging substrates for integrated circuits and soldering methods
JP4467318B2 (ja) 2004-01-28 2010-05-26 Ｎｅｃエレクトロニクス株式会社 半導体装置、マルチチップ半導体装置用チップのアライメント方法およびマルチチップ半導体装置用チップの製造方法
JP4205613B2 (ja) 2004-03-01 2009-01-07 エルピーダメモリ株式会社 半導体装置
US7262495B2 (en) 2004-10-07 2007-08-28 Hewlett-Packard Development Company, L.P. 3D interconnect with protruding contacts
US7297574B2 (en) 2005-06-17 2007-11-20 Infineon Technologies Ag Multi-chip device and method for producing a multi-chip device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050136635A1 (en) * 2003-12-17 2005-06-23 Sergey Savastiouk Attachment of integrated circuit structures and other substrates to substrates with vias
TW200840041A (en) * 2003-12-30 2008-10-01 Fairchild Semiconductor Power semiconductor devices and methods of manufacture
TW200839915A (en) * 2007-03-19 2008-10-01 Taiwan Semiconductor Mfg Semiconductor die and package structure
TW200843061A (en) * 2007-04-27 2008-11-01 Taiwan Semiconductor Mfg Semiconductor package structure

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI719202B (zh) * 2016-09-02 2021-02-21 台灣積體電路製造股份有限公司 半導體封裝結構及其製造方法

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