KR101171526B1 - 캐리어 웨이퍼 수정을 통한 ｔｓｖ 후면 상호연결부 형성의 개선 - Google Patents

캐리어 웨이퍼 수정을 통한 ｔｓｖ 후면 상호연결부 형성의 개선 Download PDF

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KR101171526B1
KR101171526B1 KR1020100058111A KR20100058111A KR101171526B1 KR 101171526 B1 KR101171526 B1 KR 101171526B1 KR 1020100058111 A KR1020100058111 A KR 1020100058111A KR 20100058111 A KR20100058111 A KR 20100058111A KR 101171526 B1 KR101171526 B1 KR 101171526B1
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wafer
notch
semiconductor wafer
carrier
carrier wafer
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KR1020100058111A
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KR20110000502A (ko
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혼-린 황
칭-웬 샤오
큐오-칭 수
첸-시엔 첸
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타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드
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Abstract

집적 회로 구조는 반도체 웨이퍼를 포함하며, 상기 반도체 웨이퍼는 그 모서리로부터 내측으로 연장된 제1 노치를 포함한다. 캐리어 웨이퍼가 반도체 웨이퍼 상에 장착된다. 캐리어 웨이퍼는 상기 제1 노치의 적어도 일부분 위에 배치되는 제2 노치를 갖는다. 반도체 웨이퍼를 마주하는 캐리어 웨이퍼의 일측면은 캐리어 웨이퍼의 가장자리에 날카로운 각을 형성한다. 캐리어 웨이퍼는 약 1x108 Ohm-cm 이하의 저항률을 갖는다.

Description

캐리어 웨이퍼 수정을 통한 ＴＳＶ 후면 상호연결부 형성의 개선 {Improving the Formation of TSV Backside Interconnects by Modifying Carrier Wafers}
본 발명은 집적 회로 구조들에 관한 것으로서, 보다 특정적으로는 관통-실리콘-비아들(through-silicon-vias), 및 보다 더 특정적으로는 웨이퍼들의 후면 상에있으며 상기 관통-실리콘-비아들과 연결되는 상호연결 구조들(interconnect structures)의 형성에 관한 것이다.
집적 회로가 발명된 이래로, 다양한 전자 부품들(예로써, 트랜지스터, 다이오드, 저항, 축전기, 등)의 지속적인 집적도 향상으로 인해 반도체 산업은 지속적인 고속 성장을 이뤄 왔다. 무엇보다도, 이러한 집적도 향상은 최소 피처(feature) 사이즈의 계속적인 감소에 따른 것이며, 이는 주어진 칩 영역에 보다 많은 부품들이 집적될 수 있도록 한다.
집적된 부품들이 차지하는 공간은 본질적으로 반도체 웨이퍼의 표면 상에 존재한다는 점에서, 집적도 향상은 자연히 실질적으로 2차원(2D)적이다. 비록 리소그래피(lithography)의 놀란만한 향상에 의해 2차원 집적 회로 형성에 대한 상당한 발전이 있었지만, 2차원적으로 성취 가능한 밀도에는 물리적인 제약들이 있다. 이러한 제약들 중 하나는 그러한 부품들을 만드는데 요구되는 최소 사이즈이다. 또한, 보다 많은 장치들이 하나의 칩에 실장될 때, 보다 복잡한 설계들이 요구된다.
추가적인 제약은, 장치들 개수가 증가함에 따라 장치들 간의 상호연결부들의 개수 및 길이가 상당히 증가한다는 것에 기인한다. 상호연결부들의 개수 및 길이가 증가할 때, 회로 RC 지연(circuit RC delay) 및 전력 소비가 증가한다.
전술한 제약들을 해결하기 위한 노력들은 3차원 집적 회로들(3DICs)의 사용을 포함하며 적층된 다이들(stacked dies)이 공통적으로 사용된다. 따라서 3DIC들 및 적층 다이들에서는 관통-실리콘 비아들(TSVs)이 사용된다. 이러한 경우, TSV들은 다이 상의 집적 회로들을 다이의 후면에 연결하기 위해 종종 사용된다. 그리고, TSV들은 다이의 후면을 통해 집적 회로들을 접지(grounding)시키기 위한 짧은 접지 경로들을 제공하기 위해 또한 사용되며, 이들 경로들은 접지된 금속성 필름에 의해 덮여질 수 있다.
후면 TSV 연결부들의 통상적인 형성 공정은 단점들로 인한 곤란을 겪는다. 후면 상호연결 구조의 제조에서 중간 단계의 단면도를 도시하는 도 1을 참조하면, 실리콘 웨이퍼(100)는 TSV들(102)을 포함한다. 실리콘 웨이퍼(100)는 접착제(106)를 통해 캐리어 웨이퍼(104: carrier wafer) 상에 설치된다. 실리콘 웨이퍼(100) 상에 UBM(108: under-bump metallurgy)이 증착된다. 캐리어 웨이퍼(104)는 전형적으로 실리콘 웨이퍼(100)보다 더 크다. 따라서 UBM(108)은 캐리어 웨이퍼(104) 상에 또한 증착된다. 캐리어 웨이퍼(104)가 경사 영역들(110: beveled areas)을 갖기 때문에, UBM(108)은 경사 영역들(110) 상에 증착되는 부분들을 포함하며, UBM(108)의 이러한 부분들은 긁히거나 벗겨지기 쉽다. 제조 공정들에서, 도 1에 도시된 구조는 로봇들에 의해 클램핑되거나 이송된다. 경사 영역들(110) 상의 UBM(108)의 영역들이 클램프들 또는 로봇들에 의해 클램핑되거나 접촉될 때, 파티클들(particles)이 떨어져 상기 웨이퍼들을 오염시킬 수 있다.
다른 하나의 문제점은 노치(notch)들을 찾아내기 어렵다는 것이다. 도 2a는 도 1에 도시된 구조의 평면도를 도시한다. 정렬 목적으로 실리콘 웨이퍼(100) 상에 노치(112)가 형성된다. 도 2b는 도 2a에 도시된 구조의 단면도를 도시하며, 이 단면도는 도 2a의 평면 교차선 2B-2B에 의해 얻어진 것이다. 노치(112)를 통해 노출된 캐리어 웨이퍼(104)의 영역에 UBM(108)이 또한 증착되어 있음을 유념한다. UBM(108)은 투명하지 않기 때문에, 포토 스테퍼(photo stepper)와 같은 도구들은 종종 노치(112)를 찾을 수 없으며, 따라서 후속 공정들을 위한 정렬을 수행할 수 없다.
후면 TSV 연결을 형성하기 위해, 도 1에 도시된 구조는 챔버들 내에 배치되며 정전 척(electrostatic chuck: ESC 또는 E-Chuck)에 의해 고정될 필요가 있다. 하지만, 캐리어 웨이퍼(104)는 전형적으로 유리로 형성되며 ESC에 단단히 고정될 수 없다. 이는 부분적으로, 유리 내의 부적절한 이동성 이온들 때문이다. 따라서 전술한 문제점들을 극복하기 위한 후면 상호연결 구조 및 그 제조 방법이 필요하다.
본 발명의 일 관점에 따르면, 집적 회로 구조는 반도체 웨이퍼를 포함하며, 상기 반도체 웨이퍼는 상기 반도체 웨이퍼의 일 가장자리로부터 상기 반도체 웨이퍼 안으로 연장된 제1 노치를 포함한다. 상기 반도체 웨이퍼 상에 캐리어 웨이퍼가 장착된다. 상기 캐리어 웨이퍼는 상기 제1 노치의 적어도 일부분과 중첩되는 제2 노치를 갖는다. 상기 반도체 웨이퍼를 마주하는 상기 캐리어 웨이퍼의 일 측면은 상기 캐리어 웨이퍼의 일 가장자리와 예리한 각도를 형성한다. 상기 캐리어 웨이퍼는 약 1x108 Ohm-cm 이하의 저항률을 갖는다.
다른 실시예들이 또한 개시된다.
본 발명의 유리한 특징들은 보다 신뢰성 있는 정렬, 감소된 파티클 생성, 및 캐리어 웨이퍼들을 E-척들 상에 고정하는 능력의 개선을 포함한다.
본 발명 및 그의 이점들에 대한 보다 완전한 이해를 위해, 첨부된 도면들과 연계한 이하의 설명들이 참조된다.
도 1은 TSV 후면 연결부들의 제조에서 하나의 중간 단계에 대한 단면도를 도시하며, 여기서 캐리어 웨이퍼의 경사 영역들은 UBM(under-bump metallurgy) 층으로 증착되어 있다.
도 2a는 캐리어 웨이퍼 상에 설치된 실리콘 웨이퍼의 평면도를 도시하며, 실리콘 웨이퍼에는 노치가 형성되어 있다.
도 2b는 도 2a에 도시된 구조이 단면도를 도시한다.
도 3a 내지 12는 일 실시예에 따른, 상호연결 구조의 제조에서의 중간 단계들에 대한 평면도들 및 단면도들이다.
이하에서는 본 발명의 실시예들의 제조 및 사용이 설명된다. 하지만, 상기 실시예들은 폭넓은 특정 항목들로 구체화될 수 있는 적용가능한 발명적 개념들을 제공함을 이해되어야 한다. 설명되는 특정 실시예들은 본 발명을 제조하고 사용하는 특정 발명을 예시하는 것에 불과하며 본 발명의 범위를 제한하는 것은 아니다.
관통-실리콘 비아(TSV: through-silicon via)(또는 관통-반도체 비아(through-semiconductor via)'로 알려짐)들에 연결되는 신규한 후면 상호연결 구조(backside interconnect structure)가 제공된다. 일 실시예의 제조과정의 중간 단계들이 예시된다. 실시예들의 변경들이 설명된다. 다양한 관점들 및 예시적 실시예들을 통하여, 동일 요소들을 가리키기 위해 동일 참조 번호들이 사용된다.
도 3a를 참조하면, 기판(10)을 포함하는 웨이퍼(2)가 제공된다. 기판(10)은 벌크 실리콘 기판(bulk silicon substrate)과 같은 반도체 기판일 수 있으며, 다만 그것은 Ⅲ족, Ⅳ족, 및/또는 Ⅴ족 원소들과 같은 다른 반도체 물질들을 포함할 수 있다. 기판(10)의 전면(도 3a에서 위를 향하는 표면)에는 트랜지스터(블럭 4로 도시됨)와 같은 집적 회로 장치들이 형성될 수 있다. 내부에 형성된 금속선들 및 비아들(미도시)을 포함하는 상호연결 구조(12: interconnect structure)가 기판(10) 위에 형성되어 상기 집적회로 장치들에 연결될 수 있다. 상기 금속선들 및 비아들은 구리 또는 구리 합금들로 형성될 수 있으며, 잘 알려진 다마신 공정들(damascene processes)을 사용하여 형성될 수 있다. 상호연결 구조(12)는 일반적으로 공지된 상호-층 유전체들(inter-layer dielectrics: ILDs) 및 상호-금속 유전체들(inter-metal dielectrics: IMDs)을 포함할 수 있다.
TSV(20)는 기판(10)에 형성되며, 기판(10)의 전면(도 3a에서 위를 향하는 면)으로부터 기판(10) 내부로 연장된다. 제1 실시예에서는, 도 3a에 도시된 바와 같이, TSV(20)는 비아-퍼스트 방법(via-first approach)을 사용하여 형성되며, 하부 금속층(bottom metallization layer, 일반적으로 M1으로 공지됨)을 형성하기 이전에 형성된다. 따라서, TSV(20)는 활성 장치들(active devices)을 커버하기 위해 사용되는 ILD 안으로만 연장될 뿐이며, 상호연결 구조(12) 내의 IMD 층들 안으로는 연장되지 않는다. 대안적인 실시예들(미도시)에서, TSV(20)는 비아-라스트 방법(via-last approach)을 사용하여 형성됨으로써, 상호연결 구조(12)를 형성한 이후 형성된다. 따라서, TSV(20)는 기판(10)과 상호연결 구조(12)를 모두 관통한다. TSV(20)의 측벽들 상에 고립층(22: isolation layer)이 형성되어 TSV(20)를 기판(10)으로부터 절연한다. 고립층(22)은 실리콘 나이트라이드(silicon nitride), 실리콘 옥사이드(silicon oxide), TEOS 옥사이드(tetra-ethyl-ortho-silicate oxide) 등과 같은 일반적으로 사용되는 유전체 물질들로 형성될 수 있다.
도 3b는 웨이퍼(2)의 평면도를 도시하며, 이는 웨이퍼(2)에 노치(15)가 형성된 것을 예시하고 있다. 노치(15)는 웨이퍼(2)의 일 표면으로부터 반대 표면으로 연장될 수 있다(양 표면은 평탄한 표면들임). 또한, 노치(15)는 웨이퍼(2)의 가장자리로부터 내측으로 연장된다. 일 실시예에서, 노치(15)는 평면도 상에서 직사각형과 같은 다른 형상들을 가질 수 있다.
도 4a는 캐리어 웨이퍼(16)(캐리어 기판으로도 지칭됨)의 평면도를 도시한다. 캐리어 웨이퍼(16)는 유리, Si, 또는 유리 세라믹스(glass ceramics) 등으로 형성될 수 있다. 일 실시예에서, 캐리어 웨이퍼(16)는 대략 1x108 Ohm-cm 이하의 저항률(resistivity)을 갖는다. 상기 저항률은 또한 대략 1x106 Ohm-cm 이하일 수도 있고, 심지어 대략 1x103 Ohm-cm 이하일 수도 있다. 이는, 예로써 캐리어 웨이퍼(16)의 제조시 Na, K, Al 등과 같은 보다 많은 이동성 이온들(mobile ions)을 적절한 농도로 도핑(doping)함으로써 달성될 수 있다. 캐리어 웨이퍼(16)의 저항률을 감소시킴으로써, 후속 공정들에서, 캐리어 웨이퍼(16)는 보다 신뢰성 있게 정전 척(electrostatic chuck)에 고정될 수 있다.
캐리어 웨이퍼(16)도 노치(17)를 포함하며, 상기 노치도 캐리어 웨이퍼(16)의 일 표면으로부터 반대측 표면으로 연장될 수 있다(두 표면들은 평탄한 표면들임). 일 실시예에서, 캐리어 웨이퍼(16)의 직경(D2)은 웨이퍼(2)의 직경(D1)보다 크다. 또한, 캐리어 웨이퍼(16)의 중심(C2)으로부터 노치(17) 까지의 거리(S2)는 웨이퍼(2)의 반경(R1)(도 3b 참조)보다 작다. 상기 거리 S2는 또한 웨이퍼(2)의 중심(C1)으로부터 노치(15)의 최단 지점까지의 거리(S1)보다 크거나, 같거나, 또는 작을 수 있다.
도 4b는 캐리어 웨이퍼(16)의 단면도를 도시한다. 바람직하게는, 상측 모서리들(19)(이후 결합되는 웨이퍼(2)를 마주하는 측면에 있으며, 상기 웨이퍼는 점선들을 사용하여 도시되어 있음)은 어떠한 경사 영역들도 갖지 않는 날카로운 형상(sharp profile)을 갖는다. 즉, 캐리어 웨이퍼(16)의 상기 측면은 캐리어 웨이퍼(16)의 가장자리에 날카로운 각(예로써, 90°)을 형성한다.
도 5a를 참조하면, 결합 패드(14: bond pad)는 웨이퍼(2)의 전방 측면(도 3a에서 위를 향하는 측면)에 형성되어 웨이퍼(2)의 상기 전면을 넘어 돌출된다. 이후 웨이퍼(2)는 접착제(18)를 통해 캐리어 웨이퍼(16)에 설치된다. 바람직하게는, 이러한 결합 이후, 웨이퍼(2)와 캐리어 웨이퍼(16)를 포함하는 조합 구조의 뒤틀림(W: warpage)(도 5e 및 5f 참조)은 대략 20 ㎛ 이하이거나, 심지어 대략 1 ㎛ 이하이다. 도 5e는 뒤틀림(W)의 제1 예를 도시한다. 도 5f에 도시된 바와 같이, 뒤틀림(W)은 반대 방향으로 일어날 수도 있다. 뒤틀림(W)의 감소는 유리 평탄도(flatness) 또는 접착 물질 조절에 의해 달성될 수 있다.
도 5b는 도 5a에 도시된 구조의 평면도를 도시한다. 일 실시예에서는, 도 5b에 도시된 바와 같이, 노치(17)의 일부분이 노치(15) 전체와 중첩되며 웨이퍼(2) 아래로 연장될 수 있다. 대안적인 실시예들에서는, 도 5c에 도시된 바와 같이, 노치(17)의 가장자리들은 노치(15)의 가장자리들과 정렬된다. 또 다른 실시예들에서는, 도 5d에 도시된 바와 같이, 노치(17) 전체가 노치(15)의 단지 일부분과 중첩된다.
도 6에서, 기판(10)의 잉여 부분들을 제거하기 위해 후면 그라인딩(backside grinding)이 수행된다. 웨이퍼(2)의 후면에 화학적 기계적 연마(CMP)가 수행됨으로써, TSV(20)가 노출된다. 기판(10)의 후면을 커버하기 위해 후면 고립층(24)이 형성된다. 예시적인 일 실시예에서, 후면 고립층(24)을 형성하는 것은, 기판(10)의 후면을 다시 에칭하는 것, 후면 고립층(24)을 블랭킷-형성(blank forming)하는 것, 및 후면 고립층(24)의 TSV(20) 바로 위 부분을 제거하기 위해 가벼운 화학적 기계적 연마(CMP)를 수행하는 것을 포함한다. 따라서, TSV(20)는 후면 고립층(24) 내의 개구를 통해 노출된다. 대안적인 실시예들에서, TSV(20)가 노출되는 후면 고립층(24)의 개구는 에칭에 의해 형성된다. 웨이퍼(2)가 복수의 TSV들을 포함할 수 있는데, 일부 TSV들은 노출되지 않고 다른 일부들은 노출되는 경우에 비하여, 웨이퍼(2) 상의 모든 TSV들이 균일하게 노출된 경우에 뒤틀림(warpage)의 감소가 있을 것이다.
도 7a를 참조하면, UBM(26: under-bump metallurgy)으로도 알려진 얇은 시드층(26: seed layer)이 후면 고립층(24) 및 TSV(20) 상에 블랭킷-형성된다. UBM(26)은 스퍼터링 또는 다른 적용가능한 방법들에 의해 형성될 수 있다. UBM(26)에 적용가능한 물질들은 구리 또는 구리 합금들을 포함한다. 하지만, 은, 금, 알루미늄, 및 그것들의 조합과 같은, 다른 금속들이 또한 포함될 수 있다.
도 7b는 도 7a에 도시된 구조의 가장자리 부분을 도시한다. 단순성을 위해, UBM(26), 웨이퍼(2), 접착제(18), 및 캐리어 웨이퍼(16)가 단지 보여지며, 다른 구성들은 보이지 않는다. 캐리어 웨이퍼(16)에 있는 노치(17)는 웨이퍼(2)에 있는 노치(15) 아래에 형성되기 때문에, 캐리어 웨이퍼(16) 상에서 증착되어 노치(15)를 통해 노출되는 UBM(26)은 없을 것이다. 따라서, 포토 스테퍼들(photo steppers)과 같은, 이후의 공정 단계들을 수행하는 장비는 노치(15)를 쉽게 찾아낼 수 있으며, 그 결과 공정 신뢰도가 증대된다.
도 7a는 마스크(46)를 형성하는 것을 또한 도시한다. 일 실시예에서, 마스크(46)는 포토레지스트이다. 대안적으로, 마스크(46)는 드라이 필름(dry film)으로 형성되며, 드라이 필름은 ABF(Ajinimoto buildup film)와 같은 유기 물질을 포함할 수 있다. 이후 마스크(46)는 마스크(46)에 개구(50)를 형성하도록 패터닝되며, 이때 TSV(20)는 (그 위에 놓인 UBM 26과 함께) 개구(50)를 통해 노출된다. 캐리어 웨이퍼(16)가 노치되기(notched) 때문에, 마스크(46) 패터닝에서 보다 정확한 정렬이 수행될 수 있다.
도 8에서는, 도 7a에서 도시된 바와 같은 개구(50)가 금속 물질로 선택적으로 충진되며, 상기 금속 물질은 개구(50) 내에서 RDL(52: redistribution line)을 형성한다. 알루미늄, 은, 금 또는 그것들의 조합과 같은 다른 물질들이 사용될수도 있으나, 바람직한 본 실시예에서 상기 충진 물질은 구리 또는 구리 합금들을 포함한다. 형성 방법들로는 전기-화학 도금(ECP: electro-chemical plating), 무전해 도금(electroless plating), 또는 스퍼터링, 프린팅, 화학 기상 증착(CVD)과 같은 증착 방법들이 포함될 수 있다. 이후 마스크(46)는 제거된다. 그리하여, 마스크(46) 아래에 배치되는 UBM(26) 부분들이 노출된다.
도 9를 참조하면, 플래시 에칭(flash etching)에 의해 UBM(26)의 노출 부분들이 제거된다. 남아 있는 RDL(52)은 RDL 스트립(521)(재분배 트레이스(redistribution trace)로도 지칭됨)을 포함하고, RDL(521)과 결합하는 패드(522)를 선택적으로 포함하며, 이때 상기 RDL 스트립(521)은 TSV(20) 바로 위에서 그 TSV(20)와 연결된 부분을 포함한다. 도 9 및 그 이후의 도면들에서, UBM(26)은 전형적으로 RDL(52)과 유사한 물질로 형성되기 때문에 보이지 않으며, 따라서 RDL(52)과 병합된 것으로 보인다. 플래시 에칭의 결과로서, 얇은 RDL(52) 층이 또한 제거된다. 하지만, 제거된 RDL(52) 부분은 그것의 전체 두께와 비교할 때 무시할 수 있는 정도이다.
다음으로, 도 10에 도시된 바와 같이, 패시베이션 층(56: passivation layer)이 블랭킷-형성되며 개구(58)를 형성하도록 패터닝된다. 패시베이션 층(56)은 질화물들(nitrides), 산화물들(oxides), 폴리이미드(polyimide)와 같은 것들로 형성될 수 있다. 개구(58)의 패턴을 형성하기 위해 포토레지스트(60)가 적용되어 현상된다. 패시베이션 층(56)에 있는 개구(58)를 통해 패드(522)의 일부가 노출된다. 개구(58)는 패드(522)의 중앙부를 차지할 수 있다. RDL 스트립 부분(521)은 패시베이션 층(56)에 의해 연속적으로 덮여질 수 있다.
다음으로, 도 11에 도시된 바와 같이, 포토레지스트(60)가 제거되며, 64 및 66을 포함하는 본딩 패드가 형성된다. 일 실시예에서, 포토레지스트(63)가 형성된다. 포토레지스트(63)는 포토레지스트(60)보다 더 두꺼운 것이 바람직하다. 일 실시예에서, 포토레지스트(63)의 두께는 약 20 ㎛ 이상, 또는 약 60 ㎛ 이상이다. 포토레지스트(63)는 개구(65)를 형성하기 위해 패터닝되며, 상기 개구(65)를 통해 RDL 패드(522)가 노출된다. 다음으로, 전해 도금(electro plating)에 의해 개구(65)에서부터 시작되는 구리 기둥(64: copper pillar)이 형성된다. 구리 기둥(64)은 구리 및/또는 다른 금속들을 포함할 수 있으며, 상기 다른 금속들은 은, 금, 텅스텐, 알루미늄, 및 이들의 조합들과 같은 것이 해당된다. 구리 기둥(64) 상에는 니켈로 형성될 수 있는 베리어 층(66)이 형성될 수 있으며, 베리어 층(66) 상에는 솔더(68: solder)가 형성될 수 있다.
도 12를 참조하면, 포토레지스트(63)가 제거된다. 이후 웨이퍼(2)로부터 캐리어 웨이퍼(16)가 분리될 수 있다. 도 10에 도시된 바와 같은 구조는 칩/웨이퍼(80)와 같은 다른 칩 또는 웨이퍼에 본딩될 수 있다. 예시적인 일 실시예에서, 칩/웨이퍼(80)는 구리 포스트(86: copper post) 및 그 전방면 상의 베리어 층(84)을 가지며, 이때 웨이퍼들(2, 80)을 결합하기 위해 솔더(68)가 남땜될 수 있다. 웨이퍼(2)와 칩/웨이퍼(80) 사이에 언더필(90: underfill)이 충진될 수 있다. 대안적인 실시예들에서, 웨이퍼(2)는 다른 칩/웨이퍼에 본딩되기 이전에 칩들로 절단될 수 있다. 대안적인 실시예들에서, 캐리어 웨이퍼(16)의 분리는 웨이퍼(92)가 칩/웨이퍼(80)에 본딩된 이후 수행될 수 있다.
앞서 논의된 실시예들에서는, 해당 실시예의 개념을 설명하기 위해 TSV들의 후면 연결 구조가 예로써 사용되었다. 해당 실시예의 개념은 웨이퍼-대-웨이퍼(wafer-to-wafer) 본딩 공정들과 같은, 캐리어 웨이퍼들을 포함하는 다른 모든 제조 공정들에서 또한 사용될 수 있음을 이해할 수 있다.
상기 실시예들은 여러 유리한 특징들을 갖는다. 캐리어 웨이퍼들에 노치들을 형성함으로써, 반도체 웨이퍼들의 노치들을 통해 노출되는 캐리어 웨이퍼들의 부분들에는 어떠한 UBM도 증착되지 않을 것이다. 따라서 보다 신뢰성 있는 정렬이 수행될 수 있다. 경사진 영역들(beveled areas)을 갖지 않는 캐리어의 코너(corner)들로 인해, UBM의 벗겨짐(peeling)이 감소된다. 또한, 캐리어 웨이퍼들의 감소된 저항률(resistivity)로 인해, 캐리어 웨이퍼들은 E-척에 보다 신뢰성 있게 고정될 수 있다.
본 발명 및 그것의 이점들이 상세하게 기술되었으나, 첨부된 청구항들에 의해 정의된 본 발명의 사상 및 범위를 벗어남 없이 여러 가지 수정들, 치환들 및 변경들이 가능함을 이해해야 할 것이다. 더욱이, 본 출원의 범위는 명세서에서 기술되어진 공정, 기계, 제조, 물질의 조합, 수단, 방법들 및 단계들에 관한 특정 실시예들에 제한되도록 하려는 것은 아니다. 해당 분야의 당업자는 본 발명이 개시하는 것으로부터, 현존하는 또는 이후 개발될, 앞서 기술된 대응하는 실시예들과 동일한 기능을 실질적으로 수행하거나 실질적으로 동일한 결과를 달성하는 공정, 기계, 제조, 물질의 조합, 수단들, 방법들, 또는 단계들이 본 발명에 따라 유용될 수 있음을 이해할 것이다. 따라서, 첨부된 청구항들은 그 범위 내에서 그와 같은 공정들, 기계들, 제조, 물질의 조합, 수단들, 방법들, 또는 단계들을 포함하도록 의도되어진다. 추가적으로, 각각의 청구항은 개별 실시예를 구성하며, 여러 청구항들 및 실시예들의 조합은 본 발명의 범위 내에 있다.

Claims (12)

  1. 집적 회로 구조의 형성 방법에 있어서,
    반도체 웨이퍼의 일 가장자리로부터 상기 반도체 웨이퍼 내측으로 연장하는 제1 노치를 포함하는 반도체 웨이퍼를 제공하는 단계; 및
    상기 반도체 웨이퍼 상에 캐리어 웨이퍼를 장착하는 단계
    를 포함하고,
    상기 캐리어 웨이퍼는 상기 캐리어 웨이퍼 내에 제2 노치를 포함하고, 상기 캐리어 웨이퍼를 장착하는 단계는 상기 제1 노치의 적어도 일부분을 상기 제2 노치의 적어도 일부분과 중첩시키는 것을 포함하며, 상기 반도체 웨이퍼와 대향하는(facing) 상기 캐리어 웨이퍼의 일 측면은 상기 캐리어 웨이퍼의 일 가장자리와 90도의 각을 형성하는 것인 집적 회로 구조의 형성 방법.
  2. 제1항에 있어서,
    상기 반도체 웨이퍼는 상기 반도체 웨이퍼 내측으로 연장하는 관통-반도체 비아(TSV; through-semiconductor via)를 포함하는 것이고,
    상기 집적 회로 구조의 형성 방법은,
    상기 캐리어 웨이퍼를 장착하는 단계 이후, 상기 TSV를 노출시키기 위해 상기 반도체 웨이퍼의 후면을 그라인딩(grinding)하는 단계; 및
    상기 반도체 웨이퍼의 후면 상에 상기 TSV와 전기적으로 연결된 도전층을 증착하는 단계
    를 더 포함하는 것인 집적 회로 구조의 형성 방법.
  3. 제1항에 있어서,
    상기 제2 노치는 상기 캐리어 웨이퍼의 일 가장자리로부터 상기 캐리어 웨이퍼 내측으로 연장하는 것인 집적 회로 구조의 형성 방법.
  4. 제1항에 있어서,
    상기 캐리어 웨이퍼를 장착하는 단계는 상기 제2 노치의 가장자리들을 상기 제1 노치의 가장자리들과 정렬시키는 것을 포함하는 것인 집적 회로 구조의 형성 방법.
  5. 제1항에 있어서,
    상기 제2 노치 전체보다 작은 상기 제2 노치의 일부분이 상기 제1 노치 전체와 중첩되는 것인 집적 회로 구조의 형성 방법.
  6. 제1항에 있어서,
    상기 제1 노치 전체보다 작은 상기 제1 노치의 일부분이 상기 제2 노치 전체와 중첩되는 것인 집적 회로 구조의 형성 방법.
  7. 집적 회로 구조의 형성 방법에 있어서,
    반도체 웨이퍼를 제공하는 단계; 및
    상기 반도체 웨이퍼 상에 캐리어 웨이퍼를 장착하는 단계
    를 포함하고,
    상기 반도체 웨이퍼와 대향하는 상기 캐리어 웨이퍼의 일 측면은 상기 캐리어 웨이퍼의 일 가장자리와 90도의 각을 형성하는 것인 집적 회로 구조의 형성 방법.
  8. 제7항에 있어서,
    상기 반도체 웨이퍼는 반도체 기판, 및 상기 반도체 기판 내측으로 연장하는 관통-반도체 비아(TSV)를 포함하는 것이고,
    상기 집적 회로 구조의 형성 방법은,
    상기 반도체 기판의 일 측면 상에 상기 TSV와 전기적으로 연결된 UBM(under-bump metallurgy)을 형성하는 단계; 및
    상기 UBM을 형성하는 단계 이후, 상기 반도체 웨이퍼로부터 상기 캐리어 웨이퍼를 분리하는 단계
    를 더 포함하는 것인 집적 회로 구조의 형성 방법.
  9. 제7항에 있어서,
    상기 반도체 웨이퍼는 상기 반도체 웨이퍼의 일 가장자리로부터 상기 반도체 웨이퍼 내측으로 연장하는 제1 노치를 포함하고, 상기 캐리어 웨이퍼는 제2 노치를 포함하는 것이며, 상기 캐리어 웨이퍼를 장착하는 단계는 상기 제1 노치의 적어도 일부분과 중첩되도록 상기 제2 노치를 정렬시키는 것을 포함하는 것인 집적 회로 구조의 형성 방법.
  10. 집적 회로 구조의 형성 방법에 있어서,
    반도체 웨이퍼를 제공하는 단계; 및
    상기 반도체 웨이퍼 상에 캐리어 웨이퍼를 장착하는 단계
    를 포함하고,
    상기 캐리어 웨이퍼는 1x108 Ohm-cm 보다 낮은 저항률(resistivity)을 가지며, 상기 반도체 웨이퍼와 대향하는 상기 캐리어 웨이퍼의 일 측면은 상기 캐리어 웨이퍼의 일 가장자리와 90도의 각을 형성하는 것인 집적 회로 구조의 형성 방법.
  11. 삭제
  12. 제10항에 있어서,
    상기 반도체 웨이퍼는 상기 반도체 웨이퍼의 일 가장자리로부터 상기 반도체 웨이퍼 내측으로 연장하는 제1 노치를 포함하고, 상기 캐리어 웨이퍼는 제2 노치를 포함하는 것이며, 상기 캐리어 웨이퍼를 장착하는 단계는 상기 제1 노치의 적어도 일부분과 중첩되도록 상기 제2 노치를 정렬시키는 것을 포함하는 것인 집적 회로 구조의 형성 방법.
KR1020100058111A 2009-06-26 2010-06-18 캐리어 웨이퍼 수정을 통한 ｔｓｖ 후면 상호연결부 형성의 개선 KR101171526B1 (ko)

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CN101937853B (zh) 2013-07-17
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