TWI653695B - 封裝體及其形成方法 - Google Patents

封裝體及其形成方法 Download PDF

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Publication number
TWI653695B
TWI653695B TW106135279A TW106135279A TWI653695B TW I653695 B TWI653695 B TW I653695B TW 106135279 A TW106135279 A TW 106135279A TW 106135279 A TW106135279 A TW 106135279A TW I653695 B TWI653695 B TW I653695B
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Taiwan
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layer
forming
dielectric layer
dielectric
dielectric layers
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TW106135279A
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TW201838047A (zh
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陳明發
余振華
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台灣積體電路製造股份有限公司
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Abstract

一種方法包括：形成多個介電層；在所述多個介電層中形成多個重配置線；蝕刻所述多個介電層，以形成開口；填充所述開口以形成介電層穿孔，所述介電層穿孔穿透所述多個介電層；在所述介電層穿孔及所述多個介電層之上形成絕緣層；在所述介電層中形成多個接合墊；以及藉由混合接合將裝置接合至所述絕緣層及所述多個接合墊的一部分。

Description

封裝體及其形成方法
本發明的實施例是有關於一種封裝及形成所述封裝的方法。
[優先權聲明及交叉參考]
本申請案主張以下臨時提出申請的美國專利申請案的權利：於2017年4月7日提出申請且名稱為「具有無矽基底的中介層的封裝及形成所述封裝的方法」的申請案序列號62/483,256，所述申請案併入本案供參考。
積體電路的封裝正變得日益複雜，其中在相同封裝中封裝更多裝置晶粒以達成更多功能。舉例而言，封裝可包括多個裝置晶粒，例如接合至同一中介層的多個處理器及記憶體立方體(memory cube)。可基於半導體基底形成所述中介層，其中在所述半導體基底中形成多個矽穿孔以使形成於中介層的相對兩側上的特徵互連。裝置晶粒包封於模製化合物(molding compound)中。 包括中介層的封裝及裝置晶粒進一步接合至封裝基底。此外，表面安裝裝置(surface mount device)亦可接合至基底。散熱器可貼合至裝置晶粒的頂表面，以便消散在裝置晶粒中產生的熱能。所述散熱器可具有固定至所述封裝基底上的邊緣部分。
本發明實施例的一種形成封裝的方法包括：形成多個介電層；在所述多個介電層中形成多個重配置線；蝕刻所述多個介電層，以形成開口；填充所述開口以形成介電層穿孔，所述介電層穿孔穿透所述多個介電層的一部分；在所述介電層穿孔及所述多個介電層之上形成絕緣層；在所述絕緣層中形成多個接合墊；以及藉由混合接合將第一裝置結合至所述絕緣層及所述多個接合墊的第一部分。
本發明實施例的一種形成封裝的方法包括：形成多個介電層；在所述多個介電層中形成多個重配置線；形成穿透所述多個介電層的一部分的第一介電層穿孔及第二介電層穿孔；在所述多個介電層之上形成絕緣層；在所述絕緣層中形成多個接合墊，所述多個接合墊電性耦合至所述第一介電層穿孔及所述第二介電層穿孔以及所述多個重配置線；以及藉由混合接合將第一裝置及第二裝置接合至所述介電層及所述多個接合墊的一些部分，其中所述第一裝置與所述第二裝置藉由所述多個重配置線中的至少一者來電性互連。
本發明實施例的一種封裝包括多個介電層、多個重配置線、介電層穿孔、多個接合墊、第一絕緣層以及第一裝置。多個重配置線位於所述多個介電層中。介電層穿孔穿透所述多個介電層的一部分。多個接合墊位於所述介電層穿孔及所述多個重配置線之上且連接至所述介電層穿孔及所述多個重配置線。所述多個接合墊位於所述第一絕緣層中。第一裝置接合至所述第一絕緣層及所述多個接合墊的第一部分，其中所述第一裝置包括表面金屬特徵以及表面介電層。表面金屬特徵接合至所述多個接合墊。表面介電層接合至所述第一絕緣層。
20‧‧‧載體
22‧‧‧釋放層
24、28、34、46、48、50A、50B、50C、54A、54B、54C、58、64、76A、76B、90‧‧‧介電層
26、32、36、40、44‧‧‧重配置線
30‧‧‧開口
38、42‧‧‧鈍化層
45‧‧‧金屬墊
52A、52B、52C‧‧‧蝕刻終止層
56、56A、56B、56C‧‧‧微間距重配置線
60‧‧‧介電層穿孔(TDV)開口
62‧‧‧介電層穿孔
66、74A、74B、86、92‧‧‧接合墊
68A、68B‧‧‧裝置或裝置晶粒
70A、70B、94‧‧‧基底
72A、72B‧‧‧互連結構
78‧‧‧間隙
80‧‧‧間隙填充材料
82‧‧‧介電層或絕緣層
84‧‧‧溝渠
88‧‧‧晶圓
100‧‧‧中介層
102‧‧‧複合晶圓
104、112、140‧‧‧封裝
110‧‧‧電性連接件
114‧‧‧記憶體管
116、146‧‧‧介電層及重配置線
118、130‧‧‧封裝材料
132‧‧‧層疊式封裝(PoP)結構
134‧‧‧穿孔
138‧‧‧整合扇出型(InFO)封裝
300‧‧‧製程流程
302、304、306、308、310、312、314、316、318、320、322、324‧‧‧步驟
D1‧‧‧深度
T1‧‧‧厚度
結合附圖閱讀以下詳細說明，會最佳地理解本發明的各個態樣。應注意，根據本行業中的標準慣例，各種特徵並非按比例繪製。事實上，為論述清晰起見，可任意增大或減小各種特徵的尺寸。
圖1至圖20說明根據一些實施例的無矽基底(無矽)封裝的形成過程中的各中間階段的剖視圖。
圖21及圖22說明根據一些實施例的無矽封裝的形成過程中的各中間階段的剖視圖。
圖23及圖24說明根據一些實施例的包括無矽封裝的一些封裝的剖視圖。
圖25說明根據一些實施例的形成封裝的製程流程。
以下揭露內容提供用於實作本發明的不同特徵的諸多不同的實施例或實例。以下闡述組件及排列的具體實例以簡化本揭露內容。當然，該些僅為實例且不旨在進行限制。舉例而言，以下說明中將第一特徵形成於第二特徵「之上」或第二特徵「上」可包括其中第一特徵及第二特徵被形成為直接接觸的實施例，且亦可包括其中第一特徵與第二特徵之間可形成有附加特徵、進而使得所述第一特徵與所述第二特徵可能不直接接觸的實施例。另外，本發明可能在各種實例中重複使用參考編號及/或字母。此種重複使用是出於簡潔及清晰的目的，但自身並不表示所論述的各種實施例及/或配置之間的關係。
另外，為了易於描述圖中所示的一個元件或特徵與另一元件或特徵的關係，本文中可使用例如「在...下」、「在...下方」、「下部」、「上覆」、及「上部」等空間相對用語。除了圖中所繪示的取向之外，所述空間相對用語亦旨在涵蓋裝置在使用或操作時的不同取向。設備可被另外取向(旋轉90度或在其他取向)，而本文所用的空間相對描述語可同樣相應地作出解釋。
根據各種示例性實施例提供一種基於無矽基底(無矽)的中介層形成的封裝及形成所述封裝的方法。根據一些實施例說明形成所述封裝的中間階段。對一些實施例的一些變型進行詳述。於通篇的各個視圖及說明性實施例中，相同的參考編號用於指示相同或相似的元件。
圖1至圖20說明根據本發明一些實施例的封裝的形成過程中的各中間階段的剖視圖。圖1至圖20中所示的步驟亦以圖表方式反映於圖25所示的製程流程300中。
圖1說明載體20及形成於載體20上的釋放層22。載體20可為玻璃載體、矽晶圓或有機載體等。載體20可具有俯視為圓形的外形，且可具有常見矽晶圓的大小。舉例而言，載體20可具有8英吋的直徑或12英吋的直徑等。釋放層22可由聚合物系材料(例如，光熱轉換(Light To Heat Conversion，LTHC)材料)形成，其可與載體20一起被移除自將在後續步驟中形成的上覆結構。根據本發明的一些實施例，釋放層22是由環氧樹脂系(epoxy-based)熱釋放材料形成。可將釋放層22塗佈至載體20上。釋放層22的頂表面被整平且具有高共面程度(degree of co-planarity)。
在釋放層22上形成介電層24。根據本發明的一些實施例，介電層24是由聚合物形成，所述聚合物亦可為可利用微影製程輕易地進行圖案化的感光性材料，例如聚苯並噁唑(polybenzoxazole，PBO)、聚醯亞胺(polymide)、苯並環丁烯(benzocyclobutene，BCB)等。
在介電層24之上形成重配置線(RDL)26。形成重配置線26可包括：在介電層24之上形成晶種層(圖中未示出)，在所述晶種層之上形成例如光阻等經圖案化的罩幕(圖中未示出)，且然後在被暴露出的晶種層上執行金屬電鍍。然後移除經圖案化的 罩幕及晶種層中被經圖案化的罩幕覆蓋的部分，從而留下如圖1所示的重配置線26。根據本發明的一些實施例中，晶種層包括鈦層及位於所述鈦層之上的銅層。可使用例如物理氣相沉積(physical vapor deposition，PVD)等來形成所述晶種層。可使用例如無電電鍍(electro-less)來執行所述電鍍。
進一步參照圖1，在重配置線26上形成介電層28。介電層28的底表面接觸重配置線26的頂表面及介電層24的頂表面。根據本發明的一些實施例，介電層28是由聚合物形成，所述聚合物可為例如聚苯並噁唑(PBO)、聚醯亞胺、苯並環丁烯(BCB)等感光性材料。然後對介電層28進行圖案化，以在其中形成開口30。因此，重配置線26的一些部分經由介電層28中的開口30被暴露出。
接下來，參照圖2，形成重配置線32以連接至重配置線26。重配置線32包括位於介電層28之上的金屬跡線(金屬線)。重配置線32亦包括延伸至介電層28中的開口中的通孔(through via)。重配置線32亦是在電鍍製程中形成，其中重配置線32中的每一者包括晶種層(圖中未示出)及位於晶種層之上的電鍍金屬性材料。晶種層及電鍍材料可由相同材料或不同材料形成。重配置線32可包括金屬或金屬合金，所述金屬或金屬合金包括鋁、銅、鎢、及其合金。用於形成介電層28、介電層34、重配置線32及重配置線36的步驟作為步驟302表示於如圖25所示的製程流程300中。
參照圖3，在重配置線32及介電層28之上形成介電層34。介電層34可使用聚合物形成，所述聚合物可選自與介電層28的候選材料相同的候選材料中。舉例而言，可由聚苯並噁唑、聚醯亞胺、苯並環丁烯等來形成介電層34。作為另一選擇，介電層34可包括例如氧化矽、氮化矽、碳化矽、氮氧化矽等無機介電材料。
圖3進一步說明形成電性連接至重配置線32的重配置線36。重配置線36的形成可採用與形成重配置線32類似的方法及材料。應理解，儘管在所說明的示例性實施例中論述了兩個介電層28及介電層34及在其中形成的相應重配置線32及重配置線36，但可根據佈線要求及使用聚合物來緩衝應力的要求而採用更少或更多介電層。舉例而言，可存在單個聚合物層或三個、四個或更多個聚合物層。
圖4說明形成鈍化層38及鈍化層42以及重配置線40及重配置線44。對應步驟作為步驟304說明於如圖25中所示的製程流程300中。根據本發明的一些實施例，鈍化層38及鈍化層42是由例如以下無機材料形成的：氧化矽、氮化矽、碳化矽、氮氧化矽、矽氧碳氮化物、未經摻雜的矽酸鹽玻璃(Un-doped Silicate Glass，USG)或其多個層。鈍化層38及鈍化層42中的每一者可為單層或複合層，且可由無孔性材料形成。根據本發明的一些實施例，鈍化層38及鈍化層42中的一者或鈍化層38及鈍化層42二者為複合層，所述複合層包括氧化矽層(圖中未單獨示出)及 位於所述氧化矽層之上的氮化矽層(圖中未單獨示出)。鈍化層38及鈍化層42具有阻擋濕氣及有害化學物質接近封裝中的導電特徵(例如，微間距重配置線(fine-pitch RDL))的功能，如將在隨後的段落中進行詳述。
重配置線40及重配置線44可由鋁、銅、鋁銅、鎳或其合金形成。根據一些實施例，如圖11所示，重配置線44的一些部分被形成為足夠大的金屬墊，以供後續形成的介電層穿孔(Through-Dielectric Via，TDV)形成於其上。該些金屬墊根據一些實施例被相應地稱為金屬墊或鋁墊。此外，鈍化層的數目可為任意整數，例如一個、兩個(如圖所示)、三個或更多個。
圖5說明形成一個或多個介電層。舉例而言，如圖所示，可形成介電層46以將頂部的重配置線44嵌置於其中。在介電層46之上形成介電層48，且介電層48可作為蝕刻終止層。根據本發明的一些實施例，亦可以單個介電層來替代介電層46及介電層48。可用於介電層46及介電層48的材料包括氧化矽、氮化矽、碳化矽、氮氧化矽等。
圖6、圖7及圖8說明根據本發明一些實施例形成介電層及微間距重配置線。對應步驟作為步驟306說明於如圖25中所示的製程流程300中。所述形成方法可採用用於以矽基底為基礎所形成裝置晶粒的互連結構的方法。舉例而言，互連結構的形成方法可包括單鑲嵌(single damascene)製程及/或雙鑲嵌(dual damascene)製程。因此，所得的重配置線亦或者被稱為金屬線及 通孔，且對應的介電層或者被稱為金屬間介電(Inter-Metal-Dielectric，IMD)層。
參照圖6，形成介電層50A、介電層54A以及蝕刻終止層52A。介電層50A及介電層54A可由氧化矽、氮氧化矽、氮化矽等或介電常數值低於約3.0的低介電常數介電材料形成。低介電常數介電材料可包括黑金剛石(Black Diamond)(應用材料公司(Applied Materials)的註冊商標)、含碳低介電常數介電材料、氫矽倍半氧烷(Hydrogen SilsesQuioxane，HSQ)、甲基矽倍半氧烷(MethylSilsesQuioxane，MSQ)等。蝕刻終止層52A是由相對於介電層50A及介電層54A具有高蝕刻選擇性的材料形成，且可由碳化矽、矽碳氮化物等形成。根據替代實施例，可不形成蝕刻終止層52A。
在蝕刻終止層52A及介電層54A中形成微間距重配置線56A用於進行佈線。應理解，所說明的單個微間距重配置線56A代表多個微間距重配置線。由於根據本發明一些實施例的微間距重配置線是利用鑲嵌製程形成的，因此其能以小於例如0.8微米的間距(自結構的頂部觀察)被形成為極細。此顯著提高微間距重配置線的密度及佈線能力。根據一些實施例，微間距重配置線56A是利用單鑲嵌製程形成，所述單鑲嵌製程包括：蝕刻介電層50A及蝕刻終止層52A以形成溝渠，使用導電材料填充所述溝渠，以及執行平面化(例如，化學機械研磨(Chemical Mechanical Polish，CMP)或機械磨削)以移除導電材料的位於介電層54A之上的部 分。
根據本發明的一些實施例，用於形成微間距重配置線56A的導電材料是均質材料。根據本發明的其他實施例，所述導電材料是包括障壁層及位於所述障壁層之上的含銅材料(其可為銅或銅合金)的複合材料，所述障壁層由鈦、氮化鈦、鉭、氮化鉭等形成。微間距重配置線56A亦可由雙鑲嵌製程形成，以使得可在一些微間距重配置線56A之下形成一些通孔，且所述通孔可用於將微間距重配置線56A連接至重配置線44。
圖7說明形成介電層50B、介電層54B以及蝕刻終止層52B。介電層50B及介電層54B的材料可選自與用於形成介電層50A及介電層54A的候選材料相同的候選材料，且蝕刻終止層52B的材料可選自與用於形成蝕刻終止層52A的候選材料相同的候選材料。
亦在介電層50B、蝕刻終止層52B及介電層54B中形成微間距重配置線56B。微間距重配置線56B包括形成於介電層54B中的金屬線以及形成於介電層50B及蝕刻終止層52B中的通孔。儘管圖7示出金屬線由於過度蝕刻而延伸至蝕刻終止層52B中，但重配置線56B中的金屬線可實際上在蝕刻終止層52B的頂表面上停止且不穿透蝕刻終止層52B。所述形成可包括雙鑲嵌製程，所述雙鑲嵌製程包括：在介電層54B中形成溝渠及在介電層50B及蝕刻終止層52B中形成通孔開口，填充導電材料，以及然後執行平面化，例如機械磨削或化學機械研磨(CMP)。類似地，微間 距重配置線56B可由均質材料形成，或可由包括障壁層及位於障壁層之上的含銅材料的複合材料形成。
圖8說明形成介電層50C、介電層54C、蝕刻終止層52C以及微間距重配置線56C。所述形成方法及材料可類似於位於下方的對應層，且因此本文中不再對其予以贅述。此外，可根據一些實施例省略蝕刻終止層52A、蝕刻終止層52B及蝕刻終止層52C，且可利用時間模式(time-mode)執行用於形成溝渠的對應蝕刻，以控制溝渠的深度。應理解，可形成更多的介電層及微間距重配置線層。此外，即使可跳過蝕刻終止層52A、蝕刻終止層52B及蝕刻終止層52C中的一些或全部，由於微間距重配置線所處的介電層是在不同的製程中形成，因此在用於形成微間距重配置線56A、微間距重配置線56B及微間距重配置線56C的介電層之間仍可存在可區分的介面，而無論這些介電層是由相同的介電材料還是不同的介電材料形成。在隨後的段落中，為辨識簡潔起見，介電層50A、蝕刻終止層52A、介電層54A、介電層50B、蝕刻終止層52B、介電層54B、介電層50C、蝕刻終止層52C及介電層54C被共同地且個別地稱為介電層58。微間距重配置線56A、微間距重配置線56B及微間距重配置線56C亦被共同地且個別地稱為微間距重配置線56。類似地，儘管圖8示出微間距重配置線56C中的金屬線由於過度蝕刻而延伸至蝕刻終止層52C中，但微間距重配置線56C中的金屬線可實際上在蝕刻終止層52C的頂表面上停止且不穿透蝕刻終止層52C。
參照圖9，蝕刻介電層48及介電層58以形成介電層穿孔(TDV)開口60。對應步驟作為步驟308說明於如圖25中所示製程流程300中。金屬墊44暴露於介電層穿孔開口60。在自圖9所示結構的頂部觀察時，介電層穿孔開口60可對準至環以包圍其中形成有微間距重配置線56的區域。介電層穿孔開口60的俯視形狀可為矩形、圓形、六邊形等。
接下來，以導電材料填充介電層穿孔開口60以形成介電層穿孔62，且所得結構示出於圖10中。對應步驟作為步驟310說明於如圖25中所示製程流程300中。根據本發明的一些實施例，介電層穿孔62是由均質導電材料形成，所述均質導電材料可為包括銅、鋁、鎢等的金屬或金屬合金。根據本發明的替代實施例，介電層穿孔62具有包括導電障壁層及位於所述障壁層之上的含金屬材料的複合結構，所述導電障壁層是由鈦、氮化鈦、鉭、氮化鉭等形成。根據本發明的一些實施例，形成介電隔離層以包圍介電層穿孔62中的每一者。根據替代實施例，不形成介電隔離層來包圍介電層穿孔62，且介電層穿孔62與介電層58實體接觸。形成介電層穿孔62亦包括：將導電材料沉積至介電層穿孔開口60中(圖9)，以及執行平面化以移除所沉積材料的位於介電層58之上的多餘部分。
圖11說明形成接合墊66及介電層64，且接合墊66位於介電層64中。在所作說明通篇中，介電層64或者被稱為絕緣層或介電絕緣區域。對應步驟作為步驟312說明於如圖25中所示製 程流程300中。接合墊66可由易於形成混合接合的金屬形成。根據本發明的一些實施例，接合墊66是由銅或銅合金形成。舉例而言，介電層64可由氧化矽形成。接合墊66的頂表面與介電層64的頂表面是共面的。所述平面性可例如藉由平面化步驟(例如，CMP或機械磨削步驟)達成。
在所作說明通篇中，位於釋放層22之上的組件被合併稱為中介層100。以介電層58為基礎所形成的中介層100不同於以矽基底為基礎所形成的傳統中介層。中介層100中不存在矽基底，且因此中介層100被稱為無矽基底中介層或無矽中介層。於介電層58中形成介電層穿孔62以替代傳統矽穿孔(through-silicon vias)。由於矽基底是半導電的，因此其可對形成於其中及其上的電路及連接的效能產生不利影響。舉例而言，存在由矽基底導致的訊號劣化，且在本發明的實施例中可避免此種劣化，乃因於介電層穿孔62是形成於介電層中。
接下來，如圖12所示，將裝置68A及68B結合至中介層100。對應步驟作為步驟314說明於如圖25中所示製程流程300中。裝置68A及裝置68B可為裝置晶粒，且因此在以下被稱為裝置晶粒，但其可為其他類型的裝置，例如封裝。根據本發明的一些實施例，裝置晶粒68A及裝置晶粒68B可包括邏輯晶粒，所述邏輯晶粒可為中央處理單元(Central Processing Unit，CPU)晶粒、微控制單元(Micro Control Unit，MCU)晶粒、輸入-輸出(input-output，IO)晶粒、基帶(BaseBand，BB)晶粒或應用處 理器(Application processor，AP)晶粒。裝置晶粒68A及裝置晶粒68B亦可包括記憶體晶粒。裝置晶粒68A及裝置晶粒68B分別包括可為矽基底的基底70A及基底70B。此外，裝置晶粒68A及裝置晶粒68B分別包括互連結構72A及互連結構72B，用於連接至裝置晶粒68A及裝置晶粒68B中的主動裝置及被動裝置。互連結構72A及互連結構72B包括金屬線及通孔(圖中未示出)。
裝置晶粒68A包括位於裝置晶粒68A的所示底表面處的接合墊74A及介電層76A。接合墊74A的所示底表面與介電層76A的所示底表面共面。裝置晶粒68B包括位於所示底表面處的接合墊74B及介電層76B。接合墊74B的所示底表面與介電層76B的所示底表面共面。
所述接合可藉由混合接合達成。舉例而言，接合墊74A及接合墊74B藉由金屬至金屬直接接合(metal-to-metal direct bonding)而結合至接合墊66。根據本發明的一些實施例，所述金屬至金屬直接結合是銅至銅直接接合。此外，介電層76A及介電層76B例如利用所產生的矽-氧-矽鍵而接合至介電層64。混合接合可包括預接合及退火，以使得接合墊74A(及接合墊74B)中的金屬與位於下方的相應接合墊66中的金屬互相擴散。
微間距重配置線56電性互連於接合墊74A與接合墊74B，並用於裝置晶粒68A與裝置晶粒68B之間的訊號通訊。微間距重配置線56具有小的間距及小的寬度。因此，微間距重配置線56的密度高，且因此可形成足夠的通訊通道以用於裝置晶粒 68A與裝置晶粒68B之間的直接通訊。另一方面，介電層穿孔62提供從裝置晶粒68A及裝置晶粒68B到將接合至中介層100的組件(其可為封裝基底、印刷電路板(Printed Circuit Board，PCB)等)的直接連接。此外，接合墊74A/接合墊74B與接合墊66之間的接合是藉由接合墊而非藉由通常較接合墊大得多的焊接接頭(solder joint)。因此，接合的水平尺寸小，且可實施更多接合以提供足夠的通訊通道。
參照圖13，執行背面磨削以將裝置晶粒68A及裝置晶粒68B薄化至例如介於約15微米與約30微米之間的厚度。對應步驟作為步驟316說明於如圖25中所示製程流程300中。藉由所述薄化，相鄰裝置晶粒68A與裝置晶粒68B之間的間隙78的深寬比減小，以便執行間隙填充。否則，由於存在高的深寬比而難以進行間隙填充。
接下來，如圖14所示，由間隙填充材料80來填充間隙78。對應步驟作為步驟318說明於如圖25中所示製程流程300中。根據本發明的一些實施例，間隙填充材料80包含氧化物，例如為可由正矽酸四乙酯(tetraethyl orthosilicate，TEOS)形成的氧化矽。所述形成方法可包括化學氣相沉積(Chemical Vapor Deposition，CVD)、高密度電漿化學氣相沉積(High-Density Plasma Chemical Vapor Deposition，HDPCVD)等。根據替代實施例，間隙填充材料80是由例如聚苯並噁唑、聚醯亞胺等聚合物形成。然後執行平面化以移除間隙填充材料80的多餘部分，以暴露出裝置晶粒68A 及裝置晶粒68B的基底70A及基底70B。在圖15A中示出所得結構。根據其中間隙填充材料80是由氧化物(例如，氧化矽)形成的本發明的替代實施例，可在基底70A及基底70B之上留下間隙填充材料80的薄層，且所得結構示出於圖15B中。間隙填充材料80中位於裝置晶粒68A及裝置晶粒68B之上的剩餘部分在下文中或者被稱為介電層82或絕緣層82。
根據其中基底70A及70B被暴露出的圖15所示的實施例，例如利用CVD、電漿增強型CVD(Plasma Enhanced CVD，PECVD)、原子層沉積(Atomic Layer Deposition，ALD)等沉積介電層82(如圖16所示)來作為毯覆層(blanket layer)。對應步驟作為步驟320說明於如圖25中所示製程流程300中。根據其中間隙填充材料80的薄層(其亦被稱為82)留在基底70A及基底70B之上的替代實施例(如圖15B所示)，可跳過對介電層的沉積。接下來，藉由蝕刻介電層82及基底70A及基底70B來形成溝渠84，以使得溝渠84亦延伸至介電層82及基底70A及基底70B中。在圖16中示出所得結構。根據基底70A及基底70B的厚度T1，溝渠84的位於基底70A及基底70B內的部分的深度D1可大於約1微米，且可介於約2微米與約5微米之間。舉例而言，深度D1可介於厚度T1的約20%與約60%之間。應理解，在所作說明通篇中所述的值是實例，且可改變成不同的值。
溝渠84可分佈於各種圖案中。舉例而言，溝渠84可被形成為分離的開口，所述分離的開口可被分佈成陣列、蜂巢圖案 或其他重複圖案。溝渠84的俯視形狀可為矩形、方形、圓形、六邊形等。根據替代實施例，當在圖16所示結構的俯視圖中觀察時，溝渠84可為在單一方向上延伸的平行溝渠。溝渠84亦可互連以形成格柵。所述格柵可包括多個彼此平行且均勻地或不均勻地間隔開的第一溝渠、以及多個彼此平行且均勻地或不均勻地間隔開的第二溝渠。所述多個第一溝渠與所述多個第二溝渠彼此相交以形成格柵，且所述多個第一溝渠與所述多個第二溝渠在俯視圖中可彼此垂直或可不彼此垂直。
如圖17所示，然後填充溝渠84以形成接合墊86。對應步驟亦作為步驟320說明於如圖25中所示製程流程300中。應理解，儘管將特徵86稱為接合墊，但特徵86可為分離的墊或互連的金屬線。根據一些實施例，接合墊86是由銅或適合於混合接合的其他金屬(由於在擴散方面的相對容易性)形成。在填充之後，執行平面化以使接合墊86的頂表面與介電層82的頂表面平面化。所述平面化可包括CMP或機械磨削製程。
接下來，如圖18A所示，將晶圓88接合至裝置晶粒68A及裝置晶粒68B。對應步驟作為步驟322說明於如圖25中所示製程流程300中。晶圓88包括可為矽基底或金屬基底的基底94。基底94亦為在放置於同一載體20之上的多個裝置晶粒68A及多個裝置晶粒68B上延伸的晶圓。當基底94由金屬形成時，基底94可由銅、鋁、不銹鋼等形成。當基底94是由矽形成時，晶圓88中沒有主動裝置及被動裝置形成於其中。晶圓88具有兩個功能。 首先，由於裝置晶粒68A及68B已被薄化以便使得能夠進行更佳的間隙填充，因此晶圓88向位於下方的結構提供機械支撐。此外，(基底94的)矽或金屬具有高的導熱性，因此晶圓88可作為散熱器。
在基底94的表面上形成介電層90。舉例而言，介電層90可由氧化矽形成。此外，在介電層90中形成接合墊92，且接合墊92的所示底表面與介電層90的所示底表面共面。接合墊92的圖案及水平大小可與相應接合墊86的圖案及水平大小相同或類似。
將晶圓88接合至裝置晶粒68A及裝置晶粒68B上是藉由混合接合。舉例而言，介電層82與介電層90彼此結合，且可形成矽-氧-矽鍵。接合墊92藉由金屬至金屬直接接合而接合至相應的接合墊86。
有利地，接合墊86藉由接觸(且甚至插入至)基底70A及70B而提供良好的散熱路徑，以使得在裝置晶粒68A及裝置晶粒68B中產生的熱量可輕易地散入基底94中。
圖18B說明根據本發明一些實施例形成的封裝。除接合墊86穿透介電層82且不延伸至基底70A及70B中以外，該些實施例與圖18A所示的實施例類似。根據一些實施例，接合墊86與基底70A及70B接觸。根據替代實施例，接合墊86及接合墊92中的一者或兩者自發生結合的介面部分地延伸至相應的介電層82及90中而不穿透相應的介電層82及介電層90。根據本發明的一 些實施例，接合墊86及接合墊92以及基底94可電性地接地，以為基底70A及70B提供電性接地。
圖18C說明根據本發明一些實施例形成的封裝。除未形成接合墊86、接合墊92以及介電層90(如圖18A及圖18B所示)以外，該些實施例類似於圖18A及圖18B所示的實施例。基底94(其亦為晶圓88且為矽晶圓)藉由熔融接合(fusion bonding)而接合至介電層82。
根據本發明的替代實施例，晶圓88是金屬晶圓。因此，圖18C中的層82可為熱介面材料(Thermal Interface Material，TIM)，所述熱介面材料為具有高導熱性的黏著劑層。
接下來，例如藉由向釋放層22照射例如紫外線或雷射等光以分解釋放層22而自載體20剝離形成於載體20上的結構，並自上覆結構移除載體20及釋放層22，所述上覆結構被稱為複合晶圓102(圖19)。
圖20說明形成電性連接件110，所述電性連接件110可穿透介電層24並連接至重配置線26。電性連接件110可為金屬凸塊、焊料凸塊、金屬柱、導線接合(wire bond)或其他可應用的連接件。對複合晶圓102執行晶粒切割步驟以將複合晶圓102分隔成多個封裝104。相應步驟作為步驟324說明於如圖25中所示製程流程300中。封裝104彼此相同，且封裝104中的每一者包括裝置晶粒68A及裝置晶粒68B兩者。
圖21及圖22說明根據本發明一些實施例的封裝的形成 過程中的各中間階段的剖視圖。除非另外具體指明，否則在該些實施例中的組件的材料及形成方法本質上與在圖1至圖20所示實施例中由相同參考編號指代的相同組件相同。因此可在對圖1至圖20中所示實施例的論述中找到關於圖21及圖22中所示組件的形成製程及材料的細節。圖21說明複合晶圓102的剖視圖，除了是在介電層24上形成金屬墊45，而不是在載體20上形成如圖20所示的介電層28、介電層34、鈍化層38及鈍化層42以及重配置線32、重配置線36、重配置線40及重配置線44的特徵以外，圖21的複合晶圓102與圖20所示的複合晶圓102本質上相同。確切而言，如說明圖21所示步驟之後的結構的圖22所示，在分離載體20(圖21)之後，形成介電層28、介電層34、鈍化層38及鈍化層42、以及重配置線32、重配置線36、重配置線40及重配置線44。根據該些實施例用於形成介電層28、介電層34、鈍化層38及鈍化層42的順序相對於圖1至圖11所示的順序相反。應注意，由於不同的形成順序，重配置線32、重配置線36、重配置線40及重配置線44的方向相較於圖20中所示者相反(沿垂直方向)。然後藉由對複合晶圓102進行晶粒切割而形成封裝104。
圖23說明其中嵌置封裝104(圖20及圖22)的封裝112。所述封裝包括記憶體立方體114，所述記憶體立方體114包括多個堆疊的記憶體晶粒(圖中未分別示出)。封裝104及記憶體立方體114包封於可為模製化合物的封裝材料118中。介電層及重配置線(統稱為116)位於封裝104及記憶體立方體114之下且連接至封 裝104及記憶體立方體114。根據一些實施例，介電層及重配置線116使用與圖1至圖11所示者類似的材料形成且具有與圖1至圖11所示者類似的結構。
圖24說明層疊式封裝(Package-on-Package，PoP)結構132，其具有與頂部封裝140相接合的整合扇出型(Integrated Fan-Out，InFO)封裝138。積體扇出型封裝138亦包括嵌置在其中的封裝104。封裝104及穿孔134包封在可為模製化合物的封裝材料130中。封裝104接合至統稱為146的介電層及重配置線。介電層及重配置線146亦可使用與圖1至圖11所示者類似的材料形成且具有與圖1至圖11所示者類似的結構。
本發明的實施例具有某些有利特徵。藉由使用通常用於矽晶圓的製程(例如，鑲嵌製程)來形成用於中介層的微間距重配置線，所述微間距重配置線可被形成為足夠細，以提供二或更多個裝置晶粒皆藉由微間距重配置線進行通訊的能力。在中介層中未使用矽基底，因此避免由矽基底產生的電性效能的劣化。且於封裝中建立的一些散熱機制用以更佳地散熱。
根據本發明的一些實施例，一種形成封裝體的方法包括：形成多個介電層；在所述多個介電層中形成多個重配置線；蝕刻所述多個介電層，以形成開口；填充所述開口以形成介電層穿孔，所述介電層穿孔穿透所述多個介電層；在所述介電層穿孔及所述多個介電層之上形成絕緣層；在所述絕緣層中形成多個接合墊；以及藉由混合接合將裝置接合至所述絕緣層及所述多個接 合墊的一部分。在一或多個以上或以下實施例中，藉由混合接合將第二裝置結合至所述絕緣層及所述多個接合墊的第二部分，其中所述多個重配置線將所述第一裝置連接至所述第二裝置。在一或多個以上或以下實施例中，所述形成所述多個重配置線包括鑲嵌製程。在一或多個以上或以下實施例中，所述介電層穿孔不延伸至任何半導體基底內。在一或多個以上或以下實施例中，所述的方法更包括：形成氧化物層，所述氧化物層上覆於所述第一裝置的半導體基底上且接觸所述第一裝置的所述半導體基底；形成延伸至所述氧化物層內的接合墊；以及藉由混合接合將塊狀晶圓接合至所述氧化物層及所述接合墊。在一或多個以上或以下實施例中，所述接合墊延伸至所述第一裝置的所述半導體基底內。在一或多個以上或以下實施例中，所述接合墊接觸所述第一裝置的所述半導體基底但不延伸至所述第一裝置的所述半導體基底內。
根據本發明的一些實施例，一種形成封裝體的方法包括：形成多個第一介電層；在所述多個第一介電層中形成多個重配置線；形成穿透所述多個第一介電層的第一介電層穿孔及第二介電層穿孔；在所述多個第一介電層之上形成絕緣層；在所述絕緣層中形成多個接合墊，所述多個接合墊電性耦合至所述第一介電層穿孔及所述第二介電層穿孔以及所述多個重配置線；以及藉由混合接合將第一裝置及第二裝置接合至所述第一介電層及所述多個接合墊。所述第一裝置與所述第二裝置藉由所述多個重配置線來電性互連。在一或多個以上或以下實施例中，所述多個重配 置線是使用鑲嵌製程形成。在一或多個以上或以下實施例中，所述的方法更包括：在載體之上形成聚合物層；在所述聚合物層之上形成鈍化層，其中所述多個第一介電層是形成於所述鈍化層之上；在所述聚合物層及所述鈍化層中形成額外的重配置線；以及將所述載體自所述聚合物層分離。在一或多個以上或以下實施例中，所述多個第一介電層形成於載體之上，且所述方法更包括：將所述多個第一介電層自所述載體剝離；在所述剝離之後，在所述多個第一介電層之上形成鈍化層；以及在所述鈍化層之上形成聚合物層。在一或多個以上或以下實施例中，所述形成所述第一介電層穿孔及所述第二介電層穿孔包括：蝕刻所述多個第一介電層，以形成第一開口及第二開口；以及使用導電材料填充所述第一開口及所述第二開口。在一或多個以上或以下實施例中，所述的方法更包括：薄化所述第一裝置及所述第二裝置；以及將間隙填充材料填充至所述第一裝置與所述第二裝置之間的間隙中。在一或多個以上或以下實施例中，所述的方法更包括：在已薄化的所述第一裝置及所述第二裝置之上形成第二介電層；以及將塊狀晶圓接合至所述絕緣層。
根據本發明的一些實施例，一種封裝體包括多個介電層；多個重配置線，位於所述多個介電層中的每一者中；介電層穿孔，穿透所述多個介電層；多個第一接合墊，位於所述介電層穿孔及所述多個重配置線之上且連接至所述介電層穿孔及所述多個重配置線；以及絕緣層，所述多個第一接合墊位於所述絕緣層 中。裝置藉由混合接合而接合至所述絕緣層及所述多個第一接合墊的一部分，其中所述第一裝置包括接合至所述多個第一接合墊的表面金屬特徵，以及接合至所述第一絕緣層表面介電層。在一或多個以上或以下實施例中，更包括第二裝置，所述第二裝置藉由混合接合而接合至所述第一絕緣層及所述多個第一接合墊的第二部分，其中所述第一裝置與所述第二裝置經由所述多個重配置線電性耦合至彼此。在一或多個以上或以下實施例中，更包括第二接合墊、第二絕緣層以及塊狀基底。第二接合墊實體接觸所述第一裝置的半導體基底。所述第二接合墊具有至少一部分位於所述第二絕緣層中。塊狀基底接合至所述第二絕緣層及所述第二接合墊。在一或多個以上或以下實施例中，所述塊狀基底是由矽形成，且在所述塊狀基底上未形成有主動裝置及被動裝置。在一或多個以上或以下實施例中，所述第二接合墊形成格柵。
以上概述了若干實施例的特徵，以使熟習此項技術者可更佳地理解本發明的各個態樣。熟習此項技術者應知，其可容易地使用本發明作為設計或修改其他製程及結構的基礎來施行與本文中所介紹的實施例相同的目的及/或達成與本文中所介紹的實施例相同的優點。熟習此項技術者亦應認識到，該些等效構造並不背離本發明的精神及範圍，而且他們可在不背離本發明的精神及範圍的條件下對其作出各種改變、代替、及變更。

Claims (10)

  1. 一種形成封裝體的方法，包括：形成多個介電層；在所述多個介電層中形成多個重配置線；蝕刻所述多個介電層，以形成開口；填充所述開口以形成介電層穿孔，所述介電層穿孔穿透所述多個介電層的一部分；在所述介電層穿孔及所述多個介電層之上形成絕緣層；在所述絕緣層中形成多個接合墊；以及藉由混合接合將第一裝置結合至所述絕緣層及所述多個接合墊的第一部分。
  2. 如申請專利範圍第1項所述的方法，其中所述形成所述多個重配置線包括鑲嵌製程。
  3. 如申請專利範圍第1項所述的方法，其中所述介電層穿孔不延伸至任何半導體基底內。
  4. 如申請專利範圍第1項所述的方法，更包括：形成氧化物層，所述氧化物層上覆於所述第一裝置的半導體基底上且接觸所述第一裝置的所述半導體基底；形成延伸至所述氧化物層內的接合墊；以及藉由混合接合將塊狀晶圓接合至所述氧化物層及所述接合墊。
  5. 一種形成封裝體的方法，包括：形成多個介電層；在所述多個介電層中形成多個重配置線；形成穿透所述多個介電層的一部分的第一介電層穿孔及第二介電層穿孔；在所述多個介電層之上形成絕緣層；在所述絕緣層中形成多個接合墊，所述多個接合墊電性耦合至所述第一介電層穿孔及所述第二介電層穿孔以及所述多個重配置線；以及藉由混合接合將第一裝置及第二裝置接合至所述介電層及所述多個接合墊的一些部分，其中所述第一裝置與所述第二裝置藉由所述多個重配置線中的至少一者來電性互連。
  6. 如申請專利範圍第5項所述的方法，其中所述多個重配置線是使用鑲嵌製程形成。
  7. 如申請專利範圍第5項所述的方法，更包括：在載體之上形成聚合物層；在所述聚合物層之上形成鈍化層，其中所述多個介電層是形成於所述鈍化層之上；在所述聚合物層及所述鈍化層中形成額外的重配置線；以及將所述載體自所述聚合物層分離。
  8. 如申請專利範圍第5項所述的方法，其中所述多個介電層形成於載體之上，且所述方法更包括：將所述多個介電層自所述載體剝離；在所述剝離之後，在所述多個介電層之上形成鈍化層；以及在所述鈍化層之上形成聚合物層。
  9. 如申請專利範圍第5項所述的方法，更包括：薄化所述第一裝置及所述第二裝置；以及將間隙填充材料填充至所述第一裝置與所述第二裝置之間的間隙中。
  10. 一種封裝體，包括：多個介電層；多個重配置線，位於所述多個介電層中；介電層穿孔，穿透所述多個介電層的一部分；多個接合墊，位於所述介電層穿孔及所述多個重配置線之上且連接至所述介電層穿孔及所述多個重配置線；第一絕緣層，所述多個接合墊位於所述第一絕緣層中；以及第一裝置，接合至所述第一絕緣層及所述多個接合墊的第一部分，其中所述第一裝置包括：表面金屬特徵，接合至所述多個接合墊；以及表面介電層，接合至所述第一絕緣層。
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US11610858B2 (en) 2023-03-21
US10854568B2 (en) 2020-12-01
KR20180113897A (ko) 2018-10-17
US20180294241A1 (en) 2018-10-11
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US20210082857A1 (en) 2021-03-18
TW201838047A (zh) 2018-10-16

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