CN108695166A - 封装件及其形成方法 - Google Patents

封装件及其形成方法 Download PDF

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Publication number
CN108695166A
CN108695166A CN201711286530.7A CN201711286530A CN108695166A CN 108695166 A CN108695166 A CN 108695166A CN 201711286530 A CN201711286530 A CN 201711286530A CN 108695166 A CN108695166 A CN 108695166A
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China
Prior art keywords
dielectric
layer
dielectric layer
landing pad
hole
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Granted
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CN201711286530.7A
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CN108695166B (zh
Inventor
陈明发
余振华
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一种方法，包括：形成多个介电层；在多个介电层中形成多个再分布线；蚀刻多个介电层以形成开口；填充开口以形成穿透多个介电层的介电通孔；在介电通孔和多个介电层上方形成绝缘层；在介电层中形成多个接合焊盘；以及通过混合接合将器件接合至绝缘层和多个接合焊盘的一部分。本发明的实施例还涉及封装件及其形成方法。

Description

封装件及其形成方法
技术领域
本发明的实施例涉及封装件及其形成方法。
背景技术
集成电路的封装件变得越来越复杂，更多的器件管芯封装在同一封装件中以实现更多的功能。例如，封装件可以包括接合至同一中介层的多个器件管芯(诸如处理器和存储器数据集)。中介层可以基于半导体衬底形成，硅通孔形成在半导体衬底中以将形成在中介层的相对侧上的部件进行互连。模塑料将器件管芯封装在其中。包括中介层和器件管芯的封装件进一步接合至封装衬底。此外，表面贴装器件也可以接合至该衬底。散热器可以附接至器件管芯的顶面，以便消散器件管芯中产生的热量。散热器可以具有固定到封装衬底上的裙部(skirt portion)。
发明内容
本发明的实施例提供了一种形成封装件的方法，包括：形成多个介电层；在所述多个介电层中形成多个再分布线；蚀刻所述多个介电层以形成开口；填充所述开口以形成穿透所述多个介电层的一部分的介电通孔；在所述介电通孔和所述多个介电层上方形成绝缘层；在所述绝缘层中形成多个接合焊盘；以及通过混合接合将第一器件接合至所述绝缘层和所述多个接合焊盘的第一部分。
本发明的另一实施例提供了一种形成封装件的方法，包括：形成多个介电层；在所述多个介电层中形成多个再分布线；形成穿透所述多个介电层的一部分的第一介电通孔和第二介电通孔；在所述多个介电层上方形成绝缘层；在所述绝缘层中形成多个接合焊盘，并且所述多个接合焊盘电连接至所述第一介电通孔和所述第二介电通孔以及所述多个再分布线；以及通过混合接合将第一器件和第二器件接合至所述绝缘层和所述多个接合焊盘的一部分，其中，所述第一器件通过所述多个再分布线中的至少一个与所述第二器件电互连。
本发明的又一实施例提供了一种封装件，包括：多个介电层；多个再分布线，位于所述多个介电层中；介电通孔，穿透所述多个介电层的一部分；多个接合焊盘，位于所述介电通孔和所述多个再分布线上方，并且连接至所述介电通孔和所述多个再分布线；第一绝缘层，所述多个接合焊盘位于所述第一绝缘层中；以及第一器件，接合至所述第一绝缘层和所述多个接合焊盘的第一部分，其中，所述第一器件包括：表面金属部件，接合至所述多个接合焊盘；以及表面介电层，接合至所述第一绝缘层。
附图说明
当结合附图进行阅读时，根据下面详细的描述可以最好地理解本发明的各个方面。应该注意，根据工业中的标准实践，各种部件没有被按比例绘制。实际上，为了清楚的讨论，各种部件的尺寸可以被任意增加或减少。
图1至图20示出了根据一些实施例的形成无硅衬底(少硅)封装件的中间阶段的截面图。
图21至图22示出了根据一些实施例的形成少硅封装件的中间阶段的截面图。
图23至图24示出了根据一些实施例的包括少硅封装件的一些封装件的截面图。
图25示出了根据一些实施例的用于形成封装件的工艺流程图。
具体实施方式
以下公开内容提供了多种不同实施例或实例，以实现本发明的不同特征。以下将描述组件和布置的具体实例以简化本发明。当然，这些仅是实例并且不意欲限制本发明。例如，在以下描述中，在第二部件上方或上形成第一部件可以包括第一部件和第二部件直接接触的实施例，也可以包括形成在第一部件和第二部件之间的附加部件使得第一部件和第二部件不直接接触的实施例。而且，本发明在各个实例中可以重复参考数字和/或字母。该重复仅是为了简明和清楚，其自身并不表示所论述的各个实施例和/或配置之间的关系。
而且，为便于描述，在此可以使用诸如“在...下面”、“在...下方”、“下部”、“在...上面”、“上部”等的空间相对术语，以便于描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。空间相对术语旨在包括除了附图中所示的方位之外，在使用中或操作中的器件的不同方位。装置可以以其他方式定位(旋转90度或在其他方位)，并且在本文中使用的空间关系描述符可以同样地作相应地解释。
根据各个示例性实施例提供了基于无硅衬底(少硅)的中介层形成的封装件及其形成方法。根据一些实施例示出了形成封装件的中间阶段。讨论了一些实施例的一些变型。在各个视图和说明性实施例中，相同的参考标号用于指定相同的元件。
图1至图20示出了根据本发明的一些实施例的形成封装件的中间阶段的截面图。图1至图20示出的步骤也示意性地反映在图25示出的工艺流程300中。
图1示出了载体20和形成在载体20上的释放层22。载体20可以是玻璃载体、硅晶圆、有机载体等。载体20可以具有圆形的顶视图形状，并且可以具有普通硅晶圆的尺寸。例如，载体20可以具有8英寸直径、12英寸直径等。释放层22可由聚合物基材料(诸如，光热转换(LTHC)材料)形成，其可连同载体20从将在后续步骤中形成的上面结构被去除。根据本发明的一些实施例，释放层22由环氧树脂基热释放材料形成。释放层22可以涂覆到载体20上。释放层22的顶面是水平的并且具有高度的共面性。
介电层24形成在释放层22上。根据本发明的一些实施例，介电层24由聚合物形成，该聚合物也可以是使用光刻工艺可以易于被图案化的诸如聚苯并恶唑(PBO)、聚酰亚胺、苯并环丁烯(BCB)等的光敏材料。
再分布线(RDL)26形成在介电层24上方。RDL 26的形成可以包括在介电层24上方形成晶种层(未示出)，在晶种层上方形成诸如光刻胶的图案化掩模(未示出)，然后在暴露的晶种层上执行金属镀。然后去除图案化掩模和晶种层的由图案化掩模覆盖的部分，从而留下如图1中的RDL26。根据本发明的一些实施例，晶种层包括钛层和位于钛层上方的铜层。例如，可以使用物理气相沉积(PVD)形成晶种层。例如，可以使用化学镀来执行镀。
进一步参考图1，介电层28形成在RDL 26上。介电层28的底面与RDL 26的顶面以及介电层24的顶面接触。根据本发明的一些实施例，介电层28由聚合物形成，该聚合物可以是诸如PBO、聚酰亚胺、BCB等的光敏材料。然后图案化介电层28以在其中形成开口30。因此，通过介电层28中的开口30暴露出RDL 26的一些部分。
接下来，参考图2，形成RDL 32以连接至RDL 26。RDL 32包括介电层28上方的金属迹线(金属线)。RDL 32还包括延伸进入介电层28中的开口的通孔。RDL 32也在镀工艺中形成，其中每一个RDL 32均包括晶种层(未示出)和晶种层上方的镀金属材料。晶种层和镀材料可以由相同材料或不同材料形成。RDL 32可包括金属或包括铝、铜、钨和它们的合金的金属合金。形成介电层28和24以及RDL 32和26的步骤被示出为图25所示的工艺流程300的步骤302。
参考图3，介电层34形成在RDL 32和介电层28上方。介电层34可以使用聚合物来形成，聚合物可以选自与介电层28的材料相同的候选材料。例如，介电层34可以由PBO、聚酰亚胺、BCB等形成。可选地，介电层34可包括无机介电材料，诸如氧化硅、氮化硅、碳化硅、氮氧化硅等。
图3还示出了形成RDL 36，RDL 36电连接至RDL 32。RDL 36的形成可采用与形成RDL 32的方法和材料类似的方法和材料。应当理解，尽管在说明性示例性实施例中讨论了两个聚合物层28和34以及在其中形成的相应的RDL 32和36，但是取决于布线要求和用聚合物缓冲应力的要求，可以采用更少或更多的介电层。例如，可以有单个聚合物层或三个、四个或更多个聚合物层。
图4示出了钝化层38和42以及RDL 40和44的形成。相应的步骤被示出为图25所示的工艺流程300中的步骤304。根据本发明的一些实施例，钝化层38和42由无机材料形成，例如氧化硅、氮化硅、碳化硅、氮氧化硅、硅氧碳氮化物、未掺杂的硅酸盐玻璃(USG)或它们的多层。钝化层38和42中的每一个均可以是单层或复合层，并且可以由无孔材料形成。根据本发明的一些实施例，钝化层38和42中的一个或两个是包括氧化硅层(未单独示出)和位于氧化硅层上方的氮化硅层(未单独示出)的复合层。钝化层38和42具有阻止湿气和有害化学物质进入导电部件(例如封装件中的细间距RDL)的功能，如将在下文中所讨论的。
RDL 40和44可以由铝、铜、铝铜、镍或它们的合金形成。根据一些实施例，如图11所示，RDL 44的一些部分形成为足够大的金属焊盘，用于接合随后形成的介电通孔(TDV)。根据一些实施例，这些金属焊盘因此被称为金属焊盘44或铝焊盘44。此外，钝化层的数量可以是任何整数，例如一个、两个(如图所示)、三个或更多个。
图5示出了一个或多个介电层的形成。例如，如图所示，介电层46可以形成为将顶部RDL 44嵌入其中。介电层48形成在介电层46上方，并且可以用作蚀刻停止层。根据本发明的一些实施例，介电层46和48也可以用单个介电层代替。介电层46和48的可用材料包括氧化硅、氮化硅、碳化硅、氮氧化硅等。
图6、图7和图8示出了根据本发明的一些实施例的介电层和细间距RDL的形成。相应的步骤被示出为如图25所示的工艺流程300中的步骤306。形成方法可以采用形成用于基于硅衬底的器件管芯的互连结构的方法。例如，互连结构的形成方法可以包括单镶嵌和/或双镶嵌工艺。因此，所得到的RDL也可选地称为金属线和通孔，并且相应的介电层可选地称为金属间介电(IMD)层。
参照图6，形成介电层50A和54A以及蚀刻停止层52A。介电层50A和54A可以由氧化硅、氮氧化硅、氮化硅等或者具有低于约3.0的k值的低k介电材料形成。低k介电材料可以包括Black Diamond(应用材料公司的注册商标)、含碳低k介电材料、氢倍半硅氧烷(HSQ)、甲基倍半硅氧烷(MSQ)等。蚀刻停止层52A由相对于介电层50A和54A具有高蚀刻选择性的材料形成，并且可以由碳化硅、碳氮化硅等形成。根据可选实施例，不形成蚀刻停止层52A。
在介电层52A和54A中形成细间距RDL 56A用于布线。应当理解，单个所示的细间距RDL 56A表示多个细间距RDL。由于根据本发明的一些实施例的细间距RDL是使用镶嵌工艺形成的，所以它可以形成为非常薄、具有小于例如0.8μm的间距(从结构的顶部看)。这显著提高了细间距RDL的密度和布线能力。根据一些实施例，细间距RDL 56A使用单镶嵌工艺形成，其包括蚀刻介电层52A和54A以形成沟槽，用导电材料填充沟槽，以及执行诸如化学机械抛光(CMP)或机械研磨的平坦化以去除介电层54A上方的导电材料的部分。
根据本发明的一些实施例，用于形成细间距RDL 56A的导电材料是均质材料。根据本发明的其它实施例，导电材料是复合材料，该复合材料包括由钛、氮化钛、钽、氮化钽等形成的阻挡层以及位于阻挡层上方的含铜材料(可以是铜或铜合金)。细间距RDL 56A也可以由双镶嵌工艺形成，使得可以在一些细间距RDL 56A下方形成一些通孔，并且通孔可用于将细间距RDL 56A连接到RDL 44。
图7示出了介电层50B和54B以及蚀刻停止层52B的形成。介电层50B和54B的材料可以从与用于形成介电层50A和54A相同的候选材料中选择，并且蚀刻停止层52B的材料可以从与用于形成蚀刻停止层52A相同的候选材料中选择。
细间距RDL 56B也形成在介电层50B、52B和54B中。细间距RDL 56B包括在介电层54B中形成的金属线和在介电层50B和52B中形成的通孔。尽管图7示出了金属线由于过蚀刻而延伸到蚀刻停止层52B中，但是RDL56B中的金属线实际上可能停止在蚀刻停止层52B的顶面上并且不穿透蚀刻停止层52B。该形成可以包括双镶嵌工艺，其包括在介电层54B中形成沟槽、并在介电层50B和52B中形成通孔开口、填充导电材料、并且然后进行诸如机械研磨或化学机械抛光(CMP)的平坦化。类似地，细间距RDL56B可以由均质材料形成，或者可以由复合材料形成，复合材料包括阻挡层和位于阻挡层上方的含铜材料。
图8示出了介电层50C和54C以及蚀刻停止层52C和细间距RDL 56C的形成。形成方法和材料可以类似于下方的相应的层，因此这里不再重复。此外，根据一些实施例，可以省略蚀刻停止层52A、52B和52C，并且可以使用时间模式来执行用于形成沟槽的相应蚀刻，以控制沟槽的深度。应当理解，可以形成更多的介电层和细间距RDL的层。此外，即使可以跳过蚀刻停止层52A、52B和52C中的一些或全部，由于细间距RDL所处的介电层以不同的工艺形成，所以用于形成细间距RDL 56A、56B和56C的介电层之间可能存在可区分的界面，不管这些介电层是由相同的介电材料还是不同的介电材料形成的。在随后的段落中，为了简化识别，介电层50A、52A、54A、50B、52B、54B、50C、52C和54C被共同且单独地称为介电层58。细间距RDL 56A、56B和56C也被共同地且单独地称为细间距RDL56。类似地，尽管图8示出了RDL56C中的金属线由于过蚀刻而延伸到蚀刻停止层52C中，但RDL 56C中的金属线实际上可能停止在蚀刻停止层52C的顶面上并且不穿透蚀刻停止层52C。
参照图9，对介电层48和58进行蚀刻以形成介电通孔(TDV)开口60。相应的步骤被示出为图25所示的工艺流程300中的步骤308。金属焊盘44暴露于TDV开口60。当从图9所示的结构的顶部观察时，通孔开口60可以对齐成环形，以环绕形成细间距RDL 56的区域。通孔开口60的顶视图形状可以是矩形、圆形、六边形等。
接下来，用导电材料填充TDV开口60以形成TDV 62，并且所得到的结构如图10所示。相应的步骤被示出为图25所示的工艺流程300中的步骤310。根据本发明的一些实施例，TDV 62由均匀的导电材料形成，导电材料可以是包括铜、铝、钨等的金属或金属合金。根据本发明的可选实施例，TDV 62具有复合结构，该复合结构包括由钛、氮化钛、钽、氮化钽等形成的导电阻挡层和位于阻挡层上方的含金属材料。根据本发明的一些实施例，形成介电隔离层以环绕每个TDV 62。根据可选实施例，不形成用于环绕TDV 62的介电隔离层，并且TDV62与介电层58物理接触。TDV 62的形成还包括将导电材料沉积到TDV开口60(图9)中，并且执行平坦化以去除介电层58上方的沉积材料的多余部分。
图11示出了接合焊盘66和介电层64的形成，并且接合焊盘66位于介电层64中。在整个说明书中，介电层64可选地被称为绝缘层或介电绝缘区域。相应的步骤被示出为图25所示的工艺流程300中的步骤312。接合焊盘66可以由易于形成混合接合的金属形成。根据本发明的一些实施例，接合焊盘66由铜或铜合金形成。例如，介电层64可以由氧化硅形成。接合焊盘66和介电层64的顶面是共面的。平面化可以通过诸如CMP或机械研磨步骤的平坦化步骤来实现。
在整个说明书中，层22上方的组件被总称为中介层100。与基于硅衬底形成的常规中介层不同，中介层100基于介电层58形成。中介层100中没有硅衬底，因此中介层100被称为无硅衬底中介层或少Si中介层。在介电层58中形成TDV 62，以代替常规的硅通孔。由于硅衬底是半导体性质的，所以它可能不利地影响电路及在硅衬底中和在硅衬底上形成的连接件的性能。例如，存在由硅衬底引起的信号劣化，并且这种劣化在本发明的实施例中可以避免，因为TDV 62形成在介电层中。
接下来，如图12所示，将器件68A和68B接合到中介层100。相应的步骤被示出为图25所示的工艺流程300中的步骤314。器件68A和68B可以是器件管芯，并且因此在下文中被称为器件管芯，而它们可以是其它类型的器件，例如封装件。根据本发明的一些实施例，器件管芯68A和68B可以包括逻辑管芯，逻辑管芯可以是中央处理单元(CPU)管芯、微控制单元(MCU)管芯、输入-输出(IO)管芯、基带(BB)管芯或应用处理器(AP)管芯。器件管芯68A和68B还可以包括存储器管芯。器件管芯68A和68B分别包括可以是硅衬底的半导体衬底70A和70B。此外，器件管芯68A和68B分别包括用于连接到器件管芯68A和68B中的有源器件和无源器件的互连结构72A和72B。互连结构72A和72B包括金属线和通孔(未示出)。
器件管芯68A包括在器件管芯68A的所示底面处的接合焊盘74A和介电层76A。接合焊盘74A的所示底面与介电层76A的所示底面共面。器件管芯68B包括在所示底面处的接合焊盘74B和介电层76B。接合焊盘74B的所示底面与介电层76B的所示底面共面。
可以通过混合接合来实现接合。例如，接合焊盘74A和74B通过金属对金属直接接合而接合到接合焊盘66。根据本发明的一些实施例，金属对金属直接接合是铜对铜的直接结合。此外，例如，介电层76A和76B通过产生的Si-O-Si键接合到介电层64。混合接合可以包括预接合和退火，使得接合焊盘74A(和74B)中的金属与相应的下方的接合焊盘66中的金属互相扩散。
细间距RDL 56将接合焊盘74A和接合焊盘74B电互连，并且用于器件管芯68A和68B之间的信号通信。细间距RDL 56具有小间距和小宽度。因此，细间距RDL 56的密度高，因此可以形成足够的通信通道用于器件管芯68A和68B之间的直接通信。另一方面，TDV 62提供从器件管芯68A和68B到将被结合到中介层100的部件(其可以是封装衬底、印刷电路板(PCB)等)的直接连接。此外，接合焊盘74A/74B和66之间的接合是通过接合焊盘而不是通过焊料接头，焊料接头通常比接合焊盘大很多。因此，接合的水平尺寸小，并且可以实现更多的接合以提供足够的通信通道。
参考图13，例如，进行背侧研磨以将器件管芯68A和68B减薄至约15μm和约30μm之间的厚度。相应的步骤被示出为图25所示的工艺流程300中的步骤316。通过减薄，相邻的器件管芯68A和68B之间的间隙78的纵横比被减小以便进行间隙填充。否则，由于高的纵横比，难以填充间隙。
接下来，如图14所示，用间隙填充材料80填充间隙78。相应的步骤被示出为图25所示的工艺流程300中的步骤318。根据本发明的一些实施例，间隙填充材料80包括可以由原硅酸四乙酯(TEOS)形成的诸如氧化硅的氧化物。形成方法可以包括化学气相沉积(CVD)、高密度等离子体化学气相沉积(HDPCVD)等。根据可选实施例，间隙填充材料80由诸如PBO、聚酰亚胺等的聚合物形成。然后进行平坦化以去除间隙填充材料80的多余部分，使得露出器件管芯68A和68B的衬底70A和70B。图15A示出了所得到的结构。根据本发明的可选实施例，其中，间隙填充材料80由氧化物(例如氧化硅)形成，间隙填充材料80的薄层可以留在衬底70A和70B上方，并且所得到的结构在图15B中示出。在器件管芯68A和68B上方的间隙填充材料80的剩余部分在下文中可选地称为介电层82或绝缘层82。
根据图15A所示的实施例，其中，衬底70A和70B露出，例如使用CVD、等离子体增强CVD(PECVD)、原子层沉积(ALD)等来将介电层82(如图16所示)沉积为毯状层。相应的步骤被示出为图25所示的工艺流程300中的步骤320。根据可选实施例(如图15B所示)，其中，间隙填充材料80的薄层(其也被称为82)留在衬底70A和70B上方，可以跳过介电层的沉积。接下来，通过对介电层82和衬底70A和70B进行蚀刻形成沟槽84，使得沟槽84也延伸到介电层82和衬底70A和70B中。所得到的结构如图16所示。沟槽84的位于衬底70A和70B内的部分的深度D1可以大于约1μm，并且可以在约2μm至约5μm之间，这取决于衬底70A和70B的厚度T1。例如，深度D1可以在厚度T1的约20％至约60％之间。然而，应当理解，整个说明书中列举的值是实例，并且可以改变为不同的值。
沟槽84可以以各种图案分布。例如，沟槽84可以形成为离散开口，离散开口可以被分配为阵列、蜂窝图案或其他重复图案。沟槽84的顶视图形状可以是矩形、正方形、圆形、六边形等。根据可选实施例，当在图16所示的结构的顶视图中观察时，沟槽84可以是沿单向延伸的平行沟槽。沟槽84也可以互连以形成栅格。栅格可以包括彼此平行且均匀或不均匀间隔开的多个第一沟槽，以及彼此平行且均匀或不均匀间隔开的多个第二沟槽。多个第一沟槽和多个第二沟槽彼此截断以形成栅格，并且多个第一沟槽和多个第二沟槽在顶视图中可以彼此垂直或可以不彼此垂直。
然后填充沟槽84以形成接合焊盘86，如图17所示。相应的步骤被示出为图25所示的工艺流程300中的步骤320。应当理解，虽然部件86被称为接合焊盘，但是部件86可以是离散焊盘或互连金属线。根据一些实施例，接合焊盘86由适于混合接合的铜或其它金属形成(由于相对容易扩散)。在填充之后，执行平坦化以使接合焊盘86的顶面和介电层82的顶面齐平。平坦化可以包括CMP或机械研磨工艺。
接下来，如图18A所示，晶圆88接合到器件管芯68A和68B。相应的步骤被示出为图25所示的工艺流程300中的步骤322。晶圆88包括可以是硅衬底或金属衬底的块状衬底94。块状衬底94也是在置于同一载体20上方的多个器件管芯68A和多个器件管芯68B上延伸的晶圆。当衬底94由金属形成时，可以由铜、铝、不锈钢等形成。当衬底94由硅形成时，在晶圆88中没有形成有源器件或无源器件。晶圆88有两个功能。首先，因为器件管芯68A和68B已被薄化，晶圆88为下面的结构提供机械支撑，以便允许更好的间隙填充。此外，(衬底94的)硅或金属具有高导热性，因此晶圆88可以用作散热器。
在衬底94的表面处形成介电层90。例如，介电层90可以由氧化硅形成。此外，在介电层90中形成接合焊盘92，并且接合焊盘92的所示底面与介电层90的所示底面是共面的。接合焊盘92的图案和水平尺寸可以与相应的接合焊盘86的图案和水平尺寸相同或类似。
通过混合接合将晶圆88接合到器件管芯68A和68B。例如，介电层82和90彼此接合，并且可以形成Si-O-Si键。通过金属对金属直接接合将接合焊盘92接合到相应的接合焊盘86。
有利的是，接合焊盘86通过接触(以及甚至插入到)衬底70A和70B，接合焊盘86提供良好的散热路径，使得在器件管芯68A和68B中产生的热量可以易于散发到块状衬底94中。
图18B示出了根据本发明的一些实施例形成的封装件。这些实施例类似于图18A所示的实施例，除了接合焊盘86穿透介电层82并且不延伸到衬底70A和70B中。根据一些实施例，接合焊盘86与衬底70A和70B接触。根据可选实施例，接合焊盘86和92中的一个或两个从发生接合的界面部分地延伸到相应的介电层82和90中，而不穿透相应的介电层82和90。根据本发明的一些实施例，接合焊盘86和92以及块状衬底94可以电接地，从而为衬底70A和70B提供电接地。
图18C示出了根据本发明的一些实施例形成的封装件。这些实施例类似于图18A和18B所示的实施例，除了不形成接合焊盘86和92以及介电层90(如图18A和图18B所示)。块状衬底94也是晶圆88并且是硅晶圆，块状衬底94通过熔融接合接合到介电层82。
根据本发明的可选实施例，晶圆88是金属晶圆。因此，图18C中的层82可以是热界面材料(TIM)，该热界面材料是具有高导热性的粘合层。
接下来，例如通过将诸如UV光或激光的光投射在释放层22上以分解释放层22，将形成在载体20上的结构与载体20脱接合，并且将载体20和释放层22从上方的结构去除，上方的结构被称为复合晶圆102(图19)。
图20示出了可以穿透介电层24并且连接到RDL 26的电连接件110的形成。电连接件110可以是金属凸块、焊料凸块、金属柱、引线接合或其它适用的连接件。对复合晶圆102执行管芯切割步骤以将复合晶圆102分离成多个封装件104。相应的步骤被示出为图25所示的工艺流程300中的步骤324。封装件104彼此相同，并且每个封装件104均包括器件管芯68A和68B。
图21和22示出了根据本发明的一些实施例的形成封装件的中间阶段的截面图。除非另有规定，这些实施例中的组件的材料和形成方法与在图1至图20所示的实施例中由相同的参考标号标示的类似的组件基本上相同。因此，关于图21和图22中示出的组件的形成工艺和材料的细节可以在图1至图20中示出的实施例的讨论中找到。图21示出了复合晶圆102的截面图，其与图20所示的基本相同，除了在介电层24上形成金属焊盘45，同时在载体20上没有形成如图20所示的包括介电层28、34、38和42以及RDL 32、36、40和44的部件。相反，如图22所示，其示出了在图21所示的步骤之后的结构，在载体20(图21)脱接合之后，形成介电层28、34、38和42以及RDL 32、36、40和44。根据这些实施例的用于形成介电层28、34、38和42的顺序相对于图1至图11所示的顺序颠倒。应注意，由于不同的形成顺序，RDL 32、36、40和44的取向与图20所示的RDL 32、36、40和44的取向相比是相反的(在垂直方向上)。然后通过复合晶圆102的管芯切割形成封装件104。
图23示出了其中嵌入有封装件104(图20和22)的封装件112。该封装件包括存储器数据集114，存储器数据集114包括多个堆叠的存储器管芯(未单独示出)。封装件104和存储器数据集114被封装在封装材料118中，封装材料118可以是模塑料。介电层和RDL(共同示为116)位于封装件104和存储器数据集114下方并且连接到封装件104和存储器数据集114。根据一些实施例，介电层和RDL 116使用相似的材料形成并且具有与图1至图11所示的结构相似的结构。
图24示出了封装件上封装件(PoP)结构132，其具有与顶部封装件140相接合的集成扇出(InFO)封装件138。InFO封装件138还包括嵌入在其中的封装件104。封装件104和通孔134被封装在封装材料130中，封装材料130可以是模塑料。封装件104接合到统称为146的介电层和RDL。介电层和RDL 146也可以使用相似的材料形成并且具有与图1至图11所示的结构相似的结构。
本发明的实施例具有一些有利的特征。通过采用通常在硅晶圆上使用的工艺(例如镶嵌工艺)来形成用于中介层的细间距RDL，细间距RDL可以形成为足够薄以提供用于两个或多个器件管芯的通信能力，所有这些都是通过细间距RDL。在中介层中不使用硅衬底，因此避免了由硅衬底导致的电性能的劣化。在封装件中还建立了一些散热机制，以实现更好的散热。
根据本发明的一些实施例，一种方法包括：形成多个介电层；在所述多个介电层中形成多个再分布线；蚀刻所述多个介电层以形成开口；填充所述开口以形成穿透所述多个介电层的介电通孔；在所述介电通孔和所述多个介电层上方形成绝缘层；在所述绝缘层中形成多个接合焊盘；以及通过混合接合将器件接合至所述绝缘层和所述多个接合焊盘的一部分。
在上述方法中，还包括通过混合接合将第二器件接合至所述绝缘层和所述多个接合焊盘的第二部分，其中，所述多个再分布线将所述第一器件连接至所述第二器件。
在上述方法中，其中，形成所述多个再分布线包括镶嵌工艺。
在上述方法中，其中，所述介电通孔不延伸至任何半导体衬底。
在上述方法中，还包括：形成覆盖并接触所述第一器件的半导体衬底的氧化物层；形成延伸到所述氧化物层中的接合焊盘；以及通过混合接合将块状晶圆接合至所述氧化物层和所述接合焊盘。
在上述方法中，还包括：形成覆盖并接触所述第一器件的半导体衬底的氧化物层；形成延伸到所述氧化物层中的接合焊盘；以及通过混合接合将块状晶圆接合至所述氧化物层和所述接合焊盘，其中，所述接合焊盘延伸到所述第一器件的半导体衬底内。
在上述方法中，还包括：形成覆盖并接触所述第一器件的半导体衬底的氧化物层；形成延伸到所述氧化物层中的接合焊盘；以及通过混合接合将块状晶圆接合至所述氧化物层和所述接合焊盘，其中，所述接合焊盘接触所述第一器件的半导体衬底而不延伸到所述第一器件的半导体衬底内。
根据本发明的一些实施例，一种方法包括：形成多个介电层；在所述多个介电层中形成多个再分布线；形成穿透所述多个介电层的第一介电通孔和第二介电通孔；在所述多个介电层上方形成绝缘层；在所述绝缘层中形成多个接合焊盘，并且所述多个接合焊盘电连接至所述第一介电通孔和第二介电通孔以及所述多个再分布线；以及通过混合接合将第一器件和第二器件接合至所述绝缘层和所述多个接合焊盘。所述第一器件通过所述多个再分布线与所述第二器件电互连。
在上述方法中，其中，使用镶嵌工艺形成所述多个再分布线。
在上述方法中，还包括：在载体上方形成聚合物层；在所述聚合物层上方形成钝化层，其中，在所述钝化层上方形成所述多个介电层；在所述聚合物层和所述钝化层中形成附加再分布线；以及将所述载体从所述聚合物层分离。
在上述方法中，其中，在载体上方形成所述多个介电层，并且所述方法还包括：将所述多个介电层从所述载体脱接合；在所述脱接合之后，在所述多个介电层上形成钝化层；以及在所述钝化层上方形成聚合物层。
在上述方法中，其中，形成所述第一介电通孔和所述第二介电通孔包括：蚀刻所述多个介电层以形成第一开口和第二开口；以及用导电材料填充所述第一开口和所述第二开口。
在上述方法中，还包括：减薄所述第一器件和所述第二器件；以及将间隙填充材料填充到所述第一器件和所述第二器件之间的间隙中。
在上述方法中，还包括：减薄所述第一器件和所述第二器件；以及将间隙填充材料填充到所述第一器件和所述第二器件之间的间隙中，还包括：在已经被减薄的所述第一器件和所述第二器件上方形成介电层；以及将块状晶圆接合至所述介电层。
根据本发明的一些实施例，一种封装件包括：多个介电层；多个再分布线，位于所述多个介电层的每一个中；介电通孔，穿透所述多个介电层；多个接合焊盘，位于所述介电通孔和所述多个再分布线上方，并且连接至所述介电通孔和所述多个再分布线；以及绝缘层，其中，所述多个接合焊盘位于所述绝缘层中。器件通过混合接合接合至所述绝缘层和所述多个接合焊盘的一部分。
在上述封装件中，还包括第二器件，通过混合接合将所述第二器件接合至所述第一绝缘层和所述多个接合焊盘的第二部分，其中，所述第一器件和所述第二器件通过所述多个再分布线彼此电连接。
在上述封装件中，还包括：接合焊盘，与所述第一器件的半导体衬底物理接触；第二绝缘层，所述接合焊盘的至少一部分位于所述第二绝缘层中；块状衬底，接合至所述第二绝缘层和所述接合焊盘。
在上述封装件中，还包括：接合焊盘，与所述第一器件的半导体衬底物理接触；第二绝缘层，所述接合焊盘的至少一部分位于所述第二绝缘层中；块状衬底，接合至所述第二绝缘层和所述接合焊盘，其中，所述块状衬底由硅形成，并且在所述块状衬底上没有形成有源器件和无源器件。
在上述封装件中，还包括：接合焊盘，与所述第一器件的半导体衬底物理接触；第二绝缘层，所述接合焊盘的至少一部分位于所述第二绝缘层中；块状衬底，接合至所述第二绝缘层和所述接合焊盘，其中，所述接合焊盘进一步延伸至所述第一器件的半导体衬底内。
在上述封装件中，还包括：接合焊盘，与所述第一器件的半导体衬底物理接触；第二绝缘层，所述接合焊盘的至少一部分位于所述第二绝缘层中；块状衬底，接合至所述第二绝缘层和所述接合焊盘，其中，所述接合焊盘形成栅格。
以上论述了若干实施例的特征，使得本领域的技术人员可以更好地理解本发明的各个方面。本领域技术人员应该理解，他们可以容易地使用本发明作为基础来设计或修改用于实施与本文所介绍的实施例相同的目的和/或实现相同优点的其他工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，本文中他们可以做出多种变化、替换以及改变。

Claims (10)

1.一种形成封装件的方法，包括：
形成多个介电层；
在所述多个介电层中形成多个再分布线；
蚀刻所述多个介电层以形成开口；
填充所述开口以形成穿透所述多个介电层的一部分的介电通孔；
在所述介电通孔和所述多个介电层上方形成绝缘层；
在所述绝缘层中形成多个接合焊盘；以及
通过混合接合将第一器件接合至所述绝缘层和所述多个接合焊盘的第一部分。
2.根据权利要求1所述的方法，还包括通过混合接合将第二器件接合至所述绝缘层和所述多个接合焊盘的第二部分，其中，所述多个再分布线将所述第一器件连接至所述第二器件。
3.根据权利要求1所述的方法，其中，形成所述多个再分布线包括镶嵌工艺。
4.根据权利要求1所述的方法，其中，所述介电通孔不延伸至任何半导体衬底。
5.根据权利要求1所述的方法，还包括：
形成覆盖并接触所述第一器件的半导体衬底的氧化物层；
形成延伸到所述氧化物层中的接合焊盘；以及
通过混合接合将块状晶圆接合至所述氧化物层和所述接合焊盘。
6.根据权利要求5所述的方法，其中，所述接合焊盘延伸到所述第一器件的半导体衬底内。
7.根据权利要求5所述的方法，其中，所述接合焊盘接触所述第一器件的半导体衬底而不延伸到所述第一器件的半导体衬底内。
8.一种形成封装件的方法，包括：
形成多个介电层；
在所述多个介电层中形成多个再分布线；
形成穿透所述多个介电层的一部分的第一介电通孔和第二介电通孔；
在所述多个介电层上方形成绝缘层；
在所述绝缘层中形成多个接合焊盘，并且所述多个接合焊盘电连接至所述第一介电通孔和所述第二介电通孔以及所述多个再分布线；以及
通过混合接合将第一器件和第二器件接合至所述绝缘层和所述多个接合焊盘的一部分，其中，所述第一器件通过所述多个再分布线中的至少一个与所述第二器件电互连。
9.根据权利要求8所述的方法，其中，使用镶嵌工艺形成所述多个再分布线。
10.一种封装件，包括：
多个介电层；
多个再分布线，位于所述多个介电层中；
介电通孔，穿透所述多个介电层的一部分；
多个接合焊盘，位于所述介电通孔和所述多个再分布线上方，并且连接至所述介电通孔和所述多个再分布线；
第一绝缘层，所述多个接合焊盘位于所述第一绝缘层中；以及
第一器件，接合至所述第一绝缘层和所述多个接合焊盘的第一部分，其中，所述第一器件包括：
表面金属部件，接合至所述多个接合焊盘；以及
表面介电层，接合至所述第一绝缘层。
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