CN108695176B - 封装件及其形成方法 - Google Patents

封装件及其形成方法 Download PDF

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Publication number
CN108695176B
CN108695176B CN201711281699.3A CN201711281699A CN108695176B CN 108695176 B CN108695176 B CN 108695176B CN 201711281699 A CN201711281699 A CN 201711281699A CN 108695176 B CN108695176 B CN 108695176B
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device die
dielectric
forming
die
dielectric layer
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CN108695176A (zh
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陈明发
余振华
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一种方法包括：形成多个介电层；在所述多个介电层中形成多个再分布线；蚀刻所述多个介电层以形成开口；填充所述开口以形成穿透所述多个介电层的介电通孔；在所述介电通孔和所述多个介电层上方形成介电层；在所述介电层中形成多个接合焊盘；通过混合接合将第一器件管芯接合至所述介电层和所述多个接合焊盘的第一部分；以及将管芯叠层接合至所述第一器件管芯中的硅通孔。本发明的实施例还涉及封装件及其形成方法。

Description

封装件及其形成方法
技术领域
本发明的实施例涉及封装件及其形成方法。
背景技术
集成电路的封装件变得越来越复杂，更多的器件管芯封装在同一封装件中以实现更多的功能。例如，封装件可以包括接合至同一中介层的多个器件管芯(诸如处理器和存储数据集)。中介层可以基于半导体衬底形成，硅通孔形成在半导体衬底中以互连形成在中介层的相对侧上的部件。模塑料封装其中的器件管芯。包括中介层和器件管芯的封装件进一步接合至封装衬底。此外，表面贴装器件也可以接合至该衬底。散热器可以附接至器件管芯的顶面，以便消散器件管芯中产生的热量。散热器可以具有固定到封装衬底上的裙部(skirt portion)。
发明内容
本发明的实施例提供了一种形成封装件的方法，包括：形成多个介电层；在所述多个介电层中形成多个再分布线；蚀刻所述多个介电层以形成开口；填充所述开口以形成穿透所述多个介电层的介电通孔；在所述介电通孔和所述多个介电层上方形成介电层；在所述介电层中形成多个接合焊盘；通过混合接合将第一器件管芯接合至所述介电层和所述多个接合焊盘的第一部分；以及将管芯叠层接合至所述第一器件管芯的硅通孔。
本发明的另一实施例提供了一种形成封装件的方法，包括：形成多个介电层；在所述多个介电层的每一个中形成多个再分布线；形成穿透所述多个介电层的第一介电通孔和第二介电通孔；在所述多个介电层上方形成介电层；在所述介电层中形成多个接合焊盘，并且所述多个接合焊盘电连接至所述第一介电通孔、所述第二介电通孔和所述多个再分布线；通过混合接合将第一器件管芯和第二器件管芯接合至所述介电层和所述多个接合焊盘，其中，所述第一器件管芯通过所述多个再分布线与所述第二器件管芯电互连；以及将管芯叠层接合至所述第二器件管芯。
本发明的又一实施例提供了一种封装件，包括：多个介电层；多个再分布线，位于所述多个介电层的每一个中；第一介电通孔，穿透所述多个介电层；多个接合焊盘，位于所述第一介电通孔和所述多个再分布线上方，并且连接至所述第一介电通孔和所述多个再分布线；第一介电层，所述多个接合焊盘位于所述第一介电层中；第一器件管芯，通过混合接合接合至所述第一介电层和所述多个接合焊盘的第一部分；间隙填充材料，位于所述第一器件管芯的相对侧上；第二介电通孔，穿透所述间隙填充材料；以及管芯叠层，接合至所述第二介电通孔。
附图说明
当结合附图进行阅读时，根据下面详细的描述可以最好地理解本发明的各个方面。应该注意，根据工业中的标准实践，各种部件没有被按比例绘制。实际上，为了清楚的讨论，各种部件的尺寸可以被任意增加或减少。
图1至图28A示出了根据一些实施例的形成无硅衬底(少硅)封装件的中间阶段的截面图。
图28B至图28C示出了根据一些实施例的包括少硅封装件的封装件的截面图。
图29至图30示出了根据一些实施例的形成少硅封装件的中间阶段的截面图。
图31至图32示出了根据一些实施例的嵌入少硅封装件的封装件的截面图。
图33示出了根据一些实施例的用于形成封装件的工艺流程。
具体实施方式
以下公开内容提供了多种不同实施例或实例，以实现本发明的不同特征。以下将描述组件和布置的具体实例以简化本发明。当然，这些仅是实例并且不旨在限制本发明。例如，在以下描述中，在第二部件上方或上形成第一部件可以包括第一部件和第二部件直接接触的实施例，也可以包括形成在第一部件和第二部件之间的附加部件使得第一部件和第二部件不直接接触的实施例。而且，本发明在各个实例中可以重复参考数字和/或字母。该重复仅是为了简明和清楚，其自身并不表示所论述的各个实施例和/或配置之间的关系。
而且，为便于描述，在此可以使用诸如“在...下面”、“在...下方”、“下部”、“在...上面”、“上部”等的空间相对术语，以便于描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外，空间关系术语旨在包括器件在使用或操作过程中的不同方位。装置可以以其他方式定位(旋转90度或在其他方位)，并且在本文中使用的空间关系描述符可以同样地作相应地解释。
根据各个示例性实施例提供了基于无硅衬底(少硅)的中介层形成的封装件及其形成方法。根据一些实施例示出了形成封装件的中间阶段。讨论了一些实施例的一些变化。在各个视图和说明性实施例中，相同的参考标号用于指定相同的元件。
图1至图28A示出了根据本发明的一些实施例的形成封装件的中间阶段的截面图。图1至图28A示出的步骤也示意性地反映在图33示出的工艺流程300中。
图1示出了载体20和形成在载体20上的释放层22。载体20可以是玻璃载体、硅晶圆、有机载体等。载体20可以具有圆形的顶视形状，并且可以具有普通硅晶圆的尺寸。例如，载体20可以具有8英寸直径、12英寸直径等。释放层22可由聚合物基材料(诸如，光热转换(LTHC)材料)形成，其可连同载体20从将在后续步骤中形成的上面结构被去除。根据本发明的一些实施例，释放层22由环氧树脂基热释放材料形成。释放层22可以涂覆到载体20上。释放层22的顶面是水平的并且具有高度共面性。
介电层24形成在释放层22上。根据本发明的一些实施例，介电层24由聚合物形成，该聚合物也可以是使用光刻工艺可以易于被图案化的诸如聚苯并恶唑(PBO)、聚酰亚胺、苯并环丁烯(BCB)等的光敏材料。
再分布线(RDL)26形成在介电层24上方。RDL 26的形成可以包括在介电层24上方形成晶种层(未示出)，在晶种层上方形成诸如光刻胶的图案化掩模(未示出)，然后在暴露的晶种层上实施金属镀。然后去除图案化掩模和晶种层的由图案化掩模覆盖的部分，从而留下如图1中的RDL26。根据本发明的一些实施例，晶种层包括钛层和位于钛层上方的铜层。例如，可以使用物理气相沉积(PVD)形成晶种层。例如，可以使用化学镀实施镀。
进一步参考图1，介电层28形成在RDL 26上。介电层28的底面与RDL 26的顶面以及介电层24的顶面接触。根据本发明的一些实施例，介电层28由聚合物形成，该聚合物可以是诸如PBO、聚酰亚胺、BCB等的光敏材料。然后图案化介电层28以在其中形成开口30。因此，通过介电层28中的开口30暴露出RDL 26的一些部分。
接下来，参考图2，RDL 32形成为连接至RDL 26。RDL 32包括介电层28上方的金属迹线(金属线)。RDL 32还包括延伸进入介电层28中的开口的通孔。RDL 32也在镀工艺中形成，其中每一个RDL 32都包括晶种层(未示出)和晶种层上方的镀的金属材料。晶种层和镀的材料可以由相同材料或不同材料形成。RDL 32可包括金属或包括铝、铜、钨和它们的合金的金属合金。用于形成介电层28和24以及RDL 32和26的步骤被示出为图33所示的工艺流程300的步骤302。
参考图3，介电层34形成在RDL 32和介电层28上方。介电层34可以使用聚合物来形成，介电层34可以选自与介电层28的材料相同的候选材料。例如，介电层34可以由PBO、聚酰亚胺、BCB等形成。可选地，介电层34可包括无机介电材料，诸如氧化硅、氮化硅、碳化硅、氮氧化硅等。
图3还示出了RDL 36的形成，RDL 36电连接至RDL 32。RDL 36的形成可采用与形成RDL 32的方法和材料类似的方法和材料。应当理解，尽管在说明性的示例性实施例中讨论了两个聚合物层28和34以及其中形成的相应的RDL 32和36，但是取决于布线要求和用聚合物缓冲应力的要求，可以采用更少或更多的介电层。例如，可以存在单个聚合物层或三个、四个或更多个聚合物层。
图4示出了钝化层38和42以及RDL 40和44的形成。相应的步骤被示出为图33所示的工艺流程300中的步骤304。根据本发明的一些实施例，钝化层38和42由无机材料形成，例如氧化硅、氮化硅、碳化硅、氮氧化硅、硅氧碳氮化物、未掺杂的硅酸盐玻璃(USG)或它们的多层。钝化层38和42中的每一个可以是单层或复合层，并且可以由无孔材料形成。根据本发明的一些实施例，钝化层38和42中的一个或两个是包括氧化硅层(未单独示出)和在氧化硅层上方的氮化硅层(未单独示出)的复合层。钝化层38和42具有阻止湿气和有害化学物质进入导电部件(例如封装件中的细间距RDL)的功能，如将在下文中所讨论的。
RDL 40和44可以由铝、铜、铝铜、镍或它们的合金形成。根据本发明的一些实施例，如图11所示，RDL 44的一些部分形成为足够大的金属焊盘，以接合随后形成的介电通孔(TDV)。根据一些实施例，这些金属焊盘因此被称为金属焊盘44或铝焊盘44。此外，钝化层的数量可以是任何整数，例如一个、两个(如图所示)、三个或更多个。
图5示出了一个或多个介电层的形成。例如，如图所示，介电层46可以形成为将顶部RDL 44嵌入其中。介电层48形成在介电层46上方，并且可以用作蚀刻停止层。根据本发明的一些实施例，介电层46和48也可以用单个介电层代替。介电层46和48的可用材料包括氧化硅、氮化硅、碳化硅、氮氧化硅等。
图6、图7和图8示出了根据本发明的一些实施例的介电层和细间距RDL的形成。相应的步骤被示出为图33所示的工艺流程300中的步骤306。形成方法可以采用形成用于基于硅衬底的器件管芯的互连结构的方法。例如，互连结构的形成方法可以包括单镶嵌和/或双镶嵌工艺。因此，所得到的RDL也可选地称为金属线和通孔，并且相应的介电层可选地称为金属间介电(IMD)层。
参考图6，形成介电层50A和54A以及蚀刻停止层52A。介电层50A和54A可以由氧化硅、氮氧化硅、氮化硅等，或者具有低于约3.0的k值的低k介电材料形成。低k介电材料可以包括Black Diamond(应用材料公司的注册商标)、含碳低k介电材料、氢倍半硅氧烷(HSQ)、甲基倍半硅氧烷(MSQ)等。蚀刻停止层52A由相对于介电层50A和54A具有高蚀刻选择性的材料形成，并且可以由碳化硅、碳氮化硅等形成。根据可选实施例，不形成蚀刻停止层52A。
在介电层52A和54A中形成细间距RDL 56A用于布线。应当理解，单个所示的细间距RDL 56A表示多个细间距RDL。由于根据本发明的一些实施例的细间距RDL是使用镶嵌工艺形成的，所以它可以形成得非常薄、具有小于例如0.8μm的间距(从结构的顶部看)。这显著提高了细间距RDL的密度和布线能力。根据本发明的一些实施例，细间距RDL 56A使用单镶嵌工艺形成，单镶嵌工艺包括蚀刻介电层52A和54A以形成沟槽，用导电材料填充沟槽，以及实施诸如化学机械抛光(CMP)或机械研磨的平坦化以去除介电层54A上方的导电材料的部分。
根据本发明的一些实施例，用于形成细间距RDL 56A的导电材料是均质材料。根据本发明的其它实施例，导电材料是复合材料，该复合材料包括由钛、氮化钛、钽、氮化钽等形成的阻挡层、以及位于阻挡层上方的含铜材料(可以是铜或铜合金)。细间距RDL 56A也可以由双镶嵌工艺形成，使得可以在一些细间距RDL 56A下方形成一些通孔，并且通孔可用于将细间距RDL 56A连接到RDL 44。
图7示出了介电层50B和54B以及蚀刻停止层52B的形成。介电层50B和54B的材料可以从与用于形成介电层50A和54A相同的候选材料中选择，并且蚀刻停止层52B的材料可以从与用于形成蚀刻停止层52A相同的候选材料中选择。
细间距RDL 56B也形成在介电层50B、52B和54B中。细间距RDL 56B包括在介电层54B和52B中形成的金属线和在介电层50B中形成的通孔。该形成可以包括双镶嵌工艺，双镶嵌工艺包括在介电层54B和52B中形成沟槽、并在介电层50B中形成通孔开口、填充导电材料、然后实施诸如机械研磨或化学机械抛光(CMP)的平坦化。类似地，细间距RDL 56B可以由均质材料形成，或者可以由复合材料形成，复合材料包括阻挡层和在阻挡层上方的含铜材料。
图8示出了介电层50C和54C、蚀刻停止层52C和细间距RDL 56C的形成。形成方法和材料可以类似于下方的相应的层，因此这里不再重复。此外，根据本发明的一些实施例，可以省略蚀刻停止层52A、52B和52C，并且形成沟槽的相应蚀刻可以使用时间模式来实施，以控制沟槽的深度。应当理解，可以形成更多的介电层和细间距RDL的层。此外，即使可以跳过一些或全部的蚀刻停止层52A、52B和52C，由于细间距RDL所位于的介电层以不同的工艺形成，所以介电层之间可能存在可区分的界面，用于形成细间距RDL 56A、56B和56C，而不管这些介电层是由相同的介电材料还是不同的介电材料形成的。在随后的段落中，为了简化识别，介电层50A、52A、54A、50B、52B、54B、50C、52C和54C被共同且单独地称为介电层58。细间距RDL 56A、56B和56C也共同地且单独地称为细间距RDL 56。
参考图9，对介电层48和58进行蚀刻以形成介电通孔(TDV)开口60。相应的步骤被示出为图33所示的工艺流程300中的步骤308。金属焊盘44暴露于TDV开口60。当从图9所示的结构的顶部观看时，通孔开口60可以对齐成环形，以环绕形成细间距RDL 56的区域。通孔开口60的顶视形状可以是矩形、圆形、六边形等。
接下来，用导电材料填充TDV开口60以形成TDV 62，并且所得到的结构如图10所示。相应的步骤被示出为图33所示的工艺流程300中的步骤310。根据本发明的一些实施例，TDV 62由均匀的导电材料形成，导电材料可以是包括铜、铝、钨等的金属或金属合金。根据本发明的可选实施例，TDV 62具有复合结构，该复合结构包括由钛、氮化钛、钽、氮化钽等形成的导电阻挡层和在阻挡层上方的含金属材料。根据本发明的一些实施例，形成介电隔离层以环绕每个TDV 62。根据可选实施例，不形成介电隔离层用于环绕TDV 62，并且TDV 62与介电层58物理接触。TDV 62的形成还包括将导电材料沉积到TDV开口60(图9)中，并且实施平坦化以去除介电层58上方的沉积材料的多余部分。
图11示出了接合焊盘66和介电层64的形成，并且接合焊盘66位于介电层64中。相应的步骤被示出为图33所示的工艺流程300中的步骤312。接合焊盘66可以由易于形成混合接合的金属形成。根据本发明的一些实施例，接合焊盘66由铜或铜合金形成。例如，介电层64可以由氧化硅形成。接合焊盘66和介电层64的顶面是共面的。平面度可以通过诸如CMP或机械研磨步骤的平坦化步骤来实现。
在整个说明书中，层22上方的组件总称为中介层100。与基于硅衬底形成的常规中介层不同，中介层100基于介电层58形成。中介层100中没有硅衬底，因此中介层100称为无硅衬底中介层或少Si中介层。TDV 62形成在介电层58中，以代替常规的硅通孔。由于硅衬底是半导体性质的，所以它可能不利地影响电路及在其中和在其上形成的连接件的性能。例如，信号劣化可能由硅衬底引起，并且这种劣化在本发明的实施例中可以避免，因为TDV 62形成在介电层中。
接下来，如图12所示，将第一层器件管芯68A和68B接合到中介层100。相应的步骤被示出为图33所示的工艺流程300中的步骤314。根据本发明的一些实施例，器件管芯68A和68B包括逻辑管芯，逻辑管芯可以是中央处理单元(CPU)管芯、微控制单元(MCU)管芯、输入-输出(IO)管芯、基带(BB)管芯或应用处理器(AP)管芯。器件管芯68A和68B还可以包括存储器管芯。器件管芯68A和68B分别包括可以是硅衬底的半导体衬底70A和70B。硅通孔(TSV)71A和71B(有时称为贯穿半导体通孔或通孔)形成为分别穿透半导体衬底70A和70B，并且用于将形成在半导体衬底70A和70B的前面(所示的底面)的器件和金属线连接到背面。此外，器件管芯68A和68B分别包括用于连接到器件管芯68A和68B中的有源器件和无源器件的互连结构72A和72B。互连结构72A和72B包括金属线和通孔(未示出)。
器件管芯68A包括在器件管芯68A的所示底面处的接合焊盘74A和介电层76A。接合焊盘74A的所示底面与介电层76A的所示底面共面。器件管芯68B包括在所示底面处的接合焊盘74B和介电层76B。接合焊盘74B的所示底面与介电层76B的所示底面共面。
可以通过混合接合来实现接合。例如，接合焊盘74A和74B通过金属对金属直接接合而接合到接合焊盘66。根据本发明的一些实施例，金属对金属直接接合是铜对铜的直接接合。此外，例如，介电层76A和76B通过产生的Si-O-Si键与介电层64接合。混合接合可以包括预接合和退火，使得接合焊盘74A(和74B)中的金属与相应的下方的接合焊盘66中的金属互相扩散。
细间距RDL 56将接合焊盘74A和接合焊盘74B电互连，并且用于器件管芯68A和68B之间的信号通信。细间距RDL 56具有小间距和小宽度。因此，细间距RDL 56的密度高，因此可以形成足够的通信通道用于器件管芯68A和68B之间的直接通信。另一方面，TDV 62提供从器件管芯68A和68B到将接合到中介层100的部件(其可以是封装衬底、印刷电路板(PCB)等)的直接连接。此外，接合焊盘74A/74B和66之间的接合通过接合焊盘而不是通过焊料接头，焊料接头通常比接合焊盘大很多。因此，接合的水平尺寸小，并且可以实现更多的接合以提供足够的通信通道。
参考图13，例如，进行背侧研磨以将器件管芯68A和68B减薄至约15μm和约30μm之间的厚度。相应的步骤被示出为图33所示的工艺流程300中的步骤316。通过减薄，相邻的器件管芯68A和68B之间的间隙78的纵横比减小以实施间隙填充。否则，由于开口78的高纵横比，难以填充间隙。在背面研磨之后，可以露出TSV 71A和71B。可选地，此时不露出TSV 71A和71B。而是可以在图17所示的步骤中露出TSV 71A和71B。
接下来，如图14所示，用间隙填充材料80填充间隙78。相应的步骤被示出为图33所示的工艺流程300中的步骤318。根据本发明的一些实施例，间隙填充材料80包括诸如可以由原硅酸四乙酯(TEOS)形成的氧化硅的氧化物。形成方法可以包括化学气相沉积(CVD)、高密度等离子体化学气相沉积(HDPCVD)等。根据可选实施例，间隙填充材料80由诸如PBO、聚酰亚胺等的聚合物形成。然后实施平坦化步骤以去除间隙填充材料80的多余部分，使得露出器件管芯68A和68B的衬底70A和70B。所得到的结构如图15所示。
图16示出了通孔开口161的形成，通孔开口161在各向异性蚀刻步骤中通过蚀刻穿透间隙填充材料80形成。相应的步骤被示出为图33所示的工艺流程300中的步骤320。一些接合焊盘66暴露于通孔开口161，其中，可以将接合焊盘66用作蚀刻停止层来实施蚀刻。接下来，用导电材料填充通孔开口161以形成TDV 162，如图17所示。相应的步骤被示出为图33所示的工艺流程300中的步骤322。形成工艺包括将导电材料填充到通孔开口161中，然后实施平坦化以去除多余的导电材料。TDV 162的结构可以类似于TDV 62的结构，并且可以包括阻挡层和在阻挡层上方的金属化材料。TDV 162的材料也可以从用于形成TDV 62的类似候选材料中选择。
参考图18，衬底70A和70B被凹进以形成凹槽73，并且TSV 71A和71B的顶端分别稍微突出于衬底70A和70B的顶面上方。相应的步骤被示出为图33所示的工艺流程300中的步骤324。然后用诸如氧化硅的介电材料填充凹槽73以形成介电层75A和75B，并且所得的结构示出在图19中。相应的步骤被示出为图33所示的工艺流程300中的步骤326。形成工艺包括沉积一层毯状介电层的沉积工艺，并且实施平坦化以去除高于TSV 71A和71B的顶端的毯状介电层的部分。
接下来，如图20所示，第二层器件管芯168A和168B接合到器件管芯68A和68B。相应的步骤被示出为图33所示的工艺流程300中的步骤328。根据本发明的一些实施例，器件管芯168A和168B包括逻辑管芯、存储器管芯或它们的组合。器件管芯168A和168B分别包括半导体衬底170A和170B，其可以是诸如硅衬底的半导体衬底。如果在器件管芯168A和168B上方存在第三层器件管芯，则可以在半导体衬底170A和170B中形成TSV(未示出)。可选地，在半导体衬底170A和170B中不形成TSV。此外，器件管芯168A和168B分别包括用于连接到器件管芯168A和168B中的有源器件和无源器件的互连结构172A和172B。互连结构172A和172B包括金属线和通孔(未示出)。
器件管芯168A包括在在器件管芯168A的所示底面处的接合焊盘174A和介电层176A。接合焊盘174A的所示底面与介电层176A的所示底面共面。器件管芯168B包括在所示底面处的接合焊盘174B和介电层176B。接合焊盘174B的所示底面与介电层176B的所示底面共面。
可以通过混合接合来实现接合。例如，接合焊盘174A和174B通过金属对金属直接接合被直接接合到TSV 71A和71B以及TDV 162。根据本发明的一些实施例，金属对金属直接接合是铜对铜的直接接合。此外，介电层176A和176B例如通过产生的Si-O-Si键接合至介电层75A和75B。取决于间隙填充材料80的材料，介电层176A和176B可以接合到间隙填充材料80，或者可以与间隙填充材料80接触但不接合(没有形成接合)。
接下来，与器件管芯68A和68B的减薄相似，可以减薄器件管芯168A和168B。然后如图21所示，用间隙填充材料180填充相邻的器件管芯168A和168B之间的间隙。相应的步骤被示出为图33所示的工艺流程300中的步骤330。根据本发明的一些实施例，使用从用于形成间隙填充材料80的相同候选方法中选择的方法形成间隙填充材料180。间隙填充材料180还可以选自用于形成间隙填充材料80的相同候选材料，并且可以包括氧化物(诸如氧化硅)、PBO、聚酰亚胺等。然后实施平坦化步骤以去除间隙填充材料180的多余部分，使得露出器件管芯168A和168B的衬底170A和170B。
然后例如采用CVD、PECVD、ALD等将介电层182沉积为毯状层。所得到的结构也示出在图21中。相应的步骤被示出为图33所示的工艺流程300中的步骤332。根据本发明的一些实施例，介电层182由诸如氧化硅的氧化物、氮氧化硅等形成。
接下来，参照图22，通过蚀刻介电层182和衬底170A和170B形成沟槽184，使得沟槽184延伸到介电层182和衬底170A和170B中。衬底170A和170B内的沟槽184的部分的深度D1可以大于约1μm，并且可以在约2μm至约5μm之间，这取决于衬底170A和170B的厚度T1。例如，深度D1可以在厚度T1的约20％至约60％之间。应当理解，整个说明书中列举的值是实例，并且可以改变为不同的值。
沟槽184可以以各种图案分布。例如，沟槽184可以形成为离散开口，离散开口可以被分配为具有阵列的图案、蜂窝的图案或其它重复图案。沟槽184的顶视图形状可以是矩形、圆形、六边形等。根据可选实施例，当图22所示的结构在顶视图中观察时，沟槽184可以是在单个方向上具有纵向方向的平行沟槽。沟槽184也可以互连以形成栅格。栅格可以包括彼此平行且均匀或不均匀间隔开的多个第一沟槽，以及彼此平行且均匀或不均匀间隔开的多个第二沟槽。多个第一沟槽和多个第二沟槽彼此截断以形成栅格，并且多个第一沟槽和多个第二沟槽在顶视图中可以彼此垂直或可以不彼此垂直。
然后填充沟槽184以形成接合焊盘187，如图23所示。相应的步骤被示出为图33所示的工艺流程300中的步骤332。应当理解，虽然部件187称为接合焊盘，但是部件187可以是离散焊盘、互连金属线或金属栅格。根据本发明的一些实施例，接合焊盘187由适于混合接合的铜或其它金属形成(由于相对容易扩散)。在填充之后，实施平坦化以使接合焊盘187的顶面和介电层182的顶面平坦。平坦化可以包括CMP或机械研磨。
接下来，如图24所示，空白管芯88接合到器件管芯168A和168B。相应的步骤被示出为图33所示的工艺流程300中的步骤334。空白管芯88包括可以是硅衬底或金属衬底的块状衬底194。当衬底194由金属形成时，可以由铜、铝、不锈钢等形成。当衬底194由硅形成时，在空白管芯88中没有形成有源器件或无源器件。空白管芯88包括两个功能。首先，因为器件管芯68A、68B、168A和168B已被减薄，空白管芯88为下面的结构提供机械支撑，以便允许更好的间隙填充。此外，(衬底194的)硅或金属具有高导热性，因此空白管芯88可以用作散热器。由于图24中的结构的形成是在晶圆级，所以与所示的空白管芯88相同的多个空白管芯也接合到与器件管芯168A和168B相同的各自的下方的器件管芯。
根据可选实施例，代替接合空白管芯88，将第三层器件管芯放置在空白管芯88的位置，并且接合到器件管芯168A和168B。
在衬底194的表面处形成介电层190。例如，介电层190可以由氧化硅或氮氧化硅形成。此外，在介电层190中形成接合焊盘192，并且接合焊盘192的所示底面与介电层190的所示底面共面。接合焊盘192的图案和水平尺寸可以与相应的接合焊盘187的图案和水平尺寸相同或相似，使得接合焊盘192和接合焊盘187可以以一一对应的方式彼此接合。
空白管芯88接合到器件管芯168A和168B之上可以通过混合接合来实现。例如，介电层182和190彼此接合，并且可以形成Si-O-Si键。通过金属对金属直接接合将接合焊盘192接合到相应的接合焊盘187。
有利的是，接合焊盘187通过接触(并且甚至插入到)衬底170A和170B中提供良好的散热路径，使得在器件管芯68A、68B、168A和168B中产生的热量可以易于扩散到块状衬底194中，因此，块状衬底194用作散热器。
参照图25，施加并且图案化光刻胶183。然后使用图案化的光刻胶183作为蚀刻掩模来蚀刻介电层182和间隙填充材料180，以暴露中介层100的一些部分。相应的步骤被示出为图33所示的工艺流程300中的步骤336。根据本发明的一些实施例，露出了诸如器件管芯168B的一些器件管芯。TSV 71B和TDV 162中的一些也可以被暴露。
图26示出了将管芯叠层212接合到第二层结构之上。相应的步骤被示出为图33所示的工艺流程300中的步骤338。管芯叠层212可以接合到TDV162、器件管芯(例如管芯168B)、或者TDV 162和器件管芯的两者。管芯叠层212可以是包括多个堆叠管芯214的存储器叠层，其中，可以在管芯214中形成TSV(未示出)以实施互连。管芯叠层212也可以是高带宽存储器(HBM)数据集。根据本发明的一些实施例，管芯叠层212通过混合接合被接合到下面的结构，其中管芯叠层212中的电连接件216(一些实施例中的接合焊盘)通过金属对金属直接接合接合到TDV 162和TSV71B，并且管芯叠层212的介电层218通过氧化物对氧化物接合(或熔接接合)接合到间隙填充材料80(例如氧化物)和介电层75B。根据可选实施例，电连接件216是焊接区域，并且接合是焊接。根据另外的可选实施例，电连接件216是突出超过管芯叠层212的表面介电层218的微凸块，并且在管芯叠层212和间隙填充材料80和介电层75B之间不发生氧化物对氧化物接合。微凸块216可以通过金属对金属直接接合或焊接与TDV162和TSV 71B接合。
接下来，将间隙填充材料220(图27)填充到空白管芯88和管芯叠层212之间的间隙中。间隙填充材料220可以由诸如氧化硅或聚合物的氧化物形成。然后将形成在载体20上的结构从载体20(图26)脱接合，例如通过将诸如UV光或激光的光投射在释放层22上以分解释放层22。所得到的结构如图27所示。载体20和释放层22从称为复合晶圆102(图27)的覆盖结构去除。相应的步骤被示出为图33所示的工艺流程300中的步骤340。如果需要，可以实施载体互换以在载体20脱接合之前将另一个载体(未示出)附接在所示的结构上方，并且新的载体用于在后续步骤中形成电连接件期间提供机械支撑。
图28A示出了电连接件110的形成，电连接件110可以穿透介电层24并连接到RDL26。电连接件110可以是金属凸块、焊料凸块、金属柱、引线接合或其它适用的连接件。对复合晶圆102实施管芯切割步骤以将复合晶圆102分离成多个封装件104。封装件104彼此相同，并且每个封装件104均可以包括器件管芯和管芯叠层212的两层。相应的步骤被示出为图33所示的工艺流程300中的步骤340。
图28B示出了根据本发明的一些实施例形成的封装件104。这些实施例类似于图28A所示的实施例，除了接合焊盘187穿过介电层182并且不延伸到衬底170A和170B中。根据一些实施例，接合焊盘187与衬底170A和170B接触。根据可选实施例，接合焊盘187和192中的一个或两个从发生接合的界面部分地延伸到相应的介电层182和190中，而不穿透相应的介电层182和190。根据本发明的一些实施例，接合焊盘187和192以及块状衬底194可以电接地，从而为衬底170A和170B提供电接地。
图28C示出了根据本发明的一些实施例形成的封装件。这些实施例类似于图28A和28B所示的实施例，除了不形成接合焊盘187和192以及介电层190(如图28A和28B所示)。块状衬底194(也是空白管芯88)通过熔融接合接合到介电层182。
根据本发明的可选实施例，空白管芯88是金属管芯。因此，图28C中的层182可以由具有高导热性的粘合剂的热界面材料(TIM)形成。
图29和30示出了根据本发明的一些实施例的形成封装件的中间阶段的截面图。除非另有说明，否则这些实施例中的组件的材料和形成方法与类似组件基本上相同，在图1至图28A中示出的实施例中，相同组件由相同的参考标号表示。因此，关于图29和图30中示出的组件的形成工艺和材料的细节可以在图1至图28A中示出的实施例的讨论中找到。图29示出了复合晶圆102的截面图，其与图28A所示的复合晶圆102基本相同，除了在介电层24上形成金属焊盘45，而包括如图28A所示的介电层28、34、38和42以及RDL 32、36、40和44的部件没有形成在载体20上。相反，如图30所示，其示出了在图29所示的步骤之后形成的结构，在载体20(图21)脱接合之后，形成介电层28、34、38和42以及RDL 32、36、40和44。根据这些实施例的用于形成介电层28、34、38和42的顺序相对于图1至图11所示的顺序是相反的。应注意，由于不同的形成顺序，RDL 32、36、40和44的取向与图28A所示的取向相比是相反的(在垂直方向上)。然后通过复合晶圆102的管芯切割形成封装件104。
图31示出了其中嵌入有封装件104(图28A、图28B、图28C和图30)的封装件112。该封装件包括存储数据集114，存储数据集114包括多个堆叠的存储器管芯(未单独示出)。封装件104和存储数据集114封装在封装材料118中，封装材料118可以是模塑料。介电层和RDL(共同示为116)在封装件104和存储数据集114下方并且连接到封装件104和存储数据集114。根据本发明的一些实施例，介电层和RDL 116也可以使用相似的材料形成并且具有与图1至图11所示的结构相似的结构。
图32示出了封装件上封装件(PoP)结构132，其具有与顶部封装件140相接合的集成扇出(InFO)封装件138。集成扇出封装件138还包括嵌入其中的封装件104。封装件104和通孔134封装在封装材料130中，封装材料130可以是模塑料。封装件104接合到统称为146的介电层和RDL。介电层和RDL 146也可以使用相似的材料形成并且具有与图1至图11所示的结构相似的结构。
本发明的实施例具有一些有利的特征。通过采用通常在硅晶圆上使用的工艺(例如镶嵌工艺)来形成中介层的细间距RDL，细间距RDL可以形成为足够薄以提供用于两个或多个器件管芯通信的能力，所有这些通信都是通过细间距RDL。该封装件还提供用于集成存储数据集的解决方案。在中介层中不使用硅衬底，因此避免了由硅衬底导致的电性能方面的劣化。在封装件中还建立了一些散热机制，以实现更好的散热。
在一个实施例中，一种方法包括：形成多个介电层；在所述多个介电层中形成多个再分布线；蚀刻所述多个介电层以形成开口；填充所述开口以形成穿透所述多个介电层的介电通孔；在所述介电通孔和所述多个介电层上方形成介电层；在所述介电层中形成多个接合焊盘；通过混合接合将第一器件管芯接合至所述介电层和所述多个接合焊盘的第一部分；以及将管芯叠层接合至所述第一器件管芯中的硅通孔。在一个实施例中，所述方法还包括：通过混合接合将第二器件管芯接合至所述介电层和所述多个接合焊盘的第二部分，其中，所述多个再分布线将所述第一器件管芯连接至所述第二器件管芯。在一个实施例中，形成所述多个再分布线包括镶嵌工艺。在一个实施例中，所述介电通孔不延伸至任一个半导体衬底。在一个实施例中，所述方法还包括：将附加器件管芯接合至所述第一器件管芯，其中，所述附加器件管芯直接接合至所述第一器件管芯中的硅通孔；形成氧化物层，位于所述附加器件管芯的半导体衬底上方，并且接触所述附加器件管芯的半导体衬底；形成接合焊盘，延伸到所述氧化物层内；以及通过混合接合将空白管芯接合至所述氧化物层和所述接合焊盘。在一个实施例中，所述接合焊盘延伸到所述附加器件管芯的半导体衬底内。在一个实施例中，所述接合焊盘接触而不延伸到所述附加器件管芯的半导体衬底内。
在一个实施例中，一种方法包括：形成多个介电层；在所述多个介电层的每一个中形成多个再分布线；形成穿透所述多个介电层的第一介电通孔和第二介电通孔；在所述多个介电层上方形成介电层；在所述介电层中形成多个接合焊盘并且所述多个接合焊盘电连接至所述第一介电通孔、所述第二介电通孔和所述多个再分布线；通过混合接合将第一器件管芯和第二器件管芯接合至所述介电层和所述多个接合焊盘，其中，所述第一器件管芯通过所述多个再分布线与所述第二器件管芯电互连；以及将管芯叠层接合至所述第二器件管芯。在一个实施例中，使用镶嵌工艺形成所述多个再分布线。在一个实施例中，所述方法还包括：在所述第一器件管芯和所述第二器件管芯的相对侧上填充间隙填充材料；形成穿透所述间隙填充材料的第三介电通孔；将所述第三器件管芯直接接合至所述第三介电通孔，并且与所述第三介电通孔物理接触。在一个实施例中，所述方法还包括形成穿透所述间隙填充材料的第四介电通孔，其中，所述第二器件管芯直接接合至所述第三介电通孔，并且与所述第三介电通孔物理接触，并且所述管芯叠层直接接合至所述第四介电通孔，并且与所述第四介电通孔物理接触。在一个实施例中，形成所述第一介电通孔和所述第二介电通孔包括：蚀刻所述多个介电层以形成第一开口和第二开口；以及用导电材料填充所述第一开口和所述第二开口。在一个实施例中，所述方法还包括：薄化所述第一器件管芯和所述第二器件管芯，以露出所述第一器件管芯和所述第二器件管芯中的硅通孔；以及将第三器件管芯接合至所述硅通孔。在一个实施例中，所述方法还包括在所述第三器件管芯上方形成介电层，以及将块状晶圆接合至所述介电层。
在一个实施例中，一种封装件包括：多个介电层；多个再分布线，在所述多个介电层的每一个中；第一介电通孔，穿透所述多个介电层；多个接合焊盘，在所述第一介电通孔和所述多个再分布线上方，并且连接至所述第一介电通孔和所述多个再分布线；第一介电层，所述多个接合焊盘位于所述第一介电层中；第一器件管芯，通过混合接合接合至所述第一介电层和所述多个接合焊盘的第一部分；间隙填充材料，在所述第一器件管芯的相对侧上；第二介电通孔，穿透所述间隙填充材料；以及管芯叠层，接合至所述第二介电通孔。在一个实施例中，所述封装件还包括第二器件管芯，通过混合接合接合至所述第一介电层和所述多个接合焊盘的第二部分，其中，所述第一器件管芯和所述第二器件管芯通过所述多个再分布线彼此电连接。在一个实施例中，所述封装件还包括：第二器件管芯，位于所述第一器件管芯上方，并且接合至所述第一器件管芯；接合焊盘，与所述第二器件管芯的半导体衬底接触，其中，所述接合焊盘的至少一部分在所述第二器件管芯的半导体衬底上方；第二介电层，所述接合焊盘的至少一部分在所述第二介电层中；以及块状衬底，在所述第二介电层和所述接合焊盘上方并且接合至所述第二介电层和所述接合焊盘。在一个实施例中，所述块状衬底由硅形成，并且在所述块状衬底上没有有源器件和无源器件形成。在一个实施例中，所述接合焊盘进一步延伸至所述第二器件管芯的半导体衬底内。在一个实施例中，所述接合焊盘形成栅格。
在一个实施例中，一种方法包括：在载体上方形成多个介电层，在形成所述多个介电层之后，蚀刻所述多个介电层以形成穿透所述多个介电层的第一开口和第二开口，填充所述第一开口和所述第二开口以形成第一介电通孔和第二介电通孔，将器件管芯接合至所述第一介电通孔上方，并且电连接至所述第一介电通孔，其中，接合所述器件管芯包括混合接合，并且将管芯叠层接合至所述第二介电通孔上方，并且电连接至所述第二介电通孔。在一个实施例中，所述方法还包括在所述多个介电层上方形成介电层，并且在所述介电层中形成接合焊盘，其中，所述接合焊盘与所述第一介电通孔接触，并且所述器件管芯物理接合至所述接合焊盘和所述介电层。在一个实施例中，所述多个介电层包括氧化硅。
在一个实施例中，一种封装件包括多个介电层；穿透所述多个介电层的介电通孔，其中，所述介电通孔具有连续穿透所述多个介电层的边缘；位于所述多个介电层上方的器件管芯，其中，所述器件管芯通过混合接合接合至下面的结构，并且所述器件管芯电连接至所述介电通孔；以及管芯叠层，位于所述器件管芯上方，并且接合至所述器件管芯。在一个实施例中，所述封装件还包括位于所述多个介电层上方的介电层，和在所述介电层中的接合焊盘，其中，所述接合焊盘与所述介电通孔接触，并且所述器件管芯物理接合至所述接合焊盘和所述介电层。在一个实施例中，所述管芯叠层接合至所述器件管芯中的硅通孔。在一个实施例中，所述管芯叠层通过混合接合接合至所述器件管芯。
在一个实施例中，一种封装件包括多个介电层，穿透所述多个介电层的介电通孔，第一器件管芯，位于所述介电通孔上方，并且电连接至所述介电通孔，其中，所述第一器件管芯包括半导体衬底、所述第一器件管芯上方的介电层、所述介电层中的接合焊盘，其中，所述接合焊盘穿透所述介电层并且进一步延伸到所述第一器件管芯的半导体衬底内，以及管芯叠层，位于所述第一器件管芯上方，并且接合至所述第一器件管芯。在一个实施例中，所述管芯叠层通过混合接合接合至所述接合焊盘和所述介电层。在一个实施例中，所述封装件还包括位于所述第一器件管芯和所述介电通孔之间的第二器件管芯。
以上论述了若干实施例的特征，使得本领域技术人员可以更好地理解本公开的各方面。本领域技术人员应该理解，他们可以容易地使用本发明作为基础来设计或修改用于实施与本文所介绍的实施例相同的目的和/或实现相同优点的其他工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，本文中他们可以做出多种变化、替换以及改变。

Claims (20)

1.一种形成封装件的方法，包括：
形成多个介电层；
在所述多个介电层中形成多个再分布线；
蚀刻所述多个介电层以形成开口；
填充所述开口以形成穿透所述多个介电层的介电通孔；
在所述介电通孔和所述多个介电层上方形成第二介电层；
在所述第二介电层中形成多个接合焊盘；
通过混合接合将第一器件管芯接合至所述第二介电层和所述多个接合焊盘的第一部分；以及
将管芯叠层接合至所述第一器件管芯的硅通孔；
将附加器件管芯接合至所述第一器件管芯，其中，所述附加器件管芯直接接合至所述第一器件管芯中的硅通孔；
形成氧化物层，所述氧化物层位于所述附加器件管芯的半导体衬底上方并且接触所述附加器件管芯的半导体衬底；
形成第二接合焊盘，所述第二接合焊盘延伸到所述氧化物层内；以及
通过混合接合将空白管芯接合至所述氧化物层和所述第二接合焊盘，所述空白管芯包括块状衬底并且未形成有有源器件或无源器件。
2.根据权利要求1所述的方法，还包括通过混合接合将第二器件管芯接合至所述第二介电层和所述多个接合焊盘的第二部分，其中，所述多个再分布线将所述第一器件管芯连接至所述第二器件管芯。
3.根据权利要求1所述的方法，其中，形成所述多个再分布线包括镶嵌工艺。
4.根据权利要求1所述的方法，其中，所述介电通孔不延伸至任一个半导体衬底内。
5.根据权利要求1所述的方法，其中，所述附加器件管芯与所述第一器件管芯的重叠部分被所述空白管芯覆盖。
6.根据权利要求1所述的方法，其中，所述第二接合焊盘延伸到所述附加器件管芯的半导体衬底内。
7.根据权利要求1所述的方法，其中，所述第二接合焊盘接触而不延伸到所述附加器件管芯的半导体衬底内。
8.一种形成封装件的方法，包括：
形成多个介电层；
在所述多个介电层的每一个中形成多个再分布线；
形成穿透所述多个介电层的第一介电通孔和第二介电通孔；
在所述多个介电层上方形成第二介电层；
在所述第二介电层中形成多个接合焊盘，并且所述多个接合焊盘电连接至所述第一介电通孔、所述第二介电通孔和所述多个再分布线；
通过混合接合将第一器件管芯和第二器件管芯接合至所述第二介电层和所述多个接合焊盘，其中，所述第一器件管芯通过所述多个再分布线与所述第二器件管芯电互连；以及
将管芯叠层接合至所述第二器件管芯；
将第三器件管芯接合至所述第二器件管芯；
形成氧化物层，所述氧化物层位于所述第三器件管芯的半导体衬底上方并且直接接触所述第三器件管芯的半导体衬底；
形成第二接合焊盘，所述第二接合焊盘延伸到所述氧化物层内；以及
通过混合接合将块状晶圆接合至所述氧化物层和所述第二接合焊盘。
9.根据权利要求8所述的方法，其中，使用镶嵌工艺形成所述多个再分布线。
10.根据权利要求8所述的方法，还包括：
在所述第一器件管芯和所述第二器件管芯的相对侧上填充间隙填充材料；
形成穿透所述间隙填充材料的第三介电通孔；以及
将第三器件管芯直接接合至所述第三介电通孔，并且所述第三器件管芯与所述第三介电通孔物理接触。
11.根据权利要求10所述的方法，还包括形成穿透所述间隙填充材料的第四介电通孔，其中，所述第二器件管芯直接接合至所述第一介电通孔并且与所述第一介电通孔物理接触，并且所述管芯叠层直接接合至所述第四介电通孔并且与所述第四介电通孔物理接触。
12.根据权利要求8所述的方法，其中，形成所述第一介电通孔和所述第二介电通孔包括：
蚀刻所述多个介电层以形成第一开口和第二开口；以及
以导电材料填充所述第一开口和所述第二开口。
13.根据权利要求8所述的方法，还包括：
减薄所述第一器件管芯和所述第二器件管芯，以露出所述第一器件管芯和所述第二器件管芯中的硅通孔；以及
将所述第三器件管芯接合至所述硅通孔。
14.根据权利要求8所述的方法，其中，所述第三器件管芯与所述第二器件管芯的重叠部分被所述块状晶圆覆盖。
15.一种封装件，包括：
多个介电层；
多个再分布线，位于所述多个介电层的每一个中；
第一介电通孔，穿透所述多个介电层；
多个接合焊盘，位于所述第一介电通孔和所述多个再分布线上方，并且连接至所述第一介电通孔和所述多个再分布线；
第一介电层，所述多个接合焊盘位于所述第一介电层中；
第一器件管芯，通过混合接合接合至所述第一介电层和所述多个接合焊盘的第一部分；
间隙填充材料，位于所述第一器件管芯的相对侧上；
第二介电通孔，穿透所述间隙填充材料；以及
管芯叠层，接合至所述第二介电通孔；
第二器件管芯，位于所述第一器件管芯上方，并且接合至所述第一器件管芯；
第二接合焊盘，与所述第二器件管芯的半导体衬底接触；
第二介电层，所述第二接合焊盘的至少一部分位于所述第二介电层中；以及
块状衬底，位于所述第二介电层和所述第二接合焊盘上方并且混合接合至所述第二介电层和所述第二接合焊盘。
16.根据权利要求15所述的封装件，还包括第三器件管芯，通过混合接合接合至所述第一介电层和所述多个接合焊盘的第二部分，其中，所述第一器件管芯和所述第三器件管芯通过所述多个再分布线彼此电连接。
17.根据权利要求15所述的封装件，其中，所述第二接合焊盘的至少一部分位于所述第二器件管芯的半导体衬底上方。
18.根据权利要求15所述的封装件，其中，所述块状衬底由硅形成，并且在所述块状衬底上没有有源器件和无源器件形成。
19.根据权利要求15所述的封装件，其中，所述第二接合焊盘进一步延伸至所述第二器件管芯的半导体衬底内。
20.根据权利要求15所述的封装件，其中，所述第二接合焊盘形成栅格。
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Families Citing this family (45)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11625523B2 (en) 2016-12-14 2023-04-11 iCometrue Company Ltd. Logic drive based on standard commodity FPGA IC chips
TW202404049A (zh) 2016-12-14 2024-01-16 成真股份有限公司 標準大宗商品化現場可編程邏輯閘陣列(fpga)積體電路晶片組成之邏輯驅動器
US10447274B2 (en) 2017-07-11 2019-10-15 iCometrue Company Ltd. Logic drive based on standard commodity FPGA IC chips using non-volatile memory cells
US10957679B2 (en) 2017-08-08 2021-03-23 iCometrue Company Ltd. Logic drive based on standardized commodity programmable logic semiconductor IC chips
US10630296B2 (en) 2017-09-12 2020-04-21 iCometrue Company Ltd. Logic drive with brain-like elasticity and integrality based on standard commodity FPGA IC chips using non-volatile memory cells
US10608642B2 (en) 2018-02-01 2020-03-31 iCometrue Company Ltd. Logic drive using standard commodity programmable logic IC chips comprising non-volatile radom access memory cells
US10623000B2 (en) 2018-02-14 2020-04-14 iCometrue Company Ltd. Logic drive using standard commodity programmable logic IC chips
US10608638B2 (en) 2018-05-24 2020-03-31 iCometrue Company Ltd. Logic drive using standard commodity programmable logic IC chips
US11296706B2 (en) * 2018-06-27 2022-04-05 Intel Corporation Embedded network on chip accessible to programmable logic fabric of programmable logic device in multi-dimensional die systems
KR102534734B1 (ko) * 2018-09-03 2023-05-19 삼성전자 주식회사 반도체 패키지
US11309334B2 (en) 2018-09-11 2022-04-19 iCometrue Company Ltd. Logic drive using standard commodity programmable logic IC chips comprising non-volatile random access memory cells
US10892011B2 (en) 2018-09-11 2021-01-12 iCometrue Company Ltd. Logic drive using standard commodity programmable logic IC chips comprising non-volatile random access memory cells
US10937762B2 (en) 2018-10-04 2021-03-02 iCometrue Company Ltd. Logic drive based on multichip package using interconnection bridge
KR102596758B1 (ko) * 2018-10-24 2023-11-03 삼성전자주식회사 반도체 패키지
KR102538181B1 (ko) 2018-10-24 2023-06-01 삼성전자주식회사 반도체 패키지
US11616046B2 (en) 2018-11-02 2023-03-28 iCometrue Company Ltd. Logic drive based on chip scale package comprising standardized commodity programmable logic IC chip and memory IC chip
US11211334B2 (en) 2018-11-18 2021-12-28 iCometrue Company Ltd. Logic drive based on chip scale package comprising standardized commodity programmable logic IC chip and memory IC chip
JP2020088069A (ja) * 2018-11-20 2020-06-04 凸版印刷株式会社 半導体パッケージ基板およびその製造方法
TWI728561B (zh) * 2018-11-29 2021-05-21 台灣積體電路製造股份有限公司 半導體封裝件以及其製造方法
US11282761B2 (en) 2018-11-29 2022-03-22 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages and methods of manufacturing the same
DE102019128274A1 (de) * 2019-05-30 2020-12-03 Taiwan Semiconductor Manufacturing Co., Ltd. Package-in-Package-gebildetes System
US11189599B2 (en) * 2019-05-30 2021-11-30 Taiwan Semiconductor Manufacturing Company, Ltd. System formed through package-in-package formation
US11562983B2 (en) * 2019-06-28 2023-01-24 Taiwan Semiconductor Manufacturing Company, Ltd. Package having multiple chips integrated therein and manufacturing method thereof
US11227838B2 (en) 2019-07-02 2022-01-18 iCometrue Company Ltd. Logic drive based on multichip package comprising standard commodity FPGA IC chip with cooperating or supporting circuits
US10985154B2 (en) 2019-07-02 2021-04-20 iCometrue Company Ltd. Logic drive based on multichip package comprising standard commodity FPGA IC chip with cryptography circuits
US11094654B2 (en) * 2019-08-02 2021-08-17 Powertech Technology Inc. Package structure and method of manufacturing the same
US11887930B2 (en) 2019-08-05 2024-01-30 iCometrue Company Ltd. Vertical interconnect elevator based on through silicon vias
US11837575B2 (en) 2019-08-26 2023-12-05 Taiwan Semiconductor Manufacturing Company, Ltd. Bonding passive devices on active device dies to form 3D packages
US11637056B2 (en) 2019-09-20 2023-04-25 iCometrue Company Ltd. 3D chip package based on through-silicon-via interconnection elevator
DE102020114141B4 (de) 2019-10-18 2024-03-28 Taiwan Semiconductor Manufacturing Co., Ltd. Integriertes schaltungspackage und verfahren
US11515173B2 (en) * 2019-12-27 2022-11-29 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices and methods of manufacturing
US11282816B2 (en) * 2020-01-17 2022-03-22 Taiwan Semiconductor Manufacturing Company, Ltd. Memory packages and methods of forming same
US11600526B2 (en) 2020-01-22 2023-03-07 iCometrue Company Ltd. Chip package based on through-silicon-via connector and silicon interconnection bridge
US11244939B2 (en) * 2020-03-26 2022-02-08 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method of forming the same
US20210335627A1 (en) * 2020-04-23 2021-10-28 Microchip Technology Incorporated Backside interconnect for integrated circuit package interposer
US11462495B2 (en) 2020-05-21 2022-10-04 Taiwan Semiconductor Manufacturing Co., Ltd. Chiplets 3D SoIC system integration and fabrication methods
DE102020128855A1 (de) * 2020-05-21 2021-11-25 Taiwan Semiconductor Manufacturing Co., Ltd. Chiplets-3d-soic-systemintegrations- und herstellungsverfahren
US11508665B2 (en) * 2020-06-23 2022-11-22 Taiwan Semiconductor Manufacturing Co., Ltd. Packages with thick RDLs and thin RDLs stacked alternatingly
US11469197B2 (en) * 2020-08-26 2022-10-11 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit package and method
US11538760B2 (en) * 2020-12-17 2022-12-27 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and method for manufacturing the same
US11652075B2 (en) * 2021-05-13 2023-05-16 Taiwan Semiconductor Manufacturing Co., Ltd. Honeycomb pattern for conductive features
US20220399294A1 (en) * 2021-06-14 2022-12-15 Intel Corporation Microelectronic assemblies having a hybrid bonded interposer for die-to-die fan-out scaling
US11894293B2 (en) * 2021-07-23 2024-02-06 Advanced Semiconductor Engineering, Inc. Circuit structure and electronic structure
US20230110957A1 (en) * 2021-10-13 2023-04-13 Mediatek Inc. Electronic device with stacked printed circuit boards
WO2023179845A1 (en) * 2022-03-22 2023-09-28 Huawei Digital Power Technologies Co., Ltd. Semiconductor power entity and method for producing such entity by hybrid bonding

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103515305A (zh) * 2012-06-27 2014-01-15 台湾积体电路制造股份有限公司 3d ic堆叠器件及制造方法
CN103579204A (zh) * 2012-07-18 2014-02-12 台湾积体电路制造股份有限公司 包括电容器的封装结构及其形成方法
CN104377192A (zh) * 2013-08-13 2015-02-25 台湾积体电路制造股份有限公司 多芯片结构及其形成方法
US20160013133A1 (en) * 2014-07-14 2016-01-14 Qualcomm Incorporated Air gap between tungsten metal lines for interconnects with reduced rc delay
CN106257658A (zh) * 2015-06-22 2016-12-28 华亚科技股份有限公司 半导体器件
CN106328608A (zh) * 2015-07-02 2017-01-11 台湾积体电路制造股份有限公司 用于芯片封装件的结构和形成方法

Family Cites Families (70)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3973340B2 (ja) 1999-10-05 2007-09-12 Ｎｅｃエレクトロニクス株式会社 半導体装置、配線基板、及び、それらの製造方法
JP2003298232A (ja) 2002-04-02 2003-10-17 Sony Corp 多層配線基板の製造方法および多層配線基板
JP2006253631A (ja) 2005-02-14 2006-09-21 Fujitsu Ltd 半導体装置及びその製造方法、キャパシタ構造体及びその製造方法
US7621041B2 (en) 2005-07-11 2009-11-24 E. I. Du Pont De Nemours And Company Methods for forming multilayer structures
US7514797B2 (en) 2007-05-31 2009-04-07 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-die wafer level packaging
US8759964B2 (en) 2007-07-17 2014-06-24 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer level package structure and fabrication methods
US8227902B2 (en) 2007-11-26 2012-07-24 Taiwan Semiconductor Manufacturing Company, Ltd. Structures for preventing cross-talk between through-silicon vias and integrated circuits
US8674482B2 (en) * 2008-11-18 2014-03-18 Hong Kong Applied Science And Technology Research Institute Co. Ltd. Semiconductor chip with through-silicon-via and sidewall pad
US7825024B2 (en) 2008-11-25 2010-11-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming through-silicon vias
US7858441B2 (en) 2008-12-08 2010-12-28 Stats Chippac, Ltd. Semiconductor package with semiconductor core structure and method of forming same
US8168529B2 (en) * 2009-01-26 2012-05-01 Taiwan Semiconductor Manufacturing Company, Ltd. Forming seal ring in an integrated circuit die
US8552563B2 (en) 2009-04-07 2013-10-08 Taiwan Semiconductor Manufacturing Company, Ltd. Three-dimensional semiconductor architecture
US20110186960A1 (en) 2010-02-03 2011-08-04 Albert Wu Techniques and configurations for recessed semiconductor substrates
WO2011125277A1 (ja) 2010-04-07 2011-10-13 株式会社島津製作所 放射線検出器およびそれを製造する方法
US8546188B2 (en) 2010-04-09 2013-10-01 International Business Machines Corporation Bow-balanced 3D chip stacking
US9048233B2 (en) 2010-05-26 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Package systems having interposers
US8361842B2 (en) 2010-07-30 2013-01-29 Taiwan Semiconductor Manufacturing Company, Ltd. Embedded wafer-level bonding approaches
US8884431B2 (en) 2011-09-09 2014-11-11 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods and structures for semiconductor devices
US9064879B2 (en) 2010-10-14 2015-06-23 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods and structures using a die attach film
US8836137B2 (en) 2012-04-19 2014-09-16 Macronix International Co., Ltd. Method for creating a 3D stacked multichip module
JP5704230B2 (ja) 2011-03-31 2015-04-22 トヨタ自動車株式会社 ベルト式無段変速機
US8829676B2 (en) 2011-06-28 2014-09-09 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structure for wafer level package
US8642385B2 (en) * 2011-08-09 2014-02-04 Alpha & Omega Semiconductor, Inc. Wafer level package structure and the fabrication method thereof
US9000584B2 (en) 2011-12-28 2015-04-07 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor device with a molding compound and a method of forming the same
US8680647B2 (en) 2011-12-29 2014-03-25 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with passive devices and methods of forming the same
US9991190B2 (en) 2012-05-18 2018-06-05 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging with interposer frame
US8703542B2 (en) 2012-05-18 2014-04-22 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer-level packaging mechanisms
US8809996B2 (en) 2012-06-29 2014-08-19 Taiwan Semiconductor Manufacturing Company, Ltd. Package with passive devices and method of forming the same
US9391041B2 (en) * 2012-10-19 2016-07-12 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out wafer level package structure
US8785299B2 (en) 2012-11-30 2014-07-22 Taiwan Semiconductor Manufacturing Company, Ltd. Package with a fan-out structure and method of forming the same
US8803306B1 (en) 2013-01-18 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out package structure and methods for forming the same
US8778738B1 (en) 2013-02-19 2014-07-15 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor devices and packaging devices and methods
US9263511B2 (en) 2013-02-11 2016-02-16 Taiwan Semiconductor Manufacturing Co., Ltd. Package with metal-insulator-metal capacitor and method of manufacturing the same
US9048222B2 (en) 2013-03-06 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating interconnect structure for package-on-package devices
US8946884B2 (en) 2013-03-08 2015-02-03 Xilinx, Inc. Substrate-less interposer technology for a stacked silicon interconnect technology (SSIT) product
US9337073B2 (en) 2013-03-12 2016-05-10 Taiwan Semiconductor Manufacturing Company, Ltd. 3D shielding case and methods for forming the same
US9446467B2 (en) 2013-03-14 2016-09-20 Taiwan Semiconductor Manufacturing Company, Ltd. Integrate rinse module in hybrid bonding platform
US9728453B2 (en) 2013-03-15 2017-08-08 Taiwan Semiconductor Manufacturing Company, Ltd. Methods for hybrid wafer bonding integrated with CMOS processing
US9443796B2 (en) 2013-03-15 2016-09-13 Taiwan Semiconductor Manufacturing Company, Ltd. Air trench in packages incorporating hybrid bonding
US8877554B2 (en) 2013-03-15 2014-11-04 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor devices, methods of packaging semiconductor devices, and PoP devices
US9368460B2 (en) 2013-03-15 2016-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out interconnect structure and method for forming same
US9373434B2 (en) 2013-06-20 2016-06-21 Taiwan Semiconductor Manufacturing Co., Ltd. Inductor assembly and method of using same
US9633869B2 (en) * 2013-08-16 2017-04-25 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with interposers and methods for forming the same
US9257399B2 (en) 2013-10-17 2016-02-09 Taiwan Semiconductor Manufacturing Company, Ltd. 3D integrated circuit and methods of forming the same
US9184128B2 (en) 2013-12-13 2015-11-10 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC package and methods of forming the same
US9425150B2 (en) 2014-02-13 2016-08-23 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-via interconnect structure and method of manufacture
US9583460B2 (en) 2014-02-14 2017-02-28 Qualcomm Incorporated Integrated device comprising stacked dies on redistribution layers
US9735129B2 (en) 2014-03-21 2017-08-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages and methods of forming the same
US9666520B2 (en) 2014-04-30 2017-05-30 Taiwan Semiconductor Manufactuing Company, Ltd. 3D stacked-chip package
US9711379B2 (en) 2014-04-30 2017-07-18 Taiwan Semiconductor Manufacturing Company, Ltd. 3D stacked-chip package
US9331021B2 (en) 2014-04-30 2016-05-03 Taiwan Semiconductor Manufacturing Company, Ltd. Chip-on-wafer package and method of forming same
US9418877B2 (en) 2014-05-05 2016-08-16 Qualcomm Incorporated Integrated device comprising high density interconnects in inorganic layers and redistribution layers in organic layers
US20150340305A1 (en) * 2014-05-20 2015-11-26 Freescale Semiconductor, Inc. Stacked die package with redistribution layer
US9385110B2 (en) * 2014-06-18 2016-07-05 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
US9449914B2 (en) 2014-07-17 2016-09-20 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked integrated circuits with redistribution lines
US9515035B2 (en) * 2014-12-19 2016-12-06 International Business Machines Corporation Three-dimensional integrated circuit integration
US10319701B2 (en) * 2015-01-07 2019-06-11 Taiwan Semiconductor Manufacturing Company, Ltd. Bonded 3D integrated circuit (3DIC) structure
US10032704B2 (en) 2015-02-13 2018-07-24 Taiwan Semiconductor Manufacturing Company, Ltd. Reducing cracking by adjusting opening size in pop packages
US9461110B1 (en) * 2015-04-30 2016-10-04 Taiwan Semiconductor Manufacturing Company, Ltd. FETs and methods of forming FETs
US9666523B2 (en) * 2015-07-24 2017-05-30 Nxp Usa, Inc. Semiconductor wafers with through substrate vias and back metal, and methods of fabrication thereof
US11018025B2 (en) 2015-07-31 2021-05-25 Taiwan Semiconductor Manufacturing Company, Ltd. Redistribution lines having stacking vias
US9691743B2 (en) * 2015-09-21 2017-06-27 Nxp Usa, Inc. Localized redistribution layer structure for embedded component package and method
KR101787832B1 (ko) * 2015-10-22 2017-10-19 앰코 테크놀로지 코리아 주식회사 반도체 패키지 제조 방법 및 이를 이용한 반도체 패키지
WO2017096167A1 (en) 2015-12-02 2017-06-08 Multek Technologies Limited Pcb hybrid redistribution layer
US9893042B2 (en) 2015-12-14 2018-02-13 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
US9818726B2 (en) * 2015-12-28 2017-11-14 International Business Machines Corporation Chip stack cooling structure
US9773757B2 (en) 2016-01-19 2017-09-26 Taiwan Semiconductor Manufacturing Company, Ltd. Devices, packaged semiconductor devices, and semiconductor device packaging methods
KR102579880B1 (ko) * 2016-05-12 2023-09-18 삼성전자주식회사 인터포저, 반도체 패키지, 및 인터포저의 제조 방법
TWM531651U (zh) 2016-05-17 2016-11-01 zhi-xiong Li 無基板中介層及應用彼之半導體裝置
KR102570582B1 (ko) * 2016-06-30 2023-08-24 삼성전자 주식회사 반도체 패키지 및 그 제조 방법

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103515305A (zh) * 2012-06-27 2014-01-15 台湾积体电路制造股份有限公司 3d ic堆叠器件及制造方法
CN103579204A (zh) * 2012-07-18 2014-02-12 台湾积体电路制造股份有限公司 包括电容器的封装结构及其形成方法
CN104377192A (zh) * 2013-08-13 2015-02-25 台湾积体电路制造股份有限公司 多芯片结构及其形成方法
US20160013133A1 (en) * 2014-07-14 2016-01-14 Qualcomm Incorporated Air gap between tungsten metal lines for interconnects with reduced rc delay
CN106257658A (zh) * 2015-06-22 2016-12-28 华亚科技股份有限公司 半导体器件
CN106328608A (zh) * 2015-07-02 2017-01-11 台湾积体电路制造股份有限公司 用于芯片封装件的结构和形成方法

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US11469166B2 (en) 2022-10-11
CN108695176A (zh) 2018-10-23
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US20200381346A1 (en) 2020-12-03
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