TWI681476B - 具有無矽基底插板的封裝及其形成方法 - Google Patents

具有無矽基底插板的封裝及其形成方法 Download PDF

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TWI681476B
TWI681476B TW106135557A TW106135557A TWI681476B TW I681476 B TWI681476 B TW I681476B TW 106135557 A TW106135557 A TW 106135557A TW 106135557 A TW106135557 A TW 106135557A TW I681476 B TWI681476 B TW I681476B
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dielectric layer
device die
bonding
dielectric
die
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TW106135557A
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TW201842598A (zh
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陳明發
余振華
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台灣積體電路製造股份有限公司
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Abstract

一種方法包括：形成多個介電層；在所述多個介電層中形成多個重佈線線路；對所述多個介電層進行蝕刻以形成開口；填充所述開口以形成貫穿介電層孔，所述貫穿介電層孔穿透所述多個介電層；在所述貫穿介電層孔以及所述多個介電層上形成介電層；在所述介電層中形成多個接合墊；藉由混合接合將裝置晶粒接合至所述介電層以及所述多個接合墊的第一部分；且將晶粒堆疊接合至裝置晶粒中的矽貫穿孔。

Description

具有無矽基底插板的封裝及其形成方法
本發明實施例是有關於一種封裝，且特別是有關於一種具有無矽基底插板的封裝及形成所述封裝的方法。
積體電路的封裝正變得日益複雜，其中在相同封裝中封裝更多裝置晶粒以達成更多功能。舉例而言，封裝可包括多個裝置晶粒，例如接合至同一插板的多個處理器及記憶體管。所述插板可基於半導體基底而形成所述插板，其中在所述半導體基底中形成多個矽貫穿孔以使形成於插板的相對側上的特徵互連。裝置晶粒包封於模製化合物中。包括插板的封裝及裝置晶粒進一步接合至封裝基底。此外，表面安裝裝置亦可接合至基底。散熱器可貼合至裝置晶粒的頂表面，以便消散在裝置晶粒中產生的熱量。所述散熱器可具有固定至所述封裝基底上的緣擺部分。
本發明實施例提供一種封裝的形成方法包括：形成多個 介電層；在所述多個介電層中形成多個重佈線線路；對所述多個介電層進行蝕刻以形成開口；填充所述開口以形成穿透所述多個介電層的貫穿介電層孔；在所述貫穿介電層孔以及所述多個介電層上形成介電層；在所述介電層中形成多個接合墊；藉由混合接合將第一裝置晶粒接合至所述介電層以及所述多個接合墊的第一部分；以及將晶粒堆疊接合至所述第一裝置晶粒中的矽貫穿孔。
本發明實施例提供一種封裝，包括：多個介電層；多個重佈線線路，分別位於所述多個介電層中；第一貫穿介電層孔，穿透所述多個介電層；多個接合墊，位於所述第一貫穿介電層孔及所述多個重佈線線路上，且連接至所述第一貫穿介電層孔及所述多個重佈線線路；第一介電層，所述多個接合墊位於所述第一介電層中；第一裝置晶粒，藉由混合接合使所述第一裝置晶粒接合至所述第一介電層以及所述多個接合墊的第一部分；間隙填充材料，位於所述第一裝置晶粒的相對側上；第二貫穿介電層孔，穿透所述間隙填充材料；以及晶粒堆疊，接合至所述第二貫穿介電層孔。
20‧‧‧載板
22‧‧‧釋放層
24、28、34、46、48、50A、50B、50C、54A、54B、54C、 58、64、75A、75B、76A、76B、176A、176B、182、190‧‧‧介電層
26、32、36、40、44‧‧‧重佈線線路
30、210‧‧‧開口
38、42‧‧‧鈍化層
45‧‧‧金屬墊
52A、52B、52C‧‧‧蝕刻終止層
56、56A、56B、56C‧‧‧小間距重佈線線路
60‧‧‧貫穿介電層孔開口
62、162‧‧‧貫穿介電層孔
66、74A、74B、174A、174B、187、192‧‧‧接合墊
68A、68B、168A、168B‧‧‧裝置晶粒
70A、70B、170A、170B‧‧‧半導體基底
71A、71B‧‧‧矽貫穿孔
72A、72B、172A、172B‧‧‧內連結構
73‧‧‧凹槽
78‧‧‧間隙
80、180、220‧‧‧間隙填充材料
88‧‧‧空白晶粒
100‧‧‧插板
102‧‧‧複合晶圓
104、112‧‧‧封裝
110‧‧‧電連接器
114‧‧‧記憶體管
116、146‧‧‧疊層
118、130‧‧‧密封材料
132‧‧‧層疊式封裝(PoP)結構
134‧‧‧貫穿孔
138‧‧‧積體扇出型(InFO)封裝
140‧‧‧頂部封裝
161‧‧‧通孔開口
183‧‧‧光阻
184‧‧‧溝渠
194‧‧‧塊狀基底
212‧‧‧晶粒堆疊
214‧‧‧晶粒
300‧‧‧製造流程
302、304、306、308、310、312、314、316、318、320、322、324、326、328、330、332、334、336、338、340‧‧‧步驟
D1‧‧‧深度
T1‧‧‧厚度
接合附圖閱讀以下詳細說明，會最佳地理解本發明實施例的各個態樣。應注意的是，根據本行業中的標準慣例，各種特徵並非按比例繪製。事實上，為論述清晰起見，可任意增大或減小各種特徵的尺寸。
圖1至圖28A為根據一些實施例形成無矽基底(無矽)封裝的形成過程中的各中間階段的剖面圖。
圖28B至圖28C為根據一些實施例具有無矽封裝的一些封裝的剖視圖。
圖29以及圖30為根據一些實施例的無矽封裝的形成過程中的各中間階段的剖視圖。
圖31以及圖32為根據一些實施例嵌入無矽封裝的一些封裝的剖視圖。
圖33為根據一些實施例形成封裝的製造流程圖。
以下揭露內容提供用於實作本發明實施例的不同特徵的諸多不同的實施例或實例。以下闡述組件及排列的具體實例以簡化本揭露內容。當然，該些僅為實例且不旨在進行限制。舉例而言，以下說明中將第一特徵形成於第二特徵「之上」或第二特徵「上」可包括其中第一特徵及第二特徵被形成為直接接觸的實施例，且亦可包括其中第一特徵與第二特徵之間可形成有附加特徵、進而使得所述第一特徵與所述第二特徵可能不直接接觸的實施例。另外，本發明實施例可能在各種實例中重複使用參考編號及/或字母。此種重複使用是出於簡潔及清晰的目的，但自身並不表示所論述的各種實施例及/或配置之間的關係。
另外，為了易於描述圖中所示的一個元件或特徵與另一 元件或特徵的關係，本文中可使用例如「在...下」、「在...下方」、「下部」、「上覆」、及「上部」等空間相對用語。除了圖中所繪示的取向之外，所述空間相對用語亦旨在涵蓋裝置在使用或操作時的不同取向。設備可被另外取向(旋轉90度或在其他取向)，而本文所用的空間相對描述語可同樣相應地作出解釋。
根據各種示例性實施例提供一種基於無矽基底(無矽；Si-less)插板所形成的封裝及形成所述封裝的方法。根據一些實施例說明形成所述封裝的中間階段。對一些實施例的一些變型進行論述。在各個圖中及說明性實施例通篇中，相同標號將用以表示相同的元件。
圖1至圖28A為根據一些實施例封裝的形成過程中的各中間階段的剖面圖。在圖1至圖28A中所表示的步驟亦會在圖33中所示的製造流程300中進行示意性地反映。
圖1顯示了載板20及形成於載板20上的釋放層22。載板20可為玻璃載板、矽晶圓、有機載板等。載板20可具有圓形的俯視形狀，且可具有常見於矽晶圓的大小。舉例而言，載板20可具有8英吋的直徑、12英吋的直徑等。釋放層22可由聚合物類材料(例如，光熱轉換(Light To Heat Conversion，LTHC)材料)形成，其可與載板20一起從將在後續步驟中形成的上覆結構被移除。根據本發明的一些實施例，釋放層22是由環氧樹脂系熱釋放材料形成。可將釋放層22塗佈至載板20上。釋放層22的頂表面被整平且具有高共面程度(high degree of co-planarity)。
在釋放層22上形成介電層24。根據本發明的一些實施例，介電層24是由聚合物所形成，所述聚合物亦可為可利用微影製程輕易地進行圖案化的感光性材料，例如聚苯並噁唑(polybenzoxazole，PBO)、聚醯亞胺、苯並環丁烯(benzocyclobutene，BCB)等。
在介電層24上形成重佈線線路(Redistribution Lines；RDLs)26。形成重佈線線路26可包括在介電層24上形成晶種層(圖中未示出)，在所述晶種層(seed layer)之上形成例如光阻等經圖案化的罩幕(圖中未示出)，且接著在被暴露出的晶種層上執行金屬鍍覆。然後，移除經圖案化的罩幕以及被經圖案化的罩幕所覆蓋的晶種層的一部分，從而留下如圖1所示的重佈線線路26。根據本發明的一些實施例中，晶種層包括鈦層及位於所述鈦層之上的銅層。可使用例如物理氣相沉積(physical vapor deposition，PVD)等來形成所述晶種層。可使用例如無電鍍覆來執行所述鍍覆。
進一步參照圖1，在重佈線線路26上形成介電層28。介電層28的底表面與重佈線線路26的頂表面以及介電層24的頂表面接觸。根據本發明的一些實施例，介電層28是由聚合物形成，所述聚合物可為例如聚苯並噁唑(PBO)、聚醯亞胺、苯並環丁烯(BCB)等感光性材料。接著，對介電層28進行圖案化，以在其中形成開口30。因此，重佈線線路26的一些部分經由介電層28中的開口30而被暴露出。
接下來，請參照圖2，形成重佈線線路32以連接至重佈線線路26。所述重佈線線路32包括位於介電層28之上的金屬跡線(金屬線)。重佈線線路32亦包括延伸至介電層28中的開口中的通孔。重佈線線路32亦是在電鍍製程中形成，其中重佈線線路32中的每一者包括晶種層(圖中未示出)及位於晶種層之上的鍍覆金屬性材料。晶種層及鍍覆材料可由相同材料或不同材料形成。重佈線線路32可包括金屬或金屬合金，所述金屬或金屬合金包括鋁、銅、鎢、及其合金。用於形成介電層28及34以及重佈線線路32及36的步驟做為步驟302表示於如圖33所示的製造流程300中。
請參照圖3，在重佈線線路32及介電層28之上形成介電層34。介電層34可使用聚合物而形成，所述聚合物可選自與介電層28相同的候選材料。舉例而言，可由聚苯並噁唑、聚醯亞胺、苯並環丁烯等來形成介電層34。做為另一選擇，介電層34可包括例如氧化矽、氮化矽、碳化矽、氮氧化矽等無機介電材料。
圖3進一步顯示形成電性連接至重佈線線路32的重佈線線路36。重佈線線路36的形成可採用與形成重佈線線路32類似的方法及材料。應理解的是，儘管在所說明的示例性實施例中論述了兩個聚合物層28及34及在其中形成的相應重佈線線路32及36，但可根據佈線要求及使用聚合物來緩衝應力的要求而採用更少或更多的介電層。舉例而言，可存在有單個聚合物層或三個、四個、或更多個聚合物層。
圖4顯示鈍化層38與42以及重佈線線路40與44的形成。相應的步驟做為步驟304說明於如圖33中所示製造流程300中。根據本發明的一些實施例，鈍化層38及42是由例如以下無機材料形成的：氧化矽、氮化矽、碳化矽、氮氧化矽、矽氧碳氮化物、未經摻雜的矽酸鹽玻璃(Un-doped Silicate Glass，USG)、或上述多個層。鈍化層38及42中的每一者可為單層或複合層，且可由無孔性材料(non-porous material)所形成。根據本發明的一些實施例，鈍化層38及42中的一者或鈍化層38及42二者為複合層，所述複合層包括氧化矽層(圖中未單獨示出)及位於所述氧化矽層之上的氮化矽層(圖中未單獨示出)。鈍化層38及42具有阻擋濕氣以及有害化學物質接近封裝中的導電特徵(例如，小間距重佈線線路(fine-pitch RDL))的功能，如將在隨後的段落中進行論述。
重佈線線路40及44可由鋁、銅、鋁銅、鎳、或其合金形成。根據一些實施例，重佈線線路44的一些部分被形成為足夠大的金屬墊，以供後續形成的貫穿介電層孔(Through-Dielectric Via，TDV)形成於其上方，如圖11所示。該些金屬墊根據一些實施例被相應地稱為金屬墊44或鋁墊44。此外，鈍化層的數目可為任意整數，例如為一個、兩個(如圖所示)、三個、或更多個。
圖5顯示出一個或多個介電層的形成。舉例而言，如圖所示，可形成介電層46以將頂部重佈線線路44嵌置於其中。在介電層46之上形成介電層48，且介電層48可充當蝕刻終止層。 根據本發明的一些實施例，亦可以由單個介電層來替代介電層46及48。可用於介電層46及48的材料包括氧化矽、氮化矽、碳化矽、氮氧化矽等。
圖6、圖7、及圖8顯示了根據本發明一些實施例介電層及小間距重佈線線路的形成。相應步驟做為步驟306說明於如圖33中所示製造流程300中。所述形成方法可採用用在基於矽基底形成裝置晶粒的內連結構的方法。舉例而言，內連結構的形成方法可包括單鑲嵌製程及/或雙鑲嵌製程。據此，所得到的重佈線線路可另外被稱為金屬線及通孔，且對應的介電層可另外被稱為金屬間介電層(Inter-Metal-Dielectric，IMD)。
參照圖6，形成介電層50A與54A、以及蝕刻終止層52A。介電層50A及54A可由氧化矽、氮氧化矽、氮化矽等、或介電常數值低於約3.0的低介電常數介電材料所形成。低介電常數介電材料可包括黑金剛石(Black Diamond)(應用材料公司(Applied Materials)的註冊商標)、含碳低介電常數介電材料、氫矽倍半氧烷(Hydrogen SilsesQuioxane，HSQ)、甲基矽倍半氧烷(MethylSilsesQuioxane，MSQ)等。蝕刻終止層52A是由相對於介電層50A及54A具有高蝕刻選擇性的材料所形成，且可由碳化矽、矽碳氮化物等所形成。根據替代性實施例，並未形成蝕刻終止層52A。
小間距重佈線線路56A是形成在蝕刻終止層52A及介電層54A中以用於進行佈線。應理解的是，所說明的單個小間距重 佈線線路56A代表多個小間距重佈線線路。由於根據本發明一些實施例的小間距重佈線線路是利用鑲嵌製程形成的，因此其可以被形成為極薄，且小於例如0.8微米的間距(自結構的頂部觀察)。如此，能夠顯著提高小間距重佈線線路的密度及佈線能力。根據本發明的一些實施例，小間距重佈線線路56A是利用單鑲嵌製程形成，所述單鑲嵌製程包括蝕刻介電層54A及蝕刻終止層52A以形成溝渠，使用導電材料填充所述溝渠，以及執行平坦化(例如，透過化學機械研磨(Chemical Mechanical Polish，CMP)或機械磨削)以移除導電材料的位於介電層54A之上的部分。
根據本發明的一些實施例，用於形成小間距重佈線線路56A的導電材料是均質材料(homogenous material)。根據本發明的其他實施例，所述導電材料是包括阻障層及位於所述阻障層之上的含銅材料(其可為銅或銅合金)的複合材料，所述阻障層由鈦、氮化鈦、鉭、氮化鉭等形成。小間距重佈線線路56A亦可由雙鑲嵌製程形成，以使得可在一些小間距重佈線線路56A之下形成一些通孔，且所述通孔可用於將小間距重佈線線路56A連接至重佈線線路44。
圖7顯示了介電層50B及54B以及蝕刻終止層52B的形成。介電層50B及54B的材料可選自與用於形成介電層50A及54A相同的候選材料，且蝕刻終止層52B的材料可選自與用於形成蝕刻終止層52A相同的候選材料。
小間距重佈線線路56B亦會在介電層50B、52B以及54B 中形成。小間距重佈線線路56B包括形成於介電層54B及52B中的金屬線、以及形成於介電層50B中的通孔。所述形成可包括雙鑲嵌製程，所述雙鑲嵌製程包括：在介電層54B及52B中形成溝渠以及在介電層50B中形成通孔開口，填充導電材料，並且接著執行平坦化，例如機械磨削或化學機械研磨(CMP)。類似地，小間距重佈線線路56B可由均質材料形成，或可由包括阻障層及位於阻障層之上的含銅材料的複合材料所形成。
圖8顯示了介電層50C與54C及蝕刻終止層52C、以及小間距重佈線線路56C的形成。所述形成方法及材料可類似於位於其下方的相應層面，因此本文中不再對其予以贅述。此外，可根據一些實施例省略蝕刻終止層52A、52B及52C，且可利用時間模式(time-mode)執行用於形成溝渠的對應蝕刻，以控制溝渠的深度。應理解的是，可形成更多的介電層及小間距重佈線線路層。此外，即使可跳過蝕刻終止層52A、52B、及52C中的一些或全部，由於小間距重佈線線路所處的介電層是在不同的製程中形成，因此在用於形成小間距重佈線線路56A、56B、及56C的介電層之間仍可存在可區分的界面，而無論這些介電層是由相同的介電材料還是不同的介電材料所形成。在後續的段落中，為了簡潔辨識，介電層50A、52A、54A、50B、52B、54B、50C、52C、及54C被共同地且個別地稱為介電層58。小間距重佈線線路56A、56B、及56C亦被共同地且個別地稱為小間距重佈線線路56。
參照圖9，是對介電層48及58進行蝕刻以形成貫穿介電 層孔(TDV)開口60。相應步驟做為步驟308說明於如圖33中所示的製造流程300中。金屬墊44由貫穿介電層孔開口60所暴露出。在從圖9所示結構的頂部觀察時，通孔開口60可對準至環以包圍其中形成有小間距重佈線線路56的區域。通孔開口60的俯視圖形狀可為矩形、圓形、六邊形等。
接著，以導電材料填充貫穿介電層孔開口60以形成貫穿介電層孔62，且所得結構示出於圖10中。相應步驟做為步驟310說明於如圖33中所示的製造流程300中。根據本發明的一些實施例，貫穿介電層孔62是由均質導電材料形成，所述均質導電材料可為包括銅、鋁、鎢等的金屬或金屬合金。根據本發明的替代性實施例，貫穿介電層孔62具有包括導電阻障層及位於所述阻障層之上的含金屬材料的複合結構，所述導電阻障層是由鈦、氮化鈦、鉭、氮化鉭等所形成。根據本發明的一些實施例，形成介電隔離層以包圍貫穿介電層孔62中的每一者。根據替代性實施例，不形成介電隔離層來包圍貫穿介電層孔62，且貫穿介電層孔62與介電層58物理接觸。形成貫穿介電層孔62亦包括將導電材料沉積至貫穿介電層孔開口60中(圖9)，以及執行平坦化以移除所沉積材料的位於介電層58上的多餘部分。
圖11顯示接合墊66及介電層64的形成，且接合墊66位於介電層64中。相應步驟做為步驟312說明於如圖33中所示的製造流程300中。接合墊66可由易於形成混合接合的金屬形成。根據本發明的一些實施例，接合墊66是由銅或銅合金所形成。 介電層64可例如由氧化矽形成。接合墊66的頂表面與介電層64的頂表面是共平面的。所述平面性可例如藉由平坦化步驟(例如，化學機械研磨或機械磨削步驟)達成。
在通篇的說明中，位於層面22之上的組件相結合地被稱為插板(interposer)100。插板100與基於矽基底而形成的傳統插板不同，其是基於介電層58而形成。插板100中不存在矽基底，因此，插板100被稱為無矽基底插板或無矽插板(Si-less interposer)。貫穿介電層孔62是形成於介電層58中以替代傳統矽貫穿孔。由於矽基底是半導電的，因此其可對形成於其中及其上的電路及連接的效能產生不利影響。舉例而言，存在由矽基底導致的訊號劣化，且在本發明的實施例中可避免此種劣化，乃因於貫穿介電層孔62是形成於介電層中。
接著，如圖12所示，將第一層裝置晶粒68A及68B接合至插板100。相應步驟做為步驟314說明於如圖33中所示的製造流程300中。根據本發明的一些實施例，裝置晶粒68A及68B可包括邏輯晶粒，所述邏輯晶粒可為中央處理單元(Central Processing Unit，CPU)晶粒、微控制單元(Micro Control Unit，MCU)晶粒、輸入-輸出(input-output，IO)晶粒、基帶(BaseBand，BB)晶粒、或應用處理器(Application processor，AP)晶粒。裝置晶粒68A及68B亦可包括記憶體晶粒。裝置晶粒68A及68B分別包括可為矽基底的半導體基底70A及70B。矽貫穿孔(Through-Silicon Vias；TSV)71A及71B亦稱之為半導體貫穿孔 (through-semiconductor vias)或是貫穿孔(through-vias)，其是分別穿透半導體基底70A及70B而形成，且其是用於將形成於半導體基底70A及70B前側(所繪示的底側)的裝置及金屬線連接至背面側。此外，裝置晶粒68A及68B分別包括內連結構72A及72B，用於連接至裝置晶粒68A及68B中的主動元件及被動元件。內連結構72A及72B包括金屬線及通孔(圖中未示出)。
裝置晶粒68A包括位於裝置晶粒68A的所示底表面處的接合墊74A及介電層76A。接合墊74A的所示底表面與介電層76A的所示底表面為共平面。裝置晶粒68B包括位於所示底表面處的接合墊74B及介電層76B。接合墊74B的所示底表面與介電層76B的所示底表面為共平面。
所述接合可藉由混合接合達成。舉例而言，接合墊74A及74B是藉由金屬至金屬直接接合(metal-to-metal direct bonding)而接合至接合墊66。根據本發明的一些實施例，所述金屬至金屬直接結合是銅至銅直接結合。此外，介電層76A及76B例如利用所產生的Si-O-Si鍵而接合至介電層64。所述混合接合可包括預先接合及退火，以使得接合墊74A(及74B)中的金屬與位於下方的相應接合墊66中的金屬互擴散。
小間距重佈線線路56是與接合墊74A及接合墊74B電性內連，並且是用於裝置晶粒68A與裝置晶粒68B之間的訊號通訊。小間距重佈線線路56具有小的間距及小的寬度。因此，小間距重佈線線路56的密度高，且因此可形成足夠的通訊通道以用於裝置 晶粒68A與裝置晶粒68B之間的直接通訊。另一方面，貫穿介電層孔62提供從裝置晶粒68A及68B至將接合至插板100的組件(其可為封裝基底、印刷電路板(Printed Circuit Board，PCB)等)的直接連接。此外，接合墊74A/74B與接合墊66之間的接合是藉由接合墊而非藉由通常較接合墊大得多的焊接接頭(solder joint)。因此，接合具有較小的水平尺寸，且可實作更多接合以提供足夠的通訊通道。
參照圖13，執行背面磨削以將裝置晶粒68A及68B薄化至例如介於約15微米與約30微米之間的厚度。相應步驟做為步驟316說明於如圖33中所示的製造流程300中。藉由所述薄化，相鄰裝置晶粒68A與68B之間的間隙78的寬高比會減小，以便執行間隙填充。否則，由於開口78存在有較高的寬高比，間隙填充將難以進行。在進行背面磨削之後，可以暴露出矽貫穿孔71A及71B。做為另一種選擇，矽貫穿孔71A及71B在此時並未暴露出。取而代之，矽貫穿孔71A及71B可以在圖17所示的步驟中被暴露出。
接著，如圖14所示，運用間隙填充材料80填充間隙78。相應步驟做為步驟318說明於如圖33中所示的製造流程300中。根據本發明的一些實施例，間隙填充材料80包含可由正矽酸四乙酯(tetraethyl orthosilicate；TEOS)所形成的氧化物，例如氧化矽。所述形成方法可包括化學氣相沉積(Chemical Vapor Deposition，CVD)、高密度電漿化學氣相沉積(High-Density Plasma Chemical Vapor Deposition，HDPCVD)等。根據替代性實施例，間隙填充材料80是由例如聚苯並噁唑、聚醯亞胺等聚合物所形成。接著，執行平坦化步驟以移除間隙填充材料80的多餘部分，以使得顯露出裝置晶粒68A及68B的基底70A及70B。在圖15中示出了所得結構。
圖16顯示出通孔開口161的形成，其是透過異向性蝕刻步驟對間隙填充材料80進行蝕刻而成。相應步驟做為步驟320說明於如圖33中所示的製造流程300中。一些接合墊66是被通孔開口161所暴露出，其中可以使用接合墊66做為蝕刻蝕刻終止層以進行蝕刻。接著，如圖17所示，在通孔開口161中填充導電材料以形成貫穿介電層孔162。相應步驟做為步驟322說明於如圖33中所示的製造流程300中。所述形成步驟包括在通孔開口161中填充導電材料，接著進行平坦化以移除多餘的導電材料。貫穿介電層孔162可以具有與貫穿介電層孔62類似的結構，且可以包括阻障層及位於所述阻障層之上的金屬材料。貫穿介電層孔162的材料亦可選自與貫穿介電層孔62類似的候選材料。
參照圖18，使基底70A及70B凹陷以形成凹槽73，且矽貫穿孔71A及71B的頂端分別在基底70A及70B的頂表面上方些微突出。相應步驟做為步驟324說明於如圖33中所示的製造流程300中。接著，在凹槽73填充如氧化矽的介電材料以形成介電層75A及75B，圖19中示出了所得結構。相應步驟做為步驟326說明於如圖33中所示的製造流程300中。所述形成步驟包括沉積一 層覆蓋性介電層的沉積步驟，以及進行平坦化以移除覆蓋性介電層中高於矽貫穿孔71A及71B的頂端的部分。
接著，如圖20所示，將第二層裝置晶粒168A及168B接合至裝置晶粒68A及68B。相應步驟做為步驟328說明於如圖33中所示的製造流程300中。在本發明的一些實施例中，裝置晶粒168A及168B包括邏輯晶粒、記憶體晶粒，或是上述的組合。裝置晶粒168A及168B分別具有半導體基底170A及170B，且可例如為矽基底的半導體基底。如果在裝置晶粒168A及168B上接合有第三層裝置晶粒，則矽貫穿孔(圖中未示出)可形成在半導體基底170A及170B中。做為另一種選擇，矽貫穿孔不形於半導體基底170A及170B中。另外，裝置晶粒168A及168B包括內連結構172A及172B，其分別用以連接至裝置晶粒168A及168B中的主動元件及被動元件。內連結構172A及172B包括金屬線以及通孔(圖中未示出)。
裝置晶粒168A包括位於裝置晶粒168A的所示底表面處的接合墊174A及介電層176A。接合墊174A的所示底表面與介電層176A的所示底表面為共平面。裝置晶粒168B包括位於所示底表面處的接合墊174B及介電層176B。接合墊174B的所示底表面與介電層176B的所示底表面為共平面。
所述接合可藉由混合接合達成。舉例而言，接合墊174A及174B是藉由金屬至金屬直接接合(metal-to-metal direct bonding)而直接接合至矽貫穿孔71A與71B以及貫穿介電層孔 162。根據本發明的一些實施例，所述金屬至金屬直接結合是銅至銅直接結合。此外，介電層176A及176B例如利用所產生的Si-O-Si鍵而接合至介電層75A及75B。取決於間隙填充材料80的材料，介電層176A及176B可接合至間隙填充材料80，又或是可以與間隙填充材料80接觸但不與其接合(沒有形成接合)。
接著，以與薄化裝置晶粒68A及68B類似的方式，可將裝置晶粒168A及168B進行薄化。如圖21所示，接著運用間隙填充材料180填充在相鄰裝置晶粒168A及168B之間的間隙。相應步驟做為步驟330說明於如圖33中所示的製造流程300中。根據本發明的一些實施例，間隙填充材料180的形成方式是使用選自用於形成間隙填充材料80相同的候選方法而形成。間隙填充材料180也可以是選自與形成間隙填充材料80相同的候選材料，且可以包括氧化物如氧化矽、聚苯並噁唑、聚醯亞胺等。接著，進行平坦化步驟以移除間隙填充材料180的多餘部分，以顯露出裝置晶粒168A及168B的基底170A及170B。
接著，使用例如化學氣相沉積(CVD)、電漿輔助化學氣相沉積(PECVD)、原子層沉積(ALD)等方式形成介電層182，以做為一個覆蓋性層面。所形成的結構如圖21所示。相應步驟做為步驟332說明於如圖33中所示的製造流程300中。根據本發明的一些實施例，介電層182可由氧化物來形成，例如氧化矽、氮氧化矽等。
接著，請參照圖22，對介電層182以及基底170A及170B 進行蝕刻以形成溝渠184，其中溝渠184延伸至介電層182以及基底170A及170B中。取決於基底170A及170B的厚度T1，基底170A及170B內的溝渠184的一部分的深度D1可以大於1微米，且可以在約2微米與5微米之間。舉例來說，深度D1可以是厚度T1的大約20%至大約60%之間。應理解的是，在本文中所描述的數值僅為示例，並且可以改變為不同的數值。
溝渠184可以以各種圖案分佈。舉例來說，溝渠184可以形成為離散的開口，其可以被分配為具有陣列的圖案，蜂巢圖案或其他類的重複圖案。溝渠184的俯視圖形狀可為矩形、圓形、六邊形等。根據本發明的替代性實施例，當在圖16所示的結構的俯視圖中觀察時，溝渠184可以是在單個方向上具有縱向方向的平行溝渠。溝渠184也可以互連並形成網格。所述網格可以包括彼此平行且均勻或不均勻間隔開來的多個第一溝渠，以及彼此平行且均勻或不均勻間隔開來的多個第二溝渠。所述多個第一溝渠與多個第二溝渠可以彼此相交以形成所述網格，並且所述多個第一溝渠與多個第二溝渠在上視圖中來看，可以彼此垂直或彼此不垂直。
接著，如圖23所示，填充溝渠184以形成接合墊187。相應步驟做為步驟332說明於如圖33中所示的製造流程300中。應理解的是，雖然特徵187被稱為接合墊187，但特徵187亦可以是離散焊墊、互連金屬線或是金屬網格。根據本發明的一些實施例，接合墊187是由銅所形成，或是其它適用於混合接合(因其 相對的容易擴散)的金屬。在填充之後，進行平坦化以使接合墊187的頂表面與介電層182的頂表面平坦。所述平坦化可包括化學機械研磨或機械磨削步驟。
接著，如圖24所示，將空白晶粒88接合至裝置晶粒168A及168B。相應步驟做為步驟334說明於如圖33中所示的製造流程300中。空白晶粒88包括塊狀基底194，其可以是矽基底或是金屬基底。當其是由金屬形成時，基底194可由銅、鋁、不銹鋼等形成。當基底194是由矽所形成時，空白晶粒88中沒有形成主動元件及被動元件。空白晶粒88具有兩種功能。首先，由於裝置晶粒68A及68B已被薄化以便使得能夠進行更佳的間隙填充，因此空白晶粒88向位於下方的結構提供機械支撐。此外，(基底194的)矽或金屬具有高的導熱性，因此空白晶粒88可充當散熱器。由於圖24中所示的結構是晶圓級製程，因此，多個與所示的空白晶粒88相同的空白晶粒亦會被接合至與裝置晶粒168A及168B相同的各個下方相應裝置晶粒上。
根據替代性的實施例，做為接合空白晶粒88的代替，是將第三層裝置晶粒放置在空白晶粒88的位置上，以使其接合至裝置晶粒168A及168B。
介電層190是形成在基底194的表面。介電層190可例如由氧化矽、氮氧化矽所形成。此外，接合墊192是形成在介電層190中，且接合墊192的所示底表面與介電層190的所示底表面為共平面。接合墊192的圖案和水平尺寸可以與各個接合墊187 的圖案和水平尺寸相同或相似，使得接合墊192與接合墊187可以以一對一的對應方式彼此接合。
空白晶粒88與裝置晶粒168A及168B的接合可以透過混合接合來實現。舉例來說，介電層182及190可以彼此接合，並且形成Si-O-Si鍵。接合墊192是透過金屬至金屬直接接合以接合至相應的接合墊187。
有利地，結合墊187藉由接觸(且甚至插入至)基底170A及170B而提供良好的散熱路徑，以使得在裝置晶粒68A、68B、168A及168B中產生的熱量可輕易地散入塊狀基底194中，也因此塊狀基底194可充當散熱器。
參照圖25，施加光阻183並圖案化。接著，使用光阻183做為蝕刻罩幕，並對介電層182以及間隙填充材料180進行蝕刻以形成暴露出插板100的一部分的開口210。相應步驟做為步驟336說明於如圖33中所示的製造流程300中。根據本發明的一些實施利，一些裝置晶粒，如裝置晶粒68B被顯露出。一些矽貫穿孔71B以及貫穿介電層孔162亦可被暴露出。
圖26顯示了將晶粒堆疊212接合至第二層結構上方。相應步驟做為步驟338說明於如圖33中所示的製造流程300中。晶粒堆疊212可以接合至貫穿介電層孔162、裝置晶粒(例如晶粒68B)或是接合至貫穿介電層孔162以及裝置晶粒兩者。晶粒堆疊212可以為包括多個堆疊晶粒214的記憶體堆疊，其中矽貫穿孔(圖中未示出)可以形成在晶粒214中以進行互連。晶粒堆疊212 也可以是高頻寬記憶體(high bandwidth memory；HBM)管。根據本發明的一些實施例，晶粒堆疊212是透過混合接合以接合至下方的結構，其中在晶粒堆疊212中的電連接器216(在一些實施例的接合墊)是透過金屬至金屬直接接合以接合至貫穿介電層孔162以及矽貫穿孔71B，且晶粒堆疊212的介電層218是透過氧化物至氧化物接合(oxide-to-oxide bonding)(或熔融接合；fusion bonding)以接合至間隙填充材料80(例如氧化物)以及介電層75B。根據替代性實施例，電連接器216為焊接區域，且所述接合為焊接接合(solder bonding)。根據另外的替代性實施例，電連接器216是突出超過晶粒堆疊212的表面介電層218的微凸塊(micro-bumps)，且晶粒堆疊212與間隙填充材料80以及介電層75B之間沒有氧化物至氧化物接合。微凸塊216可以透過金屬至金屬直接接合或是焊接接合以接合至貫穿介電層孔162與矽貫穿孔71B。
接著，將間隙填充材料220(圖27)填充到空白晶粒88以及晶粒堆疊212之間的間隙中。間隙填充材料220可以例如由為氧化物的氧化矽或是聚合物所形成。接著，例如是透過將如紫外光或是雷射光投射在釋放層22上以分解釋放層22，以使載板20上形成的結構能夠從載板20(圖26)剝離。所形成的結構如圖27所示。載板20和釋放層22從上層結構中被移除，其被稱為複合晶圓102(圖27)。相應步驟做為步驟340說明於如圖33中所示的製造流程300中。如有需要，可以執行載板互換以在載板20 拆卸之前將另一個載板(未示出)附接在所示的結構上，並且在後續步驟中形成電連接器的期間使用新的載板來提供機械支撐。
圖28A顯示了電連接器110的形成，其可穿透介電層24並連接至重佈線線路26。電連接器110可以是金屬凸塊、焊料凸塊、金屬柱、導線接合(wire bonds)或其它適用的連接器。對複合晶圓102執行晶粒鋸切步驟以將複合晶圓102分隔成多個封裝104。封裝104彼此相同，且每一封裝104可以具有兩層的裝置晶粒與晶粒堆疊212。相應步驟做為步驟340說明於如圖33中所示的製造流程300中。
圖28B顯示了根據本發明的一些實施例所形成的封裝104。這些實施例類似於圖28A所示的實施例，差異在於接合墊187穿透介電層182並且不延伸到基底170A和170B中。根據一些實施例，接合墊187是與基底170A及170B接觸。根據替代性實施例，接合墊187及192的一個或兩個從發生接合的界面開始會部分延伸至相應的介電層182及190中，而不是穿透相應的介電層182及190。根據本發明的一些實施例，接合墊187與192以及塊狀基底194可以被電接地，以提供用於基底170A及170B的電接地(electrical grounding)。
圖28C顯示了根據本發明的一些實施例所形成的封裝。這些實施例類似於圖28A及28B所示的實施例，差異在於並未形成接合墊187與192以及介電層190(如圖28A及28B所示)。塊狀基底194，亦即空白晶粒88，是透過熔融接合而接合至介電層 182。
根據本發明的替代性實施例，空白晶粒88為金屬晶粒。據此，圖28C中所示的層面182可以由高導熱性的黏合劑的熱界面材料(Thermal Interface Material；TIM)所形成。
圖29及30為根據本發明一些實施例的封裝的形成過程中的各中間階段的剖視圖。除非另外具體指明，否則在該些實施例中的組件的材料及形成方法本質上與在圖1至圖28A所示實施例中將由相同標號來表示相同組件。因此可在對圖1至圖28A中所示實施例的論述中找到關於圖29及圖30中所示組件的形成製程及材料的細節。圖29顯示複合晶圓102的剖視圖，除金屬墊45形成於介電層24上而未在載板20上形成如圖28A所示包括介電層28、34、38、及42、以及重佈線線路32、36、40、及44的特徵以外，複合晶圓102與圖28A所示者本質上相同。確切而言，如圖29所示步驟之後的結構的圖30所示，在剝離載板20(圖21)之後，形成介電層28、34、38、及42、以及重佈線線路32、36、40、及44。根據該些實施例用於形成介電層28、34、38、及42的順序相對於圖1至圖11所示的順序相反。應注意的是，由於不同的形成順序，重佈線線路32、36、40、及44的取向相較於圖28A中所示者相反(沿垂直方向)。接著，藉由對複合晶圓102進行晶粒鋸切而形成封裝104。
圖31說明其中嵌置封裝104(圖28A、28B、28C及圖30)的封裝112。所述封裝包括記憶體管114，所述記憶體管114 包括多個堆疊記憶體晶粒(圖中未分別示出)。封裝104及記憶體管114密封於可為封裝膠體的密封材料118中。介電層及重佈線線路(統稱為疊層116)位於封裝104及記憶體管114之下且連接至封裝104及記憶體管114。根據本發明的一些實施例，介電層及重佈線線路(疊層116)使用與圖1至圖11所示者類似的材料形成且具有與圖1至圖11所示者類似的結構。
圖32顯示了層疊式封裝(Package-on-Package，PoP)結構132，其具有與頂部封裝140相結合的積體扇出型(Integrated Fan-Out，InFO)封裝138。積體扇出型封裝138亦包括嵌置在其中的封裝104。封裝104及貫穿孔134密封在可為封裝膠體的密封材料130中。封裝104接合至統稱為疊層146的介電層及重佈線線路。介電層及重佈線線路(疊層146)亦可使用與圖1至圖11所示者類似的材料形成且具有與圖1至圖11所示者類似的結構。
本發明的實施例具有某些有利特徵。藉由使用通常用於矽晶圓的製程(例如，鑲嵌製程)來形成用於插板的小間距重佈線線路，所述小間距重佈線線路可被形成為足夠薄，以提供兩個以上的裝置晶粒皆藉由小間距重佈線線路進行通訊的能力。所述封裝亦提供集成記憶體管的解決方案。在插板中未使用矽基底，因此避免由矽基底產生的電性效能的劣化。亦存在建於封裝中的一些散熱機制用於更佳地散熱。
在一實施例中，提供一種方法包括：形成多個介電層；在所述多個介電層中形成多個重佈線線路；對所述多個介電層進 行蝕刻以形成開口；填充所述開口以形成穿透所述多個介電層的貫穿介電層孔；在所述貫穿介電層孔以及所述多個介電層上形成介電層；在所述介電層中形成多個接合墊；藉由混合接合將第一裝置晶粒接合至所述介電層以及所述多個接合墊的第一部分；以及將晶粒堆疊接合至所述第一裝置晶粒中的矽貫穿孔。在一實施例中，所述方法更包括藉由混合接合將第二裝置晶粒接合至所述介電層以及所述多個接合墊的第二部分，其中所述重佈線線路將所述第一裝置晶粒連接至所述第二裝置晶粒。在一實施例中，形成所述多個重佈線線路的方法包括鑲嵌製程。在一實施例中，所述貫穿介電層孔不延伸至任何半導體基底中。在一實施例中，所述方法更包括：將另外的裝置晶粒接合至所述第一裝置晶粒，其中所述另外的裝置晶粒直接與所述第一裝置晶粒中的所述矽貫穿孔接合；在所述另外的裝置晶粒的半導體基底上形成氧化層，並使氧化層與所述半導體基底接觸；形成延伸至所述氧化層中的接合墊；以及藉由混合接合將空白晶粒接合至所述氧化層及所述接合墊。在一實施例中，所述接合墊延伸至所述另外的裝置晶粒的所述半導體基底中。在一實施例中，所述接合墊與所述另外的裝置晶粒的所述半導體基底接觸，但不延伸至所述另外的裝置晶粒的所述半導體基底中。
在一實施例中，提供一種方法包括：形成多個介電層；在每一個所述多個介電層中形成重佈線線路；形成穿透所述多個介電層的第一貫穿介電層孔與第二貫穿介電層孔；在所述多個介 電層上形成介電層；在所述介電層中形成多個接合墊，所述多個接合墊電性耦合至所述第一貫穿介電層孔、所述第二貫穿介電層孔及所述多個重佈線線路；藉由混和接合將第一裝置晶粒與第二裝置晶粒接合至所述介電層及所述多個接合墊，其中所述第一裝置晶粒與所述第二裝置晶粒藉由所述多個重佈線線路電性內連；以及將晶粒堆疊接合至所述第二裝置晶粒。在一實施例中，所述多個重佈線線路是藉由鑲嵌製程形成。在一實施例中，所述方法更包括：在所述第一裝置晶粒與所述第二裝置晶粒的相對側上填充間隙填充材料；形成穿透所述間隙填充材料的第三貫穿介電層孔；以及直接將第三裝置晶粒接合至所述第三貫穿介電層孔，並與其物理接觸。在一實施例中，所述更包括形成穿透所述間隙填充材料的第四貫穿介電層孔，其中所述第二裝置晶粒直接接合至所述第三貫穿介電層孔，並與其物理接觸，且所述晶粒堆疊直接接合至所述第四貫穿介電層孔，並與其物理接觸。在一實施例中，形成所述第一貫穿介電層孔與所述第二貫穿介電層孔包括：對所述多個介電層進行蝕刻以形成第一開口與第二開口；以及在所述第一開口與所述第二開口中填充導電材料。在一實施例中，所述方法更包括：薄化所述第一裝置晶粒及所述第二裝置晶粒以暴露出在所述第一裝置晶粒及所述第二裝置晶粒中的矽貫穿孔；以及將第三裝置晶粒接合至所述矽貫穿孔。在一實施例中，所述方法更包括：在所述第三裝置晶粒上形成介電層；以及將塊狀晶圓接合至所述介電層。
在一實施例中，提供一種封裝，包括：多個介電層；多個重佈線線路，分別位於所述多個介電層中；第一貫穿介電層孔，穿透所述多個介電層；多個接合墊，位於所述第一貫穿介電層孔及所述多個重佈線線路上，且連接至所述第一貫穿介電層孔及所述多個重佈線線路；第一介電層，所述多個接合墊位於所述第一介電層中；第一裝置晶粒，藉由混合接合使所述第一裝置晶粒接合至所述第一介電層以及所述多個接合墊的第一部分；間隙填充材料，位於所述第一裝置晶粒的相對側上；第二貫穿介電層孔，穿透所述間隙填充材料；以及晶粒堆疊，接合至所述第二貫穿介電層孔。在一實施例中，所述封裝更包括第二裝置晶粒，所述第二裝置晶粒藉由混合接合而接合至所述第一介電層以及所述多個接合墊的第二部分，其中所述第一裝置晶粒與所述第二裝置晶粒藉由所述多個重佈線線路彼此電性耦合。在一實施例中，所述封裝更包括：第二裝置晶粒，位於所述第一裝置晶粒上，且接合至所述第一裝置晶粒；接合墊，與所述第二裝置晶粒的半導體基底接觸，其中所述接合墊的至少一部分位於所述第二裝置晶粒的所述半導體基底之上；第二介電層，所述接合墊的至少一部分位於所述第二介電層中；以及塊狀基底，位於所述第二介電層與所述接合墊上，且接合至所述第二介電層與所述接合墊。在一實施例中，所述塊狀基底由矽所形成，且在所述塊狀基底上沒有形成主動元件以及被動元件。在一實施例中，所述接合墊更延伸到所述第二裝置晶粒的所述半導體基底中。在一實施例中，所述接合墊 形成網格。
在一實施例中，提供一種方法包括：在載板上形成多介電層；在所述介電層形成之後，對所述多個介電層進行蝕刻以形成穿透所述多個介電層的第一開口及第二開口；填充所述第一開口及第二開口以形成第一及第二貫穿介電層孔；將裝置晶粒接合並電性耦合至第一貫穿介電層孔上，其中所述裝置晶粒的接合包括混合接合；以及將晶粒堆疊接合並電性耦合至第二貫穿介電層孔上。在一實施例中，所述方更包括在所述多介電層上形成介電層；以及，在所述介電層中形成接合墊，其中所述接合墊與第一貫穿介電層孔接觸，且所述裝置晶粒與所述介電層的接合墊物理接合。在一實施例中，所述多個介電層包括氧化矽。
在一實施例中，提供一種封裝，包括：多個介電層；穿透所述多個介電層的貫穿介電層孔，其中所述貫穿介電層孔具有連續穿透所述多個介電層的邊緣；裝置晶粒，位於所述多個介電層上，其中所述裝置晶粒介由混合接合以與下方結構接合，且所述裝置晶粒與所述貫穿介電層孔電性耦合；以及晶粒堆疊，位於裝置晶粒上方，並與其接合。在一實施例中，所述封裝更包括介電層，位於所述多個介電層上方；以及，接合墊位於所述介電層中，其中所述接合墊與貫穿介電層孔接觸，且所述裝置晶粒與所述接合墊以及所述介電層物理接觸。在一實施例中，所述晶粒堆疊是接合至裝置晶粒中的矽貫穿孔。在一實施例中，所述晶粒堆疊透過混合接合以接合至裝置晶粒。
在一實施例中，提供一種封裝，包括：多個介電層；穿透所述多個介電層的貫穿介電層孔；第一裝置晶粒，位於所述貫穿介電層孔上並與其電性耦合，其中所述第一裝置晶粒包括一半導體基底；介電層，位於所述第一裝置晶粒上；接合墊，位於所述介電層中，其中所述接合墊穿透所述介電層並延伸至第一裝置晶粒的半導體基底中；以及晶粒堆疊，位於第一裝置晶粒上，並與其接合。在一實施例中，所述晶粒堆疊是藉由混合接合以接合至所述接合墊以及所述介電層。在一實施例中，所述封裝更包括第二裝置晶粒，其位於第一裝置晶粒與貫穿介電層孔之間。
以上概述了若干實施例的特徵，以使熟習此項技術者可更佳地理解本發明的各個態樣。熟習此項技術者應知，其可容易地使用本發明作為設計或修改其他製程及結構的基礎來施行與本文中所介紹的實施例相同的目的及/或達成與本文中所介紹的實施例相同的優點。熟習此項技術者亦應認識到，該些等效構造並不背離本發明的精神及範圍，而且他們可在不背離本發明的精神及範圍的條件下對其作出各種改變、代替、及變更。
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Claims (9)

  1. 一種封裝的形成方法，包括：形成多個介電層；在所述多個介電層中形成多個重佈線線路；對所述多個介電層進行蝕刻以形成開口；填充所述開口以形成穿透所述多個介電層的貫穿介電層孔；在所述貫穿介電層孔以及所述多個介電層上形成介電層；在所述介電層中形成多個接合墊；藉由混合接合將第一裝置晶粒接合至所述介電層以及所述多個接合墊的第一部分；將晶粒堆疊接合至所述第一裝置晶粒中的矽貫穿孔；將另外的裝置晶粒接合至所述第一裝置晶粒，其中所述另外的裝置晶粒直接與所述第一裝置晶粒中的所述矽貫穿孔接合；在所述另外的裝置晶粒的半導體基底上形成氧化層，並使氧化層與所述半導體基底接觸；形成延伸至所述氧化層中的接合墊；以及藉由混合接合將空白晶粒接合至所述氧化層及所述接合墊。
  2. 如申請專利範圍第1項所述的方法，更包括藉由混合接合將第二裝置晶粒接合至所述介電層以及所述多個接合墊的第二部分，其中所述重佈線線路將所述第一裝置晶粒連接至所述第二裝置晶粒。
  3. 如申請專利範圍第1項所述的方法，其中所述接合墊延伸至所述另外的裝置晶粒的所述半導體基底中。
  4. 如申請專利範圍第1項所述的方法，其中所述接合墊與所述另外的裝置晶粒的所述半導體基底接觸，但不延伸至所述另外的裝置晶粒的所述半導體基底中。
  5. 一種封裝，包括：多個介電層；多個重佈線線路，分別位於所述多個介電層中；第一貫穿介電層孔，穿透所述多個介電層；多個接合墊，位於所述第一貫穿介電層孔及所述多個重佈線線路上，且連接至所述第一貫穿介電層孔及所述多個重佈線線路；第一介電層，所述多個接合墊位於所述第一介電層中；第一裝置晶粒，藉由混合接合使所述第一裝置晶粒接合至所述第一介電層以及所述多個接合墊的第一部分；間隙填充材料，位於所述第一裝置晶粒的相對側上；第二貫穿介電層孔，穿透所述間隙填充材料；以及晶粒堆疊，接合至所述第二貫穿介電層孔。
  6. 如申請專利範圍第5項所述的封裝，更包括第二裝置晶粒，所述第二裝置晶粒藉由混合接合而接合至所述第一介電層以及所述多個接合墊的第二部分，其中所述第一裝置晶粒與所述第二裝置晶粒藉由所述多個重佈線線路彼此電性耦合。
  7. 如申請專利範圍第5項所述的封裝，更包括： 第二裝置晶粒，位於所述第一裝置晶粒上，且接合至所述第一裝置晶粒；接合墊，與所述第二裝置晶粒的半導體基底接觸，其中所述接合墊的至少一部分位於所述第二裝置晶粒的所述半導體基底之上；第二介電層，所述接合墊的至少一部分位於所述第二介電層中；以及塊狀基底，位於所述第二介電層與所述接合墊上，且接合至所述第二介電層與所述接合墊。
  8. 如申請專利範圍第7項所述的封裝，其中所述塊狀基底由矽所形成，且在所述塊狀基底上沒有形成主動元件以及被動元件。
  9. 如申請專利範圍第7項所述的封裝，其中所述接合墊更延伸到所述第二裝置晶粒的所述半導體基底中。
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