TWI652773B - 封裝結構及其製造方法 - Google Patents

封裝結構及其製造方法 Download PDF

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TWI652773B
TWI652773B TW106135947A TW106135947A TWI652773B TW I652773 B TWI652773 B TW I652773B TW 106135947 A TW106135947 A TW 106135947A TW 106135947 A TW106135947 A TW 106135947A TW I652773 B TWI652773 B TW I652773B
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Taiwan
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device die
substrate
layer
dielectric
metal
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TW106135947A
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TW201906092A (zh
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陳明發
余振華
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台灣積體電路製造股份有限公司
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Abstract

本發明實施例的一種封裝結構的製造方法包括：將第一裝置晶粒及第二裝置晶粒接合至基底；以及使用間隙填充材料填充第一裝置晶粒與第二裝置晶粒之間的間隙。間隙填充材料的頂部部分覆蓋第一裝置晶粒及第二裝置晶粒。形成穿透間隙填充材料的頂部部分的第一通孔。第一通孔電性耦合至第一裝置晶粒及第二裝置晶粒。所述方法更包括使用鑲嵌製程在間隙填充材料之上形成重佈線；以及在重佈線之上形成電性耦合至所述重佈線的電性連接件。

Description

封裝結構及其製造方法
本發明實施例是有關於封裝結構及其製造方法。
積體電路的封裝變得日益複雜，更多裝置晶粒被封裝於同一封裝中以達成更多功能。舉例而言，封裝可包括例如接合至同一中介層(interposer)的處理器與記憶體立方體(memory cube)等多個裝置晶粒。中介層可由半導體基底來形成，所述半導體基底中形成有內連線於中介層的相對兩側上的特徵之間的矽穿孔(through-silicon via)。裝置晶粒包封於模塑化合物(molding compound)中。包括中介層及裝置晶粒的封裝進一步接合至封裝基底。另外，表面安裝裝置(surface mount device)亦可接合至基底。散熱件(heat spreader)可附接至裝置晶粒的頂表面以使在裝置晶粒中產生的熱量逸散。散熱件可具有固定至封裝基底上的外圍部分(skirt portion)。
本發明一些實施例的封裝結構的製造方法包括：將第一裝置晶粒及第二裝置晶粒接合至基底；使用間隙填充材料填充所述第一裝置晶粒與所述第二裝置晶粒之間的間隙，其中所述間隙填充材料的頂部部分覆蓋所述第一裝置晶粒及所述第二裝置晶粒；形成穿透所述間隙填充材料的所述頂部部分的第一通孔，其中所述第一通孔電性耦合至所述第一裝置晶粒及所述第二裝置晶粒；使用鑲嵌製程在所述間隙填充材料之上形成重佈線；以及在所述重佈線之上形成電性耦合至所述重佈線的電性連接件。
本發明另一些實施例的封裝結構的製造方法包括：將第一裝置晶粒及第二裝置晶粒附接至散熱件；以介電材料填充所述第一裝置晶粒與所述第二裝置晶粒之間的間隙，其中所述介電材料的頂部部分覆蓋所述第一裝置晶粒及所述第二裝置晶粒；形成穿透所述介電材料的所述頂部部分的通孔，其中所述通孔電性耦合至所述第一裝置晶粒及所述第二裝置晶粒；在所述介電材料之上形成多個介電層；使用雙重鑲嵌製程在所述多個介電層中形成重佈線；在所述重佈線之上形成電性連接件，其中所述電性連接件電性耦合至所述重佈線；以及執行晶粒鋸切來切穿所述散熱件、所述介電材料及所述多個介電層，以形成多個封裝。
本發明一些實施例的封裝結構包括：空白基底；第一裝置晶粒及第二裝置晶粒，接合至所述空白基底；間隙填充材料，包括第一部分與第二部分，其中所述第一部分填充所述第一裝置晶粒與所述第二裝置晶粒之間的間隙，所述第二部分覆蓋所述第 一裝置晶粒及所述第二裝置晶粒；第一通孔，穿透所述間隙填充材料的所述第二部分，以電性耦合至所述第一裝置晶粒及所述第二裝置晶粒；多個介電層，位於所述間隙填充材料之上；以及多條重佈線，位於所述多個介電層中，其中所述多條重佈線包括雙重鑲嵌結構。
10‧‧‧晶圓
12‧‧‧基底
12A、12B‧‧‧基底
14‧‧‧介電層
15‧‧‧開口
16‧‧‧接合接墊/特徵
18‧‧‧微溝渠
20A、20B‧‧‧封裝組件/裝置晶粒
22A、22B‧‧‧基底
24A、24B‧‧‧內連線結構
25A、25B‧‧‧金屬接墊
26A、26B、44、56A2、64‧‧‧通孔
28A、28B、30A、30B、60、66‧‧‧鈍化層
32A、32B、62‧‧‧金屬接墊
34‧‧‧接合接墊
36A、36B‧‧‧介電層
38‧‧‧間隙
40‧‧‧間隙填充材料
42‧‧‧通孔開口
46‧‧‧擴散阻障層
48‧‧‧金屬材料
50A、50B、50C、54A、54B、54C、58‧‧‧介電層
52A、52B、52C‧‧‧蝕刻終止層
56、56A、56B、56C‧‧‧重佈線
56A1‧‧‧金屬線
68‧‧‧凸塊下金屬
70‧‧‧非焊料部件
72‧‧‧焊料頂蓋
74‧‧‧電性連接件
76‧‧‧複合晶圓
78‧‧‧封裝
80、82‧‧‧聚合物層
84‧‧‧鈍化後內連線
200‧‧‧製程流程
202、204、206、208、210、212、214、216、218‧‧‧步驟
D1‧‧‧深度
結合附圖閱讀以下詳細說明，會最佳地理解本發明的各個態樣。應注意，根據本行業中的標準慣例，各種特徵並非按比例繪製。事實上，為論述清晰起見，可任意增大或減小各種特徵的尺寸。
圖1A及圖1B至圖11說明根據一些實施例的使用重佈線在後(Redistribution Line-last，RDL-last)製程形成封裝的過程中的各種中間階段的剖視圖。
圖12至圖13說明根據一些實施例的使用重佈線在後製程形成的一些封裝的剖視圖。
圖14說明根據一些實施例的封裝中的雙重鑲嵌結構(dual damascene structure)及凸塊下金屬(Under-Bump metallurgy，UBM)。
圖15說明根據一些實施例的形成封裝的製程流程。
以下揭露內容提供用於實作本發明的不同特徵的諸多不同的實施例或實例。以下闡述組件及排列的具體實例以簡化本揭露內容。當然，該些僅為實例且不旨在進行限制。舉例而言，以下說明中將第一特徵形成於第二特徵「之上」或第二特徵「上」可包括其中第一特徵及第二特徵被形成為直接接觸的實施例，且亦可包括其中第一特徵與第二特徵之間可形成有附加特徵、進而使得所述第一特徵與所述第二特徵可能不直接接觸的實施例。另外，本發明可能在各種實例中重複使用參考編號及/或字母。此種重複使用是出於簡潔及清晰的目的，而並非自身表示所論述的各種實施例及/或配置之間的關係。
此外，為了易於說明，本文中可能使用例如「之下」、「下面」、「下部的」、「上覆的」、「上部的」等空間相對用語來闡述圖中所示的一個元件或特徵與另一(其他)元件或特徵的關係。所述空間相對用語旨在除圖中所繪示的定向外亦囊括裝置在使用或操作中的不同定向。設備可具有其他定向(旋轉90度或處於其他定向)，且本文使用的空間相對描述語可相應地進行解釋。
根據各種示例性實施例提供一種基於重佈線在後(Redistribution Line-last，RDL-last)製程形成的封裝及其形成方法。根據一些實施例說明形成所述封裝的中間階段。對一些實施例的一些變形進行論述。在各種圖中及說明性實施例通篇中，相似的參考編號用於表示相似的元件。
圖1A及圖1B至圖11說明根據本發明一些實施例的使用 重佈線在後製程形成封裝的過程中的各種中間階段的剖視圖。圖1A及圖1B至圖11中所示步驟亦示意性地反映於圖15中所示製程流程200中。
圖1A說明晶圓10。晶圓10包括塊狀基底12，塊狀基底12可為矽基底、玻璃基底、或金屬基底。晶圓10可具有典型的半導體晶圓形狀。舉例而言，晶圓10可具有圓形俯視圖形狀，且可具有8英吋(inch)的直徑、12英吋的直徑等。當基底12是以金屬形成時，基底12可以是以銅、鋁、不銹鋼等來形成。根據本發明的一些實施例，在晶圓10中不形成主動裝置(例如，電晶體及二極體)及被動裝置(例如，電容器、電感器、及電阻器)。晶圓10具有兩種功能。首先，由於隨後接合的裝置晶粒非常薄(以良好地填充間隙)，因此晶圓10可以對在隨後的步驟中所將形成的結構提供機械支撐。此外，基底12可具有高導熱性(thermal conductivity)，且因此晶圓10可充當散熱件。
在基底12的表面處可形成介電層14。相應步驟被示為圖15中所示製程流程中的步驟202。介電層14可由氧化矽形成，舉例而言，氧化矽可藉由在含氧環境中對基底12進行氧化來形成。做為另一選擇，介電層14可以藉由在水蒸氣中對基底12進行氧化來形成。根據本發明的一些實施例，介電層14可以藉由沈積例如是氧化矽(其可由四乙氧基矽烷(tetraethyl orthosilicate，TEOS)形成)、氮氧化矽等氧化物來形成。根據本發明的一些實施例，在介電層14中形成接合接墊16。相應步驟被示為圖15中所示製程 流程中的步驟204。根據本發明的一些實施例，接合接墊16的底表面可與介電層14的所示底表面共面。根據本發明的替代性實施例，接合接墊16延伸至基底12中，且使用虛線示出接合接墊16的位於基底12中的部分，以表示接合接墊16可延伸至或可不延伸至基底12中。
為形成接合接墊16，藉由蝕刻介電層14及基底12來形成溝渠(示出為被接合接墊16填充)，以使所述溝渠亦延伸至介電層14及基底12中。溝渠之位於基底12內部的部分的深度D1可大於約1微米(μm)，且可依據基底12的厚度而介於約2微米與約20微米之間。舉例而言，深度D1可介於基底12的厚度的約20%與約60%之間。應知，在本說明中通篇中所陳述的值為範例，其可經改變為不同的值。
如圖1A中所示，接著填充溝渠以形成接合接墊16。應知，儘管將特徵16稱為接合接墊，然而特徵16可為分離的接墊或彼此內連的金屬線。根據一些實施例，接合接墊16是由銅或其他適合於進行混合接合(hybrid bonding)(由於相對地容易擴散)的金屬形成。在填充之後，執行平坦化(planarization)以將接合接墊16的頂表面與介電層14的頂表面平坦化。平坦化可包括化學機械研磨(Chemical Mechanical Polish，CMP)製程或機械磨制(mechanical grinding)製程。
可在各種圖案中分佈溝渠(以及所得的接合接墊16)。舉例而言，可將溝渠形成為分離的開口，所述分離的開口可被佈置 成陣列、蜂窩圖案、或其他重複圖案。溝渠的俯視圖形狀可為矩形、正方形、圓形、六邊形等。根據本發明的替代性實施例，當在圖1A中所示結構的俯視圖中觀察時，溝渠可為在單一方向上延伸的平行溝渠。亦可對溝渠進行內連以形成格柵(grid)。格柵可包括彼此平行且均勻地或不均勻地間隔開的第一多個溝渠、及彼此平行且均勻地或不均勻地間隔開的第二多個溝渠。第一多個溝渠與第二多個溝渠彼此交錯以形成格柵，且在俯視圖中所述第一多個溝渠與所述第二多個溝渠可彼此垂直或可不彼此垂直。
根據本發明的替代性實施例，在介電層14及基底12中不形成金屬接合接墊。因此，如圖1B中所示，基底12是由均質材料(半導體、玻璃、或金屬)形成的空白基底，且介電層14是毯覆平坦層(blanket planar layer)。
根據本發明的一些實施例，在基底12中形成微溝渠(micro-trench)18。微溝渠18是冷卻劑(例如油、水、氣體等)可在其中流動的空隙(void)。形成微溝渠18可包括蝕刻第一基底(例如，圖1A中的基底12A)以形成微溝渠，及使用另一基底(例如，基底12B)覆蓋所述微溝渠以密封所述微溝渠，其中在基底12B中形成開口15以連接至微溝渠18。以虛線來說明微溝渠18以表示可形成微溝渠18或可不形成微溝渠18。
參照圖2，將封裝組件20A及裝組件20B接合至晶圓10。相應步驟被示為圖15中所示製程流程中的步驟206。封裝組件20A及封裝組件20B可為裝置晶粒或封裝。根據本發明的一些實施 例，封裝組件20A及封裝組件20B包括一個邏輯晶粒或多個邏輯晶粒。所述一個邏輯晶粒或多個邏輯晶粒可選自中央處理單元(Central Processing Unit，CPU)晶粒、微控制單元(Micro Control Unit，MCU)晶粒、輸入/輸出(input-output，IO)晶粒、基頻帶(BaseBand，BB)晶粒、或應用處理器(Application processor，AP)晶粒。封裝組件20A及封裝組件20B亦可包括一個記憶體晶粒或多個記憶體晶粒。在隨後的論述中，將封裝組件20A及封裝組件20B例如稱為裝置晶粒，同時封裝組件20A及封裝組件20B亦可為例如封裝、晶粒堆疊、記憶體立方體等其他類型的裝置。此外，儘管將封裝組件20A及封裝組件20B示為具有相同的結構，然而封裝組件20A及封裝組件20B可具有不同的電路、不同的大小、不同的厚度、及/或可在其中包括不同數目的裝置晶粒。
封裝組件20A及封裝組件20B分別包括可為矽基底的半導體基底22A及半導體基底22B。此外，封裝組件20A及封裝組件20B可分別包括用於與封裝組件20A及封裝組件20B中的主動裝置及被動裝置連接的內連線結構24A及內連線結構24B。內連線結構24A及內連線結構24B包括金屬線及通孔(圖中未示出)。此外，可使用介電常數(k值)低於約3.0、低於約2.5或甚至更低的低介電常數介電材料(low-k dielectric material)形成介電層。介電層中形成有內連線結構24A及內連線結構24B的金屬線及通孔。介電材料可由黑金剛石(Black Diamond)(應用材料公司(Applied Materials)的註冊商標)、含碳低介電常數介電材料、 氫矽倍半氧烷(Hydrogen SilsesQuioxane，HSQ)、甲基矽倍半氧烷(MethylSilsesQuioxane，MSQ)等形成。根據本發明的替代性實施例，內連線結構24A及內連線結構24B中的介電層是由例如氧化矽或氮氧化矽等氧化物系介電材料形成。
內連線結構24A及內連線結構24B分別包括位於所述內連線結構的頂部金屬層中的金屬接墊25A及金屬接墊25B。可分別形成上覆於內連線結構24A及內連線結構24B上的鈍化層28A及鈍化層28B(做為另一選擇，稱作保護-1)。根據本發明的一些實施例，鈍化層28A及鈍化層28B是由例如氧化矽或氮化矽等無機介電材料形成，且可具有單層結構或複合結構。複合結構可包括例如氧化矽層與位於所述氧化矽層之上的氮化矽層。分別在鈍化層28A及鈍化層28B之上形成金屬接墊32A金屬接墊及32B，並將金屬接墊32A及金屬接墊32B分別經由在鈍化層28A及鈍化層28B中形成的通孔26A及通孔26B而連接至位於其下的裝置。
根據本發明的一些實施例，金屬接墊32A及金屬接墊32B是由鋁或鋁銅形成，且因此有時稱為鋁接墊。在金屬接墊32A及金屬接墊32B之上形成鈍化層30A及鈍化層30B(做為另一選擇，稱為保護-2)。鈍化層30A及鈍化層30B可使用選自與用於形成鈍化層28A及鈍化層28B的候選材料相同的候選材料中的材料來形成。
封裝組件20A可包括位於封裝組件20A的所示底表面處的接合接墊34及介電層36A。接合接墊34的所示底表面與介電 層36A的所示底表面共面。封裝組件20B包括位於所示底表面處的接合接墊34及介電層36B。接合接墊34的所示底表面與介電層36B的所示底表面共面。介電層36A/36B及接合接墊34的形成製程可分別相似於介電層14及接合接墊16的形成製程。舉例而言，介電層36A及介電層36B可由氧化矽或例如氮氧化矽等其他含氧介電材料形成。接合接墊34的圖案及水平尺寸可相同於或相似於與接合接墊34接合的相應接合接墊16的圖案及水平尺寸。有利地，接合接墊34藉由接觸基底22A及基底22B(及甚至插入基底22A及基底22B中)來提供良好的散熱路徑，以使在封裝組件20A及封裝組件20B中產生的熱量可經由接合接墊16輕易地向塊狀基底12中散出。
封裝組件20A及封裝組件20B是例如厚度介於約15微米與約30微米之間的薄晶粒。由於封裝組件20A及封裝組件20B是薄的，因此將鄰近的封裝組件20A與封裝組件20B之間的間隙38的高寬比(aspect ratio)保持為低的以達成良好的間隙填充。否則，會由於高的高寬比而難以進行間隙填充。
將封裝組件20A及封裝組件20B與位於其下方的結構的接合的接合製程可經由混合接合(hybrid bonding)來達成。舉例而言，接合接墊34與接合接墊16可經由金屬-金屬直接接合(metal-to-metal direct bonding)而接合。根據本發明的一些實施例，金屬-金屬直接接合為銅-銅直接接合(copper-to-copper direct bonding)。此外，介電層36A及介電層36B可以例如使用Si-O-Si 鍵來與介電層14接合。混合接合可包括預接合(pre-bonding)及隨後進行的退火(anneal)，以使接合接墊34中的金屬與相應的位於其下方的接合接墊16中的金屬進行金屬間擴散而形成金屬-金屬直接接合。
根據替代性實施例，如圖1B中所示，在晶圓10中不形成接合接墊。因此，亦不形成如圖2中所示的接合接墊36A及接合接墊36B，封裝組件20A及封裝組件20B可以經由熔融接合(fusion bonding)(介電質-介電質接合(dielectric-to-dielectric bonding))來與介電層14接合。
根據本發明的替代性實施例，基底12為玻璃基底或金屬基底。因此，介電層14可由熱介面材料(Thermal Interface Material，TIM)形成。所述熱介面材料為具有高導熱性的黏合劑。因此封裝組件20A及封裝組件20B可以藉由熱介面材料(介電層14)黏合至基底12(參照圖12)。根據該些實施例，可不形成圖1中的介電層36A及介電層36B，且可形成或可不形成接合接墊34。
接下來，如圖3中所示，以間隙填充材料40來填充間隙38。相應步驟被示為圖15中所示製程流程中的步驟208。根據本發明的一些實施例，間隙填充材料40包括無機介電質。所述無機介電質可以例如是氧化矽等氧化物系介電質。舉例而言，氧化矽可由四乙氧基矽烷形成。形成方法可包括化學氣相沈積(Chemical Vapor Deposition，CVD)、高密度電漿化學氣相沈積(High-Density Plasma Chemical Vapor Deposition，HDPCVD)等。根據本發明的 一些實施例，間隙填充材料40為非聚合物材料(non-polymer material)。所述非聚合物材料不包括例如聚苯並噁唑(polybenzoxazole，PBO)、聚醯亞胺、苯並環丁烯(benzocyclobutene，BCB)等聚合物。所述聚合物具有與封裝組件顯著不同的熱膨脹係數(Coefficient of Thermal Expansion，CTE)，且將會造成所得封裝的翹曲(warpage)且隨後在具有精細間距的重佈線的形成過程中造成困難。
接著執行平坦化步驟，以移除間隙填充材料40的過量部分，以使間隙填充材料40的頂表面變為平坦的。間隙填充材料40的頂表面直接留在封裝組件20A及封裝組件20B之上。在所得結構中，間隙填充材料40可接觸介電層14的頂表面，並包圍封裝組件20A及封裝組件20B中的每一者。此外，間隙填充材料40可接觸鈍化層30A及鈍化層30B的頂表面。
根據本發明的一些實施例，在圖3中所示結構中不存在聚合物層(例如，聚醯亞胺、聚苯並噁唑、苯並環丁烯、模塑化合物、底部填充物(underfill)、模塑底部填充物(molding underfill)等)。舉例而言，封裝組件20A及封裝組件20B不含有聚合物層，且位於之下的晶圓10亦不含有聚合物。因此，圖3中所示結構不具有因聚合物與矽/氧化矽等之間的顯著差異造成的熱膨脹係數不匹配問題。因此，使用用於形成裝置晶圓中的內連線結構的製程(例如，鑲嵌製程)及材料(例如，銅及/或低介電常數介電質)在圖3中所示結構之上形成具有精細間距的重佈線是可行的。
參照圖4，蝕刻間隙填充材料40以及鈍化層30A及鈍化層30B以形成通孔開口42。根據本發明的一些實施例，通孔開口42暴露出金屬接墊32A及金屬接墊32B。根據本發明的替代性實施例，一些通孔開口42或全部的通孔開口42還穿透鈍化層28A及/或鈍化層28B，以使一些頂部金屬接墊25A及頂部金屬接墊25B暴露於通孔開口42。根據本發明的又一些替代性實施例，一些通孔開口42暴露出頂部金屬接墊25A及/或頂部金屬接墊25B，而一些其他通孔開口42暴露出金屬接墊32A及/或金屬接墊32B。通孔開口42的俯視圖形狀可以是，但不限於，矩形、圓形、六邊形等。
接下來，使用導電材料填充通孔開口42，以形成通孔44，且所得結構示出於圖5中。相應步驟被示為圖15中所示製程流程中的步驟210。根據本發明的一些實施例，通孔44是由均質導電材料(homogenous conductive material)形成，所述均質導電材料可為包括銅、鋁、鎢等金屬或金屬合金。根據本發明的替代性實施例，通孔44具有複合結構，所述複合結構包括由鈦、氮化鈦、鉭、氮化鉭等形成的導電阻障層、及位於所述導電阻障層之上的含金屬材料(例如，銅或銅合金)。根據本發明的一些實施例，形成包圍通孔44中的每一者的介電隔離層。根據替代性實施例，不形成包圍通孔44的介電隔離層，且通孔44實體接觸間隙填充材料40。形成通孔44亦包括將導電材料沈積至通孔開口42中(圖4)，以及執行平坦化以移除所沈積材料的位於間隙填充材料40之 上的過量部分。
應知，當製造封裝組件20A及封裝組件20B時，出於測試(探測(probing))目的，可使用金屬接墊32A及金屬接墊32B。根據本發明的一些實施例，在測試之後可不再使用一些金屬接墊32A及金屬接墊32B，且因此相應金屬接墊32A及/或金屬接墊32B之上可能不存在與相應金屬接墊32A及/或金屬接墊32B接觸的任何通孔44。根據該些實施例，做為替代，使用頂部金屬接墊25A及/或頂部金屬接墊25B來與上覆結構連接。根據替代性實施例，使用一些或全部的金屬接墊32A及金屬接墊32B來進行測試及訊號連接二者，且因此如圖5中所示形成通孔44以連接至一些或全部的金屬接墊32A及金屬接墊32B。通孔44亦可包括與金屬接墊32A及/或金屬接墊32B連接的一些通孔44、及與頂部金屬接墊25A及/或頂部金屬接墊25B連接的其他通孔44。
圖6、圖7、及圖8說明用於形成具有精細間距的重佈線的示例性製程。相應步驟被示為圖15中所示製程流程中的步驟212。參照圖6，形成介電層50A及介電層54A以及蝕刻終止層52A。介電層50A及介電層54A可由氧化矽、氮氧化矽、氮化矽、類似材料、或k值低於約3.0的低介電常數介電材料形成。低介電常數介電材料可包括黑金剛石(應用材料公司的註冊商標)、含碳低介電常數介電材料、氫矽倍半氧烷(HSQ)、甲基矽倍半氧烷(MSQ)等。蝕刻終止層52A是由相對於介電層50A及介電層54A具有高蝕刻選擇比(etching selectivity)的材料形成，且可由碳化 矽、碳氮化矽等形成。根據替代性實施例，不形成蝕刻終止層52A。因此，使用虛線說明蝕刻終止層52A以表示可形成或可不形成蝕刻終止層52A。
在介電層50A、蝕刻終止層52A及介電層54A中形成具有精細間距的重佈線56A以進行繞線(routing)。由於根據本發明一些實施例的具有精細間距的重佈線是使用鑲嵌製程形成，因此所述具有精細間距的重佈線可被形成為非常薄的(在俯視圖中為窄的)且所具有的精細間距(從結構的頂部觀察)小於例如0.8微米。根據一些實施例，使用雙重鑲嵌製程(dual damascene process)形成具有精細間距的重佈線56A，所述雙重鑲嵌製程包括蝕刻介電層54A以形成溝渠，以及蝕刻介電層50A及蝕刻終止層52A以形成通孔開口。接著使用導電材料同時填充溝渠及通孔開口。接著執行例如化學機械研磨或機械磨制等平坦化步驟，以移除導電材料中位於介電層54A之上的部分。
圖14說明具有精細間距的重佈線56A中的一者的示例性結構的放大圖，具有精細間距的重佈線56A包括金屬線56A1及位於金屬線56A1之下且連接至金屬線56A1的通孔56A2。金屬線56A1與通孔56A2組合起來包括擴散阻障層46、及位於擴散阻障層46之上的金屬材料48。根據本發明的一些實施例，擴散阻障層46是由鈦、氮化鈦、鉭、或氮化鈦形成。金屬材料48可由銅或銅合金形成。由於雙重鑲嵌結構，因此擴散阻障層46連續地延伸至金屬線56A1及通孔56A2中。
圖7說明介電層50B及介電層54B以及蝕刻終止層52B的形成。介電層50B及介電層54B的材料可選自與用於形成介電層50A及介電層54A的候選材料相同的候選材料，而蝕刻終止層52B的材料可選自與用於形成蝕刻終止層52A的候選材料相同的候選材料。
在介電層50B、蝕刻終止層52B、及介電層54B中亦形成具有精細間距的重佈線56B。具有精細間距的重佈線56B包括形成在介電層54B中的金屬線及形成在介電層50B及蝕刻終止層52B中的通孔。所述形成可包括雙重鑲嵌製程，所述雙重鑲嵌製程包括在介電層54B中形成溝渠以及在介電層50B及蝕刻終止層52B中形成通孔開口，填充導電材料，及接著執行例如機械磨製程或化學機械研磨等平坦化。相似地，具有精細間距的重佈線56B可由包括擴散阻障層及位於所述擴散阻障層之上的含銅材料(與圖14中所示者相似)的複合材料形成。
圖8說明介電層50C及介電層54C、蝕刻終止層52C、及精細間距重佈線56C的形成。形成方法及材料可相似於位於之下的相應層，且因此本文中不再對其予以贅述。此外，根據一些實施例，可省略蝕刻終止層52A、蝕刻終止層52B、及蝕刻終止層52C，且可使用時間模式(time-mode)來執行用於形成溝渠的對應蝕刻以控制所述溝渠的深度。應知，可存在更多用於形成具有精細間距的重佈線的介電層及金屬層。另外，即使可跳過一些或全部的蝕刻終止層52A、蝕刻終止層52B、及蝕刻終止層52C，然 而由於其中具有精細間距的重佈線的介電層是在不同製程中形成，因此無論該些介電層是否由相同介電材料或不同介電材料形成，用於形成具有精細間距的重佈線56A、重佈線56B、及重佈線56C的所述介電層之間仍可能存在可分辨的界面。在隨後的段落中，為使標識簡明起見，將介電層50A、蝕刻終止層52A、介電層54A、介電層50B、蝕刻終止層52B、介電層54B、介電層50C、蝕刻終止層52C、及介電層54C統稱為及各別地稱為介電層58。此外，將具有精細間距的重佈線56A、重佈線56B、及重佈線56C統稱為及各別地稱為具有精細間距的重佈線56。重佈線56B及重佈線56C可具有與圖14中所示重佈線56A相似的雙重鑲嵌結構。
將具有精細間距的重佈線56A、重佈線56B、及重佈線56C對封裝組件20A與封裝組件20B電性內連。由於具有精細間距的重佈線56A、重佈線56B、及重佈線56C的間距非常小，因此可將更多具有精細間距的重佈線56A、重佈線56B、及重佈線56C形成為封裝組件20A與封裝組件20B之間的內連。此會顯著提高具有精細間距的重佈線的密度及繞線能力(routing ability)。
圖9及圖10說明鈍化層及重佈線的形成。相應步驟被示為圖15中所示製程流程中的步驟214。參照圖9，在介電層58之上形成鈍化層60(有時稱為保護-1)。在鈍化層60中形成通孔(via)64，通孔64將具有精細間距的重佈線56C電性連接至上覆金屬接墊。
參照圖10，在鈍化層60之上形成金屬接墊62，並經由 鈍化層60中的通孔64將金屬接墊62電性耦合至精細間距的重佈線56C。金屬接墊62可為鋁接墊或鋁銅接墊，且可使用其他金屬材料。
亦如圖10中所示，在鈍化層60之上形成鈍化層66(有時稱為保護-2)。鈍化層60及鈍化層66中的每一者可為單層或複合層，且可由非多孔性材料形成。根據本發明的一些實施例，鈍化層60及鈍化層66中的一者為複合層，或鈍化層60及鈍化層66二者為複合層。所述複合層包括氧化矽層(圖中未單獨示出)及位於所述氧化矽層之上的氮化矽層(圖中未單獨示出)。鈍化層60及鈍化層66亦可由例如未經摻雜的矽酸鹽玻璃(Un-doped Silicate Glass，USG)、氮氧化矽、及/或類似材料等其他非多孔性介電材料形成。
接下來，如圖11中所示，將鈍化層66圖案化，以使一些鈍化層66部分覆蓋金屬接墊62的邊緣部分，而金屬接墊62的中心部分被鈍化層66中的開口暴露出來。形成凸塊下金屬(under-bump metallurgy，UBM)68，且凸塊下金屬68延伸至鈍化層66中。相應步驟被示為圖15中所示製程流程中的步驟216。凸塊下金屬68可接觸金屬接墊62。根據本發明的一些實施例，凸塊下金屬68中的每一者包括阻障層(圖中未示出)及位於所述阻障層之上的晶種層(圖中未示出)。阻障層可為鈦層、氮化鈦層、鉭層、氮化鉭層、或由鈦合金或鉭合金形成的層。晶種層的材料可包括銅或銅合金。凸塊下金屬68中亦可包含例如銀、金、鋁、 鈀、鎳、鎳合金、鎢合金、鉻、鉻合金、及其組合等其他金屬。根據本發明的一些實施例，凸塊下金屬68可以使用物理氣相沈積(Physical Vapor Deposition，PVD)或其他適用方法來形成。
亦如圖11中所示，形成電性連接件74。相應步驟被示為圖15中所示製程流程中的步驟218。用於形成凸塊下金屬68及電性連接件74的示例性形成製程包括沈積毯覆凸塊下金屬層、形成罩幕(其可為光阻，圖中未示出)及將所述罩幕圖案化，部分的毯覆凸塊下金屬層經由所述罩幕中的開口暴露出來。在形成凸塊下金屬68之後，將所示封裝放置於鍍覆溶液(圖中未示出)中，並執行鍍覆步驟，以在凸塊下金屬68上形成電性連接件74。鍍覆可為電鍍(electro-plating)、無電鍍覆(electroless-plating)、浸鍍(immersion plating)等。根據本發明的一些示例性實施例，電性連接件74包括不會在隨後的回流製程(reflow process)中熔化的非焊料部件70。非焊料部件70可由銅形成，且因此儘管非焊料部件70可由其他非焊料材料形成，在下文中仍將非焊料部件70稱為銅凸塊。電性連接件74中的每一者亦可包括選自鎳層、鎳合金、鈀層、金層、銀層、或其多層形式中的頂蓋層(cap layer)(圖中未示出)。頂蓋層形成於銅凸塊(非焊料部件70)之上。電性連接件74可更包括焊料頂蓋72，焊料頂蓋72可由Sn-Ag合金、Sn-Cu合金、Sn-Ag-Cu合金等形成，且可不含有鉛或可含有鉛。將在前面的步驟中形成的結構稱為複合晶圓76。
對複合晶圓76執行晶粒鋸切步驟(die-saw step)以將複 合晶圓76分隔成多個封裝78。各封裝78彼此相同，且封裝78中的每一者包括封裝組件20A及封裝組件20B二者、基底12、及上覆內連線結構。
圖12說明根據本發明一些實施例形成的封裝78。除在圖12中所示實施例中不形成接合接墊16及接合接墊34以及介電層36A/36B(如圖11中所示)之外，該些實施例與圖11中所示實施例相似。根據本發明的一些實施例，如圖12中所示，塊狀基底12(其亦為空白晶粒)經由熔融接合或黏合而接合至介電層14。已參照圖1B論述了介電層14的形成。根據本發明的一些實施例，介電層14是例如氧化矽層等氧化物系介電層，且將介電層14接合至基底12以及基底22A及基底22B的接合過程可為熔融接合。根據本發明的替代性實施例，介電層14是例如具有高導熱性(例如，高於約1瓦/米．度(W/mk))的熱介面材料等黏合層，且基底12可為玻璃基底或金屬基底。
圖13說明根據本發明一些實施例形成的封裝78。除電性連接件74為焊料區(有時稱為受控塌陷晶片連接(controlled collapse chip connection，C4)凸塊)以外，該些實施例與圖11中所示實施例相似。可形成吸收應力的聚合物層。舉例而言，如圖13中所示，鈍化層66之上形成有聚合物層80。聚合物層80可由聚醯亞胺、聚苯並噁唑、苯並環丁烯等形成。形成方法可包括例如旋轉塗佈(spin coating)。聚合物層80可以可流動形式進行點膠(dispensed)，接著固化。聚合物層80被圖案化成暴露出 金屬接墊62的中心部分。
接下來，形成填充聚合物層80中的開口的鈍化後內連線(Post-Passivation Interconnect，PPI)84。鈍化後內連線84接觸金屬接墊62的頂表面。根據本發明的一些實施例，鈍化後內連線84的形成包括沈積晶種層(圖中未示出)，及接著在所述晶種層之上鍍覆金屬層。晶種層可包括鈦層及位於所述鈦層之上的銅層(鈦層與銅層二者可為共形層)。晶種層可使用物理氣相沈積(Physical Vapor Deposition，PVD)來沈積。位於晶種層之上的所鍍覆導電材料可包括銅層、金層，或者包括銅層及位於所述銅層之上的金層。所述鍍覆可使用例如電化學鍍覆(Electro-Chemical Plating，ECP)或無電(Electro-less，E-less)鍍覆來執行。
接下來，形成覆蓋鈍化後內連線84的聚合物層82。聚合物層82亦可由聚醯亞胺、聚苯並噁唑、苯並環丁烯等形成。接下來，形成凸塊下金屬68，隨後放置焊料球，並接著對所述焊料球進行回流以形成焊料區(電性連接件74)。
圖14說明自圖11、圖12、及圖13中取出的重佈線56A(及具有相似結構的重佈線56B及重佈線56C)中的一者及凸塊下金屬68中的一者的放大圖，為簡潔起見未示出圖11、圖12、及圖13中的其他特徵。應觀察出，擴散阻障層46與凸塊下金屬68二者具有面對同一方向(在圖14中面朝上)的開口，且所述開口面對電性連接件74(圖11、圖12、及圖13)。當將封裝78(圖11、圖12、及圖13)接合至另一裝置(例如裝置晶粒、中介層、 或封裝基底等)時會產生應力，且所述應力自接合點傳遞(propagate)至擴散阻障層46及凸塊下金屬68。由於擴散阻障層46及凸塊下金屬68具有面對應力產生點的開口，因此擴散阻障層46及凸塊下金屬68可更好地吸收應力而不將所述應力繼續傳遞到位於其下方的結構。然而，若擴散阻障層46及凸塊下金屬68中的一者的開口背對電性連接件74，則擴散阻障層46及凸塊下金屬68中相應的一者的應力吸收能力會劣化。
如圖11、圖12、及圖13中所示的封裝78，當具有內建的微通道(微通道18)時，可具有管線(圖中未示出)及冷卻劑，所述管線連接至相對的端部(例如，所示的左端部與右端部)，所述冷卻劑可被傳導至所述微通道中，以將在封裝組件20A及封裝組件20B中產生的熱量傳導走。
根據本發明的一些實施例論述用於三維(three-dimensional，3D)封裝的一些示例性製程及特徵。亦可包括其他特徵及製程。舉例而言，可包括測試結構，以幫助對三維(3D)封裝或三維積體電路(3D integrated circuit，3DIC)裝置進行驗證測試。所述測試結構可例如包括在重佈線層中或在基底上形成的測試接墊，所述測試接墊容許對三維封裝或三維積體電路進行測試、對探針及/或探針卡(probe card)進行使用等。可對中間結構以及最終結構執行驗證測試。另外，本文中所公開的結構及方法可接合包括對已知良好晶粒進行中間驗證的測試方法而使用，以提高良率並降低成本。
本發明的實施例具有一些有利特徵。藉由通常對矽晶圓使用的製程(例如，鑲嵌製程)來形成具有精細間距的重佈線，所述具有精細間距的重佈線可被形成為足夠薄(窄)而使二個或更多個裝置晶粒均藉由所述具有精細間距的重佈線連通。在傳統製程中，使用重佈線在後製程(在裝置接合、模塑、及平坦化之後)達成具有精細間距的重佈線是不可行的。已發現熱膨脹係數不匹配會使具有精細間距的重佈線(如果形成)因應力而斷裂。根據本發明的一些實施例，在具有精細間距重佈線之下方，不使用聚合物或模塑化合物。做為替代，使用例如氧化矽等氧化物系材料。此會顯著減少熱膨脹係數不匹配，並可適用於重佈線在後製程。所述封裝中亦內建有用於達成更好的散熱的一些散熱機構。
根據本發明的一些實施例，一種封裝結構的製造方法包括：將第一裝置晶粒及第二裝置晶粒接合至基底；以及使用間隙填充材料填充第一裝置晶粒與第二裝置晶粒之間的間隙。間隙填充材料的頂部部分覆蓋第一裝置晶粒及第二裝置晶粒。形成穿透間隙填充材料的頂部部分的第一通孔。第一通孔電性耦合至第一裝置晶粒及第二裝置晶粒。所述方法更包括使用鑲嵌製程在間隙填充材料之上形成重佈線；以及在重佈線之上形成電性耦合至所述重佈線的電性連接件。在實施例中，其中所述間隙填充材料括沈積氧化物。在實施例中，所述將第一裝置晶粒及第二裝置晶粒接合至基底包括熔合接合。在實施例中，所述方法包括：形成延伸至基底中的多個第一接合接墊，其中所述基底是空白半導體基 底；以及形成延伸至第一裝置晶粒的半導體基底及第二裝置晶粒的半導體基底中的多個第二接合接墊，其中所述接合更包括將多個第一接合接墊經由金屬-金屬直接接合而接合至所述多個第二接合接墊。在實施例中，所述形成重佈線包括：形成對第一裝置晶粒與第二裝置晶粒進行內連線的多條金屬線及多個第二通孔。在實施例中，在基底與重佈線之間不形成聚合物。在實施例中，所述方法包括將間隙填充材料與基底鋸切至同一封裝中。在實施例中，第一裝置晶粒與第二裝置晶粒二者處於同一封裝中。在實施例中，所述方法包括在基底中形成微通道，其中所述微通道被配置以傳導冷卻劑。在實施例中，所述形成第一通孔包括：蝕刻間隙填充材料及第一裝置晶粒中的鈍化層以形成通孔開口，其中頂部金屬接墊暴露至所述通孔開口，且所述頂部金屬接墊處於所述第一裝置晶粒的低介電常數介電層中；以及使用導電材料填充通孔開口。
根據本發明的一些實施例，一種封裝結構的製造方法包括：將第一裝置晶粒及第二裝置晶粒附接至散熱件；使用介電材料填充第一裝置晶粒與第二裝置晶粒之間的間隙，其中所述介電材料的頂部部分覆蓋所述第一裝置晶粒及所述第二裝置晶粒；形成穿透介電材料的頂部部分的通孔，其中所述通孔電性耦合至第一裝置晶粒及第二裝置晶粒；在介電材料之上形成多個介電層；使用雙重鑲嵌製程在所述多個介電層中形成重佈線；在重佈線之上形成電性連接件，其中所述電性連接件電性耦合至所述重佈 線；以及執行晶粒鋸切來切穿散熱件、介電材料及所述多個介電層，以形成多個封裝。在實施例中，在晶粒鋸切之後，第一裝置晶粒與第二裝置晶粒處於所述多個封裝中的同一封裝中。在實施例中，重佈線是間距小於約0.8微米的精細間距重佈線。在實施例中，散熱件包括玻璃基底或金屬基底，且第一裝置晶粒及第二裝置晶粒經由熱介面材料附接至散熱件。在實施例中，散熱件包括空白塊狀矽基底，且所述方法更包括：形成延伸至所述空白塊狀矽基底中的多個第一接合接墊；以及形成延伸至第一裝置晶粒的半導體基底及第二裝置晶粒的半導體基底中的多個第二接合接墊，其中所述附接包括混合接合。
根據本發明的一些實施例，一種封裝結構包括：空白基底；第一裝置晶粒及第二裝置晶粒，接合至空白基底；間隙填充材料，包括第一部分及第二部分，所述第一部分填充第一裝置晶粒與第二裝置晶粒之間的間隙，所述第二部分覆蓋所述第一裝置晶粒及所述第二裝置晶粒；第一通孔，穿透間隙填充材料的第二部分，以電性耦合至第一裝置晶粒及第二裝置晶粒；多個介電層，位於間隙填充材料之上；以及多條重佈線，位於所述多個介電層中，其中所述多條重佈線包括雙重鑲嵌結構。在實施例中，雙重鑲嵌結構中的一者包括：第二通孔及金屬線，位於所述第一通孔之上且連續地連接至所述第一通孔，其中所述第二通孔及所述金屬線組合起來包括：擴散阻障層，延伸至第二通孔及金屬線二者中；以及含銅材料，位於擴散阻障層之上。在實施例中，所述裝 置更包括：第一介電層，位於空白基底的表面上；第二介電層，位於第一裝置晶粒的表面上，其中第一介電層經由介電質-介電質接合而接合至所述第二介電層；第一金屬接墊，位於第一介電層中；以及第二金屬接墊，位於第二介電層中，其中第一金屬接墊經由金屬-金屬接合而接合至所述第二金屬接墊。在實施例中，所述裝置包括間隙填充材料是氧化物。在實施例中，所述裝置包括在空白基底與所述多個介電層之間不存在聚合物。
根據本發明的一些實施例，一種封裝結構包括：散熱件；第一氧化物層，位於散熱件之上；第一裝置晶粒，位於散熱件之上且經由第一氧化物層接合至散熱件；介電間隙填充材料，包圍第一裝置晶粒；多個低介電常數介電層，位於介電間隙填充材料之上；多條金屬線及多個通孔，位於所述多個低介電常數介電層中，其中所述多條金屬線及所述多個通孔電性連接至第一裝置晶粒；以及多個焊料區，位於所述多條金屬線及所述多個通孔之上且電性耦合至所述多條金屬線及所述多個通孔。在實施例中，所述多條金屬線及所述多個通孔包括雙重鑲嵌結構。在實施例中，介電間隙填充材料更包括與第一裝置晶粒交疊的頂部部分，且所述裝置更包括導電通孔，所述導電通孔穿透所述介電間隙填充材料的所述頂部部分以電性耦合至所述第一裝置晶粒。在實施例中，所述裝置更包括：第二氧化物層，位於散熱件之上；以及第二裝置晶粒，位於散熱件之上且經由第二氧化物層接合至所述散熱件，其中所述多條金屬線及所述多個通孔將第一裝置晶粒與所 述第二裝置晶粒電性地相互耦合。在實施例中，所述裝置更包括：第三氧化物層，位於第一裝置晶粒的表面上，其中所述第三氧化物層接合至第一氧化物層。在實施例中，所述裝置更包括：第一接合接墊，延伸至第一氧化物層中；以及第二接合接墊，延伸至第三氧化物層中，其中第一接合接墊進一步接合至所述第二接合接墊。在實施例中，第一接合接墊進一步延伸至散熱件中。在實施例中，第一裝置晶粒包括半導體基底，且第二接合接墊進一步延伸至所述半導體基底中。在實施例中，第一接合接墊及第二接合接墊中的每一者形成格柵。
根據本發明的一些實施例，一種封裝結構包括：散熱件；第一裝置晶粒及第二裝置晶粒，位於散熱件之上且附接至所述散熱件；介電間隙填充材料，第一裝置晶粒及第二裝置晶粒包封於所述介電間隙填充材料中；通孔，穿透介電間隙填充材料以電性耦合至第一裝置晶粒及第二裝置晶粒；多條重佈線，位於通孔之上且電性耦合至所述通孔，其中所述重佈線包括雙重鑲嵌結構；以及多個電性連接件，電性耦合至所述多條重佈線。在實施例中，散熱件包含半導體材料。在實施例中，第一裝置晶粒包括半導體基底，且其中第一裝置晶粒經由金屬接墊接合至散熱件，且所述金屬接墊延伸至第一裝置晶粒的半導體基底中。在實施例中，散熱件是由金屬形成。在實施例中，通孔接觸第一裝置晶粒的鋁接墊。在實施例中，通孔中的一者接觸第一裝置晶粒的頂部金屬接墊，且所述頂部金屬接墊處於低介電常數介電層中。
根據本發明的一些實施例，一種封裝結構的製造方法包括：將第一裝置晶粒及第二裝置晶粒接合至空白基底；形成氧化物層，以填充第一裝置晶粒與第二裝置晶粒之間的間隙；在氧化物層之上形成重佈線，其中第一裝置晶粒及第二裝置晶粒藉由重佈線而電性地相互耦合；在重佈線之上形成電性耦合至所述重佈線的電性連接件；以及鋸切穿過空白基底及氧化物層以形成多個封裝，其中所述第一裝置晶粒及所述第二裝置晶粒處於所述多個封裝中的一者中。在實施例中，所述接合包括熔融接合。在實施例中，所述接合更包括金屬-金屬直接接合。在實施例中，藉由熱介面材料來執行所述接合。在實施例中，空白基底為半導體基底，在半導體基底上不形成主動裝置。
以上概述了若干實施例的特徵，以使熟習此項技術者可更佳地理解本發明的各個態樣。熟習此項技術者應知，其可容易地使用本發明做為設計或修改其他製程及結構的基礎來施行與本文中所介紹的實施例相同的目的及/或達成與本文中所介紹的實施例相同的優點。熟習此項技術者亦應認識到，該些等效構造並不悖離本發明的精神及範圍，而且他們可在不悖離本發明的精神及範圍的條件下對其作出各種改變、代替、及變更。

Claims (13)

  1. 一種封裝結構的製造方法，包括：將第一裝置晶粒及第二裝置晶粒接合至基底；使用間隙填充材料填充所述第一裝置晶粒與所述第二裝置晶粒之間的間隙，其中所述間隙填充材料的頂部部分覆蓋所述第一裝置晶粒及所述第二裝置晶粒，且所述間隙填充材料為單層；形成穿透所述間隙填充材料的所述頂部部分的第一通孔，其中所述第一通孔電性耦合至所述第一裝置晶粒及所述第二裝置晶粒；使用鑲嵌製程在所述間隙填充材料之上形成重佈線，其中所述形成所述重佈線包括：形成內連所述第一裝置晶粒與所述第二裝置晶粒的多條金屬線及多個第二通孔，其中所述多個第二通孔位於所述第一通孔上且所述多個第二通孔的一者直接接觸所述第一通孔；以及在所述重佈線之上形成電性耦合至所述重佈線的電性連接件。
  2. 如申請專利範圍第1項所述的封裝結構的製造方法，其中所述間隙填充材料包括沈積氧化物；或其中在所述基底與所述重佈線之間無聚合物形成；或所述封裝結構的製造方法更包括在所述基底中形成微通道，其中所述微通道被配置以傳導冷卻劑。
  3. 如申請專利範圍第1項所述的封裝結構的製造方法，其中所述將所述第一裝置晶粒及所述第二裝置晶粒接合至所述基底包括熔合接合。
  4. 如申請專利範圍第3項所述的封裝結構的製造方法，更包括：形成延伸至所述基底中的第一多個接合接墊，其中所述基底是空白半導體基底；以及形成延伸至所述第一裝置晶粒的半導體基底及所述第二裝置晶粒的半導體基底中的第二多個接合接墊，其中所述接合更包括將所述多個第一接合接墊經由金屬-金屬直接接合而接合至所述第二多個接合接墊。
  5. 如申請專利範圍第1項所述的封裝結構的製造方法，更包括將所述間隙填充材料與所述基底鋸切至同一封裝中。
  6. 如申請專利範圍第5項所述的封裝結構的製造方法，其中所述第一裝置晶粒與所述第二裝置晶粒二者在所述同一封裝中。
  7. 如申請專利範圍第1項所述的封裝結構的製造方法，其中所述形成所述第一通孔包括：蝕刻所述間隙填充材料及所述第一裝置晶粒中的鈍化層，以形成通孔開口，其中頂部金屬接墊暴露於所述通孔開口，且所述頂部金屬接墊位於所述第一裝置晶粒的低介電常數介電層中；以及以導電材料填充所述通孔開口。
  8. 一種封裝結構的製造方法，包括：將第一裝置晶粒及第二裝置晶粒附接至散熱件；以介電材料填充所述第一裝置晶粒與所述第二裝置晶粒之間的間隙，其中所述介電材料的頂部部分覆蓋所述第一裝置晶粒及所述第二裝置晶粒，且所述介電材料為單層；形成穿透所述介電材料的所述頂部部分的第一通孔，其中所述第一通孔電性耦合至所述第一裝置晶粒及所述第二裝置晶粒；在所述介電材料之上形成多個介電層；使用雙重鑲嵌製程在所述多個介電層中形成重佈線，其中所述形成所述重佈線包括：形成內連所述第一裝置晶粒與所述第二裝置晶粒的多條金屬線及多個第二通孔，其中所述多個第二通孔位於所述第一通孔上且所述多個第二通孔的一者直接接觸所述第一通孔；在所述重佈線之上形成電性連接件，其中所述電性連接件電性耦合至所述重佈線；以及執行晶粒鋸切來切穿所述散熱件、所述介電材料及所述多個介電層，以形成多個封裝。
  9. 如申請專利範圍第8項所述的封裝結構的製造方法，其中在所述晶粒鋸切之後，所述第一裝置晶粒與所述第二裝置晶粒在所述多個封裝中的同一封裝中；或其中所述重佈線是間距小於約0.8微米的精細間距重佈線；或其中所述散熱件包括玻璃基底或金屬基底，且所述第一裝置晶粒及所述第二裝置晶粒經由熱介面材料附接至所述散熱件；或其中所述散熱件包括空白塊狀矽基底，且所述方法更包括形成延伸至所述空白塊狀矽基底中的多個第一接合接墊，以及形成延伸至所述第一裝置晶粒的半導體基底及所述第二裝置晶粒的半導體基底中的多個第二接合接墊，其中所述附接包括混合接合。
  10. 一種封裝結構，包括：空白基底；第一裝置晶粒及第二裝置晶粒，接合至所述空白基底；單層的間隙填充材料，包括：第一部分，填充所述第一裝置晶粒與所述第二裝置晶粒之間的間隙；以及第二部分，覆蓋所述第一裝置晶粒及所述第二裝置晶粒；第一通孔，穿透所述間隙填充材料的所述第二部分，以電性耦合至所述第一裝置晶粒及所述第二裝置晶粒；多個介電層，位於所述間隙填充材料之上；以及多條重佈線，位於所述多個介電層中，其中所述多條重佈線包括雙重鑲嵌結構，所述雙重鑲嵌結構中的一者包括第二通孔及金屬線，所述第二通孔位於所述第一通孔之上且直接接觸所述第一通孔。
  11. 如申請專利範圍第10項所述的封裝結構，其中所述第二通孔及所述金屬線組合起來包括：擴散阻障層，延伸至所述第二通孔及所述金屬線二者中；以及含銅材料，位於所述擴散阻障層之上。
  12. 如申請專利範圍第10項所述的封裝結構，更包括：第一介電層，位於所述空白基底的表面上；第二介電層，位於所述第一裝置晶粒的表面上，其中所述第一介電層經由介電質-介電質接合而接合至所述第二介電層；第一金屬接墊，位於所述第一介電層中；以及第二金屬接墊，位於所述第二介電層中，其中所述第一金屬接墊經由金屬-金屬接合而接合至所述第二金屬接墊。
  13. 如申請專利範圍第10項所述的封裝結構，其中所述間隙填充材料是氧化物；或其中在所述空白基底與所述多個介電層之間不存在聚合物。
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