CN109148308B - 封装件及其形成方法 - Google Patents

封装件及其形成方法 Download PDF

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Publication number
CN109148308B
CN109148308B CN201711274600.7A CN201711274600A CN109148308B CN 109148308 B CN109148308 B CN 109148308B CN 201711274600 A CN201711274600 A CN 201711274600A CN 109148308 B CN109148308 B CN 109148308B
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device die
forming
substrate
dielectric
metal
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CN109148308A (zh
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陈明发
余振华
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一种方法包括将第一器件管芯和第二器件管芯接合至衬底，以及用间隙填充材料填充第一器件管芯和第二器件管芯之间的间隙。间隙填充材料的顶部覆盖第一器件管芯和第二器件管芯。形成通孔以穿过间隙填充材料的顶部。通孔电连接至第一器件管芯和第二器件管芯。该方法还包括使用镶嵌工艺在间隙填充材料上方形成再分布线，以及在再分布线上方形成电连接至再分布线的电连接件。本发明的实施例还涉及封装件及其形成方法。

Description

封装件及其形成方法
技术领域
本发明的实施例涉及封装件及其形成方法。
背景技术
随着更多的器件管芯封装在相同的封装件中以实现更多的功能，集成电路的封装件变得越来越复杂。例如，封装件可以包括接合至相同的中介层的诸如处理器和存储器数据集的多个器件管芯。可以基于半导体衬底形成中介层，其中硅通孔形成在半导体衬底中以互连形成在中介层的相对侧上的部件。模塑料将器件管芯包封在其中。包括中介层和器件管芯的封装件进一步接合至封装衬底。此外，表面安装器件也可以接合至衬底。散热器可以附接至器件管芯的顶面以消散器件管芯中产生的热量。散热器可以具有固定在封装衬底上的裙部(skirt portion)。
发明内容
本发明的实施例提供了一种形成封装件的方法，包括：将第一器件管芯和第二器件管芯接合至衬底；用间隙填充材料填充所述第一器件管芯和所述第二器件管芯之间的间隙，其中，所述间隙填充材料的顶部覆盖所述第一器件管芯和所述第二器件管芯；形成通孔，所述通孔穿过所述间隙填充材料的顶部，其中，所述通孔电连接至所述第一器件管芯和所述第二器件管芯；使用镶嵌工艺在所述间隙填充材料上方形成再分布线；以及在所述再分布线上方形成电连接至所述再分布线的电连接件。
本发明的另一实施例提供了一种形成封装件的方法，包括：将第一器件管芯和第二器件管芯附接至散热器；用介电材料填充所述第一器件管芯和所述第二器件管芯之间的间隙，其中，所述介电材料的的顶部覆盖所述第一器件管芯和所述第二器件管芯；形成穿过所述介电材料的顶部的通孔，其中，所述通孔电连接至所述第一器件管芯和所述第二器件管芯；在所述介电材料上方形成多个介电层；使用双镶嵌工艺在所述多个介电层中形成再分布线；在所述再分布线上方形成电连接至所述再分布线的电连接件；以及实施管芯锯切以割穿所述散热器、所述介电材料和所述多个介电层以形成多个封装件。
本发明的又一实施例提供了一种封装件器件，包括：空白衬底；第一器件管芯和第二器件管芯，接合至所述空白衬底；间隙填充材料，包括：第一部分，填充所述第一器件管芯和所述第二器件管芯之间的间隙；以及第二部分，覆盖所述第一器件管芯和所述第二器件管芯；通孔，穿过所述间隙填充材料的第二部分以电连接至所述第一器件管芯和所述第二器件管芯；多个介电层，位于所述间隙填充材料上方；以及多条再分布线，位于所述多个介电层中，其中，所述多条再分布线包括双镶嵌结构。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本发明的各个方面。应该指出，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1A和图1B至图11示出了根据一些实施例的在使用再分布线(RDL)后工艺形成封装件中的中间阶段的截面图。
图12至图13示出了根据一些实施例的使用RDL后工艺形成的一些封装件的截面图。
图14示出了根据一些实施例的封装件中的双镶嵌结构和凸块下金属(UBM)。
图15示出了根据一些实施例的用于形成封装件的工艺流程。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实施例中重复参考标号和/或字符。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为便于描述，在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等空间相对术语，以描述如图所示的一个元件或部件与另一个(或另一些)原件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上)，而本文使用的空间相对描述符可以同样地作出相应的解释。
根据各个示例性实施例提供了基于再分布线(RDL)后工艺形成的封装件及其形成方法。根据一些实施例，示出了形成封装件的中间阶段。讨论了实施例的一些变化。贯穿各个视图和说明性实施例，相同的数字用于表示相同的元件。
图1A和图1B至图11示出了根据一些实施例的在使用RDL后工艺形成封装件中的中间阶段的截面图。图1A和图1B至图11中示出的步骤也在图15中示出的工艺流程200中示意性地反映。
图1A示出了晶圆10。晶圆10包括块状衬底12，块状衬底12可以是硅衬底、玻璃衬底或金属衬底。晶圆10可以具有典型的半导体晶圆的形状。例如，晶圆10可以具有圆形顶视形状，并且可以具有8英寸直径、12英寸直径等。当由金属形成时，衬底12可以由铜、铝、不锈钢等形成。根据本发明的一些实施例，在晶圆10中不存在有源器件(诸如晶体管和二极管)和无源器件(诸如电容器、电感器和电阻器)。晶圆10具有两个功能。首先，由于随后接合的器件管芯非常薄以具有良好的间隙填充，晶圆10为将在随后的步骤中形成的结构提供机械支撑。而且，衬底12可以具有高导热性，并且因此晶圆10可以用作散热器。
介电层14可以形成在衬底12的表面处。相应的步骤示出为图15中示出的工艺流程中的步骤202。介电层14可以由氧化硅形成，例如，可以通过在含氧环境中氧化衬底12来形成。可选地，通过在水蒸气中氧化衬底12形成介电层14。根据本发明的一些实施例，通过诸如氧化硅(可以由正硅酸乙酯(TEOS))的氧化物、氮氧化硅等的沉积形成介电层14。根据本发明的的一些实施例，在介电层14中形成接合焊盘16。相应的步骤示出为图15中示出的工艺流程中的步骤204。根据本发明的的一些实施例，接合焊盘16的底面可以与介电层14的示出的底面共面。根据本发明的的可选实施例，接合焊盘16延伸至衬底12中，并且使用虚线示出了衬底12中的接合焊盘16的部分以表明接合焊盘16可以或可以不延伸至衬底12中。
为了形成接合焊盘16，通过蚀刻介电层14和衬底12形成沟槽(示出为由接合焊盘16填充)，使得沟槽也延伸至介电层14和衬底12中。取决于衬底12的厚度，衬底12内的沟槽的部分的深度D1可以大于约1μm，并且可以介于约2μm和约20μm之间。例如，深度D1可以介于约衬底12的厚度的约20％和约60％之间。应该理解，整个说明书中列举的值是实例，并且可以改变为不同的值。
如图1A所示，然后填充沟槽以形成接合焊盘16。应该理解，虽然部件16称为接合焊盘，但是部件16可以是离散的焊盘或互连金属线。根据一些实施例，接合焊盘16由适合于混合接合的铜或其他金属形成(由于相对容易扩散)。在填充之后，实施平坦化以平坦化接合焊盘16的顶面和介电层14的顶面。平坦化可以包括化学机械抛光(CMP)工艺或机械研磨工艺。
沟槽(以及产生的接合焊盘16)可以以各种图案分布。例如，沟槽可以形成为离散的开口，其可以布置成阵列、蜂窝图案或其他重复图案。沟槽的顶视形状可以是矩形、方形、圆形、六边形等。根据本发明的可选实施例，当从图1A中示出的结构的顶视图中观察时，沟槽可以是在单个方向上延伸的平行沟槽。沟槽也可以互连以形成栅格。栅格可以包括彼此平行并且均匀或不均匀间隔开的多个第一沟槽、以及彼此平行并且均匀或不均匀间隔开的多个第二沟槽。多个第一沟槽和多个第二沟槽彼此截断以形成栅格，并且多个第一沟槽和多个第二沟槽在顶视图中可以或可以不彼此垂直。
根据本发明的可选实施例，在介电层14和衬底12中不形成金属接合焊盘。因此，如图1B所示，衬底12是由均匀材料(半导体、玻璃或金属)形成的空白衬底，并且介电层14是毯状平坦层。
根据本发明的一些实施例，在衬底12中形成微沟槽18。微沟槽18是空隙，其中，诸如油、水、气体等的冷却剂可以在微沟槽18中流动。微沟槽18的形成可以包括蚀刻第一衬底(诸如图1A中的衬底12A)以形成微沟槽，以及用另一衬底(诸如衬底12B)覆盖微沟槽以密封微沟槽18，其中，在衬底12B中形成开口15以连接至微沟槽18。使用虚线示出微沟槽18以表明可以或可以不形成微沟槽18。
参照图2，封装组件20A和20B接合至晶圆10。相应的步骤示出为图15中示出的工艺流程中的步骤206。封装组件20A和20B可以是器件管芯或封装件。根据本发明的一些实施例，封装组件20A和20B包括一个或多个逻辑管芯，其可以选自中央处理单元(CPU)管芯、微控制单元(MCU)管芯、输入输出(IO)管芯、基带(BB)管芯或应用处理器(AP)管芯。封装组件20A和20B也可以包括一个或多个存储器管芯。作为实例，在随后的讨论中，封装组件20A和20B称为器件管芯，然而它们可以是诸如封装件、管芯堆叠件、存储器数据集等的其他类型的器件。而且，虽然封装组件20A和20B示出为具有相同的结构，它们可以具有不同的电路、不同的尺寸、不同的厚度和/或可以包括其中的不同数量的器件管芯。
器件管芯20A和20B分别包括半导体衬底22A和22B，半导体衬底22A和22B可以是硅衬底。而且，器件管芯20A和20B可以分别包括用于连接至器件管芯20A和20B中的有源器件和无源器件的互连结构24A和24B。互连结构24A和24B包括金属线和通孔(未示出)。此外，可以使用具有低于约3.0、低于约2.5或甚至更低的介电常数(k值)的低k介电材料形成介电层，在介电层中形成互连结构24A和24B的金属线和通孔。介电材料可以由Black Diamond(应用材料公司的注册商标)、含碳低k介电材料、氢倍半硅氧烷(HSQ)、甲基倍半硅氧烷(MSQ)等形成。根据本发明的可选实施例，互连结构24A和24B中的介电层由诸如氧化硅或氮氧化硅的氧化物基介电材料形成。
互连结构24A和24B分别包括金属焊盘25A和25B，金属焊盘25A和25B位于互连结构的顶部金属层中。钝化层28A和28B(可选地称为钝化-1)可以分别形成在互连结构24A和24B上面。根据本发明的一些实施例，钝化层28A和28B由诸如氧化硅或氮化硅的无机介电材料形成，并且可以具有单层结构或复合结构。例如，复合结构可以包括氧化硅层和位于氧化硅层上方的氮化硅层。金属焊盘32A和32B分别形成在钝化层28A和28B上方，并且通过分别形成在钝化层28A和28B中的通孔26A和26B连接至下面的器件。
根据本发明的一些实施例，金属焊盘32A和32B由铝或铝铜形成，并且因此有时称为铝焊盘。在金属焊盘32A和32B上方形成钝化层30A和30B(可选地称为钝化-2)，可以使用选自用于形成钝化层28A和28B的相同的候选材料的材料形成钝化层30A和30B。
器件管芯20A可以包括位于器件管芯20A的示出的底面处的接合焊盘34和介电层36A。接合焊盘34的示出的底面与介电层36A的示出的底面共面。器件管芯20B可以包括位于示出的底面处的接合焊盘34和介电层36B。接合焊盘34的示出的底面与介电层36B的示出的底面共面。介电层36A/36B和接合焊盘34的形成工艺可以分别类似于介电层14和接合焊盘16的形成。例如，介电层36A和36B可以由氧化硅或诸如氮氧化硅的其他含氧介电材料形成。接合焊盘34的图案和横向尺寸可以与相应的接合焊盘16的图案和横向尺寸相同或类似，接合焊盘34接合至接合焊盘16。有利地，通过接触(或甚至插入)衬底22A和22B，接合焊盘34提供良好的散热路径，使得器件管芯20A和20B中生成的热量可以通过接合焊盘16容易地散发至块状衬底12。
例如，器件管芯20A和20B是薄管芯，厚度介于约15μm和约30μm之间。由于器件管芯20A和20B薄，相邻的器件管芯20A和20B之间的间隙38的高宽比保持较低，以获得良好的间隙填充。否则，由于高的高宽比，间隙填充较难。
可以通过混合接合实现器件管芯20A和20B与下面的结构的接合。例如，接合焊盘34通过金属至金属直接接合而接合至接合焊盘16。根据本发明的一些实施例，金属至金属直接接合是铜至铜直接接合。此外，例如，介电层36A和36B通过Si-O-Si键接合至介电层14。混合接合可以包括预接合和之后的退火，使得接合焊盘34中的金属与相应的下面的接合焊盘16中的金属相互扩散以形成金属至金属直接接合。
根据可选实施例，如图1B所示，在晶圆10中未形成接合焊盘。因此，也没有形成如图2所示的接合焊盘34，并且通过熔融接合(电介质至电介质接合)将器件管芯20A和20B接合至介电层14。
根据本发明的可选实施例，衬底12是玻璃衬底或金属衬底。因此，层14可以由热界面材料(TIM)形成，热界面材料是具有高导热性的粘合剂。器件管芯20A和20B因此通过TIM14粘合至衬底12(参照图12)。根据这些实施例，可以不形成图2中的介电层36A和36B，并且可以或可以不形成接合焊盘34。
接下来，如图3所示，通过间隙填充材料40填充间隙38。相应的步骤示出为图15中示出的工艺流程中的步骤208。根据本发明的一些实施例，间隙填充材料40包括无机电介质，其可以是诸如氧化硅的氧化物基电介质。例如，氧化硅可以由TEOS形成。形成方法可以包括化学气相沉积(CVD)、高密度等离子体化学气相沉积(HDPCVD)等。根据本发明的一些实施例，间隙填充材料40是非聚合物材料，其不包括诸如聚苯并恶唑(PBO)、聚酰亚胺、苯并环丁烯(BCB)等的聚合物。聚合物具有与器件管芯显著不同的热膨胀系数(CTE)，并且将导致产生的封装件的翘曲以及形成随后的细间距RDL中的困难。
然后实施平坦化步骤以去除间隙填充材料40的过量部分，使得间隙填充材料40的顶面变得平坦。间隙填充材料40的顶层直接位于器件管芯20A和20B上方。在产生的结构中，间隙填充材料40可以与介电层14的顶面接触，并且环绕器件管芯20A和20B的每个。此外，间隙填充材料40可以与钝化层30A和30B的顶面接触。
根据本发明的一些实施例，在图3中示出的结构中不存在聚合物层(诸如聚酰亚胺、PBO、BCB、模塑料、底部填充物、模制底部填充物等)。例如，器件管芯20A和20B没有聚合物层，并且下面的晶圆10也没有聚合物。因此，图3中示出的结构没有CTE失配问题，CTE失配问题是由于聚合物和硅/氧化硅等之间的显著不同之间的差别引起的。因此，使用用于形成器件晶圆中的互连结构的工艺(诸如镶嵌工艺)和材料(诸如铜和/或低k电介质)在图3中示出的结构上方形成细间距RDL是可行的。
参照图4，蚀刻间隙填充材料40与钝化层30A和30B以形成通孔开口42。根据本发明的一些实施例，金属焊盘32A和32B暴露于通孔开口42。根据本发明的可选实施例，通孔开口42的一些或所有还穿过钝化层28A和28B，使得一些顶部金属焊盘25A和25B暴露于通孔开口42。根据本发明的可选实施例，顶部金属焊盘25A和/或25B暴露于通孔开口42的一些，而金属焊盘32A和/或32B暴露于一些其他通孔开口42。通孔开口42的顶视形状可以并且不限于矩形、圆形、六边形等。
接下来，用导电材料填充通孔开口42以形成通孔44，并且图5中示出了产生的结构。相应的步骤示出为图15中示出的工艺流程中的步骤210。根据本发明的一些实施例，通孔44由均匀的导电材料形成，其可以是包括铜、铝、钨等的金属或金属合金。根据本发明的可选实施例，通孔44具有复合结构，复合结构包括有钛、氮化钛、钽、氮化钽等形成的导电阻挡层以及位于导电阻挡层上方的含金属材料(诸如铜或铜合金)。根据本发明的一些实施例，形成介电隔离层以环绕每个通孔44。根据可选实施例，未形成围绕通孔44的介电隔离层，并且通孔44与间隙填充材料40物理接触。通孔44的形成也包括在通孔开口42(图4)中沉积导电材料，以及实施平坦化以去除位于间隙填充材料40上方的沉积的材料的过量部分。
应该理解，当制造器件管芯20A和20B时，金属焊盘32A和32B可以用于测试(探测)目的。根据本发明的一些实施例，在测试之后，可以不再使用一些金属焊盘32A和32B，并且因此可能不存在位于相应的金属焊盘32A和/或32B上方并且与相应的金属焊盘32A和/或32B接触的任何通孔44。根据这些实施例，顶部金属焊盘25A和/或25B代替用于连接至上面的结构。如图5所示，根据可选实施例，金属焊盘32A和32B的一些或所有用于测试和信号连接，并且因此形成连接至金属焊盘32A和32B的通孔44。通孔44也可以包括连接至金属焊盘32A和/或32B的一些通孔44以及连接至顶部金属焊盘25A和/或25B的其他通孔44。
图6、图7和图8示出了用于形成细间距RDL的示例性工艺。相应的步骤示出为图15中示出的工艺流程中的步骤212。参照图6，形成介电层50A和54A以及蚀刻停止层52A。介电层50A和54A可以由氧化硅、氮氧化硅、氮化硅等或具有小于约3.0的k值的低k介电材料形成。低k介电材料可以包括Black Diamond(应用材料公司的注册商标)、含碳低k介电材料、氢倍半硅氧烷(HSQ)、甲基倍半硅氧烷(MSQ)等。蚀刻停止层52A由相对于介电层50A和54A具有高蚀刻选择性的材料形成，并且可以由碳化硅、碳氮化硅等形成。根据可选实施例，未形成蚀刻停止层52A。因此，使用虚线示出蚀刻停止层52A以表明它可以或可以不形成。
细间距RDL56A形成在介电层52A和54A中用于路由。由于使用镶嵌工艺形成根据本发明的一些实施例的细间距RDL，细间距RDL可以形成为非常薄(顶视图中为窄)，细间距(从结构的顶部观察)小于例如0.8μm。根据一些实施例，使用双镶嵌工艺形成细间距RDL56A，该双镶嵌工艺包括蚀刻介电层54A以形成沟槽，以及蚀刻介电层50A和52A以形成通孔开口。然后同时用导电材料填充沟槽和通孔开口。然后实施诸如CMP或机械研磨的平坦化步骤以去除位于介电层54A上方的导电材料的部分。
图14示出了细间距RDL56A的一个的示例性结构的放大视图，细间距RDL56A包括金属线56A1以及位于金属线56A1下面并且连接至金属线56A1的通孔56A2。金属线56A1和通孔56A2的组合包括扩散阻挡层46和位于扩散阻挡层46上方的金属材料48。根据本发明的一些实施例，扩散阻挡层46由钛、氮化钛、钽或氮化钽形成。金属材料48可以由铜或铜合金形成。由于双镶嵌结构，扩散阻挡层46连续地延伸至金属线56A1和通孔56A2。
图7示出了介电层50B和54B以及蚀刻停止层52B的形成。介电层50B和54B的材料可以选自与用于形成介电层50A和54A的候选材料相同的材料，并且蚀刻停止层52B的材料可以选自与用于形成蚀刻停止层52A的候选材料相同的材料。
细间距RDL56B也形成在介电层50B、52B和54B中。细间距RDL56B包括形成在介电层54B中的金属线以及形成在介电层50B和52B中的通孔。该形成可以包括双镶嵌工艺，双镶嵌工艺包括在介电层54B中形成沟槽和在介电层50B和52B中形成通孔开口，填充导电材料，以及然后实施诸如机械研磨或CMP的平坦化。类似地，细间距RDL56B可以由复合材料形成，复合材料包括与图14中示出的类似的扩散阻挡层以及位于扩散阻挡层上方的含铜材料。
图8示出了介电层50C和54C、蚀刻停止层52C和细间距RDL56C的形成。形成方法和材料可以类似于下面的相应的层，并且因此在本文中不再重复。而且，根据一些实施例，可以省略蚀刻停止层52A、52B和52C，并且可以使用时间模式实施用于形成沟槽的相应的蚀刻以控制沟槽的深度。应该理解，可以存在为细间距RDL形成的更多的介电层和金属层。此外，即使可以跳过蚀刻停止层52A、52B和52C的一些或全部，由于细间距RDL所在的介电层在不同的工艺中形成，在用于形成细间距RDL56A、56B和56C的介电层之间可以存在可区分的界面，不论这些介电层由相同的介电材料还是由不同的介电材料形成。在随后的段落中，为了识别的简化，介电层50A、52A、54A、50B、52B、54B、50C、52C和54C共同地和单独地称为介电层58。细间距RDL56A、56B和56C也共同地和单独地称为细间距RDL56。RDL56B和56C可以具有与图14中示出的RDL56A类似的双镶嵌结构。
细间距RDL56A、56B和56C电互连器件管芯20A和20B。由于细间距RDL56A、56B和56C的间距非常小，可以形成更多的细间距RDL56A、56B和56C作为器件管芯20A和20B之间的互连件。这显著改进了细间距RDL的密度和路由能力。
图9和图10示出了钝化层和RDL的形成。相应的步骤示出为图15中示出的工艺流程中的步骤214。参照图9，在介电层58上方形成钝化层60(有时称为钝化-1)，其中，通孔64形成在钝化层60中以将细间距RDL56C电连接至上面的金属焊盘。
参照图10，金属焊盘62形成在钝化层60上方，并且通过钝化层60中的通孔64电连接至细间距RDL56C。金属焊盘62可以是铝焊盘或铝-铜焊盘，并且可以使用其他金属材料。
也如图10所示，在钝化层60上方形成钝化层66(有时称为钝化-2)。钝化层60和66的每个可以是单层或复合层，并且可以由无孔材料形成。根据本发明的一些实施例，钝化层60和66的一个或两个是复合层，该复合层包括氧化硅层(未单独示出)和位于氧化硅层上方的氮化硅层(未单独示出)。钝化层60和66也可以由其他无孔介电材料形成，诸如未掺杂的硅酸盐玻璃(USG)、氮氧化硅等。
接下来，如图11所示，图案化钝化层66，使得钝化层66的一些部分覆盖金属焊盘62的边缘部分，并且通过钝化层66中的开口暴露金属焊盘62的中心部分。形成凸块下金属(UBM)68，并且UBM68延伸至钝化层66中。相应的步骤示出为图15中示出的工艺流程中的步骤216。UBM68可以与金属焊盘62接触。根据本发明的一些实施例，UBM68的每个包括阻挡层(未示出)和位于阻挡层上方的晶种层(未示出)。阻挡层可以是钛层、氮化钛层、钽层、氮化钽层或由钛合金或钽合金形成的层。晶种层的材料可以包括铜或铜合金。诸如银、金、铝、钯、镍、镍合金、钨合金、铬、铬合金和它们的组合的其他金属也可以包括在UBM68中。根据本发明的一些实施例，使用物理气相沉积(PVD)或其他适用的方法形成UBM68。
也如图11所示，形成电连接件74。相应的步骤示出为图15中示出的工艺流程中的步骤218。用于UBM68和电连接件74的示例性形成工艺包括沉积毯状UBM层，形成和图案化掩模(掩模可以是光刻胶，未示出)，其中毯状UBM层的部分通过掩模中的开口暴露。在形成UBM68之后，将示出的封装件放置在镀溶液(未示出)中，并且实施镀步骤以在UBM68上形成电连接件74。镀可以是电镀、化学镀、浸没镀等。根据本发明的一些示例性实施例，电连接件74包括非焊料部70，非焊料部70在随后的回流工艺中不熔化。非焊料部70可以由铜形成，并且因此此后称为铜凸块70，但是它们可以由其他非焊料材料形成。电连接件74的每个也可以包括选自镍层、镍合金、钯层、金层、银层或它们的多层的覆盖层(未示出)。覆盖层形成在铜凸块70上方。电连接件74还可以包括焊帽72，焊帽72可以由Sn-Ag合金、Sn-Cu合金、Sn-Ag-Cu合金等形成并且可以是无铅的或含铅的。在前述步骤中形成的结构称为复合晶圆76。
对复合晶圆76实施管芯锯切步骤以将复合晶圆76分割成多个封装件78。封装件78彼此相同，并且每个封装件78包括器件管芯20A和20B、一块衬底12和上面的互连结构。
图12示出了根据本发明的一些实施例形成的封装件78。这些实施例类似于图11中示出的实施例，除了在图12中示出的实施例中未形成接合焊盘16和34以及介电层36A/36B(如图11所示)。根据本发明的一些实施例，如图12所示，块状衬底12(也是空白管芯)通过熔融接合或粘合剂接合至介电层14。介电层14的形成已经参照图1B进行讨论。根据本发明的一些实施例，层14是诸如氧化硅的氧化物基介电层，并且层14与衬底12和衬底22A和22B的接合可以是熔融接合。根据本发明的可选实施例，层14是诸如TIM的粘合膜，TIM具有高导热性(例如，高于约1W/mk)，并且衬底12可以是玻璃衬底或金属衬底。
图13示出了根据本发明的一些实施例形成的封装件78。这些实施例类似于图11中示出的实施例，除了电连接件74是焊料区(有时称为C4凸块)。可以形成聚合物层以吸收应力。例如，如图13所示，在钝化层66上方形成聚合物层80。聚合物层80可以由聚酰亚胺、PBO、BCB等形成。例如，形成方法可以包括旋涂。聚合物层80可以以可流动形式分配，并且然后固化。图案化聚合物层80以暴露金属焊盘62的中心部分。
接下来，形成钝化后互连件(PPI)84以填充聚合物层80中的开口。PPI84与金属焊盘62的顶面接触。根据本发明的一些实施例，PPI84的形成包括沉积晶种层(未示出)，以及然后在晶种层上方镀金属层。晶种层可以包括钛层和位于钛层上方的铜层(均可以是共形层)。可以使用物理气相沉积(PVD)沉积晶种层。位于晶种层上方的镀的导电材料可以包括铜层、金层、或铜层与位于铜层上方的金层。可以使用例如电化学镀(ECP)或化学镀(非E)镀实施镀。
接下来，形成聚合物层82以覆盖PPI84。聚合物层82也可以由聚酰亚胺、PBO、BCB等形成。接下来，形成UBM68，随后放置焊料球，以及然后回流焊料球以形成焊料区74。
图14示出了从图11、图12和图13提取的RDL56A(和具有类似结构的RDL56B和56C)的一个和UBM68的一个的放大图，为了简化，未示出图11、图12和图13中的其他部件。观察到，扩散阻挡层46和UBM68均具有面向相同方向的开口(图14中的向上)，并且开口面向电连接件74(图11、图12和图13)。当封装件78(图11、图12和图13)接合至诸如器件管芯、中介层或封装衬底的另一器件时生成应力，并且应力从接点传播至扩散阻挡层46和UBM68。由于扩散阻挡层46和UBM68具有面向应力生成点的开口，扩散阻挡层46和UBM68可以更好地吸收应力，而不将应力向下传递至下面的结构。然而，如果扩散阻挡层46和UBM68的一个具有面向远离电连接件74的开口，扩散阻挡层46和UBM68的相应的一个的应力吸收能力降低。
当具有内置微沟道18时，如图11、图12和图13所示的封装件78可以具有连接至相对端(诸如示出的左端和右端)的管(未示出)，并且冷却剂可以传导至微沟道以传导走器件管芯20A和20B中生成的热量。
根据本发明的一些实施例讨论了用于三维(3D)封装的一些示例性工艺和部件。也可以包括其他部件和工艺。例如，可以包括测试结构以辅助3D封装或3DIC器件的验证测试。例如，测试结构可以包括形成在再分布层中或衬底上的测试焊盘，测试焊盘允许3D封装或3DIC的测试、探针和/或探针卡的使用等。可以对互连结构以及最终结构实施验证测试。此外，本文公开的结构和方法可以与测试方法结合使用，这结合已知良好管芯的中间验证以增加良率并且减少成本。
本发明的实施例具有以下有利特征。通过使用常用于硅晶圆的工艺(诸如镶嵌工艺)形成细间距RDL，细间距RDL可以形成为足够薄(窄)以为两个或多个器件管芯的通信提供可能性，所有均通过细间距RDL。在传统工艺中，使用RDL后工艺(在器件接合之后，模制和平坦化)形成细间距RDL是不可行的。已经发现，由于应力，CTE失配引起细间距RDL(如果形成)断裂。根据本发明的一些实施例，在细间距RDL下面不使用聚合物或模塑料。相反，使用诸如氧化硅的氧化物基材料。这显著地减小CTE失配，并且使RDL后工艺成为可能。在封装件中也构建了一些散热机制以更好地散热。
根据本发明的一些实施例，一种方法包括将第一器件管芯和第二器件管芯接合至衬底，以及用间隙填充材料填充第一器件管芯和第二器件管芯之间的间隙。间隙填充材料的顶部覆盖第一器件管芯和第二器件管芯。形成通孔以穿过间隙填充材料的顶部。通孔电连接至第一器件管芯和第二器件管芯。该方法还包括使用镶嵌工艺在间隙填充材料上方形成再分布线，以及在再分布线上方形成电连接至再分布线的电连接件。在方法中，填充间隙包括沉积氧化物。在实施例中，将第一器件管芯和第二器件管芯接合至衬底包括熔融接合。在实施例，该方法包括形成延伸至衬底的第一多个接合焊盘，其中，衬底是空白半导体衬底；以及形成延伸至第一器件管芯和第二器件管芯的半导体衬底的第二多个接合焊盘，其中，该接合还包括通过金属至金属直接接合来接合第一多个接合焊盘和第二多个接合焊盘。在实施例中，形成再分布线包括形成互连第一器件管芯和第二器件管芯的多条金属线和通孔。在实施例中，在衬底和再分布线之间不形成聚合物。在实施例中，该方法包括将间隙填充材料和衬底锯切成相同的封装件。在实施例中，第一器件管芯和第二器件管芯位于相同的封装件中。在实施例中，该方法包括在衬底中形成微沟道，其中，微沟道配置为传导冷却剂。在实施例中，形成通孔包括蚀刻间隙填充材料和第一器件管芯中的钝化层以形成通孔开口，其中，顶部金属焊盘暴露于通孔开口，并且顶部金属焊盘位于第一器件管芯的低k介电层中；以及用导电材料填充通孔开口。
根据本发明的一些实施例，一种方法包括将第一器件管芯和第二器件管芯附接至散热器；用介电材料填充第一器件管芯和第二器件管芯之间的间隙，其中，介电材料的的顶部覆盖第一器件管芯和第二器件管芯；形成穿过介电材料的顶部的通孔，其中，通孔电连接至第一器件管芯和第二器件管芯；在介电材料上方形成多个介电层；使用双镶嵌工艺在多个介电层中形成再分布线；在再分布线上方形成电连接至再分布线的电连接件；以及实施管芯锯切以割穿散热器、介电材料和多个介电层以形成多个封装件。在实施例中，在管芯锯切之后，第一器件管芯和第二器件管芯位于多个封装件中的相同的封装件中。在实施例中，再分布线是间距小于约0.8μm的细间距RDL。在实施例中，散热器包括玻璃衬底或金属衬底，并且第一器件管芯和第二器件管芯通过热界面材料附接至散热器。在实施例中，散热器包括空白块状硅衬底，并且该方法还包括：形成延伸至空白块状硅衬底的第一多个接合焊盘，以及形成延伸至第一器件管芯和第二器件管芯的半导体衬底的第二多个接合焊盘，其中，附接包括混合接合。
根据本发明的一些实施例，一种器件包括：空白衬底；第一器件管芯和第二器件管芯，接合至空白衬底；间隙填充材料包括：第一部分，填充第一器件管芯和第二器件管芯之间的间隙；以及第二部分，覆盖第一器件管芯和第二器件管芯；通孔，穿过间隙填充材料的第二部分以电连接至第一器件管芯和第二器件管芯；多个介电层，位于间隙填充材料上方；以及多条再分布线，位于多个介电层中，其中，多条再分布线包括双镶嵌结构。在实施例中，器件包括双镶嵌结构的一个，双镶嵌结构包括：通孔以及位于通孔上方并且连续地连接至通孔的金属线，其中，通孔和金属线的组合包括：扩散阻挡层，延伸至通孔和金属线；以及含铜材料，位于扩散阻挡层上方。在实施例中，该器件还包括：第一介电层，位于空白衬底的表面上；第二介电层，位于第一器件管芯的表面上，其中，第一介电层通过电介质至电介质接合而接合至第二介电层；第一金属焊盘，位于第一介电层中，以及第二金属焊盘，位于第二介电层中，其中，第一金属焊盘通过金属至金属接合而接合至第二金属焊盘。在实施例中，该器件包括间隙填充材料，为氧化物。在实施例中，该器件在空白衬底和多个介电层之间不存在聚合物。
根据本发明的一些实施例，一种器件包括：散热器；第一氧化物层，位于散热器中；第一器件管芯，位于散热器上方并且通过第一氧化物层接合至散热器；介电间隙填充材料，环绕第一器件管芯；多个低k介电层，位于介电间隙填充材料上方；多条金属线和通孔，位于多个低k介电层中，其中，多条金属线和通孔电连接至第一器件管芯；以及多个焊料区，位于多条金属线和通孔上方并且电连接至多条金属线和通孔。在实施例中，器件包括的多条金属线和通孔包括双镶嵌结构。在实施例中，该器件包括的介电间隙填充材料还包括顶部，与第一器件管芯重叠，并且该器件还包括穿过介电间隙填充材料的顶部的导电通孔以电连接至第一器件管芯。在实施例中，该器件还包括：第二氧化物层，位于散热器上方；以及第二器件管芯，位于散热器上方并且通过第二氧化物层接合至散热器，其中，多条金属线和通孔电互连第一器件管芯和第二器件管芯。在实施例中，该器件还包括：第三氧化物层，位于第一器件管芯的表面上，其中，第三氧化物层接合至第一氧化物层。在实施例中，该器件还包括：第一接合焊盘，延伸至第一氧化物层；以及第二接合焊盘，延伸至第三氧化物层，其中，第一接合焊盘还接合至第二接合焊盘。在实施例中，该器件包括的第一接合焊盘还延伸至散热器。在实施例中，该器件包括的第一器件管芯包括半导体衬底，并且第二接合焊盘还延伸至半导体衬底中。在实施例中，该器件包括的第一接合焊盘和第二接合焊盘的每个形成栅格。
根据本发明的一些实施例，一种器件包括：散热器；第一器件管芯和第二器件管芯，位于散热器上方并且附接至散热器；介电间隙填充材料，将第一器件管芯和第二器件管芯包封在其中；通孔，穿过介电间隙填充材料以电连接至第一器件管芯和第二器件管芯；多条再分布线，位于通孔上方并且电连接至通孔，其中，再分布线包括双镶嵌结构；以及多个电连接件，电连接至多条再分布线。在实施例中，器件包括的散热器包括半导体材料。在实施例中，器件包括的第一器件管芯包括半导体衬底，并且其中，第一器件管芯通过金属焊盘接合至散热器，并且金属焊盘延伸至第一器件管芯的半导体衬底中。在实施例中，器件包括的散热器由金属形成。在实施例中，器件包括的通孔与第一器件管芯的铝焊盘接触。在实施例中，器件包括的通孔的一个与第一器件管芯的顶部金属焊盘接触，并且顶部金属焊盘位于低k介电层中。
根据本发明的一些实施例，一种方法包括将第一器件管芯和第二器件管芯接合至空白衬底；形成氧化物层以填充第一器件管芯和第二器件管芯之间的间隙；在氧化物层上方形成再分布线，其中，第一器件管芯和第二器件管芯通过再分布线电互连；在再分布线上方形成电连接至再分布线的电连接件；以及切穿空白衬底和氧化物层以形成多个封装件，其中，第一器件管芯和第二器件管芯位于多个封装件的一个中。在实施例中，接合包括熔融接合。在实施例中，该接合还包括金属至金属直接接合。在实施例中，通过热界面材料实施接合。在实施例中，空白衬底是半导体衬底，在半导体衬底上未形成有源器件。
上面概述了若干实施例的特征，使得本领域技术人员可以更好地理解本发明的方面。本领域技术人员应该理解，他们可以容易地使用本发明作为基础来设计或修改用于实施与本文所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，本文中他们可以做出多种变化、替换以及改变。

Claims (20)

1.一种形成封装件的方法，包括：
形成延伸至空白衬底的第一多个接合焊盘；
形成延伸至第一器件管芯和第二器件管芯的半导体衬底的第二多个接合焊盘；
将所述第一器件管芯和所述第二器件管芯分别接合至所述空白衬底，其中，所述接合包括通过金属至金属直接接合来接合所述第一多个接合焊盘和所述第二多个接合焊盘；
用间隙填充材料填充所述第一器件管芯和所述第二器件管芯之间的间隙，其中，所述间隙填充材料的顶部覆盖所述第一器件管芯和所述第二器件管芯；
形成通孔，所述通孔穿过所述间隙填充材料的顶部，其中，所述通孔电连接至所述第一器件管芯和所述第二器件管芯；
使用镶嵌工艺在所述间隙填充材料上方形成再分布线；以及
在所述再分布线上方形成电连接至所述再分布线的电连接件，
其中，所述间隙填充材料是非聚合物。
2.根据权利要求1所述的方法，其中，填充所述间隙包括沉积氧化物。
3.根据权利要求1所述的方法，其中，将所述第一器件管芯和所述第二器件管芯接合至所述空白衬底还包括熔融接合。
4.根据权利要求3所述的方法，其中，所述空白衬底是空白半导体衬底。
5.根据权利要求1所述的方法，其中，形成所述再分布线包括形成互连所述第一器件管芯和所述第二器件管芯的多条金属线和通孔。
6.根据权利要求1所述的方法，其中，所述空白衬底是玻璃或金属衬底。
7.根据权利要求1所述的方法，还包括将所述间隙填充材料和所述空白衬底锯切成相同的封装件。
8.根据权利要求7所述的方法，其中，所述第一器件管芯和所述第二器件管芯位于所述相同的封装件中。
9.根据权利要求1所述的方法，还包括在所述空白衬底中形成微沟道，其中，所述微沟道配置为传导冷却剂。
10.根据权利要求1所述的方法，形成所述通孔包括：
蚀刻所述间隙填充材料和所述第一器件管芯中的钝化层以形成通孔开口，其中，顶部金属焊盘暴露于所述通孔开口，并且所述顶部金属焊盘位于所述第一器件管芯的低k介电层中；以及
用导电材料填充所述通孔开口。
11.一种形成封装件的方法，包括：
形成延伸至空白块状硅衬底的第一多个接合焊盘；以及
形成延伸至第一器件管芯和第二器件管芯的半导体衬底的第二多个接合焊盘；
将所述第一器件管芯和所述第二器件管芯分别附接至所述空白块状硅衬底，其中，所述附接包括通过金属至金属直接接合来接合所述第一多个接合焊盘和所述第二多个接合焊盘；
用介电材料填充所述第一器件管芯和所述第二器件管芯之间的间隙，其中，所述介电材料的顶部覆盖所述第一器件管芯和所述第二器件管芯；
形成穿过所述介电材料的顶部的通孔，其中，所述通孔电连接至所述第一器件管芯和所述第二器件管芯；
在所述介电材料上方形成多个介电层；
使用双镶嵌工艺在所述多个介电层中形成再分布线；
在所述再分布线上方形成电连接至所述再分布线的电连接件；以及
实施管芯锯切以割穿所述空白块状硅衬底、所述介电材料和所述多个介电层以形成多个封装件，
其中，所述介电材料是非聚合物。
12.根据权利要求11所述的方法，在所述管芯锯切之后，所述第一器件管芯和所述第二器件管芯位于所述多个封装件中的相同的封装件中。
13.根据权利要求11所述的方法，其中，所述再分布线是间距小于0.8μm的细间距再分布线。
14.根据权利要求11所述的方法，其中，所述第一器件管芯和所述第二器件管芯还通过熔融接合附接至所述空白块状硅衬底。
15.根据权利要求11所述的方法，其中，所述空白块状硅衬底包括没有有源器件形成在其上的半导体衬底。
16.一种封装件器件，包括：
空白衬底；
第一多个接合焊盘，延伸至所述空白衬底内部；
第一器件管芯和第二器件管芯，分别接合至所述空白衬底；
第二多个接合焊盘，延伸至所述第一器件管芯和所述第二器件管芯的半导体衬底的内部，其中，所述第一器件管芯和所述第二器件管芯通过所述第二多个接合焊盘与所述第一多个接合焊盘的金属至金属直接接合而接合至所述空白衬底；
间隙填充材料，包括：
第一部分，填充所述第一器件管芯和所述第二器件管芯之间的间隙；以及
第二部分，覆盖所述第一器件管芯和所述第二器件管芯；
通孔，穿过所述间隙填充材料的第二部分以电连接至所述第一器件管芯和所述第二器件管芯；
多个介电层，位于所述间隙填充材料上方；以及
多条再分布线，位于所述多个介电层中，其中，所述多条再分布线包括双镶嵌结构，
其中，所述间隙填充材料是非聚合物。
17.根据权利要求16所述的封装件器件，其中，所述双镶嵌结构的一个包括：
通孔和金属线，所述金属线位于所述通孔上方并且连续地连接至所述通孔，其中，所述通孔和所述金属线的组合包括：
扩散阻挡层，延伸至所述通孔和所述金属线；以及
含铜材料，位于所述扩散阻挡层上方。
18.根据权利要求16所述的封装件器件，还包括：
第一介电层，位于所述空白衬底的表面上；
第二介电层，位于所述第一器件管芯的表面上，其中，所述第一介电层通过电介质至电介质接合而接合至所述第二介电层；
其中，所述第一多个接合焊盘位于所述第一介电层中，所述第二多个接合焊盘位于所述第二介电层中。
19.根据权利要求16所述的封装件器件，其中，所述间隙填充材料为氧化物。
20.根据权利要求16所述的封装件器件，其中，所述空白衬底是其中没有形成有源器件的玻璃或金属衬底。
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