CN109524314B - 封装件及其形成方法 - Google Patents

封装件及其形成方法 Download PDF

Info

Publication number
CN109524314B
CN109524314B CN201711279542.7A CN201711279542A CN109524314B CN 109524314 B CN109524314 B CN 109524314B CN 201711279542 A CN201711279542 A CN 201711279542A CN 109524314 B CN109524314 B CN 109524314B
Authority
CN
China
Prior art keywords
dielectric
forming
device die
dielectric layers
dielectric layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201711279542.7A
Other languages
English (en)
Other versions
CN109524314A (zh
Inventor
余振华
叶松峯
陈明发
陈宪伟
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority to CN202011247925.8A priority Critical patent/CN112509931A/zh
Publication of CN109524314A publication Critical patent/CN109524314A/zh
Application granted granted Critical
Publication of CN109524314B publication Critical patent/CN109524314B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/30—Structure, shape, material or disposition of the layer connectors prior to the connecting process of a plurality of layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H01L2221/68331—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding of passive members, e.g. die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0233—Structure of the redistribution layers
    • H01L2224/02333—Structure of the redistribution layers being a bump
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02379—Fan-out arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08135—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/08145—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/8038—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/80399—Material
    • H01L2224/804—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/80417—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/80424—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/8038—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/80399—Material
    • H01L2224/804—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/80438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/80447—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/8038—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/80399—Material
    • H01L2224/804—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/80463—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/80484—Tungsten [W] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808—Bonding techniques
    • H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H01L2224/80895—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81417—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/81424—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/81447—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81463—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/81484—Tungsten [W] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H01L2224/83896—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically insulating surfaces, e.g. oxide or nitride layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本申请的实施例提供了一种形成封装件的方法，包括：形成多个介电层；在多个介电层中形成多个再分布线；在多个介电层中形成堆叠通孔，其中，堆叠通孔形成贯穿多个介电层的连续的电连接件；在堆叠通孔和多个介电层上方形成介电层；在介电层中形成多个接合焊盘；以及通过混合接合将器件管芯接合至介电层和多个接合焊盘的第一部分。本申请的实施例还提供了另一种形成封装件的方法以及一种封装件。

Description

封装件及其形成方法
技术领域
本申请的实施例涉及半导体领域，并且更具体地，涉及封装件及其形成方法。
背景技术
集成电路的封装件变得越来越复杂，在同一封装件中封装了更多的器件管芯以实现更多的功能。例如，封装件可以包括多个器件管芯，诸如接合至同一中介层的处理器和存储器立方体。可以基于半导体衬底形成中介层，其中在半导体衬底中形成硅贯通孔以互连在中介层的相对侧上形成的部件。模塑料封装其中的器件管芯。包括中介层的封装件和器件管芯进一步接合至封装衬底。另外，表面安装器件也可以被接合至衬底。散热器可以附接至器件管芯的顶面以消散器件管芯中产生的热量。散热器可以具有固定在封装衬底上的裙部。
发明内容
根据本申请的实施例，提供了一种形成封装件的方法，包括：形成多个介电层；在多个介电层中形成多个再分布线；在多个介电层中形成堆叠通孔，其中，堆叠通孔形成贯穿多个介电层的连续的电连接件；在堆叠通孔和多个介电层上方形成介电层；在介电层中形成多个接合焊盘；以及通过混合接合将第一器件管芯接合至介电层和多个接合焊盘的第一部分。
根据本申请的实施例，提供了一种形成封装件的方法，包括：形成多个介电层；在多个介电层中的每个中形成多个再分布线；在多个介电层中形成无源器件；形成贯穿多个介电层的第一介电贯通孔和第二介电贯通孔；在多个介电层上方形成介电层；在介电层中形成多个接合焊盘并且电耦接至第一介电贯通孔、第二介电贯通孔、以及多个再分布线；以及通过混合接合将第一器件管芯和第二器件管芯接合至介电层和多个接合焊盘，其中，第一器件管芯和第二器件管芯通过多个再分布线电互连，以及第一器件管芯和第二器件管芯分别连接到第一介电贯通孔和第二介电贯通孔。
根据本申请的实施例，提供了一种封装件，包括：多个介电层；在多个介电层中的每个中的多个再分布线；贯穿多个介电层中的介电贯通孔，其中，介电贯通孔具有贯穿多个介电层的基本上笔直的边缘；在多个介电层中的堆叠通孔，其中，堆叠通孔彼此电连接以形成贯穿多个介电层的连续的电连接件；在介电贯通孔和多个再分布线上方的并且连接至介电贯通孔和多个再分布线的多个接合焊盘；第一介电层，多个接合焊盘位于第一介电层中；以及接合至第一介电层和多个接合焊盘的第一部分的第一器件管芯。
附图说明
当结合附图进行阅读时，根据下面详细的描述可以最佳地理解本发明的方面。应该强调的是，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各种部件的尺寸可以被任意增加或减少。
图1至图27A示出根据一些实施例的无硅衬底(无Si)封装件的形成中的中间阶段的横截面图。
图27B、图27C、图27D、和图27E示出根据一些实施例的无Si封装件的横截面图。
图28至图32示出根据一些实施例的无Si封装件的形成中的中间阶段的横截面图。
图33至图35示出根据一些实施例的无Si封装件的形成中的中间阶段的横截面图。
图36和图37示出根据一些实施例的嵌入无Si封装件的封装件的横截面图。
图38示出根据一些实施例的在无Si封装件中使用的自对准金属焊盘的一些顶视图。
图39示出根据一些实施例的用于形成封装件的工艺流程。
具体实施方式
以下公开内容提供了许多不同实施例或实例，用于实现本发明的不同特征。以下描述组件和布置的具体实例以简化本发明。当然，这些仅仅是实例而不旨在限制。例如，在以下描述中，在第二部件上方或上形成第一部件可以包括第一部件和第二部件直接接触的实施例，也可以包括形成在第一部件和第二部件之间的附加部件使得第一部件和第二部件不直接接触的实施例。而且，本发明在各个实例中可以重复参考数字和/或字母。这种重复仅是为了简明和清楚，其自身并不表示所论述的各个实施例和/或配置之间的关系。
而且，为了便于描述，在此可以使用诸如“在...下面”、“在...下方”、“下部”、“在...上面”、“上部”等空间相对术语以描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外，空间相对位置术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定位(旋转90度或在其他方位)，并且在本文中使用的空间关系描述符可以同样地作相应地解释。
根据各种示例性实施例，提供了一种基于无硅衬底(无Si)中介层形成的封装件及其形成方法。根据一些实施例示出了形成封装件的中间阶段。讨论一些实施例的一些变型。贯穿各个视图和说明性实施例，相同的参考标号用于指定相同的元件。
图1至图27A示出了根据本公开的一些实施例的封装件的形成中的中间阶段的横截面图。图1至图27A中所示的步骤也在图39中所示的工艺流程300中示意性地反映。
图1示出了载体20和在载体20上形成的释放层22。载体20可以是玻璃载体、硅晶圆、有机载体等。载体20可具有圆形的顶视形状，并且可具有常用的硅晶圆的尺寸。例如，载体20可以具有8英寸的直径、12英寸的直径等。释放层22可以由光热转换(LTHC)材料形成，其可以与载体20一起从将在随后步骤中形成的上面的结构去除。根据本公开的一些实施例，释放层22由环氧树脂基热释放材料形成。释放层22可被涂覆至载体20上。释放层22的顶面是平坦的并且具有高度共面性。根据可选实施例，代替使用载体20和释放层22，使用标记为23的硅晶圆。在释放层22上形成介电层24。根据本公开的一些实施例，介电层24是由可以是氧化硅、氮化硅、氮氧化硅等非聚合物(无机材料)形成。当使用硅晶圆时，可以在硅晶圆23上直接形成层24。
在介电层24上形成再分布线(RDL)26。RDL 26的形成可以包括在介电层24上方形成晶种层(未示出)，在晶种层上方形成诸如光刻胶的图案化掩模(未示出)，以及然后在暴露的晶种层上执行金属电镀。然后去除图案化掩模和晶种层的由图案化掩模覆盖的部分，从而留下如图1中的RDL 26。根据本公开的一些实施例，晶种层包括钛层和位于钛层上方的铜层。可以使用，例如，物理汽相沉积(PVD)形成晶种层。可以使用，例如，化学电镀执行电镀。
进一步参考图1，在RDL 26上形成介电层28。介电层28的底面与RDL26和介电层24的顶面接触。根据本公开的一些实施例，介电层28是由可以是氧化硅、氮化硅等非聚合物(无机材料)形成的。根据本发明的一些实施例，介电层28由可以是聚酰亚胺、聚苯并恶唑(PBO)等的聚合物形成。然后，图案化介电层28以在其中形成开口30。因此，通过介电层28中的开口30暴露出RDL 26的一些部分。
接下来，参考图2，形成RDL 32以连接至RDL 26。RDL 32包括介电层28上方的金属迹线(金属线)。RDL 32还包括延伸至介电层28中的开口中的通孔。RDL 32也在电镀工艺中形成，其中RDL 32中的每个均包括晶种层(未示出)和晶种层上方的电镀的金属材料。晶种层和电镀的材料可以由相同材料或不同材料形成。RDL 32可包括金属或金属合金，包括铝、铜、钨、或它们的合金。用于形成介电层28和介电层34以及RDL 32和RDL 36的步骤被表示为如图39所示的工艺流程300中的步骤302。
参考图3，在RDL 32和介电层28上方形成介电层34。介电层34可以由无机材料形成，无机材料可以选自氧化硅、氮化硅、碳氮化硅、氮氧化硅等。
图3还示出了电连接至RDL 32的RDL 36的形成。RDL 36的形成可采用与用于形成RDL 32的方法和材料类似的方法和材料。可以理解，尽管在说明性的示例性实施例中讨论了在其中形成的两个介电层28和34以及各自的RDL 32和RDL 36，但是取决于布线要求和使用用于缓冲应力的聚合物的要求，可以采用更少或更多的介电层。例如，可以存在单个介电层或三个、四个、或更多个介电层。
图4示出了钝化层38和钝化层42以及RDL 40和RDL 44的形成。相应的步骤被示出为图39中示出的工艺流程300中的步骤304。根据本公开的一些实施例，钝化层38和钝化层42由诸如氧化硅、氮化硅、碳氮化硅、氮氧化硅、碳氧氮化硅、未掺杂硅酸盐玻璃(USG)、或其多层的无机材料形成。钝化层38和钝化层42中的每个可以是单层或复合层，并且可以由无孔材料形成。根据本公开的一些实施例，钝化层38和钝化层42中的一者或两者是包括氧化硅层(未单独示出)和氧化硅层上方的氮化硅层(未单独示出)的复合层。钝化层38和钝化层42具有阻挡湿气和有害化学物质进入封装件中的诸如微间距(fine-pitch)RDL的导电部件的功能，如将在随后的段落中讨论的。
RDL 40和RDL 44可以由铝、铜、铝铜、镍、或其合金形成。根据本公开的一些实施例，RDL 44的一些部分被形成为足够大以用于附着随后形成的介电贯通孔(TDV)的金属焊盘，如图11所示。因此，根据一些实施例，这些金属焊盘被称为金属焊盘44或铝焊盘44。另外，钝化层的数量可以是诸如一、二(如图所示)、三或更多的任何整数。
图5示出了一个或多个介电层的形成。例如，如图所示，可以形成介电层46以将顶部RDL 44嵌入其中。在介电层46上方形成介电层48，并且介电层48可以用作蚀刻停止层。根据本公开的一些实施例，介电层46和介电层48也可以被替换为单一介电层。介电层46和介电层48的可用材料包括氧化硅、氮化硅、碳化硅、氮氧化硅等。
图6、图7、和图8示出了根据本公开的一些实施例的介电层和微间距RDL的形成。相应的步骤被示出为图39中示出的工艺流程300中的步骤306。形成方法可以采用基于硅衬底的用于形成器件管芯的互连结构的方法。例如，互连结构的形成方法可以包括单镶嵌和/或双镶嵌工艺。因此，所得到的RDL也可以可选地被称为金属线和通孔，并且相应的介电层可选地被称为金属间介电(IMD)层。
参考图6，形成通孔55、介电层50A和介电层54A、以及蚀刻停止层52A。介电层50A和介电层54A可以由氧化硅、氮氧化硅、氮化硅等、或k值低于约3.0的低k介电材料形成。低k介电材料可以包括Black Diamond(应用材料公司的注册商标)、含碳低k介电材料、氢倍半硅氧烷(HSQ)、甲基倍半硅氧烷(MSQ)等。蚀刻停止层52A由具有相对于介电层50A和介电层54A较高蚀刻选择性的材料形成，并且可由碳化硅、碳氮化硅等形成。根据可选实施例，不形成蚀刻停止层52A。
在介电层52A和介电层54A中形成微间距RDL 56A用于布线。尽管在一些示例性实施例中，通孔55和微间距RDL 56A被示为具有单一镶嵌结构，但是通孔55和微间距RDL 56A组合可以具有双镶嵌结构。可以理解，单个示出的微间距RDL 56A表示多个微间距RDL。由于根据本公开的一些实施例使用镶嵌工艺形成微间距RDL，因此其可以以小于，例如，0.8μm的间距(从结构的顶部来看)非常薄地形成。另外，由于介电层34、介电层38、介电层42、介电层46、和介电层48都可以由无机材料形成，所以微间距RDL的间距和宽度可以是较小的。如果介电层28也由无机材料形成，那么微间距RDL的间距和宽度可以进一步减小，从而在双镶嵌结构下面不存在聚合物层。这明显提高了微间距RDL的密度和布线能力。根据其中使用双镶嵌工艺形成通孔55和微间距RDL 56A的本公开的一些实施例，形成工艺包括蚀刻介电层48和介电层50A以形成通孔开口并且蚀刻介电层50A和介电层52A以形成沟槽，用导电材料填充通孔开口和沟槽，以及执行诸如化学机械抛光(CMP)或机械研磨的平面化以去除介电层上方的导电材料的部分。
根据本公开的一些实施例，用于形成通孔55和微间距RDL 56A的导电材料是均质材料。根据本公开的其它实施例，导电材料是包括由钛、氮化钛、钽、氮化钽等形成的阻挡层，以及在阻挡层上方的含铜材料(其可以是铜或铜合金)的复合材料。
图7示出了介电层50B和介电层54B以及蚀刻停止层52B的形成。介电层50B和介电层54B的材料可以从用于形成介电层50A和介电层54A的相同候选材料中选择，并且可以从用于形成蚀刻停止层52A的相同候选材料中选择蚀刻停止层52B的材料。
也在介电层50B、介电层52B、和介电层54B中形成微间距RDL 56B。微间距RDL 56B包括在介电层54B和介电层52B中形成的金属线以及介电层50B中的通孔。该形成可以包括双镶嵌工艺，其包括在介电层54B和介电层52B中形成沟槽并且在介电层50B中形成通孔开口，填充导电材料，并且然后执行诸如机械研磨或化学机械抛光(CMP)的平面化。类似地，微间距RDL 56B可以由均质材料形成，或者可以由包括阻挡层和在阻挡层上方的含铜材料的复合材料形成。
图8示出了介电层50C和介电层54C、蚀刻停止层52C、和微间距RDL56C的形成。形成方法和材料可以与下面的相应层相似，并且因此这里不再重复。另外，根据本公开的一些实施例，可以省略蚀刻停止层52A、蚀刻停止层52B、和蚀刻停止层52C，并且可以使用时间模式来执行用于形成沟槽的相应蚀刻以控制沟槽的深度。可以理解的是，可以形成更多的介电层和微间距RDL的层。另外，即使蚀刻停止层52A、蚀刻停止层52B、和蚀刻停止层52C的一些或全部可以被跳过，由于在不同的工艺中形成其中存在微间距RDL的介电层，因此可以具有在用于形成微间距RDL 56A、微间距RDL 56B、和微间距RDL 56C的介电层之间的可区分的界面，无论这些介电层是否是由相同的介电材料或不同的介电材料形成。在随后的段落中，为了简化识别，介电层50A、介电层52A、介电层54A、介电层50B、介电层52B、介电层54B、介电层50C、介电层52C、和介电层54C被共同且单独地称为介电层58。微间距RDL 56A、微间距RDL56B、和微间距RDL 56C也被共同且单独地称为微间距RDL 56。
根据本公开的一些实施例，在形成微间距RDL 56的同时形成无源器件61。因此，无源器件61被嵌入到介电层58中。无源器件61可以是电容器、电感器、射频(RF)传输线、变压器、或者这些器件的组合。无源器件61电耦接到随后接合的器件管芯。
另外，在形成微间距RDL 56的同时，还形成堆叠通孔67，每个堆叠通孔67包括被堆叠以形成贯穿介电层58的连接结构的多个双镶嵌结构(并且可以包括或不包括单镶嵌结构)。组合的堆叠通孔67具有与如图10所示的介电贯通孔(TDV)62相似的功能。形成堆叠的通孔是有利的，因为它们是使用双镶嵌工艺形成的，并且在双镶嵌结构中可以具有与金属线一样小的宽度。
堆叠通孔67也可以用于布线。例如，RDL 56中的部分56D被示意性地示出以显示为了布线目的，金属线可以同时形成为堆叠通孔67。因此，堆叠通孔67可以侧向电连接至其他电气组件。可以在微间距RDL 56的任何金属层中形成布线金属线。
参考图9，介电层48和介电层58被蚀刻以形成介电贯通孔(TDV)开口60。相应的步骤被示出为图39中示出的工艺流程300中的步骤308。金属焊盘44暴露于TDV开口60。通孔开口60的顶视图形状可以为矩形、圆形、六边形等。
接下来，用导电材料填充TDV开口60以形成TDV 62，并且所得到的结构如图10所示。相应的步骤被示出为图39中示出的工艺流程300中的步骤310。根据本公开的一些实施例，TDV 62由均匀的导电材料形成，所述导电材料可以是金属或金属合金，包括铜、铝、钨等。根据本公开的可选实施例，TDV 62具有包括由钛、氮化钛、钽、氮化钽等形成的导电阻挡层以及阻挡层上方的含金属材料的复合结构。根据本公开的一些实施例，形成介电隔离层以环绕每个TDV 62。根据可选的实施例，不形成环绕TDV62的介电隔离层，并且TDV 62与介电层58物理接触。TDV 62的形成还包括将导电材料沉积到TDV开口60(图9)中，并且执行平坦化以去除介电层58上方的沉积材料的多余部分。由于难以形成贯穿具有不同蚀刻特性的多个介电层58和介电层48的深开口60(图9)，TDV 62可具有比堆叠通孔67更大的宽度。TDV62的电阻较低。因此，由于TDV 62的数量少，TDV 62可以用于传导电力，而由TDV 62占据的面积不显著。组合堆叠通孔67和TDV 62可以增加信号连接件的数量(使用堆叠通孔67)，同时仍然可以使用宽TDV 62来服务低损耗功率传输。根据一些实施例，不形成TDV 62。
图11示出了接合焊盘66和介电层64的形成，并且接合焊盘66位于介电层64中。相应的步骤被示出为图39中示出的工艺流程300中的步骤312。接合焊盘66可以由易于形成混合接合的金属形成。根据本公开的一些实施例，接合焊盘66由铜或铜合金形成。例如，介电层64可以由氧化硅形成。接合焊盘66和介电层64的顶面共平面。例如，可以通过诸如CMP或机械研磨步骤的平坦化步骤实现平坦性。
根据本公开的一些实施例，不形成接合焊盘66和介电层64。因此，器件管芯68A和器件管芯68B被直接接合至顶部RDL 56(在图8中示为56C)和可能的介电层54C(图8)。
贯穿说明书，层22(或硅晶圆23)上方的组件被组合地称为中介层100。与基于硅衬底形成的常规中介层不同，中介层100是基于介电层58形成的。在中介层100中没有硅衬底，并且因此中介层100被称为无硅衬底中介层或无Si中介层。在介电层58中形成堆叠通孔67和TDV 62以取代常规的硅贯通孔。由于硅衬底是半导的，因此可能对其中和其上形成的电路和连接件的性能产生不利影响。例如，信号劣化可能由硅衬底引起，并且由于在介电层中形成TDV 62和堆叠通孔67，所以在本公开的实施例中可以避免这种劣化。
接下来，如图12所示，第一层器件管芯68A和第一层器件管芯68B接合至中介层100。相应的步骤被示出为图39中示出的工艺流程300中的步骤314。根据本公开的一些实施例，器件管芯68A和器件管芯68B包括可以是中央处理单元(CPU)管芯、微控制单元(MCU)管芯、输入输出(IO)管芯、基带(BB)管芯、或应用程序处理器(AP)管芯的逻辑管芯。器件管芯68A和器件管芯68B也可以包括存储器管芯。器件管芯68A和器件管芯68B分别包括可以是硅衬底的半导体衬底70A和半导体衬底70B。硅贯通孔(TSV)71A和硅贯通孔(TSV)71B(有时被称为半导体贯通孔或贯通孔)被形成为分别贯穿半导体衬底70A和半导体衬底70B，并且被用于将在半导体衬底70A和半导体衬底70B的正面(所示的底面)上形成的器件和金属线连接至背面。另外，器件管芯68A和器件管芯68B分别包括互连结构72A和互连结构72B，用于连接到器件管芯68A和器件管芯68B中的有源器件和无源器件。互连结构72A和互连结构72B包括金属线和通孔(未示出)。
器件管芯68A包括在器件管芯68A的所图示的底面处的接合焊盘74A和介电层76A。接合焊盘74A的所示底面与介电层76A的所示底面共面。器件管芯68B包括在所示的底面处的接合焊盘74B和介电层76B。所示的接合焊盘74B的底面与所示的介电层76B的底面共面。
可以通过混合接合来实现接合。例如，接合焊盘74A和接合焊盘74B通过金属与金属直接接合接合至接合焊盘66。根据本公开的一些实施例，金属与金属的直接接合是铜与铜的直接接合。此外，介电层76A和介电层76B，例如，通过生成的Si-O-Si键，接合至介电层64。混合接合可以包括预接合和退火，使得接合焊盘74A(和74B)中的金属与相应的下面的接合焊盘66中的金属相互扩散。
微间距RDL 56电互连接合焊盘74A和接合焊盘74B，并且用于器件管芯68A和器件管芯68B之间的信号通信。微间距RDL 56具有较小间距和较小宽度。因此，微间距RDL 56的密度较高，并且因此可以形成用于器件管芯68A和器件管芯68B之间的直接通信的足够的通信沟道。另一方面，TDV 62和堆叠通孔67提供从器件管芯68A和器件管芯68B至将要被接合至中介层100的组件(其可以是封装衬底、印刷电路板(PCB)等)的直接连接。此外，接合焊盘74A/74B和接合焊盘66之间的接合是通过接合焊盘的，而不是通过通常比接合焊盘大得多的焊料接点。相应地，键的横向尺寸较小，并且可以实现更多的键以提供足够的通信沟道。
进一步参考图12，执行背面研磨以薄化器件管芯68A和器件管芯68B至，例如，约15μm和约30μm之间的厚度。相应的步骤被示出为图39中示出的工艺流程300中的步骤316。通过减薄，相邻的器件管芯68A和器件管芯68B之间的间隙78的纵横比减小以执行间隙填充。否则，由于开口78的高纵横比，间隙填充是困难的。在背面研磨之后，可以露出TSV 71A和TSV 71B。可选地，此时不露出TSV 71A和TSV 71B。相反，可以在图17所示的步骤中露出TSV71A和TSV 71B。
接下来，通过间隙填充材料80填充间隙78，如图13所示。相应的步骤被示出为图39中示出的工艺流程300中的步骤318。根据本公开的一些实施例，间隙填充材料80包括可以使用原硅酸四乙酯(TEOS)形成的诸如氧化硅的氧化物。形成方法可以包括化学汽相沉积(CVD)、高密度等离子体化学汽相沉积(HDPCVD)等。根据可选实施例，间隙填充材料80由诸如PBO、聚酰亚胺等的聚合物形成。然后，执行平坦化步骤以去除间隙填充材料80的多余部分，从而露出器件管芯68A和器件管芯68B的衬底70A和衬底70B。得到的结构如图14所示。
图15示出了TDV 162的形成，其通过在各向异性蚀刻步骤中蚀刻贯穿间隙填充材料80以形成通孔开口并且用导电材料填充各个开口形成。相应的步骤被示出为图39中示出的工艺流程300中的步骤320。一些接合焊盘66暴露于通孔开口，其中，可以使用接合焊盘66作为蚀刻停止层来执行蚀刻。TDV 162可以具有与TDV 62的结构类似的结构，并且可以包括阻挡层和在阻挡层上方的金属材料。TDV 162的材料也可以从用于形成TDV 62的类似候选材料中选择。
参考图16，衬底70A和衬底70B被凹进以形成凹槽73，并且TSV 71A和TSV 71B的顶端分别在衬底70A和衬底70B的顶面之上略微突出。相应的步骤被示出为图39中示出的工艺流程300中的步骤322。然后，用诸如氧化硅的介电材料填充凹槽73以形成介电层75A和介电层75B，并且所得到的结构在图17中示出。相应的步骤被示出为图39中示出的工艺流程300中的步骤324。形成工艺包括沉积工艺以沉积毯式介电层，并且执行平坦化以去除毯式介电层的高于TSV 71A和TSV 71B的顶端的部分。
接下来，如图18所示，第二层器件管芯168A和第二层器件管芯168B被接合至器件管芯68A和器件管芯68B。相应的步骤被示出为图39中示出的工艺流程300中的步骤326。根据本公开的一些实施例，器件管芯168A和器件管芯168B包括逻辑管芯、存储器管芯、或其组合。器件管芯168A和器件管芯168B分别包括半导体衬底170A和半导体衬底170B，半导体衬底170A和半导体衬底170B可以是诸如硅衬底的半导体衬底。如果存在在器件管芯168A和器件管芯168B上方接合的第三层器件管芯，则可以在半导体衬底170A和半导体衬底170B中形成TSV(未示出)。可选地，在半导体衬底170A和半导体衬底170B中不形成TSV。另外，器件管芯168A和器件管芯168B分别包括互连结构172A和互连结构172B，以用于连接至器件管芯168A和器件管芯168B中的有源器件和无源器件。互连结构172A和互连结构172B包括金属线和通孔(未示出)。
器件管芯168A包括在所示的器件管芯168A的底面处的接合焊盘174A和介电层176A。所示的接合焊盘174A的底面与所示的介电层176A的底面共面。器件管芯168B包括在所示的底面处的接合焊盘174B和介电层176B。所示的接合焊盘174B的底面与所示的介电层176B的底面共面。
可以通过混合接合来实现接合。例如，接合焊盘174A和接合焊盘174B通过金属与金属直接接合直接地接合至TSV 71A和TSV 71B。根据本公开的一些实施例，金属与金属的直接接合是铜与铜的直接接合。此外，介电层176A和介电层176B，例如，通过生成的Si-O-Si键，接合至介电层75A和介电层75B。取决于间隙填充材料80的材料，介电层176A和介电层176B可以被接合至间隙填充材料80，或者可以与间隙填充材料80接触但不接合至(不形成键)间隙填充材料80。
接下来，可以减薄器件管芯168A和器件管芯168B，类似于器件管芯68A和器件管芯68B的减薄。然后，如图19所示，相邻器件管芯168A和器件管芯168B之间的间隙由间隙填充材料180填充。相应的步骤被示出为图39中示出的工艺流程300中的步骤328。根据本公开的一些实施例，使用从用于形成间隙填充材料80的相同候选方法中选择的方法来形成间隙填充材料180。间隙填充材料180可以包括诸如氧化硅、氮化硅、PBO、聚酰亚胺等的氧化物。然后，执行平坦化步骤以去除间隙填充材料180的多余部分，从而露出器件管芯168A和器件管芯168B的衬底170A和衬底170B。
然后，例如，使用CVD、PECVD、ALD等将介电层182沉积为毯式层。所得到的结构还在图19中示出。相应的步骤被示出为图39中示出的工艺流程300中的步骤330。根据本公开的一些实施例，介电层182由诸如氧化硅、氮氧化硅等的氧化物形成。
接下来，参考图20，通过蚀刻介电层182以及衬底170A和衬底170B来形成沟槽184，使得沟槽184延伸到介电层182以及衬底170A和衬底170B中。衬底170A和衬底170B内部的沟槽184的部分的深度D1可以大于约1μm，并且可以在大约2μm和大约5μm之间，这取决于衬底170A和衬底170B的厚度T1。例如，深度D1可以在厚度T1的大约20％和大约60％之间。应当理解，整个说明书中列举的值是实例，并且可以改变为不同的值。
沟槽184可以各种图案分布。例如，沟槽184可以形成为离散的开口，其可以被分配成具有阵列的图案、蜂窝的图案、或其他重复图案。沟槽184的顶视形状可以是矩形、圆形、六边形等。根据可选实施例，当在图20中所示的结构的顶视图中观察时，沟槽184可以是具有在单一方向上的长度方向的平行沟槽。沟槽84也可以被互连以形成栅格。栅格可包括彼此平行且均匀或不均匀间隔的第一多个沟槽，以及彼此平行且均匀或不均匀间隔的第二多个沟槽。第一多个沟槽和第二多个沟槽彼此相交以形成栅格，并且第一多个沟槽和第二多个沟槽在顶视图中可以彼此垂直或者可以不彼此垂直。
然后，如图21所示，填充沟槽184以形成接合焊盘187。相应的步骤被示出为图39中示出的工艺流程300中的步骤332。应该理解，虽然部件187被称为接合焊盘，部件187可以是离散焊盘、互连金属线、或金属栅格。根据本公开的一些实施例，接合焊盘187由铜或适合于混合接合的其他金属形成(由于扩散相对容易)。在填充之后，执行平面化以通过介电层182的顶面平坦化接合焊盘187的顶面。平坦化可以包括CMP或机械研磨。
接下来，如图22所示，空白管芯88接合至器件管芯168A和器件管芯168B。相应的步骤被示出为图39中示出的工艺流程300中的步骤332。空白管芯88包括块状衬底194，其可以是硅衬底或金属衬底。当由金属形成时，衬底194可以由铜、铝、不锈钢等形成。当衬底194由硅形成时，在空白管芯88中没有形成有源器件和无源器件。空白管芯88包括两个功能。首先，由于器件管芯68A、器件管芯68B、器件管芯168A、和器件管芯168B已被减薄以允许更好的间隙填充，所以空白管芯88为下面的结构提供机械支撑。另外，(衬底194的)硅或金属具有高导热性，并且因此空白管芯88可以充当散热器。由于图22中的结构的形成处于晶圆级，所以与所示出的空白管芯88相同的多个空白管芯也被接合至与器件管芯168A和器件管芯168B相同的相应的下面的器件管芯。
在衬底194的表面处形成介电层190。例如，介电层190可以由氧化硅或氮氧化硅形成。另外，在介电层190中形成接合焊盘192，并且所示的接合焊盘192的底面与所示的介电层190的底面共面。接合焊盘192的图案和横向尺寸可以与相应的接合焊盘187的尺寸相同或相似，使得接合焊盘192和接合焊盘187可以一一对应的方式彼此接合。
可以通过混合接合实现空白管芯88至器件管芯168A和器件管芯168B上的接合。例如，介电层182和介电层190彼此接合，并且可以形成Si-O-Si键。接合焊盘192通过金属与金属直接接合接合至相应的接合焊盘187。
有利地，通过接触(并且甚至被插入至)衬底170A和衬底170B，接合焊盘187提供良好的散热路径，使得器件管芯68A、器件管芯68B、器件管芯168A、和器件管芯168B中产生的热量能够容易地扩散至块状衬底194中，并且因此块状衬底194被用作散热器。
参考图23，应用和图案化光刻胶183。然后，使用图案化光刻胶183作为蚀刻掩模来蚀刻介电层182和间隙填充材料180以露出中介层100的一些部分。相应的步骤被示出为图39中示出的工艺流程300中的步骤334。根据本公开的一些实施例，露出诸如器件管芯68B的一些器件管芯。TSV71B和TDV 162中的一些也可以被露出。
图24示出了管芯堆叠件212至第一层结构上的接合。相应的步骤被示出为图39中示出的工艺流程300中的步骤336。管芯堆叠件212可以被接合到TDV 162、器件管芯(诸如管芯68B)、或TDV 162和器件管芯两者。管芯堆叠件212可以是包括多个堆叠管芯214的存储器堆叠件，其中，TSV(未示出)可以形成在管芯214中以执行互连。管芯堆叠件212也可以是高带宽存储器(HBM)立方体。根据本公开的一些实施例，管芯堆叠件212通过混合接合被接合至下面的结构，其中，管芯堆叠件212中的电连接件216(在一些实施例中的接合焊盘)通过金属与金属的直接接合接合至TDV162和TSV 71B，并且管芯堆叠件212的介电层218通过氧化物与氧化物的接合(或熔融接合)接合到间隙填充材料80(例如，氧化物)和介电层75B。根据可选实施例，电连接件216是焊料区域，并且接合是焊料接合。根据另外的可选实施例，电连接件216是突出超出管芯堆叠件212的表面介电层218的微凸块。微凸块216可以通过金属与金属的直接接合或焊料接合被接合至TDV 162和TSV 71B，并且在管芯堆叠件212和间隙填充材料80与介电层75B之间不发生氧化物与氧化物的接合。
接下来，将间隙填充材料220(图25)填充到空白管芯88与管芯堆叠件212之间的间隙中。间隙填充材料220可以由诸如氧化硅的氧化物或诸如PBO或聚酰亚胺的聚合物形成。根据其中使用载体20(而不是硅晶圆23)的一些实施例，在载体20上形成的结构，例如，通过在释放层22上投射诸如UV光或激光的光以分解释放层22而从载体20脱粘。得到的结构如图26所示。载体20和释放层22从被称为复合晶圆102(图26)的上面的结构去除。相应的步骤被示出为图39中示出的工艺流程300中的步骤338。根据其中使用硅晶圆23(而不是载体晶圆20，图24)的本公开的一些实施例，可以通过机械研磨、CMP、或干蚀刻去除硅晶圆23。如果需要，在载体20(或硅晶圆23)被去除之前，可以执行载体交换以将另一载体222附接在所示结构上方，并且新载体222被用于在随后步骤中的电连接件的形成期间提供机械支撑。
图26还示出了可以贯穿介电层24并连接至RDL 26的电连接件110的形成。根据一些实施例，在介电层24上形成聚合物层(未示出)，并且电连接件110也可以延伸到聚合物层中。电连接件110可以是金属凸块、焊料凸块、金属柱、接合线、或其他适用的连接件。在复合晶圆102上执行管芯锯切步骤以将复合晶圆102分离成多个封装件104。相应的步骤被示出为图39中示出的工艺流程300中的步骤340。封装件104彼此相同，并且封装件104中的每个可以包括器件管芯和管芯堆叠件212的两层。图27A中示出了得到的封装件104。
图27B、图27C、图27D、和图27E以及图28至图35示出了根据本公开的一些实施例的封装件和封装件的形成中的中间阶段的横截面图。除非另有说明，否则这些实施例中的组件的材料和形成方法与相似组件基本上相同，在图1至图27A中示出的实施例中，相似组件由相同的参考标号表示。因此，可以在图1至图27A所示的实施例的讨论中找到关于图27B、、图27C、图27D、和图27E以及图28至图35中所示的组件的形成工艺和材料的细节。
图27B示出了根据本公开的一些实施例形成的封装件。这些实施例类似于图27A所示的实施例，除了不形成接合焊盘187和接合焊盘192以及介电层190(如图27A所示)之外。可以是空白硅管芯的块状衬底194通过熔焊接合接合至介电层82。
根据本公开的可选实施例，块状衬底194是空白金属衬底。因此，图27B中的层182可由热界面材料(TIM)形成，该热界面材料是具有高导热率的粘合剂，例如，高于约1W/k*m或高于约5W/k*m。
图27C示出根据本公开的一些实施例形成的封装件104。这些实施例类似于图27A中所示的实施例，除了具有不同厚度的器件管芯可以被放置在相同的层级处之外。例如，器件管芯68B比器件管芯68A厚。因此，器件管芯68B包括延伸到与器件管芯68A和器件管芯168A相同的层级的部分。可以理解的是，虽然空白衬底194被示为通过熔合接合或通过氧化物/TIM 182接合至器件管芯168A和器件管芯68B，但是图27A中所示的包括接合焊盘187和接合焊盘192的相同的接合结构可以被使用。根据一些实施例，管芯堆叠件212具有与空白管芯88的一部分齐平的部分。
图27D示出根据本公开的一些实施例形成的封装件104。这些实施例与图27C中所示的实施例类似，除了没有使用空白管芯88(如图27C所示)。替代放置在间隙填充材料80上方，管芯堆叠件212延伸到间隙填充材料80中。
图27E示出根据本公开的一些实施例形成的封装件104。这些实施例类似于图27A中所示的实施例，不同之处在于管芯堆叠件212并不是延伸到封装材料180中，而是位于封装材料180上方。在封装材料180中形成贯通孔262以电耦接至下面的贯通孔162和堆叠通孔67。
图28至图32示出了根据本公开的一些实施例的封装件的形成中的中间阶段的横截面图。相应的封装件包括单层器件管芯。最初的步骤类似于图1至图17所示的步骤。所得到的结构也在图17中示出。接下来，参考图28，可以形成或可以不形成介电层182和接合焊盘187，并且接合焊盘187用虚线示出。
接下来，如图29所示，通过混合接合、熔融接合、或通过TIM的粘合接合空白管芯88。图30示出了管芯堆叠件212的接合。在图31中，在间隙填充材料220中封装空白管芯88和管芯堆叠件212。可以执行平坦化以暴露出空白管芯88。在随后的步骤中，中介层100和上面的结构从载体20脱粘。图32示出了电连接件110的形成。然后，执行管芯锯切以形成封装件104。
图33至图35示出了根据本公开的一些实施例的封装件的形成中的中间阶段的横截面图。图33中所示的结构的相应封装件和形成工艺与图28至图32中所示的类似，不同之处在于，没有形成TDV 162和包括堆叠通孔67、TDV 62、以及RDL 32、RDL 36、和RDL 44中的一些的它们的连接导电部件。管芯堆叠件212至下面的结构(例如，间隙填充材料80)的接合是通过熔融接合。因此，堆叠管芯212的接合焊盘216与间隙填充材料80或其上形成的介电层接触。
图33包括连接至RDL 44A的一些金属焊盘44B。金属焊盘44B和RDL44A是RDL 44的部分。金属焊盘44B可形成中空环。图38示出了一些示例性的金属焊盘44B和连接RDL 44A。金属焊盘44B形成为环，其中环内的开口45被介电层46填充(图33)。可以理解的是，尽管金属焊盘44B被示出为RDL 44的部分，但是类似的金属焊盘可以形成在中介层100中的任何一层中。因此，金属焊盘44B电连接到中介层100中的其他导电部件。
接下来，参考图34，从中介层100的底面形成深TDV 162。形成工艺包括蚀刻介电层以形成开口，并且然后用导电材料填充开口。形成工艺和材料类似于TDV 62的形成。在开口的形成中，金属焊盘44B用作蚀刻停止层，使得开口的上部由开口45的尺寸和形状限定(图38)。开口被管芯堆叠件212中的金属焊盘216进一步停止。因此，TDV 162的形成由金属焊盘44B自对准。金属焊盘44B和RDL 44A通过TDV 162组合地将器件管芯68A和器件管芯68B电连接至管芯堆叠件212。然后，形成电连接件110，并且在管芯锯切之后得到封装件104，如图35所示。
图36示出其中嵌入封装件104(参考图27A、图27B、图27C、图27D、图27E、图32、和图35)的封装件112。封装件包括存储器立方体114，其包括多个堆叠的存储器管芯(未单独示出)。封装件104和存储器立方体114被封装在封装材料118中，封装材料118可以是模塑料。介电层和RDL(统称为116)位于下面并且连接至封装件104和存储器立方体114。根据本公开的一些实施例，与图1至图11中所示的类似，介电层和RDL 116使用类似的材料被形成并且具有类似的结构。
图37示出了堆叠封装(PoP)结构，其具有与顶部封装件140接合的集成扇出(InFO)封装件138。InFO封装件138还包括嵌入其中的封装件104。封装件104和贯通孔134被封装在封装材料130中，封装材料130可以是模塑料。封装件104接合至介电层和RDL，其统称为146。与图1至图11中所示的类似，介电层和RDL 146也可以使用类似的材料形成并且具有相似的结构。
本公开的实施例具有一些有利的特征。通过使用通常在硅晶圆上使用的工艺(诸如镶嵌工艺)在中介层中形成微间距RDL，微间距RDL可以形成为足够薄以提供两个或多个器件管芯全部通过微间距的RDL通信的能力。形成堆叠通孔以替代一些TDV，从而减小了芯片面积占用。自对准TDV被形成以连接至管芯堆叠件，其中，用于对准TDV的金属焊盘也用于将自对准的TDV连接到封装件中的其他部件和器件管芯。此外，当形成微间距RDL时也可以形成无源器件。
根据一些实施例，一种方法包括形成多个介电层；在多个介电层中形成多个再分布线；当形成多个再分布线时，在多个介电层中同时形成堆叠通孔，其中，堆叠通孔形成贯穿多个介电层的连续电连接件；在堆叠通孔和多个介电层上方形成介电层；在介电层中形成多个接合焊盘；以及通过混合接合将第一器件管芯接合至介电层和多个接合焊盘的第一部分。在一个实施例中，该方法包括通过混合接合第二器件管芯至介电层和多个接合焊盘的第二部分，其中，多个再分布线将第一器件管芯连接至第二器件管芯。在一个实施例中，形成多个再分布线包括镶嵌工艺。在一个实施例中，该方法包括蚀刻多个介电层以形成开口；以及填充开口以形成贯穿多个介电层的介电贯通孔。在一个实施例中，该方法包括将附加的器件管芯接合到第一器件管芯，其中附加的器件管芯直接接合至第一器件管芯中的硅贯通孔；在附加的器件管芯的半导体衬底上方形成氧化物层并且氧化物层与附加的器件管芯的半导体衬底接触；形成延伸至氧化物层中的接合焊盘；以及通过混合接合将空白管芯接合至氧化物层和接合焊盘。在一个实施例中，在玻璃载体上方形成多个介电层；并且该方法还包括使玻璃载体脱粘；以及在玻璃载体脱粘之后，形成自对准的介电贯通孔以贯穿多个介电层，其中，在管芯堆叠件的接合焊盘上停止自对准的介电贯通孔。在一个实施例中，在硅晶圆上方形成多个介电层，并且该方法还包括从多个介电层研磨、抛光、或蚀刻硅晶圆。
根据一些实施例，一种方法包括形成多个介电层；在多个介电层中的每个中形成多个再分布线；在多个介电层中形成无源器件；形成贯穿多个介电层的第一介电贯通孔和第二介电贯通孔；在多个介电层上方形成介电层；在介电层中形成多个接合焊盘并且多个接合焊盘电耦接至第一介电贯通孔、第二介电贯通孔、以及多个再分布线；以及通过混合接合将第一器件管芯和第二器件管芯接合至介电层和多个接合焊盘，其中，通过多个再分布线电互连第一器件管芯和第二器件管芯，并且第一器件管芯和第二器件管芯分别连接至第一介电贯通孔和第二介电贯通孔。在一个实施例中，使用镶嵌工艺形成多个再分布线。在一个实施例中，该方法包括在第一器件管芯和第二器件管芯的相对侧上填充间隙填充材料；形成贯穿间隙填充材料的第三介电贯通孔；以及将管芯堆叠件接合至第三介电贯通孔。在一个实施例中，在硅晶圆上方形成多个介电层，并且该方法还包括从多个介电层去除硅晶圆。在一个实施例中，形成第一介电贯通孔和第二介电贯通孔包括蚀刻多个介电层以形成第一开口和第二开口；并用导电材料填充第一开口和第二开口。在一个实施例中，所述方法包括：当形成多个再分布线时，同时在多个介电层中形成堆叠通孔，其中，堆叠通孔形成贯穿多个介电层的连续电连接件。在一个实施例中，该方法包括将第三器件管芯接合在第一器件管芯的顶部上；在第三器件管芯上方形成介电层；并且将空白管芯接合至介电层。
根据一些实施例，一种封装件包括多个介电层；在多个介电层中的每个中的多个再分布线；贯穿多个介电层的介电贯通孔，其中，介电贯通孔具有贯穿多个介电层的基本上笔直的边缘；在多个介电层中的堆叠通孔，其中，堆叠通孔彼此电连接以形成贯穿多个介电层的连续的电连接件；在介电贯通孔和多个再分布线上方并且连接至介电贯通孔和多个再分布线的多个接合焊盘；第一介电层，多个接合焊盘位于该第一介电层中；以及通过混合接合接合至第一介电层和多个接合焊盘的第一部分的第一器件管芯。在一个实施例中，该封装件还包括通过混合接合接合第一介电层和多个接合焊盘的第二部分的第二器件管芯，其中，第一器件管芯和第二器件管芯通过多个再分配线彼此电耦接。在一个实施例中，该封装件进一步包括在第一器件管芯上方并且接合至第一器件管芯的第二器件管芯；接触第二器件管芯的半导体衬底的接合焊盘，其中，接合焊盘的至少一部分在第二器件管芯的半导体衬底上方；第二介电层，其中，接合焊盘具有在第二介电层中的至少一部分；以及在第二介电层和接合焊盘上方并且接合至第二介电层和接合焊盘的块状衬底。在一个实施例中，块状衬底由硅形成，并且在块状衬底上没有形成有源器件和无源器件。在一个实施例中，接合焊盘进一步延伸到第二器件管芯的半导体衬底中。在一个实施例中，接合焊盘形成栅格。
根据一些实施例，一种方法包括在硅晶圆上方形成多个介电层；在多个介电层中形成多个再分布线；当形成多个再分布线时，同时在多个介电层中形成堆叠通孔，其中，堆叠通孔形成贯穿多个介电层的连续电连接件；在堆叠通孔和多个介电层上方形成介电层；在该介电层中形成多个接合焊盘；通过混合接合将第一器件管芯接合至介电层和多个接合焊盘的第一部分；从多个介电层中去除硅晶圆；以及形成电耦接到多个再分配线的电连接件。在一个实施例中，去除硅晶圆包括在硅晶圆上进行机械研磨。在一个实施例中，去除硅晶圆包括在硅晶圆上执行化学机械抛光。在一个实施例中，去除硅晶圆包括对硅晶圆执行干蚀刻。在一个实施例中，该方法包括在多个介电层中形成无源器件。在一个实施例中，该方法包括在间隙填充材料中封装第一器件管芯；并且在去除硅晶圆后，形成贯穿多个介电层和间隙填充材料的介电贯通孔。
根据一些实施例，一种封装件包括多个介电层；贯穿多个介电层的堆叠通孔，其中，堆叠通孔具有双镶嵌结构，并且堆叠通孔互连以形成连续的电连接结构；在多个介电层上方的器件管芯，其中，器件管芯通过混合接合被接合至下面的结构，并且器件管芯电耦接至堆叠通孔；以及在器件管芯上方并且接合至该器件管芯的管芯堆叠件。在一个实施例中，通过混合接合将管芯堆叠件接合至器件管芯。
根据一些实施例，一种封装件包括多个介电层；在多个介电层中的无源器件；贯穿多个介电层的介电贯通孔；在介电贯通孔上方并且电耦接至介电贯通孔的第一器件管芯，其中，第一器件管芯包括半导体衬底；在第一器件管芯上方的介电层；在介电层中的接合焊盘，其中，接合焊盘贯穿介电层并且进一步延伸到第一器件管芯的半导体衬底中；以及在第一器件管芯上方并且接合到第一器件管芯的管芯堆叠件。在一个实施例中，一种封装件还包括位于第一器件管芯和介电贯通孔之间的第二器件管芯。
根据本申请的实施例，提供了一种形成封装件的方法，包括：形成多个介电层；在多个介电层中形成多个再分布线；在多个介电层中形成堆叠通孔，其中，堆叠通孔形成贯穿多个介电层的连续的电连接件；在堆叠通孔和多个介电层上方形成介电层；在介电层中形成多个接合焊盘；以及通过混合接合将第一器件管芯接合至介电层和多个接合焊盘的第一部分。
根据本申请的实施例，还包括通过混合接合将第二器件管芯接合至介电层和多个接合焊盘的第二部分，其中，多个再分布线将第一器件管芯连接至第二器件管芯。
根据本申请的实施例，形成多个再分布线包括镶嵌工艺。
根据本申请的实施例，还包括：蚀刻多个介电层以形成开口；以及填充开口以形成贯穿多个介电层的介电贯通孔。
根据本申请的实施例，还包括：将附加的器件管芯接合至第一器件管芯，其中，附加的器件管芯直接接合至第一器件管芯中的硅贯通孔；在附加的器件管芯的半导体衬底上方形成氧化物层并且氧化物层与附加的器件管芯的半导体衬底接触；形成延伸到氧化物层中的接合焊盘；以及通过混合接合接合空白管芯至氧化物层和接合焊盘。
根据本申请的实施例，多个介电层形成在玻璃载体上方；并且方法还包括：脱粘玻璃载体；以及在玻璃载体脱粘之后，形成自对准的介电贯通孔以贯穿多个介电层，其中，自对准的介电贯通孔停止在管芯堆叠件的接合焊盘上。
根据本申请的实施例，多个介电层形成在硅晶圆上方，并且方法还包括从多个介电层研磨、抛光、或蚀刻硅晶圆。
根据本申请的实施例，提供了一种形成封装件的方法，包括：形成多个介电层；在多个介电层中的每个中形成多个再分布线；在多个介电层中形成无源器件；形成贯穿多个介电层的第一介电贯通孔和第二介电贯通孔；在多个介电层上方形成介电层；在介电层中形成多个接合焊盘并且电耦接至第一介电贯通孔、第二介电贯通孔、以及多个再分布线；以及通过混合接合将第一器件管芯和第二器件管芯接合至介电层和多个接合焊盘，其中，第一器件管芯和第二器件管芯通过多个再分布线电互连，以及第一器件管芯和第二器件管芯分别连接到第一介电贯通孔和第二介电贯通孔。
根据本申请的实施例，多个再分布线使用镶嵌工艺形成。
根据本申请的实施例，还包括：在第一器件管芯和第二器件管芯的相对侧上填充间隙填充材料；形成贯穿间隙填充材料的第三介电贯通孔；以及将管芯堆叠件接合至第三介电贯通孔。
根据本申请的实施例，多个介电层形成在硅晶圆上方，并且方法还包括从多个介电层去除硅晶圆。
根据本申请的实施例，形成第一介电贯通孔和第二介电贯通孔包括：蚀刻多个介电层以形成第一开口和第二开口；以及用导电材料填充第一开口和第二开口。
根据本申请的实施例，还包括：当形成多个再分布线时，同时在多个介电层中形成堆叠通孔，其中，堆叠通孔形成贯穿多个介电层的连续电连接件。
根据本申请的实施例，还包括：将第三器件管芯接合在第一器件管芯的顶部上；在第三器件管芯上方形成介电层；以及将空白管芯接合至介电层。
根据本申请的实施例，提供了一种封装件，包括：多个介电层；在多个介电层中的每个中的多个再分布线；贯穿多个介电层中的介电贯通孔，其中，介电贯通孔具有贯穿多个介电层的基本上笔直的边缘；在多个介电层中的堆叠通孔，其中，堆叠通孔彼此电连接以形成贯穿多个介电层的连续的电连接件；在介电贯通孔和多个再分布线上方的并且连接至介电贯通孔和多个再分布线的多个接合焊盘；第一介电层，多个接合焊盘位于第一介电层中；以及接合至第一介电层和多个接合焊盘的第一部分的第一器件管芯。
根据本申请的实施例，还包括通过混合接合接合至第一介电层和多个接合焊盘的第二部分的第二器件管芯，其中，第一器件管芯和第二器件管芯通过多个再分布线彼此电耦接。
根据本申请的实施例，还包括：在第一器件管芯上方并接合至第一器件管芯的第二器件管芯；接触第二器件管芯的半导体衬底的接合焊盘，其中，接合焊盘的至少一部分在第二器件管芯的半导体衬底上方；第二介电层，接合焊盘具有在第二介电层中的至少一部分；以及在第二介电层和接合焊盘上方并且接合至第二介电层和接合焊盘的块状衬底。
根据本申请的实施例，块状衬底由硅形成，并且在块状衬底上没有形成有源器件和无源器件。
根据本申请的实施例，接合焊盘进一步延伸至第二器件管芯的半导体衬底中。
根据本申请的实施例，接合焊盘形成栅格。
以上论述了若干实施例的特征，使得本领域技术人员可以更好地理解本发明的各方面。本领域技术人员应该理解，他们可以容易地使用本发明作为基础来设计或修改用于实施与本文所介绍的实施例相同的目的和/或实现相同优点的其他工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，本文中他们可以做出多种变化、替换以及改变。

Claims (14)

1.一种形成封装件的方法，包括：
形成多个介电层；
在所述多个介电层中形成多个再分布线；
在所述多个介电层中形成堆叠通孔，其中，所述堆叠通孔形成贯穿所述多个介电层的连续的电连接件；
在所述堆叠通孔和所述多个介电层上方形成介电层；
在所述介电层中形成多个接合焊盘；以及
通过混合接合将第一器件管芯接合至所述介电层和所述多个接合焊盘的第一部分，
其中，所述多个介电层形成在玻璃载体上方；并且所述方法还包括：
脱粘所述玻璃载体；以及
在所述玻璃载体脱粘之后，形成自对准的介电贯通孔以贯穿所述多个介电层，其中，所述自对准的介电贯通孔停止在管芯堆叠件的接合焊盘上。
2.根据权利要求1所述的方法，还包括通过混合接合将第二器件管芯接合至所述介电层和所述多个接合焊盘的第二部分，其中，所述多个再分布线将所述第一器件管芯连接至所述第二器件管芯。
3.根据权利要求1所述的方法，其中，形成所述多个再分布线包括镶嵌工艺。
4.根据权利要求1所述的方法，还包括：
蚀刻所述多个介电层以形成开口；以及
填充所述开口以形成贯穿所述多个介电层的介电贯通孔。
5.根据权利要求1所述的方法，还包括：
将附加的器件管芯接合至所述第一器件管芯，其中，所述附加的器件管芯直接接合至所述第一器件管芯中的硅贯通孔；
在所述附加的器件管芯的半导体衬底上方形成氧化物层并且所述氧化物层与所述附加的器件管芯的所述半导体衬底接触；
形成延伸到所述氧化物层中的接合焊盘；以及
通过混合接合接合空白管芯至所述氧化物层和所述接合焊盘。
6.根据权利要求1所述的方法，还包括，在所述多个介电层中形成无源器件。
7.一种形成封装件的方法，包括：
形成多个介电层；
在所述多个介电层中形成多个再分布线；
在所述多个介电层中形成堆叠通孔，其中，所述堆叠通孔形成贯穿所述多个介电层的连续的电连接件；
在所述堆叠通孔和所述多个介电层上方形成介电层；
在所述介电层中形成多个接合焊盘；以及
通过混合接合将第一器件管芯接合至所述介电层和所述多个接合焊盘的第一部分，
其中，所述多个介电层形成在硅晶圆上方，并且所述方法还包括从所述多个介电层研磨、抛光、或蚀刻以去除所述硅晶圆，
在去除所述硅晶圆之后，形成自对准的介电贯通孔以贯穿所述多个介电层，其中，所述自对准的介电贯通孔停止在管芯堆叠件的接合焊盘上。
8.一种形成封装件的方法，包括：
形成多个介电层；
在所述多个介电层中的每个中形成多个再分布线；
在所述多个介电层中形成无源器件；
形成贯穿所述多个介电层的第一介电贯通孔和第二介电贯通孔；
在所述多个介电层上方形成介电层；
在所述介电层中形成多个接合焊盘并且电耦接至所述第一介电贯通孔、所述第二介电贯通孔、以及所述多个再分布线；以及
通过混合接合将第一器件管芯和第二器件管芯接合至所述介电层和所述多个接合焊盘，其中，所述第一器件管芯和所述第二器件管芯通过所述多个再分布线电互连，以及所述第一器件管芯和所述第二器件管芯分别连接到所述第一介电贯通孔和所述第二介电贯通孔，
其中，所述多个介电层形成在玻璃载体上方；并且所述方法还包括：
脱粘所述玻璃载体；以及
在所述玻璃载体脱粘之后，形成自对准的介电贯通孔以贯穿所述多个介电层，其中，所述自对准的介电贯通孔停止在管芯堆叠件的接合焊盘上。
9.根据权利要求8所述的方法，其中，所述多个再分布线使用镶嵌工艺形成。
10.根据权利要求8所述的方法，还包括：
在所述第一器件管芯和所述第二器件管芯的相对侧上填充间隙填充材料；
形成贯穿所述间隙填充材料的第三介电贯通孔；以及
将管芯堆叠件接合至所述第三介电贯通孔。
11.根据权利要求8所述的方法，其中，形成所述第一介电贯通孔和所述第二介电贯通孔包括：
蚀刻所述多个介电层以形成第一开口和第二开口；以及
用导电材料填充所述第一开口和所述第二开口。
12.根据权利要求8所述的方法，还包括：
当形成所述多个再分布线时，同时在所述多个介电层中形成堆叠通孔，其中，所述堆叠通孔形成贯穿所述多个介电层的连续电连接件。
13.根据权利要求8所述的方法，还包括：
将第三器件管芯接合在所述第一器件管芯的顶部上；
在所述第三器件管芯上方形成介电层；以及
将空白管芯接合至所述介电层。
14.一种形成封装件的方法，包括：
形成多个介电层；
在所述多个介电层中的每个中形成多个再分布线；
在所述多个介电层中形成无源器件；
形成贯穿所述多个介电层的第一介电贯通孔和第二介电贯通孔；
在所述多个介电层上方形成介电层；
在所述介电层中形成多个接合焊盘并且电耦接至所述第一介电贯通孔、所述第二介电贯通孔、以及所述多个再分布线；以及
通过混合接合将第一器件管芯和第二器件管芯接合至所述介电层和所述多个接合焊盘，其中，所述第一器件管芯和所述第二器件管芯通过所述多个再分布线电互连，以及所述第一器件管芯和所述第二器件管芯分别连接到所述第一介电贯通孔和所述第二介电贯通孔，
其中，所述多个介电层形成在硅晶圆上方，并且所述方法还包括从所述多个介电层去除所述硅晶圆，
在去除所述硅晶圆之后，形成自对准的介电贯通孔以贯穿所述多个介电层，其中，所述自对准的介电贯通孔停止在管芯堆叠件的接合焊盘上。
CN201711279542.7A 2017-09-18 2017-12-06 封装件及其形成方法 Active CN109524314B (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202011247925.8A CN112509931A (zh) 2017-09-18 2017-12-06 封装件及其形成方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15/707,237 US10290571B2 (en) 2017-09-18 2017-09-18 Packages with si-substrate-free interposer and method forming same
US15/707,237 2017-09-18

Related Child Applications (1)

Application Number Title Priority Date Filing Date
CN202011247925.8A Division CN112509931A (zh) 2017-09-18 2017-12-06 封装件及其形成方法

Publications (2)

Publication Number Publication Date
CN109524314A CN109524314A (zh) 2019-03-26
CN109524314B true CN109524314B (zh) 2020-11-27

Family

ID=65526903

Family Applications (2)

Application Number Title Priority Date Filing Date
CN202011247925.8A Pending CN112509931A (zh) 2017-09-18 2017-12-06 封装件及其形成方法
CN201711279542.7A Active CN109524314B (zh) 2017-09-18 2017-12-06 封装件及其形成方法

Family Applications Before (1)

Application Number Title Priority Date Filing Date
CN202011247925.8A Pending CN112509931A (zh) 2017-09-18 2017-12-06 封装件及其形成方法

Country Status (5)

Country Link
US (5) US10290571B2 (zh)
KR (1) KR102112640B1 (zh)
CN (2) CN112509931A (zh)
DE (1) DE102017124071A1 (zh)
TW (1) TWI664685B (zh)

Families Citing this family (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102018124695A1 (de) * 2017-11-15 2019-05-16 Taiwan Semiconductor Manufacturing Co., Ltd. Integrieren von Passivvorrichtungen in Package-Strukturen
US11735570B2 (en) * 2018-04-04 2023-08-22 Intel Corporation Fan out packaging pop mechanical attach method
US10886231B2 (en) 2018-06-29 2021-01-05 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming RDLS and structure formed thereof
DE112019005240T5 (de) * 2018-11-15 2021-07-01 San-Ei Kagaku Co., Ltd. Durchkontaktierungsverdrahtungssubstrat, Verfahren zu seiner Herstellung und Halbleitervorrichtungs-Montagekomponente
JP7331119B2 (ja) * 2019-04-15 2023-08-22 長江存儲科技有限責任公司 複数の機能性チップを伴う三次元ｎａｎｄメモリデバイスの集積
KR102574414B1 (ko) * 2019-05-21 2023-09-04 삼성전기주식회사 전자 부품 모듈
KR20210013429A (ko) 2019-07-25 2021-02-04 삼성전자주식회사 반도체 패키지 및 그의 제조 방법
KR102661671B1 (ko) 2019-07-25 2024-04-29 삼성전자주식회사 적층된 반도체 칩들을 포함하는 반도체 패키지
DE102019211371A1 (de) * 2019-07-30 2021-02-04 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Verfahren zum Herstellen eines elektronischen Schaltungsbauelements und elektronisches Schaltungsbauelement
US11088125B2 (en) 2019-09-17 2021-08-10 Taiwan Semiconductor Manufacturing Company, Ltd. IPD modules with flexible connection scheme in packaging
US11476201B2 (en) 2019-09-27 2022-10-18 Taiwan Semiconductor Manufacturing Company. Ltd. Package-on-package device
DE102020108481B4 (de) 2019-09-27 2023-07-06 Taiwan Semiconductor Manufacturing Company, Ltd. Halbleiter-Die-Package und Herstellungsverfahren
US11211371B2 (en) 2019-10-18 2021-12-28 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit package and method
TWI735353B (zh) * 2019-10-18 2021-08-01 台灣積體電路製造股份有限公司 積體電路封裝及其製作方法
WO2021092779A1 (zh) * 2019-11-12 2021-05-20 华为技术有限公司 芯片堆叠封装结构、电子设备
US11599299B2 (en) * 2019-11-19 2023-03-07 Invensas Llc 3D memory circuit
KR20210066387A (ko) 2019-11-28 2021-06-07 삼성전자주식회사 반도체 패키지
TWI717155B (zh) 2019-12-17 2021-01-21 財團法人工業技術研究院 晶片封裝結構
US11107771B2 (en) * 2019-12-26 2021-08-31 Taiwan Semiconductor Manufacturing Company, Ltd. Segregated power and ground design for yield improvement
US11545423B2 (en) 2019-12-31 2023-01-03 Powertech Technology Inc. Package structure and manufacturing method thereof
TWI768294B (zh) * 2019-12-31 2022-06-21 力成科技股份有限公司 封裝結構及其製造方法
US11393746B2 (en) * 2020-03-19 2022-07-19 Taiwan Semiconductor Manufacturing Company, Ltd. Reinforcing package using reinforcing patches
US20210335627A1 (en) * 2020-04-23 2021-10-28 Microchip Technology Incorporated Backside interconnect for integrated circuit package interposer
US11282811B2 (en) * 2020-05-13 2022-03-22 Micron Technology, Inc. Integrated circuit wire bonded to a multi-layer substrate having an open area that exposes wire bond pads at a surface of the inner layer
KR20210142465A (ko) 2020-05-18 2021-11-25 삼성전자주식회사 반도체 패키지
US11296032B2 (en) * 2020-05-28 2022-04-05 Taiwan Semiconductor Manufacturing Company Limited Silicon interposer including through-silicon via structures with enhanced overlay tolerance and methods of forming the same
US11508665B2 (en) * 2020-06-23 2022-11-22 Taiwan Semiconductor Manufacturing Co., Ltd. Packages with thick RDLs and thin RDLs stacked alternatingly
KR20220006932A (ko) * 2020-07-09 2022-01-18 삼성전자주식회사 인터포저를 포함하는 반도체 패키지 및 반도체 패키지의 제조 방법
KR20220014364A (ko) 2020-07-23 2022-02-07 삼성전자주식회사 반도체 패키지
US11527518B2 (en) 2020-07-27 2022-12-13 Taiwan Semiconductor Manufacturing Co., Ltd. Heat dissipation in semiconductor packages and methods of forming same
US11355431B2 (en) 2020-10-07 2022-06-07 United Microelectronics Corporation Semiconductor structure
US20220262766A1 (en) * 2021-02-12 2022-08-18 Taiwan Semiconductor Manufacturing Co., Ltd. Through-Dielectric Vias for Direct Connection and Method Forming Same
US11848246B2 (en) 2021-03-24 2023-12-19 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit package and method
US20220328467A1 (en) * 2021-04-08 2022-10-13 Taiwan Semiconductor Manufacturing Co., Ltd. Molded dies in semicondcutor packages and methods of forming same
US11862590B2 (en) 2021-04-14 2024-01-02 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit package and method of forming thereof

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105047651A (zh) * 2014-04-30 2015-11-11 台湾积体电路制造股份有限公司 3d堆叠芯片封装件
TWM531651U (zh) * 2016-05-17 2016-11-01 zhi-xiong Li 無基板中介層及應用彼之半導體裝置
CN106257658A (zh) * 2015-06-22 2016-12-28 华亚科技股份有限公司 半导体器件
CN106409810A (zh) * 2015-07-31 2017-02-15 台湾积体电路制造股份有限公司 具有堆叠通孔的再分布线
CN106997869A (zh) * 2015-12-14 2017-08-01 台湾积体电路制造股份有限公司 半导体装置及其制造方法

Family Cites Families (74)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3973340B2 (ja) 1999-10-05 2007-09-12 Ｎｅｃエレクトロニクス株式会社 半導体装置、配線基板、及び、それらの製造方法
JP2003298232A (ja) 2002-04-02 2003-10-17 Sony Corp 多層配線基板の製造方法および多層配線基板
JP2006253631A (ja) 2005-02-14 2006-09-21 Fujitsu Ltd 半導体装置及びその製造方法、キャパシタ構造体及びその製造方法
US7621041B2 (en) 2005-07-11 2009-11-24 E. I. Du Pont De Nemours And Company Methods for forming multilayer structures
US7514797B2 (en) 2007-05-31 2009-04-07 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-die wafer level packaging
US8759964B2 (en) 2007-07-17 2014-06-24 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer level package structure and fabrication methods
US8227902B2 (en) 2007-11-26 2012-07-24 Taiwan Semiconductor Manufacturing Company, Ltd. Structures for preventing cross-talk between through-silicon vias and integrated circuits
US20110006846A1 (en) * 2008-04-08 2011-01-13 Mitsubishi Electric Corporation High-frequency amplifier
US8674482B2 (en) 2008-11-18 2014-03-18 Hong Kong Applied Science And Technology Research Institute Co. Ltd. Semiconductor chip with through-silicon-via and sidewall pad
US7825024B2 (en) 2008-11-25 2010-11-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming through-silicon vias
US7858441B2 (en) * 2008-12-08 2010-12-28 Stats Chippac, Ltd. Semiconductor package with semiconductor core structure and method of forming same
US8749027B2 (en) * 2009-01-07 2014-06-10 Taiwan Semiconductor Manufacturing Company, Ltd. Robust TSV structure
US8168529B2 (en) * 2009-01-26 2012-05-01 Taiwan Semiconductor Manufacturing Company, Ltd. Forming seal ring in an integrated circuit die
US8552563B2 (en) 2009-04-07 2013-10-08 Taiwan Semiconductor Manufacturing Company, Ltd. Three-dimensional semiconductor architecture
CN102859691B (zh) 2010-04-07 2015-06-10 株式会社岛津制作所 放射线检测器及其制造方法
US8546188B2 (en) 2010-04-09 2013-10-01 International Business Machines Corporation Bow-balanced 3D chip stacking
US9048233B2 (en) 2010-05-26 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Package systems having interposers
US8361842B2 (en) 2010-07-30 2013-01-29 Taiwan Semiconductor Manufacturing Company, Ltd. Embedded wafer-level bonding approaches
US8884431B2 (en) 2011-09-09 2014-11-11 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods and structures for semiconductor devices
US9064879B2 (en) 2010-10-14 2015-06-23 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods and structures using a die attach film
US20120190152A1 (en) * 2011-01-25 2012-07-26 Taiwan Semiconductor Manufacturing Company, Ltd. Methods for Fabricating Integrated Passive Devices on Glass Substrates
US8836137B2 (en) 2012-04-19 2014-09-16 Macronix International Co., Ltd. Method for creating a 3D stacked multichip module
US9182017B2 (en) 2011-03-31 2015-11-10 Toyota Jidosha Kabushiki Kaisha Belt-driven continuously variable transmission
US8829676B2 (en) 2011-06-28 2014-09-09 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structure for wafer level package
US8642385B2 (en) 2011-08-09 2014-02-04 Alpha & Omega Semiconductor, Inc. Wafer level package structure and the fabrication method thereof
EP2610269A1 (en) * 2011-12-28 2013-07-03 Saudi Basic Industries Corporation Catalyst composition and method for preparing the same
US9000584B2 (en) 2011-12-28 2015-04-07 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor device with a molding compound and a method of forming the same
US8680647B2 (en) 2011-12-29 2014-03-25 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with passive devices and methods of forming the same
US8703542B2 (en) 2012-05-18 2014-04-22 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer-level packaging mechanisms
US9991190B2 (en) 2012-05-18 2018-06-05 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging with interposer frame
US9443783B2 (en) 2012-06-27 2016-09-13 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC stacking device and method of manufacture
US8809996B2 (en) 2012-06-29 2014-08-19 Taiwan Semiconductor Manufacturing Company, Ltd. Package with passive devices and method of forming the same
US8653626B2 (en) 2012-07-18 2014-02-18 Taiwan Semiconductor Manufacturing Company, Ltd. Package structures including a capacitor and methods of forming the same
US8872004B2 (en) * 2012-07-18 2014-10-28 M.S. Technologies, Llc Soybean cultivar S110126
US8785299B2 (en) 2012-11-30 2014-07-22 Taiwan Semiconductor Manufacturing Company, Ltd. Package with a fan-out structure and method of forming the same
US8803306B1 (en) 2013-01-18 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out package structure and methods for forming the same
US8778738B1 (en) 2013-02-19 2014-07-15 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor devices and packaging devices and methods
US9263511B2 (en) 2013-02-11 2016-02-16 Taiwan Semiconductor Manufacturing Co., Ltd. Package with metal-insulator-metal capacitor and method of manufacturing the same
US9048222B2 (en) 2013-03-06 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating interconnect structure for package-on-package devices
US8946884B2 (en) 2013-03-08 2015-02-03 Xilinx, Inc. Substrate-less interposer technology for a stacked silicon interconnect technology (SSIT) product
US9337073B2 (en) * 2013-03-12 2016-05-10 Taiwan Semiconductor Manufacturing Company, Ltd. 3D shielding case and methods for forming the same
US9446467B2 (en) 2013-03-14 2016-09-20 Taiwan Semiconductor Manufacturing Company, Ltd. Integrate rinse module in hybrid bonding platform
US9443796B2 (en) 2013-03-15 2016-09-13 Taiwan Semiconductor Manufacturing Company, Ltd. Air trench in packages incorporating hybrid bonding
US8877554B2 (en) 2013-03-15 2014-11-04 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor devices, methods of packaging semiconductor devices, and PoP devices
US9368460B2 (en) 2013-03-15 2016-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out interconnect structure and method for forming same
US9728453B2 (en) 2013-03-15 2017-08-08 Taiwan Semiconductor Manufacturing Company, Ltd. Methods for hybrid wafer bonding integrated with CMOS processing
US9373434B2 (en) 2013-06-20 2016-06-21 Taiwan Semiconductor Manufacturing Co., Ltd. Inductor assembly and method of using same
US9324698B2 (en) 2013-08-13 2016-04-26 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-chip structure and method of forming same
US9633869B2 (en) 2013-08-16 2017-04-25 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with interposers and methods for forming the same
US9257399B2 (en) 2013-10-17 2016-02-09 Taiwan Semiconductor Manufacturing Company, Ltd. 3D integrated circuit and methods of forming the same
US9184128B2 (en) 2013-12-13 2015-11-10 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC package and methods of forming the same
JP2015126124A (ja) * 2013-12-26 2015-07-06 日東電工株式会社 半導体パッケージの製造方法
US9425150B2 (en) 2014-02-13 2016-08-23 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-via interconnect structure and method of manufacture
US9583460B2 (en) 2014-02-14 2017-02-28 Qualcomm Incorporated Integrated device comprising stacked dies on redistribution layers
US9735129B2 (en) 2014-03-21 2017-08-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages and methods of forming the same
US9711379B2 (en) 2014-04-30 2017-07-18 Taiwan Semiconductor Manufacturing Company, Ltd. 3D stacked-chip package
US9331021B2 (en) * 2014-04-30 2016-05-03 Taiwan Semiconductor Manufacturing Company, Ltd. Chip-on-wafer package and method of forming same
US9418877B2 (en) 2014-05-05 2016-08-16 Qualcomm Incorporated Integrated device comprising high density interconnects in inorganic layers and redistribution layers in organic layers
US20150340305A1 (en) 2014-05-20 2015-11-26 Freescale Semiconductor, Inc. Stacked die package with redistribution layer
US9385110B2 (en) 2014-06-18 2016-07-05 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
US9425096B2 (en) 2014-07-14 2016-08-23 Qualcomm Incorporated Air gap between tungsten metal lines for interconnects with reduced RC delay
US9449914B2 (en) 2014-07-17 2016-09-20 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked integrated circuits with redistribution lines
US9515035B2 (en) 2014-12-19 2016-12-06 International Business Machines Corporation Three-dimensional integrated circuit integration
US10032704B2 (en) 2015-02-13 2018-07-24 Taiwan Semiconductor Manufacturing Company, Ltd. Reducing cracking by adjusting opening size in pop packages
US9806058B2 (en) 2015-07-02 2017-10-31 Taiwan Semiconductor Manufacturing Company, Ltd. Chip package having die structures of different heights and method of forming same
US9666523B2 (en) 2015-07-24 2017-05-30 Nxp Usa, Inc. Semiconductor wafers with through substrate vias and back metal, and methods of fabrication thereof
US9691743B2 (en) 2015-09-21 2017-06-27 Nxp Usa, Inc. Localized redistribution layer structure for embedded component package and method
KR101787832B1 (ko) 2015-10-22 2017-10-19 앰코 테크놀로지 코리아 주식회사 반도체 패키지 제조 방법 및 이를 이용한 반도체 패키지
DE102016100523B4 (de) * 2015-11-10 2018-04-12 Taiwan Semiconductor Manufacturing Co., Ltd. Multi-Stack-Package-on-Package-Strukturen
US10009992B2 (en) 2015-12-02 2018-06-26 Multek Technologies Limited PCB hybrid redistribution layer
US9818726B2 (en) 2015-12-28 2017-11-14 International Business Machines Corporation Chip stack cooling structure
US9773757B2 (en) 2016-01-19 2017-09-26 Taiwan Semiconductor Manufacturing Company, Ltd. Devices, packaged semiconductor devices, and semiconductor device packaging methods
KR102579880B1 (ko) * 2016-05-12 2023-09-18 삼성전자주식회사 인터포저, 반도체 패키지, 및 인터포저의 제조 방법
KR102570582B1 (ko) 2016-06-30 2023-08-24 삼성전자 주식회사 반도체 패키지 및 그 제조 방법

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105047651A (zh) * 2014-04-30 2015-11-11 台湾积体电路制造股份有限公司 3d堆叠芯片封装件
CN106257658A (zh) * 2015-06-22 2016-12-28 华亚科技股份有限公司 半导体器件
CN106409810A (zh) * 2015-07-31 2017-02-15 台湾积体电路制造股份有限公司 具有堆叠通孔的再分布线
CN106997869A (zh) * 2015-12-14 2017-08-01 台湾积体电路制造股份有限公司 半导体装置及其制造方法
TWM531651U (zh) * 2016-05-17 2016-11-01 zhi-xiong Li 無基板中介層及應用彼之半導體裝置

Also Published As

Publication number Publication date
US11527465B2 (en) 2022-12-13
DE102017124071A1 (de) 2019-03-21
US10381298B2 (en) 2019-08-13
US20190363045A1 (en) 2019-11-28
US20190109083A1 (en) 2019-04-11
TW201916191A (zh) 2019-04-16
KR20190032147A (ko) 2019-03-27
CN112509931A (zh) 2021-03-16
US20210225750A1 (en) 2021-07-22
US10685910B2 (en) 2020-06-16
CN109524314A (zh) 2019-03-26
US20200312758A1 (en) 2020-10-01
US10971443B2 (en) 2021-04-06
US10290571B2 (en) 2019-05-14
US20190088581A1 (en) 2019-03-21
TWI664685B (zh) 2019-07-01
KR102112640B1 (ko) 2020-05-19

Similar Documents

Publication Publication Date Title
CN109524314B (zh) 封装件及其形成方法
CN108695176B (zh) 封装件及其形成方法
CN108695166B (zh) 封装件及其形成方法
CN109148308B (zh) 封装件及其形成方法
US10854567B2 (en) 3D packages and methods for forming the same
US9299649B2 (en) 3D packages and methods for forming the same
KR101706119B1 (ko) 보울 형상 솔더 구조물
KR20160130839A (ko) 라이너 층 없이 기판 내에 배치되는 열 비아
US20230230909A1 (en) Packages with Si-Substrate-Free Interposer and Method Forming Same
US11769718B2 (en) Packages with Si-substrate-free interposer and method forming same

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant