TWI735353B - 積體電路封裝及其製作方法 - Google Patents

積體電路封裝及其製作方法 Download PDF

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TWI735353B
TWI735353B TW109135875A TW109135875A TWI735353B TW I735353 B TWI735353 B TW I735353B TW 109135875 A TW109135875 A TW 109135875A TW 109135875 A TW109135875 A TW 109135875A TW I735353 B TWI735353 B TW I735353B
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Taiwan
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processor element
dielectric layer
processor
integrated circuit
shared memory
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TW109135875A
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TW202117975A (zh
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余振華
王垂堂
陳頡彥
張維麟
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台灣積體電路製造股份有限公司
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Priority claimed from US16/882,191 external-priority patent/US11211371B2/en
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Publication of TW202117975A publication Critical patent/TW202117975A/zh
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Abstract

在一實施例中，一種積體電路封裝包含：圖形處理器元件；被動元件，耦接至圖形處理器元件，被動元件直接面對面接合至圖形處理器元件；共用記憶體元件，耦接至圖形處理器元件，共用記憶體元件直接面對面接合至圖形處理器元件；中央處理器元件，耦接至共用記憶體元件，中央處理器元件直接背對背接合至共用記憶體元件，中央處理器元件及圖形處理器元件各自具有比共用記憶體元件更小的技術節點的主動元件；以及重佈線結構，耦接至中央處理器元件、共用記憶體元件、被動元件以及圖形處理器元件。

Description

積體電路封裝及其製作方法
本發明的實施例是有關於一種積體電路封裝及其製作方法。
隨著半導體技術持續演變，積體電路晶粒變得愈加較小。另外，更多功能經整合於晶粒中。因此，雖然可用於I/O墊的區域減小，但晶粒所需的輸入/輸出(input/output；I/O)墊的數目增加。隨時間推移，I/O墊的密度快速增長，增大晶粒封裝的困難。一些應用需要積體電路晶粒的較大並行處理能力。封裝技術可用於整合多個晶粒，從而允許較大程度的並行處理能力。
在一些封裝技術中，在封裝積體電路晶粒之前，自晶圓單體化所述積體電路晶粒。此封裝技術的有利特徵為形成扇出封裝的可能性，所述扇出封裝允許晶粒上的I/O墊重佈至較大區域。晶粒的表面上的I/O墊的數目可由此增加。
本發明實施例提供一種積體電路封裝，包括：第一處理器元件、共用記憶體元件、第一介電層、第一導通孔、第二處理器元 件以及第一重佈線結構。第一處理器元件，具有前側。共用記憶體元件，具有前側及與前側相對的背側。共用記憶體元件的前側藉由金屬至金屬接合及藉由介電至介電接合來接合至第一處理器元件的前側。第一介電層，橫向地圍繞共用記憶體元件。第一導通孔，延伸穿過第一介電層。第二處理器元件，具有前側及與前側相對的背側。第一導通孔將第一處理器元件的前側連接至第二處理器元件的背側。第二處理器元件的背側藉由金屬至金屬接合來接合至第一導通孔及共用記憶體元件的背側。第二處理器元件的背側藉由介電至介電接合來接合至第一介電層。第一處理器元件及第二處理器元件各自為不同類型的處理器元件。第一重佈線結構，連接至第二處理器元件的前側。
本發明實施例提供一種積體電路封裝，包括：圖形處理器元件、被動元件、共用記憶體元件、中央處理器元件以及重佈線結構。被動元件，耦接至圖形處理器元件。被動元件直接面對面接合至圖形處理器元件。共用記憶體元件，耦接至圖形處理器元件。共用記憶體元件直接面對面接合至圖形處理器元件。中央處理器元件，耦接至共用記憶體元件。中央處理器元件直接背對背接合至共用記憶體元件。中央處理器元件及圖形處理器元件各自具有比共用記憶體元件更小的技術節點的主動元件。重佈線結構，耦接至中央處理器元件、共用記憶體元件、被動元件以及圖形處理器元件。
本發明實施例提供一種積體電路封裝的製作方法，包括：將共用記憶體元件接合至第一處理器元件；在共用記憶體元件周圍形成第一介電層；形成延伸穿過第一介電層的第一導通孔，第一導通孔連接至第一處理器元件；將第二處理器元件接合至第一導 通孔、第一介電層以及共用記憶體元件，第一處理器元件及第二處理器元件各自為不同類型的處理器元件；在第二處理器元件周圍形成第二介電層；形成延伸穿過第二介電層的第二導通孔，第二導通孔連接至共用記憶體元件；形成延伸穿過第一介電層及第二介電層的第三導通孔，第三導通孔連接至第一處理器元件；以及在第二導通孔、第三導通孔、第二介電層以及第二處理器元件上形成重佈線結構。
20:第一處理器元件
20F、40F、60F、80F:前側
22、42、62、82:半導體基底
22A、42A、62A:主動表面
22N、42N、62N:非主動表面
24、44、64、84:內連線結構
28、48、68、88:晶粒連接件
30、50、70、90:介電層
32、310:密封體
40:第二處理器元件
40B、60B、80B:背側
46、66、86、308:導通孔
60:記憶體元件
80:被動元件
100、300、400:積體電路封裝
102、306、312:重佈線結構
104:第一介電層
106:第一導通孔
108:第二介電層
110:第二導通孔
112:第三導通孔
114、314、316:導電連接件
120:晶圓
120A:元件區
200:封裝基底
202、406:接合墊
302:載體基底
302A:封裝區
304:釋放層
402:基底
404:晶粒
410:模製材料
A-A、B-B:參考橫截面
W1、W2、W3、W4、W5、W6、W7、W8:寬度
當結合附圖閱讀時，自以下詳細描述最佳地理解本揭露內容的態樣。應注意，根據業界中的標準慣例，各種特徵未按比例繪製。實際上，可出於論述清楚起見，任意地增大或減小各種特徵的尺寸。
圖1A，圖1B、圖1C以及圖1D為根據一些實施例的半導體元件的橫截面圖。
圖2A、圖2B、圖2C以及圖2D為根據一些實施例的積體電路封裝的各種視圖。
圖3A、圖3B、圖4A、圖4B、圖5A、圖5B、圖6A、圖6B、圖7A、圖7B、圖8A以及圖8B為根據一些實施例的在用於形成積體電路封裝的製程期間的中間步驟的橫截面圖。
圖9A及圖9B為根據一些實施例的積體電路封裝的橫截面圖。
圖10及圖11為根據一些實施例的在用於形成實施積體電路封裝的系統的製程期間的中間步驟的橫截面圖。
圖12、圖13、圖14、圖15以及圖16為根據一些實施例的在用於形成實施積體電路封裝的系統的製程期間的中間步驟的橫截面圖。
圖17為根據一些實施例的實施積體電路封裝的系統的橫截面圖。
以下揭露內容提供用以實施本發明的不同特徵的許多不同實施例或實例。下文描述組件及配置的具體實例以簡化本揭露內容。當然，這些組件及配置僅為實例且不意欲為限制性的。舉例而言，在以下描述中，第一特徵在第二特徵上方或上的形成可包含第一特徵及第二特徵直接接觸地形成的實施例，且亦可包含額外特徵可在第一特徵與第二特徵之間形成使得第一特徵及第二特徵可不直接接觸的實施例。另外，本揭露內容可在各種實例中重複圖式元件符號及/或字母。此重複是出於簡化及清楚的目的，且自身並不指示所論述的各種實施例及/或組態之間的關係。
另外，為易於描述，可使用諸如「在...下方」、「在...下」、「下部」、「在...上方」、「上部」以及類似者的空間相對術語，以描述如諸圖中所說明的一個元件或特徵相對於另一元件或特徵的關係。除圖式中所描繪的定向以外，空間相對術語意欲涵蓋元件在使用或操作中的不同定向。設備可以其他方式定向(旋轉90度或處於其他定向)且本文中所使用的空間相對描述詞因此可同樣地進行解釋。
根據一些實施例，積體電路封裝包含夾在諸如圖形處理 單元及中央處理單元的兩個不同類型的處理器元件之間的記憶體元件。記憶體元件在操作期間由兩個處理器元件共用。半導體元件藉由混合接合來接合。如下文進一步描述，積體電路封裝的半導體元件當中的資料傳信可藉由經由混合接合的直接連接而非藉由重佈線結構的資料訊號線來實現。雖然積體電路封裝可形成有重佈線結構，但藉由混合接合將晶粒互連使重佈線結構中的資料訊號線的量減少。
圖1A至圖1D為根據一些實施例的半導體元件的橫截面圖。具體言之，圖1A、圖1B、圖1C以及圖1D分別說明第一處理器元件20、第二處理器元件40、記憶體元件60以及被動元件80。半導體元件將在後續處理中封裝以形成積體電路封裝，諸如系統積體晶片(system-on-integrated-chip；SoIC)元件。每一半導體元件可為裸積體電路晶粒或封裝晶粒。在所說明實施例中，每一半導體元件為裸積體電路晶粒。在其他實施例中，所說明半導體元件中的一或多者可為經密封的封裝晶粒。
參考圖1A，第一處理器元件20可為任何可接受的處理器或邏輯元件，諸如圖形處理單元(graphics processing unit；GPU)、中央處理單元(central processing unit；CPU)、系統單晶片(system-on-a-chip；SoC)、應用程式處理器(application processor；AP)、數位訊號處理(digital signal processing；DSP)、場可程式化閘陣列(field programmable gate array；FPGA)、微控制器、人工智慧(artificial intelligence；AI)加速器或類似者。第一處理器元件20可根據適用製造製程來處理以形成積體電路。舉例而言，第一處理器元件20包含半導體基底22，諸如摻雜或未摻雜的矽，或絕緣層 上半導體(semiconductor-on-insulator；SOI)基底的主動層。半導體基底22可包含其他半導體材料，諸如：鍺；化合物半導體，包含碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦及/或銻化銦；合金半導體，包含SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP及/或GaInAsP；或其組合。亦可使用其他基底，諸如多層基底或梯度基底。半導體基底22具有主動表面22A及非主動表面22N。
元件可形成於半導體基底22的主動表面22A處。元件可為主動元件(例如，電晶體、二極體等)、電容器、電阻器等。非主動表面22N可不含元件。層間介電質(inter-layer dielectric；ILD)位於半導體基底22的主動表面22A上方。ILD圍繞且可覆蓋元件。ILD可包含由諸如磷矽酸鹽玻璃(Phospho-Silicate Glass；PSG)、硼矽酸鹽玻璃(Boro-Silicate Glass；BSG)、硼摻雜磷矽酸鹽玻璃(Boron-Doped Phospho-Silicate Glass；BPSG)、未摻雜矽酸鹽玻璃(undoped Silicate Glass；USG)或類似者的材料形成的一或多個介電層。
內連線結構24位於半導體基底22的主動表面22A上方。內連線結構24互連所述半導體基底22的主動表面22A處的元件以形成積體電路。內連線結構24可由例如介電層中的金屬化圖案形成。金屬化圖案包含形成於一或多個介電層中的金屬線及通孔。內連線結構24的金屬化圖案電連接至半導體基底22的主動表面22A處的元件。
晶粒連接件28位於第一處理器元件20的前側20F處。晶粒連接件28可為與其形成外部連接的導電柱、襯墊或類似者。晶粒連接件28位於內連線結構24中及/或內連線結構24上，且 可由諸如銅(copper)、鋁(aluminium)或類似者的金屬形成。晶粒連接件28可由例如鍍覆或類似方法形成。
介電層30位於第一處理器元件20的前側20F處，諸如在內連線結構24上。介電層30橫向地密封晶粒連接件28，且介電層30與第一處理器元件20的側壁橫向地相連。最初，介電層30可掩埋晶粒連接件28，使得介電層30的最頂部表面在晶粒連接件28的最頂部表面上方。介電層30可為聚合物，諸如PBO、聚醯亞胺、BCB或類似者；氮化物，諸如氮化矽或類似者；氧化物，諸如氧化矽、PSG、BSG、BPSG或類似者；類似者，或其組合。介電層30可例如藉由旋塗、層壓、化學氣相沈積(chemical vapor deposition；CVD)或類似者形成。在形成之後，晶粒連接件28及介電層30可使用例如化學機械研磨(chemical-mechanical polish；CMP)處理、回蝕處理、類似者或其組合。在平坦化之後，晶粒連接件28及介電層30的表面為平面且暴露於第一處理器元件20的前側20F處。
參考圖1B，第二處理器元件40可為任何可接受的處理器或邏輯元件，諸如中央處理單元(CPU)、圖形處理單元(GPU)、系統單晶片(SoC)、應用程式處理器(AP)、數位訊號處理(DSP)、場可程式化閘陣列(FPGA)、微控制器、人工智慧(AI)加速器或類似者。第二處理器元件40可根據適用製造製程來處理以形成積體電路。舉例而言，第二處理器元件40包含具有主動表面42A及非主動表面42N的半導體基底42。半導體基底42可類似於半導體基底22。第二處理器元件40亦包含第二處理器元件40的前側40F處的內連線結構44。內連線結構44可類似於內連線結構24。 第二處理器元件40更包含導通孔46，導通孔46經形成在半導體基底42的主動表面42A與非主動表面42N之間延伸。導通孔46亦有時稱為基底穿孔或矽穿孔(through-silicon via；TSV)。導通孔46實體及電性地連接至內連線結構44的金屬化圖案。
作為形成導通孔46的實例，凹部可藉由例如蝕刻、碾磨、雷射技術、其組合及/或類似者來形成於半導體基底42中。薄介電材料可諸如藉由使用氧化技術而形成於凹部中。薄障壁層可諸如藉由CVD、原子層沈積(atomic layer deposition；ALD)、物理氣相沈積(physical vapor deposition；PVD)、熱氧化、其組合及/或類似者來保形地沈積於半導體基底42的主動表面42A上方及開口中。障壁層可由諸如氮化鈦、氮氧化鈦、氮化鉭、氮氧化鉭、氮化鎢、其組合及/或類似者的氧化物、氮化物或氮氧化物形成。導電材料可沈積於障壁層上方及開口中。導電材料可由電化學鍍覆製程、CVD、ALD、PVD、其組合及/或類似方法形成。導電材料的實例為銅、鎢、鋁、銀、金、其組合及/或類似者。藉由例如CMP自半導體基底42的主動表面42A移除過量導電材料及障壁層。障壁層及導電材料的剩餘部分形成導通孔46。
晶粒連接件48及介電層50形成於半導體基底42的非主動表面42N上。晶粒連接件48可由與晶粒連接件28類似的材料及方法形成。晶粒連接件48實體地連接至導通孔46，且藉由導通孔46電連接至第二處理器元件40的積體電路。介電層50可由與介電層30類似的材料及方法形成。在形成晶粒連接件48及介電層50之前，半導體基底42的非主動表面42N可經研磨以暴露導通孔46。在形成之後，晶粒連接件48及介電層50可使用例如CMP 製程、回蝕製程、類似者、或其組合來平坦化。在平坦化之後，晶粒連接件48及介電層50的表面為平面且暴露於第二處理器元件40的背側40B處。
參考圖1C，記憶體元件60可為任何可接受的記憶體元件，諸如動態隨機存取記憶體(dynamic random access memory；DRAM)元件、靜態隨機存取記憶體(static random access memory；SRAM)元件、電阻式隨機存取記憶體(resistive random-access memory；RRAM)元件、磁阻式隨機存取記憶體(magnetoresistive random-access memory；MRAM)元件、相變隨機存取記憶體(phase-change random-access memory；PCRAM)元件或類似者。記憶體元件60可根據適用製造製程來處理以形成積體電路。舉例而言，記憶體元件60包含具有主動表面62A及非主動表面62N的半導體基底62。半導體基底62可類似於半導體基底22。記憶體元件60亦包含分別可類似於內連線結構24、導通孔46、晶粒連接件28以及介電層30的內連線結構64、晶粒連接件68以及介電層70。晶粒連接件68及介電層70暴露於記憶體元件60的前側60F處。
記憶體元件60更包含導通孔66。在所說明實施例中，導通孔66尚未暴露於記憶體元件60的背側60B處。實際上，導通孔66掩埋在半導體基底62中。如下文進一步論述，導通孔66將在後續處理中經由平坦化製程來暴露於記憶體元件60的背側60B處。
參考圖1D，被動元件80可為任何可接受的被動元件，諸如積體被動元件(integrated passive device；IPD)、功率管理積體電路(power management integrated circuit；PMIC)、積體電壓 調節器(integrated voltage regulator；IVR)或類似者。被動元件80可根據適用製造製程來處理以形成積體電路。舉例而言，被動元件80包含可類似於半導體基底22的半導體基底82，但更包含被動元件(例如，電阻器、電容器、電感器等)且不含主動元件(例如，電晶體、二極體等)。被動元件80亦包含分別可類似於內連線結構24、晶粒連接件28以及介電層30的內連線結構84、晶粒連接件88以及介電層90。晶粒連接件88及介電層90暴露於被動元件80的前側80F處。
被動元件80更包含可類似於導通孔46的導通孔86。在所說明實施例中，導通孔86尚未暴露於被動元件80的背側80B處。實際上，導通孔86掩埋在半導體基底82中。如下文進一步論述，導通孔86將在後續處理中經由平坦化製程來暴露於被動元件80的背側80B處。
可對第一處理器元件20、第二處理器元件40、記憶體元件60及/或被動元件80執行晶片探針(Chip probe；CP)測試以確認元件是否為良裸晶粒(known good die；KGD)。因此，僅為KGD的元件經歷後續處理並封裝，且未通過CP測試的元件並不經歷後續處理且並不封裝。
圖2A至圖2D為根據一些實施例的積體電路封裝100的各種視圖。積體電路封裝100包含藉由例如混合接合來接合在一起的元件堆疊。積體電路封裝100可為異質元件，諸如系統積體晶片(SoIC)元件。下文將相對於圖3A至圖8B進一步描述用於形成積體電路封裝100的製程。
圖2A及圖2B為積體電路封裝100的橫截面圖。圖2C 為說明積體電路封裝100的半導體元件當中的電連接的三維圖。圖2D為說明半導體元件的定位的積體電路封裝100的俯視圖。圖2A沿圖2C及圖2D中的參考橫截面A-A進行說明，且圖2B沿圖2C及圖2D中的參考橫截面B-B進行說明。橫截面B-B垂直於橫截面A-A。第一處理器元件20、第二處理器元件40、記憶體元件60以及被動元件80的一些特徵出於說明清楚起見未標註於圖2A及圖2B中，但分別標註於圖1A、圖1B、圖1C以及圖1D中。另外，出於說明清楚起見自圖2C及圖2D省略一些特徵。
積體電路封裝100包含第一處理器元件20、第二處理器元件40、記憶體元件60以及視情況選用的被動元件80。根據一些實施例，第一處理器元件20及第二處理器元件40為不同類型的處理器元件。舉例而言，第一處理器元件20可為圖形處理器元件且第二處理器元件40可為中央處理器元件。另外，記憶體元件60電耦接至第一處理器元件20及第二處理器元件40中的每一者，且包含由一個或兩個處理器元件使用的記憶體。舉例而言，記憶體元件60可為共用記憶體元件，諸如共用3級(level 3；L3)高速緩存、嵌入式DRAM(embedded DRAM；eDRAM)或類似者。使用單獨記憶體元件60而非包含具有第一處理器元件20及/或第二處理器元件40的記憶體可允許積體電路封裝100中的記憶體的總量增大而不實質上增大處理器元件的製造成本。另外，形成不具有記憶體的第一處理器元件20及/或第二處理器元件40允許更多處理單元(例如，核心)包含於處理器元件中而不實質上增大處理器元件的覆蓋面積。
第一處理器元件20、第二處理器元件40以及記憶體元件 60可具有不同技術節點的主動元件。具體言之，第一處理器元件20及第二處理器元件40可各自具有比記憶體元件60更小的技術節點的主動元件。舉例而言，第一處理器元件20及第二處理器元件40可各自包含7奈米技術節點的主動元件，且記憶體元件60可包含16奈米技術節點的主動元件。形成具有較大技術節點的記憶體元件60使記憶體元件60的製造成本降低。
積體電路封裝100更包含重佈線結構102(以下進一步描述)。重佈線結構102包含介電層當中的金屬化圖案。重佈線結構102的金屬化圖案電耦接至積體電路封裝100的半導體元件。具體言之，重佈線結構102的金屬化圖案包含電力供應源線(VDD)及電力供應接地線(VSS)，所述電力供應源線及電力供應接地線電耦接至第一處理器元件20、第二處理器元件40、記憶體元件60以及被動元件80中的每一者以形成用於半導體元件的電力輸送網路。在其中被動元件80為PMIC的實施例中，被動元件80亦可為用於第一處理器元件20的電力輸送網路的部分。在一些實施例中，第一處理器元件20具有其自身PMIC且不連接至被動元件80。
重佈線結構102的金屬化圖案亦包含直接連接至第二處理器元件40的前側40F的資料訊號線。在其中第二處理器元件40為中央處理器元件的實施例中，將第二處理器元件40的前側40F直接連接至重佈線結構102的金屬化圖案可幫助增大與中央處理器元件的輸入/輸出(I/O)連接的量。另外，重佈線結構102的金屬化圖案可將熱量傳導遠離第二處理器元件40，此可在第二處理器元件40為諸如中央處理器元件的具有大熱耗散的元件時尤其有 利。
如下文進一步描述，積體電路封裝100的半導體元件當中的資料傳信可藉由半導體元件之間的直接連接(例如，金屬至金屬接合)而非藉由重佈線結構102的資料訊號線來實現。重佈線結構102中的資料訊號線的量可由此減少。
介電層(下文進一步描述)位於積體電路封裝100的半導體元件中的一些周圍，由此保護半導體元件。導通孔(下文進一步描述)延伸穿過介電層，由此允許積體電路封裝100的半導體元件的互連。具體言之，第一介電層104橫向地圍繞記憶體元件60及被動元件80，且第一導通孔106延伸穿過第一介電層104。第一導通孔106將第一處理器元件20的前側20F連接至第二處理器元件40的背側40B。同樣地，第二介電層108橫向地圍繞第二處理器元件40，且第二導通孔110延伸穿過第二介電層108。第二導通孔110將重佈線結構102連接至記憶體元件60的背側60B且連接至被動元件80的背側80B。一些導通孔延伸穿過多個介電層。具體言之，第三導通孔112延伸穿過第一介電層104及第二介電層108兩者。第三導通孔112將重佈線結構102連接至第一處理器元件20的前側20F。在一些實施例中，第二導通孔110及第三導通孔112電耦接至重佈線結構102的電力供應源線(VDD)及電力供應接地線(VSS)，且將功率及接地連接提供至積體電路封裝100的半導體元件。在一些實施例中，第二導通孔110及第三導通孔112中的一些亦電耦接至重佈線結構102的資料訊號線。
積體電路封裝100的半導體元件可具有不同大小使得其並不彼此同心地交疊，由此允許用於與導通孔106、導通孔110、 導通孔112以及重佈線結構102的連接的足夠空間。具體言之，半導體元件的寬度在不同橫截面圖中可不同。
記憶體元件60在第一平面(例如，圖2A中所說明的橫截面)中比第二處理器元件40更窄，且記憶體元件60在第二平面(例如，圖2B中所說明的橫截面)中比第二處理器元件40更寬。舉例而言，參考圖2D，記憶體元件60可具有寬度W1及寬度W2，且第二處理器元件40可具有寬度W3及寬度W4，其中寬度W1大於寬度W3，且寬度W2小於寬度W4。
被動元件80在第一平面(例如，圖2A中所說明的橫截面)中比第二處理器元件40元件更窄，且被動元件80在第二平面(例如，圖2B中所說明的橫截面)中比第二處理器元件40更寬。舉例而言，參考圖2D，被動元件80可具有寬度W5及寬度W6，其中寬度W5大於寬度W3，且寬度W6小於寬度W4。
第一處理器元件20在第一平面(例如，圖2A中所說明的橫截面)及第二平面(例如，圖2B中所說明的橫截面)中比第二處理器元件40、記憶體元件60以及被動元件80更寬。舉例而言，參考圖2D，第一處理器元件20可具有寬度W7及寬度W8，其中寬度W7大於寬度W1、寬度W3以及寬度W5中的每一者，且寬度W8大於寬度W2、寬度W4以及寬度W6中的每一者。
記憶體元件60安置於第一處理器元件20與第二處理器元件40之間，且接合至此兩個處理器元件。第一處理器元件20直接面對面接合至記憶體元件60。舉例而言，第一處理器元件20的前側20F可藉由混合接合(例如，藉由金屬至金屬接合及藉由介電至介電接合)來接合至記憶體元件60的前側60F。第二處理器 元件40直接背對背接合至記憶體元件60。舉例而言，第二處理器元件40的背側40B可藉由混合接合(例如，藉由金屬至金屬接合及藉由介電至介電接合)來接合至記憶體元件60的背側60B。第二處理器元件40亦接合至積體電路封裝100的其他特徵。具體言之，第二處理器元件40直接接合至第一介電層104的部分及第一導通孔106中的一些。舉例而言，第二處理器元件40的背側40B可藉由介電至介電接合來接合至第一介電層104的部分，且第二處理器元件40的背側40B亦可藉由金屬至金屬接合來接合至第一導通孔106中的一些。
在其中包含被動元件80的實施例中，被動元件80接合至第一處理器元件20。被動元件80直接面對面接合至第一處理器元件20。舉例而言，被動元件80的前側80F可藉由混合接合(例如，藉由金屬至金屬接合及藉由介電至介電接合)來接合至第一處理器元件20的前側20F。被動元件80橫向地安置於第二處理器元件40的覆蓋面積外部，且不接合至第二處理器元件40。
在封裝之後，第一處理器元件20及第二處理器元件40可由若干特徵互連。第一處理器元件20及第二處理器元件40可經由第一導通孔106直接通信。另外，由於內連線由直接接合形成，故第一處理器元件20及第二處理器元件40可經由記憶體元件60間接地通信。具體言之，第一處理器元件20及第二處理器元件40可經由記憶體元件60的內連線結構64及導通孔66通信。半導體元件之間的資料傳信經由這些內連線執行，所述內連線短於重佈線結構102的重佈線。積體電路封裝100的半導體元件當中的資料傳信時延及內連線頻寬可由此減小。另外，亦可減小阻抗 且因此減小連接的功耗。
圖3A至圖8B為根據一些實施例的在用於形成積體電路封裝100的製程期間的中間步驟的橫截面圖。圖3A、圖4A、圖5A、圖6A、圖7A以及圖8A為沿圖2C及圖2D中的參考橫截面A-A的橫截面圖。圖3B、圖4B、圖5B、圖6B、圖7B以及圖8B為沿圖2C及圖2D中的參考橫截面B-B的橫截面圖。積體電路封裝100藉由在未單體化晶圓120上堆疊元件來形成。在晶圓120的一個元件區120A中的元件的堆疊經說明，但應瞭解，晶圓120可具有任何數目的元件區且元件可堆疊於每一元件區中。
在圖3A及圖3B中，獲得晶圓120。晶圓120包括元件區120A中的第一處理器元件20。如此，晶圓120的元件區120A具有與第一處理器元件20類似的特徵。第一處理器元件20將在後續處理中經單體化(見圖8A及圖8B)以包含於積體電路封裝100中。
記憶體元件60經接合至第一處理器元件20(例如，接合至晶圓120)。第一處理器元件20及記憶體元件60藉由混合接合以面對面方式直接接合，其中第一處理器元件20的介電層30經由介電至介電接合來接合至記憶體元件60的介電層70，而不使用任何黏著材料(例如，晶粒貼合膜)，且其中第一處理器元件20的晶粒連接件28經由金屬至金屬接合來接合至記憶體元件60的晶粒連接件68，而不使用任何共熔材料(例如，焊料)。
接合可包含預接合(pre-bonding)及退火(annealing)。在預接合期間，小的按壓力經施加以將第一處理器元件20及記憶體元件60彼此相抵按壓。預接合在低溫下執行，諸如室溫，諸如 約15℃至約30℃範圍內的溫度，且在預接合之後，介電層30及介電層70彼此接合。接合強度隨後在後續退火步驟中經改良，其中介電層30及介電層70在高溫下退火，諸如約100℃至約450℃範圍內的溫度。在退火之後，形成直接接合，諸如融合接合，從而接合介電層30與介電層70。舉例而言，接合可為介電層30的材料與介電層70的材料之間的共價接合。晶粒連接件28及晶粒連接件68實體及電性地以一對一對應方式彼此連接。晶粒連接件28及晶粒連接件68可在預接合之後實體接觸，或可擴展至在退火期間變為實體接觸。另外，在退火期間，晶粒連接件28及晶粒連接件68的材料(例如，銅)混合，使得金屬至金屬接合亦經形成。因此，第一處理器元件20與記憶體元件60之間的所得接合為包含介電至介電接合及金屬至金屬接合兩者的混合接合。
被動元件80任選地接合至第一處理器元件20(例如，接合至晶圓120)。第一處理器元件20及被動元件80藉由混合接合以面對面方式直接接合，其中第一處理器元件20的介電層30經由介電至介電接合來接合至被動元件80的介電層90，而不使用任何黏著材料(例如，晶粒貼合膜)，且其中第一處理器元件20的晶粒連接件28經由金屬至金屬接合來接合至被動元件80的晶粒連接件88，而不使用任何共熔材料(例如，焊料)。混合接合可類似於上文所描述的第一處理器元件20與記憶體元件60的接合。
在圖4A及圖4B中，第一介電層104圍繞記憶體元件60及被動元件80形成。第一介電層104可在記憶體元件60及被動元件80的置放之後但在退火之前形成以完成混合接合，或可在退火之後形成。第一介電層104填充記憶體元件60與被動元件80 之間的間隙，由此保護半導體元件。第一介電層104可為氧化物，諸如氧化矽、PSG、BSG、BPSG或類似者；氮化物，諸如氮化矽或類似者；聚合物，諸如聚苯并噁唑(polybenzoxazole；PBO)、聚醯亞胺、苯環丁烷(benzocyclobuten；BCB)或類似者；密封體，諸如模製化合物、環氧樹脂或類似者；類似者，或其組合。在一些實施例中，第一介電層104為氧化物，諸如氧化矽。
第一導通孔106隨後形成以延伸穿過第一介電層104。作為用以形成第一導通孔106的實例，開口在第一介電層104中圖案化。可藉由可接受的製程來執行圖案化，諸如當第一介電層104為感光性材料時藉由將第一介電層104曝光，或藉由使用例如非等向性蝕刻來蝕刻第一介電層104。開口暴露第一處理器元件20的晶粒連接件28。晶種層形成於第一介電層104上及由開口暴露的晶粒連接件28的部分上。在一些實施例中，晶種層為金屬層，所述金屬層可為單層或包括由不同材料形成的多個子層的複合層。在特定實施例中，晶種層包括鈦層及鈦層上方的銅層。可使用例如PVD或類似者來形成晶種層。導電材料形成於晶種層上。導電材料可藉由諸如以下的鍍覆形成：電鍍或無電極鍍覆，或類似者。導電材料可包括金屬，諸如銅、鈦、鎢、鋁或類似者。晶種層及導電材料的過量部分隨後經移除，其中過量部分為上覆於第一介電層104的部分。可藉由平坦化製程來執行移除。平坦化製程在晶種層、導電材料、第一介電層104以及半導體基底62及半導體基底82上執行。所述移除同時移除晶種層及導電材料的過量部分且暴露導通孔66及導通孔86。平坦化製程可為例如CMP製程、研磨製程、回蝕製程、類似者或其組合。開口中的晶種層及導電材 料的剩餘部分形成第一導通孔106。第一介電層104、第一導通孔106、半導體基底62及半導體基底82以及導通孔66及導通孔86的頂部表面在平坦化製程之後為平面。
在圖5A及圖5B中，第二處理器元件40接合至記憶體元件60、第一導通孔106以及第一介電層104。第二處理器元件40及記憶體元件60藉由混合接合以背對背方式直接接合。因為第二處理器元件40及記憶體元件60並不彼此同心地交疊，第一導通孔106及第一介電層104的一些部分參與在混合接合中。具體言之，第二處理器元件40的介電層50經由介電至介電接合來接合至第一介電層104的部分，而不使用任何黏著材料(例如，晶粒貼合膜)。同樣地，第二處理器元件40的晶粒連接件48經由金屬至金屬接合來接合至記憶體元件60的第一導通孔106及導通孔66，而不使用任何共熔材料(例如，焊料)。混合接合可類似於上文所描述的第一處理器元件20與記憶體元件60的接合。因為第一介電層104參與在混合接合中，故與第二處理器元件40的強介電至介電接合可經形成，即使記憶體元件60的介電特徵未暴露。
在圖6A及圖6B中，第二介電層108圍繞第二處理器元件40形成。第二介電層108可在第二處理器元件40的置放之後但在退火之前形成以完成混合接合，或可在退火之後形成。第二介電層108可由與第一介電層104類似的材料及方法形成。在一些實施例中，第二介電層108為氧化物，諸如氧化矽。
第二導通孔110隨後經形成以延伸穿過第二介電層108且連接至導通孔66及導通孔86。第二導通孔110可由與第一導通孔106類似的材料及方法形成。第三導通孔112隨後經形成以延 伸穿過第一介電層104及第二介電層108且連接至晶粒連接件28。除用於第三導通孔112的開口可經圖案化穿過第一介電層104及第二介電層108兩者之外，第三導通孔112可由與第一導通孔106類似的材料及方法形成。在一些實施例中，第二導通孔110及第三導通孔112同時形成。在第二導通孔110及/或第三導通孔112的形成期間，可執行平坦化製程。第二介電層108、第二導通孔110、第三導通孔112以及第二處理器元件40的頂部表面在平坦化製程之後為平面。
在圖7A及圖7B中，重佈線結構102形成於第二介電層108、第二導通孔110、第三導通孔112以及第二處理器元件40上。重佈線結構102包含多個介電層、金屬化圖案以及通孔。舉例而言，重佈線結構102可經圖案化為由相應介電層彼此分隔的多個離散金屬化圖案。在一些實施例中，介電層由聚合物形成，所述聚合物可為感光性材料，諸如PBO、聚醯亞胺、BCB或類似者，可使用微影罩幕來圖案化。在其他實施例中，介電層由以下形成：氮化物，諸如氮化矽；氧化物，諸如氧化矽、PSG、BSG、BPSG；或類似者。介電層可藉由旋塗、層壓、CVD、類似者或其組合形成。在形成之後，介電層經圖案化以暴露下伏導電特徵。舉例而言，底部介電層經圖案化以暴露內連線結構44的金屬化圖案的部分，且中間介電層經圖案化以暴露下伏金屬化圖案的部分。可藉由可接受的製程來執行圖案化，諸如當介電層為感光性材料時藉由將介電質層曝光，或藉由使用例如非等向性蝕刻來蝕刻。若介電層為感光性材料，則介電層可在曝光之後顯影。
形成沿每一介電層且穿過每一介電層延伸的金屬化圖 案。晶種層(未說明)形成於每一相應介電層上方及穿過相應介電層的開口中。在一些實施例中，晶種層為金屬層，所述金屬層可為單層或包括由不同材料形成的多個子層的複合層。在一些實施例中，晶種層包括鈦層及在鈦層上方的銅層。晶種層可使用諸如PVD或類似者的沈積製程形成。隨後在晶種層上形成光阻且使所述光阻圖案化。光阻可藉由旋塗或類似者形成，且可曝光以用於圖案化。光阻的圖案對應於金屬化圖案。圖案化形成穿過光阻的開口以暴露晶種層。導電材料形成於光阻的開口中及晶種層的經暴露部分上。導電材料可藉由諸如以下的鍍覆形成：電鍍或無電極鍍覆，或類似者。導電材料可包括金屬或金屬合金，諸如銅、鈦、鎢、鋁、類似者或其組合。隨後，移除光阻及晶種層上未形成導電材料的部分。可藉由可接受的灰化或剝離製程，諸如使用氧電漿或類似者來移除光阻。在移除光阻後，諸如藉由使用可接受的蝕刻製程，諸如藉由濕式蝕刻或乾式蝕刻來移除晶種層的經暴露部分。晶種層及導電材料的剩餘部分形成用於重佈線結構102的一個層的金屬化圖案。
重佈線結構102經說明為一實例。比所說明更多或更少的介電層及金屬化圖案可藉由重複或省略上文所描述的步驟來形成於重佈線結構102中。
在圖8A及圖8B中，單體化製程藉由例如在元件區120A周圍沿切割道區鋸切來執行。單體化製程包含鋸切重佈線結構102、第一介電層104、第二介電層108以及晶圓120。單體化製程將晶圓120的元件區120A(包括第一處理器元件20)與鄰近元件區(未說明)分離以形成包括第一處理器元件20的積體電路封 裝100。記憶體元件60以面對面方式接合至第一處理器元件20，且記憶體元件60以背對背方式接合至第二處理器元件40，而不使用焊料。所得積體電路封裝100由此不含焊料。在單體化之後，重佈線結構102、第一介電層104、第二介電層108以及第一處理器元件20橫向地相連。
圖9A及圖9B為根據一些實施例的積體電路封裝100的橫截面圖。圖9A沿圖2C及圖2D中的參考橫截面A-A進行說明。圖9B沿圖2C及圖2D中的參考橫截面B-B進行說明。在此實施例中，第一處理器元件20不為裸積體電路晶粒，而實際上為封裝晶粒。第一處理器元件20可藉由以下形成：獲得包括第一處理器元件20的晶圓，鋸切晶圓以單體化第一處理器元件20，且隨後用密封體32密封第一處理器元件20。積體電路封裝100的另一半導體元件可隨後堆疊於經密封第一處理器元件20上。
圖10及圖11為根據一些實施例的在用於形成實施積體電路封裝100的系統的製程期間的中間步驟的橫截面圖。圖10及圖11沿圖2C及圖2D中的參考橫截面B-B進行說明。在此實施例中，積體電路封裝100直接安裝至封裝基底。
在圖10中，形成實體及電性地連接至重佈線結構102的導電連接件114。導電連接件114可在積體電路封裝100經單體化之前或之後形成。重佈線結構102的頂部介電層可圖案化以暴露下伏金屬化圖案的部分。在一些實施例中，凸塊下金屬(under bump metallurgy；UBM)可形成於開口中。導電連接件114形成於UBM上。導電連接件114可為球柵陣列封裝(ball grid array；BGA)連接件、焊料球、金屬柱、受控塌陷晶片連接(controlled collapse chip connection；C4)凸塊、微型凸塊、無電鍍鎳-無電鍍鈀-浸鍍金技術(electroless nickel-electroless palladium-immersion gold technique；ENEPIG)形成的凸塊或類似者。導電連接件114可由金屬或金屬合金形成，所述金屬或金屬合金諸如焊料、銅、鋁、金、鎳、銀、鈀、錫、類似者或其組合。在一些實施例中，藉由經由諸如蒸鍍、電鍍、列印、焊料轉移、植球或類似者的此類常用方法最初形成焊料層來形成導電連接件114。在焊料層已形成於結構上後，可執行回焊以便將材料塑形成所要凸塊形狀。在另一實施例中，導電連接件114為藉由濺鍍、列印、電鍍、無電極鍍覆、CVD或類似者形成的金屬柱(諸如銅柱)。金屬柱可並無焊料且具有實質上豎直側壁。導電連接件114電耦接至重佈線結構102的金屬化圖案。
在圖11中，積體電路封裝100經翻轉且使用導電連接件114連接至封裝基底200。封裝基底200可由半導體材料製成，諸如矽、鍺、金剛石或類似者。替代地，亦可使用化合物材料，諸如矽鍺、碳化矽、砷化鎵、砷化銦、磷化銦、碳化矽鍺、磷砷化鎵、磷化鎵銦、這些的組合以及類似者。此外，封裝基底200可為SOI基底。通常，SOI基底包含半導體材料層，諸如磊晶矽、鍺、矽鍺、SOI、SGOI或其組合。在一個替代實施例中，封裝基底200基於諸如纖維玻璃強化樹脂芯的絕緣芯。一種實例芯材為諸如FR4的纖維玻璃樹脂。芯材的替代物包含雙馬來醯亞胺-三嗪(bismaleimide-triazine；BT)樹脂，或替代地，其他印刷電路板(PCB)材料或膜。諸如味素累積膜(Ajinomoto build-up film；ABF)的累積膜或其他層壓物可用於封裝基底200。
封裝基底200可包含主動元件及被動元件(未說明)。諸如電晶體、電容器、電阻器、這些的組合以及類似者的元件可用於產生用於系統的設計的結構及功能需求。可使用任何適合的方法來形成所述元件。
封裝基底200亦可包含金屬化層及通孔(未說明)以及在金屬化層及通孔上方的接合墊202。金屬化層可形成於主動元件及被動元件上方，且經設計以連接各種元件以形成功能電路。金屬化層可由介電質(例如，低k介電材料)與導電材料(例如，銅)的交替層形成(其中通孔將導電材料層互連)且可經由任何適合的製程(諸如沈積、鑲嵌、雙鑲嵌或類似者)形成。在一些實施例中，封裝基底200實質上不含主動元件及被動元件。
導電連接件114經回焊以將重佈線結構102的UBM附接至接合墊202。導電連接件114將封裝基底200(包含封裝基底200中的金屬化層)電性及/或實體地連接至積體電路封裝100。在一些實施例中，被動元件(例如，表面安裝元件(surface mount device；SMD)，未說明)可在安裝在封裝基底200上之前附接至積體電路封裝100(例如，接合至接合墊202)。在此類實施例中，被動元件可接合至積體電路封裝100的與導電連接件114相同的表面。在一些實施例中，被動元件(例如，SMD，未說明)可附接至封裝基底200，例如，附接至接合墊202。
導電連接件114可具有環氧樹脂焊劑(epoxy flux)(未示出)，所述環氧樹脂焊劑在導電連接件114利用在積體電路封裝100附接至封裝基底200之後剩餘的環氧樹脂焊劑的環氧樹脂部分中的至少一些來進行回焊之前形成在導電連接件114上。此剩餘環 氧樹脂部分可充當底部填充物以減小應力且保護由回焊導電連接件114產生的接合部。在一些實施例中，底部填充物(未說明)可圍繞導電連接件114形成於積體電路封裝100與封裝基底200之間。底部填充物可在附接積體電路封裝100之後藉由毛細流動製程形成，或可在附接積體電路封裝100之前藉由適合的沈積方法形成。
圖12至圖16為根據一些其他實施例的在用於形成實施積體電路封裝100的系統的製程期間的中間步驟的橫截面圖。圖12至圖16沿圖2C及圖2D中的參考橫截面B-B進行說明。在此實施例中，積體電路封裝100經單體化且包含於封裝組件中。在一個封裝區302A中的元件的封裝經說明，但應瞭解，任何數目的封裝區可同時經形成。封裝區302A將在後續處理中經單體化。單體化封裝組件可為扇出型封裝，諸如積體扇出(integrated fan-out；InFO)封裝。扇出型封裝隨後經安裝至封裝基底。
在圖12中，提供載體基底302，且釋放層304形成於載體基底302上。載體基底302可為玻璃載體基底、陶瓷載體基底或類似者。載體基底302可為晶圓，使得多個封裝可同時形成於載體基底302上。釋放層304可由聚合物類材料形成，可將所述聚合物類材料連同載體基底302一起自將在後續步驟中形成的上覆結構移除。在一些實施例中，釋放層304為在加熱時損失其黏著特性的環氧類熱釋放材料，諸如光-熱轉換(light-to-heat-conversion；LTHC)釋放塗層。在其他實施例中，釋放層304可為在暴露於UV光時損失其黏著特性的紫外(ultra-violet；UV)黏膠。釋放層304可經配製為液體且經固化，可為層壓至載體基底 302上的層壓膜，或可為類似者。釋放層304的頂部表面可經水平化，且可具有高度平坦性。
重佈線結構306可形成於釋放層304上。重佈線結構306可以與相對於圖7A及圖7B所描述的重佈線結構102類似的方式及材料形成。重佈線結構306包含介電層及金屬化圖案(有時稱為重佈線層或重佈線)。比所說明更多或更少的介電層及金屬化圖案可形成於重佈線結構306中。重佈線結構306為視情況選用的。在一些實施例中，不具有金屬化圖案的介電層代替重佈線結構306形成於釋放層304上。
在圖13中，形成延伸穿過重佈線結構306的最頂部介電層的導通孔308。因此，導通孔308連接至重佈線結構306的金屬化圖案。導通孔308為視情況選用的，且可省略。舉例而言，在其中省略重佈線結構306的實施例中可(或可不)省略導通孔308。
作為用以形成導通孔308的一實例，開口可形成於重佈線結構306的最頂部介電層中。晶種層隨後形成於重佈線結構306上方，例如，形成於重佈線結構306的最頂部介電層及由開口暴露的重佈線結構306的金屬化圖案的部分上。在一些實施例中，晶種層為金屬層，所述金屬層可為單層或包括由不同材料形成的多個子層的複合層。在特定實施例中，晶種層包括鈦層及鈦層上方的銅層。可使用例如PVD或類似者來形成晶種層。在晶種層上形成光阻並使所述光阻圖案化。光阻可藉由旋塗或類似者形成，且可曝光以用於圖案化。光阻的圖案對應於導通孔。圖案化形成穿過光阻的開口以暴露晶種層。導電材料形成於光阻的開口中及晶種層的經暴露部分上。導電材料可藉由諸如以下的鍍覆形成：電鍍或無 電極鍍覆，或類似者。導電材料可包括金屬，如銅、鈦、鎢、鋁或類似者。光阻及晶種層上未形成導電材料的部分經移除。可藉由可接受的灰化或剝離製程，諸如使用氧電漿或類似者來移除光阻。在移除光阻後，諸如藉由使用可接受的蝕刻製程，諸如藉由濕式蝕刻或乾式蝕刻來移除晶種層的經暴露部分。晶種層及導電材料的剩餘部分形成導通孔308。
單體化積體電路封裝100經置放於重佈線結構306上。在所說明實施例中，獲得類似於相對於圖8A及圖8B所描述的結構。在另一實施例中，獲得類似於相對於圖9A及圖9B所描述的結構。如上所指出，在積體電路封裝100中，元件在不使用焊料的情況下彼此接合。單體化積體電路封裝100由此不含焊料。
在圖14中，在積體電路封裝100周圍形成密封體310。密封體310橫向地圍繞積體電路封裝100。密封體310可為模製化合物、環氧樹脂或類似者。密封體310可藉由壓縮模製、轉移模製或類似方法來施加，且可以液體或半液體形式施加且隨後經固化。
在一些實施例中，密封體310形成於積體電路封裝100上方使得重佈線結構102經掩埋或覆蓋。平坦化製程可在密封體310上執行以暴露積體電路封裝100。平坦化製程可移除密封體310的材料直至重佈線結構102經暴露為止。密封體310及重佈線結構102的頂部表面在平坦化製程之後為共面的。平坦化製程可為例如CMP製程、研磨製程、回蝕製程、類似者或其組合。在其他實施例中，密封體310不形成於積體電路封裝100上方，且平坦化製程沒有必要暴露積體電路封裝100。
重佈線結構312隨後形成於密封體310及重佈線結構102 上。重佈線結構312可以與相對於圖7A及圖7B所描述的重佈線結構102類似的方式及材料形成。重佈線結構312包含介電層及金屬化圖案(有時稱為重佈線層或重佈線)。比所說明更多或更少的介電層及金屬化圖案可形成於重佈線結構306中。重佈線結構312的底部介電層實體地接觸密封體310及重佈線結構102的頂部介電層重佈線結構312的金屬化圖案電耦接至重佈線結構102的金屬化圖案。
形成實體及電性地連接至重佈線結構312的金屬化圖案的導電連接件314。導電連接件314可以與相對於圖10所描述的導電連接件114類似的方式及材料形成。
在圖15中，載體基底剝離經執行以使載體基底302自重佈線結構306(例如，重佈線結構306的最底部介電層)脫離(剝離)。根據一些實施例，剝離包含使諸如雷射光或UV光的光投影於釋放層304上，以使得釋放層304在光熱下分解且載體基底302可經移除。結構隨後經翻轉且置放於例如載帶上。
另外，形成穿過重佈線結構306的最底部介電層的導電連接件316。可形成穿過重佈線結構306的最底部介電層的開口，從而暴露重佈線結構306的金屬化圖案的部分。舉例而言，可使用雷射鑽孔、蝕刻或類似者形成開口。導電連接件316經形成於開口中，且連接至重佈線結構306的金屬化圖案的經暴露部分。導電連接件316可以與相對於圖10所描述的導電連接件114類似的方式及材料形成。
在圖16中，單體化製程藉由例如在封裝區302A周圍沿切割道區鋸切來執行。單體化製程包括鋸切重佈線結構306、重佈 線結構312以及密封體310。單體化製程將封裝區302A與鄰近封裝區(未說明)分離以形成積體電路封裝300。在單體化之後，重佈線結構306、重佈線結構312以及密封體310橫向地相連。
另一積體電路封裝400可附接至積體電路封裝300以形成疊層封裝結構。積體電路封裝400可為記憶體封裝。積體電路封裝400可在積體電路封裝300單體化之前或之後附接至積體電路封裝300。積體電路封裝400包含基底402及連接至基底402的一或多個晶粒404。在一些實施例(未示出)中，晶粒404的一或多個堆疊連接至基底402。基底402可由半導體材料製成，所述半導體材料諸如矽、鍺、金剛石或類似者。在一些實施例中，亦可使用化合物材料，諸如矽鍺、碳化矽、砷化鎵、砷化銦、磷化銦、碳化矽鍺、磷砷化鎵、磷化鎵銦、這些的組合以及類似者。此外，基底402可為絕緣層上矽(SOI)基底。通常，SOI基底包含半導體材料層，諸如磊晶矽、鍺、矽鍺、SOI、絕緣層上矽鍺(silicon germanium on insulator；SGOI)或其組合。在一個替代實施例中，基底402基於諸如纖維玻璃強化樹脂芯的絕緣芯。一種實例芯材為諸如FR4的纖維玻璃樹脂。芯材的替代物包含雙馬來醯亞胺-三嗪(BT)樹脂，或替代地，其他印刷電路板(PCB)材料或膜。諸如味素累積膜(ABF)的累積膜或其他層壓物可用於基底402。
基底402可包含主動元件及被動元件(未示出)。如於本領域具有通常知識者將認識到，諸如電晶體、電容器、電阻器、這些的組合以及類似者的廣泛多種元件可用於產生用於積體電路封裝400的設計的結構及功能需求。可使用任何適合的方法來形成所述元件。基底402亦可包含金屬化層(未示出)以及穿孔。金屬 化層可形成於主動元件及被動元件上方，且經設計以連接各種元件以形成功能電路。金屬化層可由介電質(例如，低k介電材料)與導電材料(例如，銅)的交替層形成(其中通孔將導電材料層互連)且可經由任何適合的製程(諸如沈積、鑲嵌、雙鑲嵌或類似者)形成。在一些實施例中，基底402實質上不含主動元件及被動元件。
基底402可在連接至導電連接件316的基底402的一側上具有接合墊406。在一些實施例中，藉由在基底402的所述側上將凹部(未示出)形成至介電層(未示出)中來形成接合墊406。凹部可經形成以允許將接合墊406嵌入於介電層中。在其他實施例中，省略凹部，此是由於接合墊406可形成於介電層上。在一些實施例中，接合墊406包含由銅、鈦、鎳、金、鈀、類似者或其組合製成的薄晶種層(未示出)。接合墊406的導電材料可沈積於薄晶種層上方。導電材料可藉由電化學鍍覆製程、無電極鍍覆製程、CVD、ALD、PVD、類似者或其組合形成。在一實施例中，接合墊406的導電材料為銅、鎢、鋁、銀、金、類似者或其組合。
在一實施例中，接合墊406為包含三個導電材料層(諸如，鈦層、銅層以及鎳層)的UBM。舉例而言，接合墊406可由銅形成，可形成於鈦層(未示出)上，且具有鎳修飾面層(nickel finish)，所述鎳修飾面層可改良積體電路封裝400的存放期，此可在積體電路封裝400為記憶體元件(諸如DRAM模組)時為尤其有利的。然而，於本領域具有通常知識者將認識到，存在適合於形成接合墊406的許多適合的材料及層的配置，諸如，鉻/鉻-銅合金/銅/金的配置、鈦/鈦鎢/銅的配置或銅/鎳/金的配置。可用於接合墊 406的任何適合的材料或材料層全部意欲包含於當前申請案的範疇內。
在所說明實施例中，晶粒404藉由導電凸塊連接至基底402，但可使用其他連接，諸如線接合。在一實施例中，晶粒404為堆疊記憶體晶粒。舉例而言，晶粒404可為記憶體晶粒，諸如低功率(low-power；LP)雙資料速率(double data rate；DDR)記憶體模組，諸如LPDDR1、LPDDR2、LPDDR3、LPDDR4或類似者。
晶粒404及線接合(當存在時)可由模製材料410密封。模製材料410可例如使用壓縮模製來模製於晶粒404及線接合上。在一些實施例中，模製材料410為模製化合物、聚合物、環氧樹脂、氧化矽填充物材料、類似者或其組合。固化製程可經執行以固化模製材料410；固化製程可為熱固化、UV固化、類似者，或其組合。在一些實施例中，晶粒404掩埋在模製材料410中，且在模製材料410的固化之後，諸如研磨的平坦化步驟經執行以移除模製材料410的過量部分且提供用於積體電路封裝400的實質上平坦表面。
在形成積體電路封裝400之後，積體電路封裝400藉助於導電連接件316附接至積體電路封裝300。導電連接件316可藉由回焊導電連接件316來連接至接合墊406。晶粒404可由此經由導電連接件316、導通孔308以及重佈線結構306、重佈線結構312電耦接至積體電路封裝100。
在一些實施例中，阻焊劑(未示出)形成於基底402的與晶粒404相對的側上。導電連接件316可安置於待連接至基底402中的導電特徵(例如，接合墊406)的阻焊劑中的開口中。阻焊劑 可用於保護基底402的區域不受外部損壞。
在一些實施例中，導電連接件316具有環氧樹脂焊劑(未示出)，所述環氧樹脂焊劑在導電連接件316利用在積體電路封裝400附接至重佈線結構306之後剩餘的環氧樹脂焊劑的環氧樹脂部分中的至少一些進行回焊之前形成於導電連接件316上。
在一些實施例中，底部填充物(未示出)形成於重佈線結構306與基底402之間，且圍繞導電連接件316。底部填充物可減小應力且保護由導電連接件316的回焊產生的接合部。底部填充物可在附接積體電路封裝400之後藉由毛細流動製程形成，或可在附接積體電路封裝400之前藉由適合的沈積方法形成。在其中形成環氧樹脂焊劑的實施例中，環氧樹脂焊劑可充當底部填充物。
疊層封裝結構隨後經翻轉且使用導電連接件314附接至封裝基底200。封裝基底200可類似於相對於圖11所描述的封裝基底200。舉例而言，封裝基底200可包含連接至導電連接件314的接合墊202。
圖17為根據一些其他實施例的實施積體電路封裝100的系統的橫截面圖。圖17沿圖2C及圖2D中的參考橫截面B-B進行說明。在此實施例中，形成類似於圖16的積體電路封裝300，但省略重佈線結構306、導通孔308、導電連接件316以及積體電路封裝400。
實施例可實現優勢。藉由混合接合來互連晶粒使積體電路封裝的重佈線結構中的資料訊號線的量減少。電力輸送及佈線亦可藉由使用整合於積體電路封裝中的被動元件而簡化。使用單獨記憶體元件而非包含具有積體電路封裝的處理器元件的記憶體 可允許積體電路封裝中的記憶體的總量增大而不實質上增大處理器元件的製造成本。另外，形成積體電路封裝的不具有記憶體的處理器元件允許更多處理單元(例如，核心)包含於處理器元件中而不實質上增大處理器元件的覆蓋面積。積體電路封裝的覆蓋面積及製造成本可因此減小。
亦可包含其他特性及製程。舉例而言，可包含測試結構以幫助對3D封裝或3DIC元件的校驗測試。測試結構可包含例如形成於重佈線層中或基底上的測試墊，其允許測試3D封裝或3DIC、使用探針及/或探測卡以及類似者。可對中間結構以及最末結構執行校驗測試。此外，本文中所揭露的結構及方法可結合併入有對良裸晶粒的中間校驗的測試方法而使用，以提高良率且降低成本。
在一實施例中，積體電路封裝包含：第一處理器元件，具有前側；共用記憶體元件，具有前側及與前側相對的背側，共用記憶體元件的前側藉由金屬至金屬接合及藉由介電至介電接合來接合至第一處理器元件的前側；第一介電層，橫向地圍繞共用記憶體元件；第一導通孔，延伸穿過第一介電層；第二處理器元件，具有前側及與前側相對的背側，第一導通孔將第一處理器元件的前側連接至第二處理器元件的背側，第二處理器元件的背側藉由金屬至金屬接合來接合至第一導通孔及共用記憶體元件的背側，第二處理器元件的背側藉由介電至介電接合來接合至第一介電層，第一處理器元件及第二處理器元件各自為不同類型的處理器元件；以及第一重佈線結構，連接至第二處理器元件的前側。
在一些實施例中，積體電路封裝更包含：第二介電層，橫向地圍繞第二處理器元件；第二導通孔，延伸穿過第二介電層，第 二導通孔將第一重佈線結構連接至共用記憶體元件的背側；以及第三導通孔，延伸穿過第一介電層及第二介電層，第三導通孔將第一重佈線結構連接至第一處理器元件的前側。在一些實施例中，第一重佈線結構包含電力供應源線及電力供應接地線，第二導通孔及第三導通孔各自電耦接至電力供應源線及電力供應接地線。在一些實施例中，共用記憶體元件包含基底穿孔(TSV)，第二處理器元件藉由TSV及第一導通孔來電耦接至第一處理器元件。在一些實施例中，積體電路封裝更包含：被動元件，具有前側及與前側相對的背側，被動元件的前側藉由金屬至金屬接合及藉由介電至介電接合來接合至第一處理器元件的前側；第二介電層，橫向地圍繞第二處理器元件；以及第二導通孔，延伸穿過第二介電層，第二導通孔將第一重佈線結構連接至被動元件的背側。在一些實施例中，第一處理器元件為圖形處理單元(GPU)，第二處理器元件為中央處理單元(CPU)，且被動元件為用於GPU的功率管理積體電路(PMIC)。在一些實施例中，積體電路封裝更包含：密封體，橫向地圍繞共用記憶體元件、第一處理器元件、第二處理器元件以及第一重佈線結構；以及第二重佈線結構，接觸密封體，第二重佈線結構連接至第一重佈線結構。在一些實施例中，積體電路封裝更包含：封裝基底；以及導電連接件，將封裝基底連接至第二重佈線結構。在一些實施例中，積體電路封裝更包含：封裝基底；以及導電連接件，將封裝基底連接至第一重佈線結構。在一些實施例中，第一處理器元件及第二處理器元件具有比共用記憶體元件更小的技術節點的主動元件。
在一實施例中，積體電路封裝包含：圖形處理器元件；被 動元件，耦接至圖形處理器元件，被動元件直接面對面接合至圖形處理器元件；共用記憶體元件，耦接至圖形處理器元件，共用記憶體元件直接面對面接合至圖形處理器元件；中央處理器元件，耦接至共用記憶體元件，中央處理器元件直接背對背接合至共用記憶體元件，中央處理器元件及圖形處理器元件各自具有比共用記憶體元件更小的技術節點的主動元件；以及重佈線結構，耦接至中央處理器元件、共用記憶體元件、被動元件以及圖形處理器元件。
在一些實施例中，共用記憶體元件在第一平面中比中央處理器元件更窄，且共用記憶體元件在第二平面中比中央處理器元件更寬，第一平面垂直於第二平面。在一些實施例中，圖形處理器元件在第一平面及第二平面中比中央處理器元件及共用記憶體元件更寬。
在一實施例中，積體電路封裝的製造方法包含：將共用記憶體元件接合至第一處理器元件；在共用記憶體元件周圍形成第一介電層；形成延伸穿過第一介電層的第一導通孔，第一導通孔連接至第一處理器元件；將第二處理器元件接合至第一導通孔、第一介電層以及共用記憶體元件，第一處理器元件及第二處理器元件各自為不同類型的處理器元件；在第二處理器元件周圍形成第二介電層；形成延伸穿過第二介電層的第二導通孔，第二導通孔連接至共用記憶體元件；形成延伸穿過第一介電層及第二介電層的第三導通孔，第三導通孔連接至第一處理器元件；以及在第二導通孔、第三導通孔、第二介電層以及第二處理器元件上形成重佈線結構。
在一些實施例中，方法更包含：獲得包含第一處理器元件 的晶圓，其中將共用記憶體元件接合至第一處理器元件包含將共用記憶體元件接合至晶圓；以及在形成重佈線結構之後，鋸切晶圓、第一介電層、第二介電層以及重佈線結構。在一些實施例中，方法更包含，在將共用記憶體元件接合至第一處理器元件之前：獲得包含第一處理器元件的晶圓；鋸切晶圓以單體化第一處理器元件；以及密封第一處理器元件。在一些實施例中，形成第一導通孔包含：圖案化第一介電層中的第一開口，第一開口暴露第一處理器元件的晶粒連接件；在第一開口中鍍覆導電材料；以及平坦化導電材料及第一介電層，導電材料在第一開口中的剩餘部分形成第一導通孔。在一些實施例中，形成第二導通孔包含：圖案化第二介電層中的第二開口，第二開口暴露共用記憶體元件的晶粒連接件；在第二開口中鍍覆導電材料；以及平坦化導電材料及第二介電層，導電材料在第二開口中的剩餘部分形成第二導通孔。在一些實施例中，方法更包含將被動元件接合至第一處理器元件，其中形成第一介電層包含在被動元件周圍形成第一介電層，且其中第二導通孔的一子集連接至被動元件。在一些實施例中，第一處理器元件為圖形處理單元(GPU)，第二處理器元件為中央處理單元(CPU)，且被動元件為用於GPU的功率管理積體電路(PMIC)。
前文概述若干實施例的特徵以使得本領域的技術人員可更佳地理解本揭露內容的態樣。本領域的技術人員應理解，其可易於使用本揭露內容作為設計或修改用於實現本文中所引入的實施例的相同目的及/或達成相同優勢的其他製程及結構的基礎。本領域的技術人員亦應認識到，這些等效構造並不脫離本揭露內容的精神及範疇，且本領域的技術人員可在不脫離本揭露內容的精神 及範疇的情況下在本文中作出各種改變、替代及更改。
20:第一處理器元件 40:第二處理器元件 60:記憶體元件 80:被動元件 100:積體電路封裝 102:重佈線結構 104:第一介電層 106:第一導通孔 108:第二介電層 110:第二導通孔 112:第三導通孔

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  1. 一種積體電路封裝，包括：第一處理器元件，具有前側；共用記憶體元件，具有前側及與所述前側相對的背側，所述共用記憶體元件的所述前側藉由金屬至金屬接合及藉由介電至介電接合來接合至所述第一處理器元件的所述前側；第一介電層，橫向地圍繞所述共用記憶體元件；第一導通孔，延伸穿過所述第一介電層；第二處理器元件，具有前側及與所述前側相對的背側，所述第一導通孔將所述第一處理器元件的所述前側連接至所述第二處理器元件的所述背側，所述第二處理器元件的所述背側藉由金屬至金屬接合來接合至所述第一導通孔及所述共用記憶體元件的所述背側，所述第二處理器元件的所述背側藉由介電至介電接合來接合至所述第一介電層，所述第一處理器元件及所述第二處理器元件各自為不同類型的處理器元件；以及第一重佈線結構，連接至所述第二處理器元件的所述前側。
  2. 如請求項1之積體電路封裝，更包括：第二介電層，橫向地圍繞所述第二處理器元件；第二導通孔，延伸穿過所述第二介電層，所述第二導通孔將所述第一重佈線結構連接至所述共用記憶體元件的所述背側；以及第三導通孔，延伸穿過所述第一介電層及所述第二介電層，所述第三導通孔將所述第一重佈線結構連接至所述第一處理器元件的所述前側。
  3. 如請求項1之積體電路封裝，更包括：被動元件，具有前側及與所述前側相對的背側，所述被動元件的所述前側藉由金屬至金屬接合及藉由介電至介電接合來接合至所述第一處理器元件的所述前側；第二介電層，橫向地圍繞所述第二處理器元件；以及第二導通孔，延伸穿過所述第二介電層，所述第二導通孔將所述第一重佈線結構連接至所述被動元件的所述背側。
  4. 如請求項1之積體電路封裝，更包括：密封體，橫向地圍繞所述共用記憶體元件、所述第一處理器元件、所述第二處理器元件以及所述第一重佈線結構；以及第二重佈線結構，接觸所述密封體，所述第二重佈線結構連接至所述第一重佈線結構。
  5. 如請求項1之積體電路封裝，其中所述第一處理器元件及所述第二處理器元件具有比所述共用記憶體元件更小的技術節點的主動元件。
  6. 一種積體電路封裝，包括：圖形處理器元件；被動元件，耦接至所述圖形處理器元件，所述被動元件直接面對面接合至所述圖形處理器元件；共用記憶體元件，耦接至所述圖形處理器元件，所述共用記憶體元件直接面對面接合至所述圖形處理器元件；中央處理器元件，耦接至所述共用記憶體元件，所述中央處理器元件直接背對背接合至所述共用記憶體元件，所述中央處理器元件及所述圖形處理器元件各自具有比所述共用記憶體元件更 小的技術節點的主動元件；以及重佈線結構，耦接至所述中央處理器元件、所述共用記憶體元件、所述被動元件以及所述圖形處理器元件。
  7. 如請求項6之積體電路封裝，其中所述共用記憶體元件在第一平面中比所述中央處理器元件更窄，且所述共用記憶體元件在第二平面中比所述中央處理器元件更寬，所述第一平面垂直於所述第二平面。
  8. 一種積體電路封裝的製作方法，包括：將共用記憶體元件接合至第一處理器元件；在所述共用記憶體元件周圍形成第一介電層；形成延伸穿過所述第一介電層的第一導通孔，所述第一導通孔連接至所述第一處理器元件；將第二處理器元件接合至所述第一導通孔、所述第一介電層以及所述共用記憶體元件，所述第一處理器元件及所述第二處理器元件各自為不同類型的處理器元件；在所述第二處理器元件周圍形成第二介電層；形成延伸穿過所述第二介電層的第二導通孔，所述第二導通孔連接至所述共用記憶體元件；形成延伸穿過所述第一介電層及所述第二介電層的第三導通孔，所述第三導通孔連接至所述第一處理器元件；以及在所述第二導通孔、所述第三導通孔、所述第二介電層以及所述第二處理器元件上形成重佈線結構。
  9. 如請求項8之方法，更包括：獲得包括所述第一處理器元件的晶圓，其中將所述共用記憶 體元件接合至所述第一處理器元件包括將所述共用記憶體元件接合至所述晶圓；以及在形成所述重佈線結構之後，鋸切所述晶圓、所述第一介電層、所述第二介電層以及所述重佈線結構。
  10. 如請求項8之方法，更包括，在將所述共用記憶體元件接合至所述第一處理器元件之前：獲得包括所述第一處理器元件的晶圓；鋸切所述晶圓以單體化所述第一處理器元件；以及密封所述第一處理器元件。
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