TW202205560A - 半導體封裝及其形成方法 - Google Patents

半導體封裝及其形成方法 Download PDF

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TW202205560A
TW202205560A TW110113816A TW110113816A TW202205560A TW 202205560 A TW202205560 A TW 202205560A TW 110113816 A TW110113816 A TW 110113816A TW 110113816 A TW110113816 A TW 110113816A TW 202205560 A TW202205560 A TW 202205560A
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package
semiconductor
encapsulant
substrate
heat spreader
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TW110113816A
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TWI783449B (zh
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張豐願
黃博祥
魯立忠
志純 李
盧以謙
陳又豪
張克正
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台灣積體電路製造股份有限公司
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Abstract

一種半導體封裝包含第一封裝組件，其包含: 第一半導體晶片；環繞第一半導體晶片的第一封裝劑；以及電性連接第一半導體晶片的第一重分佈結構。半導體封裝更包含接合至第一封裝組件的第二封裝組件，其中第二封裝組件包含第二半導體晶片；位於第一半導體晶片與第二封裝組件之間的散熱器；以及位於第一封裝組件與第二封裝組件之間的第二封裝劑，其中第二封裝劑的熱導率低於散熱器的熱導率。

Description

半導體封裝中的散熱器及其形成方法
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由於各種電子組件(如，電晶體、二極體、電阻、電容器等)的積體密度不斷改進，半導體產業經歷快速成長。在大多數情況下，積體密度的改善已從最小特徵大小的反覆減少得到，該減少允許更多的組件可被積體化至給定區域中。因為將電子裝置縮小之需求的增長，已浮現對於較小且更有創意之半導體晶片封裝技術的需要。此種封裝系統的一實例是封裝件上封裝件(Package-on-Package ，PoP)技術。在PoP裝置中，頂部半導體封裝件被堆疊在底部半導體封裝件的頂部上，以提供高度積體化及組件密度。PoP技術一般使得能夠生產具有增進之功能性及小的印刷電路板(printed circuit board，PCB)上底面積之半導體裝置。
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之後的揭示內容提供了許多不同的實施方式或實施例，以實現所提供的標的的不同特徵。以下描述組件和配置的具體實施例，以簡化本揭示內容。這些當然僅是實施例，並不意圖限定。例如，在隨後的描述中，形成第一特徵高於第二特徵或在第二特徵上方，可能包括第一和第二特徵以直接接觸形成的實施方式，且也可能包括附加的特徵可能形成於第一和第二特徵之間，因此第一和第二特徵可能不是直接接觸的實施方式。此外，本揭示內容可在各個實施例中重複標示數字和/或字母。這樣的重複，是為了簡化和清楚起見，並不是意指所討論的各個實施方式之間和/或配置之間的關係。
此外，諸如「在……之下」、「在……下方」、「下部」、「在……上方」、「上部」及其類似者之空間相對術語在本文中為易於描述可得以使用，以描述如諸圖中所說明之一元件或特徵與另一（多個）元件或特徵的關係。除諸圖中所描繪之方位之外，空間相對術語亦意欲涵蓋在使用或操作中之裝置的不同方位。設備可以其他方式定向（旋轉90度或以其他方位），且本文所使用之空間相對描述符可同樣經相應地解譯。
根據一些實施例，封裝包含接合至積體電路(integrated circuit，IC)封裝組件的記憶體封裝組件，其中積體電路封裝組件包含一個或多個IC晶片。在一些實施例中，具有相對較高的熱導率(thermal conductivity)的散熱器設置在記憶體封裝組件與IC封裝組件之間，以改善散熱。舉例來說，散熱器可以附接至IC晶片的背面，且散熱器可以從IC晶片延伸至記憶體封裝。在其他實施例中，IC晶片可以直接附接至記憶體封裝以改善散熱。因此，在半導體封裝實施例中，熱可以通過散熱器有效地從IC晶片散發至散熱池(heat sink)，也可以藉由將IC晶片直接連接到記憶體封裝而有效地散發。
第1圖繪示根據一些實施例之積體電路晶片50的剖面示意圖。積體電路晶片50將在後續處理中被封裝以形成積體電路封裝。積體電路晶片50可以是邏輯晶片(例如，中央處理器(central processing unit，CPU)、圖形處理單元(graphics processing unit，GPU)、晶片上系統(system-on-a-chip，SoC)、應用處理器(application processor，AP)、微控制器(microcontroller)等)，記憶晶片(例如，動態隨機存取記憶體(dynamic random access memory，DRAM)晶片、靜態隨機存取記憶體(static random access memory，SRAM)晶片等)，電源管理晶片(power management die)(例如，電源管理積體電路(power management integrated circuit，PMIC)晶片)，射頻(radio frequency，RF)晶片，感測晶片(sensor die)、微機電系統(micro-electro-mechanical-system，MEMS)晶片，信號處理晶片(signal processing die)(例如，數位信號處理(digital signal processing，DSP)晶片)，前端晶片(front-end die)(例如，模擬前端(analog front-end，AFE)晶片)，類似的或其組合。
積體電路晶片50可以形成在晶圓中，此晶圓可以包含在後續步驟中被分割以形成多個積體電路晶片的不同裝置區域。可以根據適用的製造製程來加工積體電路晶片50以形成積體電路。舉例來說，積體電路晶片50包含半導體基板52，例如矽基板、摻雜或未摻雜基板、或絕緣體上半導體(semiconductor-on-insulator，SOI)的主動層基板。半導體基板52可以包含其他半導體材料，例如 鍺(germanium)；包含碳化矽(silicon carbide)、砷化鎵(gallium arsenic)、磷化鎵(gallium phosphide)、磷化銦(indium phosphide)、砷化銦(indium arsenide)和/或銻化銦(indium antimonide)的化合物半導體；包含SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP的合金半導體；或其組合。也可以使用其他基板，例如多層 (multi-layered)基板或漸變基板(gradient substrates)。半導體基板52具有一活性表面(active surface)(例如，在第1圖中面向上的表面)，有時被稱為前側，以及一非活性表面(inactive surface)(例如，在第1圖中面向下的表面)，有時被稱為後側。
裝置(以電晶體為代表)54可以形成在半導體基板52的前表面處。裝置54可以是主動裝置(active devices)(例如，電晶體、二極體等)、電容器、電阻器等。層間介電質(inter-layer dielectric，ILD)56位於半導體基板52的前表面上方。ILD 56圍繞且可以覆蓋裝置54。ILD 56可以包含一或多個介電層，其由諸如磷矽玻璃(Phospho-Silicate Glass，PSG)、硼矽玻璃(Boro-Silicate Glass，BSG)、硼摻雜磷矽玻璃(Boron-Doped Phospho-Silicate Glass，BPSG)、未摻雜矽玻璃(undoped Silicate Glass，USG)、或類似的材料所形成。
導電栓塞58延伸穿過ILD 56，以電性地和物理性地耦合裝置54。舉例來說，當裝置54為電晶體時，導電栓塞58可以耦合電晶體的閘極和源極/汲極區域。導電栓塞58可以由鎢(tungsten)、鈷(cobalt)、鎳(nickel)、銅(copper)、銀(silver)、金(gold)、鋁(aluminum)等、或其組合所形成。互連結構60位於ILD 56和導電栓塞58的上方。互連結構60將裝置54互連以形成積體電路。互連結構60可以由例如ILD 56上之介電層中的金屬化圖案所形成。金屬化圖案包含形成在一個或多個低k介電層中的金屬線和通孔。互連結構60的金屬化圖案藉由導電栓塞58電耦合至裝置54。
積體電路晶片50還包含與外部進行連接的焊墊62，例如鋁墊。焊墊62在積體電路晶片50的主動側(active side)，例如在互連結構60中和/或互連結構60上。一或多個鈍化膜64位於積體電路晶片50上，例如互連結構60和焊墊62的多個部份上。 開口穿過鈍化膜64延伸至焊墊62。諸如導電柱(舉例來說，由諸如銅的金屬形成)的晶片連接器66延伸穿過鈍化膜64中的開口，並且物理性地和電性地耦合至焊墊62中對應的一個。晶片連接器66可以例如由電鍍或類似的方式形成。晶片連接器66電性耦合積體電路晶片50的各個積體電路。
可選地，可以在焊墊62上設置焊料區域(例如，焊料球或焊料凸塊)。焊料球可以用以對積體電路晶片50進行晶片探針(chip probe，CP)測試。可以在積體電路晶片50上進行CP測試，以確定積體電路晶片50是否為已知合格晶片(known good die，KGD)。因此，僅封裝經過後續處理的KGD積體電路晶片50，且不封裝未通過CP測試的晶片。在測試後，可以在後續處理步驟中去除焊料區域。
介電層68可以(或不可以)位於積體電路晶片50的主動側(active side)，例如位於鈍化膜64上和晶片連接器66上。介電層68橫向地包裹晶片連接器66，且介電層68橫向地與積體電路晶片50鄰接。最初，介電層68可以掩埋晶片連接器66，使得介電層68的最上表面在晶片連接器66知最上表面的上方。在將焊料區域設置在晶片連接器66上的一些實施例中，介電層68也可以掩埋焊料區域。或者，可以在形成介電層68之前去除焊料區域。
介電層68可以是聚合物，例如PBO、聚醯亞胺(polyimide)、BCB等；氮化物，例如氮化矽等；氧化物，例如氧化矽、PSG、BSG、BPSG等，或其組合。介電層68可以藉由旋塗(spin coating)、層壓(lamination)、化學氣相沉積(chemical vapor deposition，CVD)等所形成。在一些實施例中，在形成積體電路晶片50的過程中，晶片連接器66從介電層68暴露出來。在一些實施例中，晶片連接器66被掩埋並在隨後的封裝積體電路晶片50的封裝過程中被暴露出來。暴露的晶片連接器66可能會去除晶片連接器66上可能存在的任何焊料區域。
在一些實施例中，積體電路晶片50為包含多個半導體基板52的堆疊裝置。舉例來說，積體電路晶片50可以是諸如包含多個存儲晶片的混合存儲立方(hybrid memory cube，HMC)模組、高帶寬存儲(high bandwidth memory，HBM)模組等的存儲裝置。在這樣的實施例中，積體電路晶片50包含藉由基板穿孔(through-substrate vias，TSVs)互連的多個半導體基板52。每個半導體基板52可以具有(或可以不具有)互連結構60。
第2圖至第13圖繪示根據一些實施例之製造具有改善散熱的積體電路封裝的剖面示意圖。在第2圖中，提供一載體基板102，且形成一釋放層104於載體基板102上。載體基板102可以是玻璃載體基板、陶瓷載體基板等。載體基板102可以是晶圓，使得多個封裝可以同時形成在載體基板102上。舉例來說，繪示出了第一封裝區域100A和第二封裝區域100B，且一個或多個積體電路晶片50被封裝，以在每個封裝區域100A和100B中形成積體電路封裝。完成的積體電路封裝也可以稱為積體扇出(integrated fan-out，InFO)封裝。
釋放層104可以由聚合物基底材料(polymer-based material)形成，其可以與載體基板102一起從在後續步驟中形成的上覆結構(overlying structures)中被移除。在一些實施例中，釋放層104 為環氧基底熱釋放材料(epoxy-based thermal-release material)，其在加熱時會失去其黏合性能，例如光熱轉換(light-to-heat-conversion，LTHC)釋放塗層。在其他實施例中，釋放層104可以是紫外光(ultra-violet，UV)膠，當暴露於UV光時失去其黏合性。釋放層104可以以液體的形式分配並固化，可以是層壓在載體基板102上的層壓膜，或者可以是類似物。釋放層104的頂表面可以是水平的並且可以具有高度的平面度。
在第3圖中，形成一正面(front-side)重分佈結構122於釋放層104上。正面重分佈結構122包含介電層124、128、132和136；以及金屬化圖案126、130、134和110(包含導電墊110A和110B)。金屬化圖案126、130和134也可以被稱為重分佈層或重分佈線。繪示出了具有四層金屬化圖案的正面重分佈結構122作為示例。可以在正面重分佈結構122中形成更多或更少的介電層和金屬化圖案。如果要形成較少的介電層和金屬化圖案，則可以省略下面討論的步驟和過程。如果要形成更多的介電層和金屬化圖案，則可以重複下面討論的步驟和過程。
作為形成重分佈結構122的示例，沉積一介電層124於釋放層104上。在一些實施例中， 介電層124由諸如PBO、聚醯亞胺、BCB等的感光材料(photo-sensitive material)形成，其可以使用光刻掩膜來圖案化。介電層124可以藉由旋塗、層壓、CVD等或其組合來形成。
然後，形成金屬化圖案126於介電層124上。作為形成金屬化圖案126的示例，在介電層124上方形成種子層。在一些實施例中，種子層是金屬層，其可以是單層或包括由不同材料形成的多個子層的複合層。在一些實施例中，種子層包括鈦層和在鈦層上方的銅層。可以使用PVD等來形成種子層。接著在種子層上形成光阻並對其圖案化。可以通過旋塗等來形成光阻，並且可以將光阻於光照下曝光以進行圖案化。光阻的圖案對應至金屬化圖案126。圖案形成穿過光阻的開口以暴露出種子層。然後在光阻的開口中和種子層的暴露部分上形成導電材料。可以通過諸如電鍍或化學鍍之類的電鍍來形成導電材料。導電材料可以包括金屬，例如銅，鈦，鎢，鋁等。導電材料和種子層下面的部分的組合形成金屬化圖案126。去除光阻和種子層上未形成導電材料的部分。可以藉由可接受的灰化或剝離(stripping)製程，例如使用氧電漿等，來去除光阻。 一旦去除了光阻，就去除了種子層的暴露部分，諸如藉由使用可接受的蝕刻工藝，例如藉由濕式蝕刻或乾式蝕刻。
接著，沉積一介電層128於金屬化圖案126和介電層124上。介電層128可以以類似於介電層124的方式形成，並且可以由與介電層124類似的材料形成。然後可以藉由介電層124來圖案化開口，以暴露出下面的金屬化圖案126。可以藉由可接受的製程來形成圖案，例如當介電層124是感光材料時通過將介電層124曝光或通過使用各向異性蝕刻來進行蝕刻。 如果介電層124是感光材料，則可以在曝光之後使介電層124顯影。
然後形成金屬化圖案130。金屬化圖案130包括在介電層128的主表面上並沿著介電層128的主表面延伸的部分，以及延伸穿過介電層128以物理性地和電性地耦合金屬化圖案126的部分。金屬化圖案130可以以與金屬化圖案126類似的方式和類似的材料形成。 在一些實施例中，金屬化圖案130的尺寸與金屬化圖案126的尺寸不同。 舉例來說，金屬化圖案130的導線和/或通孔可以比金屬化圖案126的導線更寬或更厚。此外，金屬化圖案130可以形成為比金屬化圖案126更大的間距。
沉積介電層132在金屬化圖案130和介電層128上，並且介電層132可以被圖案化以暴露出金屬化圖案130。 可以以類似於介電層124的方式來形成和圖案化介電層132，並且可以由與介電層124類似的材料形成介電層132。
然後形成金屬化圖案134。 金屬化圖案134包括在介電層132的主表面上並沿著介電層132的主表面延伸的部分，以及延伸穿過介電層132以物理性地和電性地耦合金屬化圖案130的部分。金屬化圖案134可以以與金屬化圖案126類似的方式和類似的材料形成。 在一些實施例中，金屬化圖案134的尺寸與金屬化圖案126和130的尺寸不同。舉例來說，金屬化圖案134的導線和/或通孔可以比金屬化圖案126和130的導線和/或通孔更寬或更厚。此外，金屬化圖案134可以形成為比金屬化圖案130更大的間距。
沉積一介電層136在金屬化圖案134和介電層132上，並且介電層136可以被圖案化以暴露出金屬化圖案134。介電層136可以以類似於介電層124的方式形成，並且可以由與介電層124相同的材料形成。
然後，在電介層136的開口中形成金屬化圖案110。金屬化圖案110包括導電墊110A和110B，導電墊110A和110B延伸穿過介電層136，以物理性地和電性地耦合到下面的金屬化圖案134、130和126。
如第3圖進一步所示，在金屬化圖案110的導電墊110A上形成通孔116。通孔116可以延伸遠離重分佈結構122的最頂部電介層（例如，電介層136）。作為形成通孔116的示例，在正面重分佈結構122上，例如在電介層136和金屬化圖案110上，形成種子層（未示出）。在一些實施例中，種子層是金屬層，其可以是單層或包括由不同材料形成的多個子層的複合層。在特定實施例中，種子層包括鈦層和在鈦層上方的銅層。可以使用PVD等來形成種子層。或者，在通孔116不比下面的導電墊110A寬的實施例中，可以省略單獨的種子層，並且導電墊110A可以作為種子層。
在種子層（如果存在）和正面重分佈結構122上形成光阻並對其圖案化。可以通過旋塗等形成光阻，並且可以將其暴露於光照下以進行圖案化。光阻的圖案對應於通孔116。圖案形成穿過光阻的開口以暴露出種子層或導電墊110A。在光阻的開口中和種子層的暴露部分上形成導電材料。可以通過諸如電鍍或化學鍍之類的電鍍來形成導電材料。導電材料可以包括金屬，例如銅，鈦，鎢，鋁等。去除光阻和種子層上未形成導電材料的部分。可以藉由可接受的灰化或剝離製程，例如使用氧電漿等，來去除光阻。 一旦去除了光阻，例如通過使用可接受的蝕刻製程，例如通過濕式或乾式蝕刻，就去除了種子層（如果存在的話）的暴露部分。種子層的其餘部分和導電材料形成通孔116。
在第4圖中，積體電路晶片50 (例如，第一積體電路晶片50A和第二積體電路晶片50B)被接合在各個封裝區域100A和100B中。在所示的實施例中，多個積體電路晶片50彼此相鄰地接合，包含在第一封裝區域100A和第二封裝區域100B中的第一積體電路晶片50A和第二積體電路晶片50B。第一積體電路晶片50A可以是邏輯裝置，例如CPU、GPU、SoC、微控制器等。第二積體電路晶片50B可以是記憶裝置，例如DRAM晶片、SRAM晶片、HMC模組、HBM模組等。在一些實施例中，積體電路晶片50A和50B可以是相同類型的晶片，例如SoC晶片。第一積體電路晶片50A和第二積體電路晶片50B可以在相同技術節點的過程中形成，或者可以在不同技術節點的過程中形成。舉例來說，第一積體電路晶片50A可以具有比第二積體電路晶片50B更先進的製程節點。積體電路晶片50A和50B可以具有不同的尺寸(例如，不同的高度和/或表面積)，或者可以具有相同的尺寸(例如，相同的高度和/或表面積)。雖然兩個積體電路晶片50被繪示出為放置在每個封裝區域中，但是更少(例如，一個)或更多數量的積體電路晶片可以設置在基板102上的每個封裝區域中。
晶片50被設置為面朝下，使得晶片50的前側面對導電墊110B，並且晶片50的背側背對導電墊110B。在一些實施例中，以混合接合配置(hybrid bonding configuration)將積體電路晶片50接合至金屬化圖案110的導電墊110B。舉例來說，晶片50的鈍化層68可以直接接合到介電層136，並且晶片50的接觸墊66可以直接接合到導電墊110B。在一實施例中，鈍化層68和介電層136之間的鍵可以是氧化物鍵合至氧化物的鍵等。混合接合製程還通過直接金屬對金屬鍵合將晶片50的接觸墊66直接接合到導電墊110B。因此，通過接觸墊66到接觸墊110B的物理連接來提供晶片50和正面重分佈結構122之間的電連接。
作為示例，可以藉由對正面重分佈結構122的介電層136和/或晶片50的鈍化層68進行表面處理來開始混合接合製程。表面處理可以包括電漿處理。電漿處理可以在真空環境中進行。在電漿處理之後，表面處理可以進一步包含可以應用於晶片50的介電層136和/或鈍化層68的清潔製程（例如，用去離子水沖洗等）。然後，可以進行混合接合製程以將接觸墊66與接觸墊110B對準。接下來，混合接合包括預接合步驟，在該步驟中，使接觸墊66與接觸墊110B物理接觸。可以在室溫下 (例如，在約21℃至約25℃之間)進行預接合。混合接合製程繼續進行退火，舉例來說，在大約150℃至大約400℃的溫度下持續大約0.5小時至大約3小時，因此接觸墊66中的金屬 (例如，銅)和接觸墊110B中的金屬(例如，銅) 相互擴散，進而形成了直接的金屬對金屬的接合。退火可以進一步在鈍化層68和介電層136之間形成共價鍵。在其他實施例中，其他接合參數和/或方法(例如，焊料接合)也是可能的。
如第4圖進一步所示，在各種組件上和周圍形成封裝劑120。形成之後，封裝劑120密封通孔116和積體電路晶片50。封裝劑120可以是模製化合物(molding compound)、環氧樹脂等。可以通過壓縮成型(compression molding)、傳遞成型(transfer molding)等方式施加封裝劑120，且封裝劑120可以形成在載體基板102上方，使得通孔116和/或積體電路晶片50被掩埋或覆蓋。封裝劑120進一步形成在積體電路晶片50之間的間隙區域中。封裝劑120可以以液體或半液體形式被施加，然後固化。
在第5圖中，在封裝劑120上進行平坦化製程以暴露通孔116和晶片50。平坦化製程還可去除通孔116的材料。在製程變化內，在平坦化製程之後，通孔116、晶片50和封裝劑120的頂表面實質上共平面。平坦化製程可以是，舉例來說，化學機械拋光(chemical-mechanical polish，CMP)、研磨製程(grinding process)等。在一些實施例中，如果通孔116和晶片50已經暴露，則可以省略平坦化。
在第6圖中，散熱器170通過薄膜168附接到晶片50。散熱器170可以由具有相對高的熱導率(thermal conductivity)的導電材料形成，例如，至少約149 W/m*K或至少約380 W/m*K。舉例來說， 在一些實施例中，散熱器170由銅，金剛石(diamond)，砷化硼(boron arsenide)，銀，矽等或類似物製成。已經觀察到，當散熱器170由導熱率小於大約380 W/m*K的材料形成時，最終的封裝中的散熱並不足夠。散熱器170可以使用薄膜168附接到晶片50的基板52的背面。基板52的背面可以指與在其上形成主動裝置的表面相對的一側。薄膜168可以是高介電常數(high-k)聚合物(例如，高k DAF)、藉由回焊(reflow)製程附接的金屬(例如，In、Sn等)、熱介面材料(thermal interface material，TIM)、錫膏(solder paste)等。在所繪示的實施例中，每個散熱器170具有與晶片50中的相應一個相同的寬度並與之相鄰。在其他實施例中，散熱器170可以比晶片50更寬或更窄，和/或散熱器170的側壁可以從晶片150偏移(例如，參閱第14A-14C)。此外，多個物理上分開的散熱器170可以附接到每個晶片50(例如，參閱第14A-14C)。
如第6圖進一步繪示出的，金屬化圖案190可以形成在通孔116上。金屬化圖案190可以使用與上面關於接觸墊110B所述之類似的製程和類似的材料所形成。在各種實施例中，可以在將散熱器170附接到晶片50之前或之後形成金屬化圖案190。
因此，在每個封裝區域100A和100B中形成第一封裝組件100。第一封裝組件100包含積體電路晶片50、封裝劑120、通孔116、正面重分佈結構122，以及金屬化圖案190。在第一封裝組件100的積體電路晶片50上形成散熱器170。
在第7圖中，第二封裝組件200藉由導電連接器152耦合到第一封裝組件100。第二封裝組件200中的一個耦接在每個封裝區域100A和100B中，以在每個封裝區域上形成積體電路裝置堆疊。在一些實施例中，第二封裝組件200可以物理接觸散熱器170。舉例來說，散熱器170可以跨越晶片50與第二封裝組件200之間的距離。以這種方式，散熱器170可以提供從晶片50到第二封裝組件200的散熱路徑。在其他實施例中，可以在散熱器170與第二封裝組件200之間設置中間層。舉例來說，導熱膜(thermally conductive film)( 未明確繪示出)可以作為散熱器170中的每個與對應的第二封裝組件200之間的緩衝層。在一些實施例中，導熱膜可以包括高k聚合物(例如，高k DAF)、藉由回流焊接(reflow)製程附接的金屬(例如，In、Sn等)、TIM、錫膏等。
第二封裝組件200包含基板202以及耦合至基板202的一或多個堆疊晶片210(例如，210A和210B)。 雖然僅繪示出一組堆疊晶片210(210A和210B)，但是在其他實施例中，可以將多個堆疊的晶片210（每個具有一個或多個堆疊的晶片）並排地耦接到基板202的相同表面。基板202可以由諸如矽、鍺、金剛石等的半導體材料製成。在一些實施例中，也可以使用諸如矽鍺(silicon germanium)，碳化矽(silicon carbide)，砷化鎵(gallium arsenic)，砷化銦(indium arsenide)，磷化銦(indium phosphide)，碳化矽鍺(silicon germanium carbide)，磷化砷化鎵(gallium arsenic phosphide)，磷化銦鎵(gallium indium phosphide)等的複合材料，以及它們的組合等。另外，基板202可以是絕緣體上矽(silicon-on-insulator，SOI)基板。一般來說，SOI基板包括半導體材料層，例如外延矽(epitaxial silicon)、鍺、矽鍺、SOI、絕緣體上的矽鍺（SGOI）或其組合。在一個替代實施例中，基板202為絕緣核芯，諸如玻璃纖維增強樹脂核芯(fiberglass reinforced resin core)。一種示例性核芯材料是玻璃纖維樹脂，例如FR4。核芯材料的替代材料包括雙馬來醯亞胺三嗪(bismaleimide-triazine，BT)樹脂，或者其他印刷電路板(printed circuit board，PCB)材料或薄膜。基板202可以使用諸如味之素增層薄膜(Ajinomoto build-up film，ABF)或其他層壓材料。
基板202可以包括主動和被動裝置(未示出)。可以使用諸如電晶體，電容器，電阻器，它們的組合等的各種裝置來產生第二封裝組件200的設計的結構和功能要求。 可以使用任何合適的方法來形成裝置。
基板202還可以包括金屬化層（未示出）和導電通孔208。金屬化層可以形成在主動和被動裝置上方，並且被設計為連接各種裝置以形成功能電路。金屬化層可以由介電質（例如，低k介電材料）和導電材料（例如，銅）的交替層所形成，且互連導電材料層的通孔可以通過任何合適的製程（例如沉積、鑲嵌、雙鑲嵌等）形成。基板202基本上沒有主動和被動裝置。
基板202可以在基板202的第一側上具有接合墊204以耦合到堆疊芯片210，並且在基板202的第二側上具有接合墊206以耦合到導電連接器152，其中基板202的第二側與第一側相對。在一些實施例中，藉由在基板202的第一側和第二側上的介電層（未示出）中形成凹部（未示出）來形成接合墊204和206。可以形成凹部以允許接合墊204和206被嵌入介電層中。在其他實施例中，由於可以在介電層上形成接合墊204和206，因此省略了凹部。在一些實施例中，接合墊204和206包括由銅，鈦，鎳，金，鈀等或其組合所製成的薄種子層（未示出）。接合墊204和206的導電材料可以沉積在薄種子層上方。可以藉由電化學鍍製程、化學鍍製程、CVD、原子層沉積（atomic layer deposition，ALD）、PVD等或其組合來形成導電材料。在一實施例中，接合墊204和206的導電材料是銅、鎢、鋁、銀、金等或其組合。
在一些實施例中，接合墊204和接合墊206為UBM，其包括三層導電材料，例如一層鈦，一層銅和一層鎳。材料和層的其他佈置可以用於接合墊204和206的形成，例如鉻/鉻-銅合金/銅/金的佈置，鈦/鈦鎢/銅的佈置或銅/鎳/金的佈置。可以用於接合墊204和206的任何合適的材料或材料層完全被包括在本申請的範圍內。在一些實施例中，導電通孔208延伸穿過基板202，並將接合墊204中的至少一者耦接至接合墊206中的至少一者。
在所繪示的實施例中，堆疊晶片210藉由引線接合(wire bonds)212耦合到基板202，即便可以使用其他連接，例如導電凸塊。在一實施例中，堆疊晶片210是堆疊的存儲晶片(memory dies)。舉例來說，堆疊晶片210可以是諸如低功率(low-power，LP)雙倍數據速率(double data rate，DDR) 存儲晶片；諸如LPDDR1、LPDDR2、LPDDR3、LPDDR4等的存儲模組。
可以通過模製材料214來封裝堆疊晶片210和引線接合212。模製材料214可以使用壓縮模製(compression molding)成型在堆疊晶片210和引線接合212上。在一些實施例中，模製材料214是模製聚合物、聚合物、環氧樹脂、氧化矽填充材料等或它們的組合。可以執行固化製程以固化模製材料214。固化製程可以是熱固化、UV固化等或其組合。
在一些實施例中，將堆疊晶片210和引線接合212嵌埋於模製材料214中，並在模製材料214固化後，進行平坦化步驟，例如研磨，以去除模製材料214多餘的部分並且為第二封裝組件200提供實質上平坦的表面。
在形成第二封裝組件200之後，第二封裝組件200藉由導電連接器152、接合墊206和金屬化圖案190機械性地和電性地接合至第一封裝組件100。在一些實施例中，堆疊晶片210可以通過引線接合212、接合墊204和206、導電通孔208、導電連接器152、金屬化圖案190、通孔116以及正面重分佈結構122耦接至積體電路晶片50A和50B。
在一些實施例中， 形成一阻焊劑(solder resist) (未示出)於相對堆疊晶片210之基板202的一側上。導電連接器152可以設置在阻焊劑中的開口內，以電性地和機械性地耦合至基板202內的導電特徵(例如，接合墊206)。阻焊劑可以用於保護基板202的區域免受外部損壞。
在一些實施例中，導電連接器152在回焊之前在其上形成有環氧助焊劑(epoxy flux)(未示出)，並且在第二封裝組件200附接至第一封裝組件100之後殘留了環氧助焊劑的至少一些環氧部分。
在第8圖中，形成一封裝劑250於第一封裝組件100與第二封裝組件200之間且圍繞導電連接器152和散熱器170。封裝劑250可以進一步形成在第二封裝組件200的周圍，且封裝劑250可以形成在第一封裝組件100的周圍(未明確繪示出)。封裝劑250可以是模製化合物、環氧樹脂、模製填充底膠(molding underfill)等。在一些實施例中，封裝劑250的熱導率可能比散熱器170的熱導率低。舉例來說，封裝劑250可具有小於約10 W/m*K的熱導率。因此，散熱器170可以藉由封裝劑250改善從積體電路晶片50至第二封裝組件200的散熱。舉例來說， 通過包含散熱器170的封裝劑250，已經觀察到工作溫度降低了約22%或更多。
封裝劑250可以藉由壓縮成型、傳遞成型等來施加，並且可以形成在第二封裝組件200上方，直到第二封裝組件200被掩埋或覆蓋。封裝劑250進一步形成在第二封裝組件200與下方的第一封裝組件100之間的間隙區域中。封裝劑250可以以液體或半液體形式被施加，然後被固化。在形成封裝劑250之後，可以對封裝劑250進行平坦化製程(例如，CMP、研磨等)，直到暴露出第二封裝組件200為止。在平坦化製程之後，第二封裝組件200和封裝劑250的頂表面可以是水平的。
在第9圖中，框架(frame)252附接至第二封裝組件200。舉例來說，框架252附接至相對於第一封裝組件100 的第二封裝組件200的表面。
在第10圖中，進行載體基板剝離(de-bonding)，以使載體基板102從正面重分佈結構122，例如介電層124分離(或剝離)。根據一些實施例，剝離包括在釋放層104上投射諸如雷射光或UV光之類的光，使得釋放層104在光的熱量下分解並且可以去除載體基板102。然後將結構翻轉。
在第11圖中，形成UBM 138和導電連接器150以用於外部連接到正面重分佈結構122。UBM 138具有多個凸塊部分位於介電層124的主表面上並沿其延伸，且具有通孔部分延伸穿過介電層124以物理性地和電性地耦合至金屬化圖案126。結果，UBM 138電性耦合到通孔116和積體電路晶片50。UBM 138可以由與金屬化圖案126相同的材料和相同的製程所形成。在一些實施例中，UBM 138的尺寸與金屬化圖案110、126、130和134的尺寸不同。
在第11圖中，形成導電連接器150於UBM 138上。導電連接器150可以是球柵陣列(ball grid array，BGA)連接器、焊料球、金屬柱、可控塌陷晶片連接(controlled collapse chip connection，C4)凸塊、微凸塊、化學鎳-化學鈀-浸金技術(electroless nickel-electroless palladium-immersion gold technique，ENEPIG)形成的凸塊等。導電連接器150可以包括諸如焊料、銅、鋁、金、鎳、銀、鈀、錫等或其組合的導電材料。在一些實施例中，通過首先通過蒸發，電鍍，印刷，焊料轉移，焊球放置(ball placement)等形成焊料層來形成導電連接器150。一旦在結構上形成焊料層，就可以執行回焊以將材料成型為所需的凸塊形狀。在另一個實施例中，導電連接器150包括藉由濺射、印刷、電鍍、化學鍍、CVD等形成的金屬柱（例如銅柱）。金屬柱可以是無焊料的並且具有實質上垂直的側壁。在一些實施例中，在金屬柱的頂部上形成金屬蓋層。金屬蓋層可以包括鎳、錫、錫鉛、金、銀、鈀、銦、鎳-鈀-金、鎳-金等或它們的組合，並且可以通過電鍍製程形成。
在第12圖中，藉由沿著劃線區域(例如，在第一封裝區域100A與第二封裝區域100B之間)進行切割來執行分割過程。將第一封裝區域100A與第二封裝區域100B分開。最終，單一裝置堆疊自第一封裝區域100A或第二封裝區域100B中的一個。在一些實施例中，在將第二封裝組件200耦合到第一封裝組件100之後執行切割製程。在其他實施例中（未示出），在第二封裝組件200耦合到第一封裝組件100之前執行切割製程。
在第13圖中，然後可以使用導電連接器150將每個單獨的第一封裝組件100安裝到封裝基板300。封裝基板300包括核心基板(substrate core)302以及在核心基板302上方的接合墊304。核心基板302可以由諸如矽、鍺、金剛石等的半導體材料製成。或者，也可以使用諸如矽鍺、碳化矽、砷化鎵、砷化銦、磷化銦、碳化矽鍺、磷化砷化鎵、磷化銦鎵等的化合物，以及它們的組合等。另外，核心基板302可以是SOI基板。通常，SOI 基板包括諸如外延矽、鍺、矽鍺、SOI、SGOI或其組合的半導體材料層。在一個替代實施例中，核心基板302是以諸如玻璃纖維增強樹脂核芯(fiberglass reinforced resin core)的絕緣核芯為基底。一種示例性核芯材料是玻璃纖維樹脂，例如FR4。核芯材料的替代材料包括雙馬來醯亞胺-三嗪BT樹脂(bismaleimide-triazine BT resin)，或者其他PCB材料或薄膜。核心基板302可以使用諸如ABF或其他層壓材料。
核心基板302可以包括主動和被動裝置(未示出)。可以使用諸如電晶體，電容器，電阻器，它們的組合等的各種裝置來產生裝置堆疊的設計的結構和功能要求。可以使用任何合適的方法來形成裝置。
核心基板302可以包括金屬化層和通孔(未示出)，其中接合墊304物理性地和/或電性地耦合至金屬化層和通孔。金屬化層可以形成在主動和被動裝置上方，並且被設計為連接各種裝置以形成功能電路。金屬化層可以由介電質（例如，低k介電材料）和導電材料（例如，銅）的交替層所形成，且互連導電材料層的通孔可以通過任何合適的製程（例如沉積、鑲嵌、雙鑲嵌等）形成。在一些實施例中，核心基板302基本上沒有主動和被動裝置。
在一些實施例中，對導電連接器150進行回焊以將第一封裝組件100附接至接合墊304。導電連接器150將封裝基板300(包含在核心基板302內的金屬化層)電性地和/或物理性地耦合至第一封裝組件100。在一些實施例中，形成一阻焊劑 306於核心基板302上。導電連接器150可以設置在阻焊劑 306中的開口內，以電性地和機械性地耦合至接合墊304。阻焊劑 306 可以用於保護基板基板202的區域免受外部損壞。
導電連接器150在回焊之前在其上形成有環氧助焊劑(epoxy flux)(未示出)，並且在第一封裝組件100附接至封裝基板300之後殘留了環氧助焊劑的至少一些環氧部分。該剩餘的環氧樹脂部分可以作為底部填充物，以減少應力並保護因回焊導電連接器150而導致的接合點(joints)。在一些實施例中，底部填充物308可以形成在封裝組件100與封裝基板300之間，並且圍繞導電連接器150。底部填充物308可以在附接第一封裝組件100之後藉由毛細管流動(capillary flow)製程形成，或者可以在附接第一封裝組件100之前藉由合適的沉積方法形成。
在一些實施例中，被動裝置(例如，表面安裝元件(surface mount devices，SMDs)，未示出) 也可以附接至第一封裝組件100(例如，附接至UBM 138)或附接至封裝基板300(例如，附接至接合墊304)。舉例來說， 被動裝置可以如導電連接器150一樣接合至第一封裝組件100或封裝基板300的相同表面上。可以在將第一封裝組件100安裝至封裝基板300上之前將被動裝置附接至封裝組件100，或者可以在將第一封裝組件100安裝至封裝基板300上之前或之後將被動裝置附接至封裝基板300。
還可以包括其他特徵和過程。舉例來說，可以包括測試結構，以幫助對3D封裝或3DIC裝置進行驗證測試。測試結構可以包括，舉例來說，在重分佈層中或在基板上形成可以使用探針和/或探針卡等測試3D封裝或3DIC的測試墊(test pads)。可以在中間結構以及最終結構上執行驗證測試。 另外，本文公開的結構和方法可以與結合了已知良好晶片的中間驗證的測試方法結合使用，以增加產量並降低成本。
因此，形成半導體封裝400，其包含接合至第二封裝組件200和第三封裝組件300的第一封裝組件100。一個或多個散熱器170設置在第一封裝組件100與第二封裝組件200之間，以改善從第一封裝組件100的晶片50至第二封裝組件200的散熱。散熱器170可以具有相對較高的熱導率，舉例來說，高於第一封裝組件100與第二封裝組件200之間的封裝劑250的熱導率。如此，可以在半導體封裝400中實現改善散熱和裝置性能。舉例來說，通過包含散熱器170，可以使半導體封裝400中的工作溫度降低約22%或更多。
第14A圖、第14B圖和第14C圖分別繪示出了半導體封裝420、430和440的剖面示意圖。半導體封裝420、430和440中的每一個可以與半導體封裝400相似並且彼此相似，其中相同的附圖標記指示使用相同的製程形成的相同的元件。然而，每個半導體封裝420、430和440中的第二封裝組件200可以進一步包括散熱蓋254，此散熱蓋254附接到第二封裝組件200的基板202。散熱蓋254可以由具有較高熱導率的導電材料製成，例如銅等，並且散熱蓋254可以藉由黏著劑(adhesive)、TIM或類似物附接至基板202的頂表面。基板202將散熱器170熱連接至散熱蓋254。如此，熱量可以通過散熱器170和基板202從晶片50散發到散熱蓋254。此外，在封裝420、430和440中，封裝劑250可以僅形成在第一封裝組件100與第二封裝組件200之間，且封裝劑250可以不沿著第二封裝組件200的側壁延伸。
第14A圖的封裝420繪示出了一實施例，其中散熱器170的寬度與晶片50相同且相接。此外，封裝320中的散熱器170可以接觸基板202，並且散熱器170可以橫跨晶片50與基板202之間的整個距離。
第14B圖的封裝430繪示出了一實施例，其中散熱器170比晶片50窄且與晶片50偏離，且多個散熱器170連接到每一個晶片50。舉例來說，在封裝430中，散熱器170可以與晶片50的側壁重疊。此外，封裝330中的散熱器170可以接觸基板202，並且散熱器170可以橫跨晶片50與基板202之間的整個距離。
第14C圖的封裝340繪示出了一實施例，其中散熱器170的寬度與晶片50相同且相接。此外，封裝320中的散熱器170可以藉由封裝劑250與基板202物理性地分離。舉例來說，散熱器170可以不附接到封裝200，且封裝劑250可以形成在散熱器170的頂表面與基板202的底表面之間。雖然散熱器170不與基板202接觸，但是將散熱器170包含在封裝劑250中仍然可以改善第一和第二封裝組件100和200之間的散熱。
第15圖至第19圖繪示根據一些其他實施例之形成半導體封裝450的剖面示意圖。封裝450可以類似於第12圖的封裝400，其中相似的附圖標記指示由相似的製程形成的相似的元件。第14A圖至第14C圖繪示出了在與上述第4圖相似的製程階段但在形成封裝劑120之前的剖面示意圖。舉例來說，第14A圖至第14C圖中，正面重分佈結構122形成在載體基板102上，通孔116形成在正面重分佈結構122的接觸墊110A上，且晶片50接合至正面重分佈結構122的接觸墊110B。然而，在第14A圖至第14C圖的結構中，晶片50可以比通孔116更高並且延伸得更高。
在第16圖中，在各種組件上和周圍形成封裝劑120。形成之後，封裝劑120沿著通孔116和積體電路晶片50的側壁延伸。封裝劑120可以是模製化合物、環氧樹脂等。可以通過壓縮成型、傳遞成型等方式施加封裝劑120，且封裝劑120可以形成在載體基板102上方，使得通孔116和/或積體電路晶片50設置在封裝劑120中。封裝劑120可以以液體或半液體形式被施加，然後固化。
封裝劑120形成在積體電路晶片50之間的間隙區域中。然而，可以沉積封裝劑120而不覆蓋通孔116的頂表面。舉例來說，在沉積封裝劑120之後，通孔116的頂表面可以保持暴露，而無需對封裝劑120施加任何圖案化或平坦化製程。或者，可以沉積封裝劑120以嵌埋通孔116，並且可以應用回蝕製程(etch back process)以暴露通孔116的頂表面。在這樣的實施例中，回蝕製程可以是等向性的(isotropic)。
在一些實施例中，封裝劑120可進一步包括沿著晶片50的側壁的至少上部分圓角(fillet)。雖然第16圖繪示出了Although Figure 16 illustrate a top surface of the 封裝劑120的頂表面與通孔116的頂表面位於同一水平面(level)，但是在其他實施例中，封裝劑120的頂表面也可以低於通孔116的頂表面。
在第17圖中，第二封裝組件200耦合到第一封裝組件100。第二封裝組件200中的一個耦合在封裝區域100A和100B的每一個中，以在第一封裝組件100的每個區域中形成積體電路裝置堆疊。舉例來說，第二封裝組件200可以藉由回焊導電連接器152而直接接合到通孔116。第二封裝組件200可以類似於上述在第7圖中描述的那些，並且為簡潔起見，省略了第二封裝組件200的附加細節。
在封裝450中，晶片50可以藉由薄膜154直接附接到第二封裝組件200。薄膜154可以是高k聚合物(例如，高k DAF)、金屬(例如，In、Sn等)、TIM、錫膏等。舉例來說，晶片50的基板52可以藉由薄膜154附接到第二封裝組件200的基板202。因為基板52包括半導體材料(例如，具有相對較高的熱導率) ，所以可以通過將其放置在緊密靠近第二封裝組件200的位置，可以促進散熱。藉由使用具有較高熱導率的材料(例如，薄膜154) 作為晶片50和基板202之間的介面材料，可以進一步改善散熱。舉例來說，已經觀察到，藉由將晶片50直接附接到具有相對較高熱導率的材料的第二封裝組件200上，可以使已完成的封裝的工作溫度降低至少約18%。
在第18圖中，封裝劑250形成在第一封裝組件100與第二封裝組件200之間，並圍繞導電連接器152。封裝劑250可以以與上述第8圖中描述之類似的方式和類似的材料所形成。封裝劑250可以具有比晶片50的基板52更低的熱導率。由於晶片50藉由薄膜154直接連接到第二封裝組件200，因此封裝劑250 可能不會在晶片50的頂面與基板202的底面之間直接垂直於晶片50的頂面延伸。因此，可以改善散熱。
在第19圖中，可以執行類似於上述關於第9圖至第13圖描述的附加製程，以將第一和第二封裝組件100和200分離並接合至第三封裝組件300。因此，形成了半導體封裝450，其包括結合到第二封裝組件200和第三封裝組件300的第一封裝組件100。第一封裝組件100的晶片50的基板52接附接到第二封裝組件200的基板202，以改善從第一封裝組件100的晶片50到第二封裝組件200的散熱。晶片50的基板52可以具有相對較高的熱導率，舉例來說，高於第一封裝組件100與第二封裝組件200之間的封裝劑250的熱導率。如此，可以在半導體封裝450中實現改善散熱和裝置性能。舉例來說，半導體封裝450中的工作溫度可以降低18%。
第20圖繪示出半導體封裝460的剖面示意圖。半導體封裝460可以類似於半導體封裝450，其中相同的附圖標記指示使用相同的製程形成的相同的元件。然而，半導體封裝460中的第二封裝組件200可以進一步包括散熱蓋254，其附接到第二封裝組件200的基板202。散熱蓋254可以由具有高熱導率的導電材料製成，例如銅等，並且散熱蓋254可以通過黏著劑、TIM或類似物附接到基板202的頂表面。基板202將晶片50熱連接到散熱蓋254。此外，在半導體封裝460中，封裝劑250可以僅形成在第一封裝組件100與第二封裝組件200之間，並且封裝劑250可以不沿著第二封裝組件200的側壁延伸。
第21圖至第29圖繪示出根據一些其他實施例之形成半導體封裝470的剖面示意圖。封裝470可以類似於第12圖的封裝400，其中相似的附圖標記指示由相似的製程形成的相似的元件。
在第20圖中，提供一載體基板102，且形成一釋放層104於載體基板102上。背面(back-side)重分佈結構106可以形成在釋放層104上。在所示的實施例中，背面重分佈結構106包括介電層108、金屬化圖案111 (有時稱為重分佈層或重分佈線)、金屬化圖案110以及介電層112。金屬化圖案110和111可以由與上述金屬化圖案136相似的製程和相似的材料形成。背面重分佈結構106是可選擇的。在一些實施例中，在釋放層104上形成沒有金屬化圖案的介電層替代背面重分佈結構106。
在第21圖中，通過背面重分佈結構106來對開口113進行圖案化。例如，可以使用微影和蝕刻的組合來對開口113進行圖案化。開口可以暴露釋放層104。
在第22圖中，散熱器170形成在開口113中。散熱器170可以例如以與金屬化圖案110和111類似的方式形成。散熱器170可以包括具有相對高的熱導率的導電材料，例如銅等。在一些實施例中，散熱器170可具有至少約380 W/m*K的熱導率。在一些實施例中，散熱器170可以形成為覆蓋介電層112的頂表面，並且可以使用平坦化製程來去除散熱器170多餘的部分並暴露金屬化圖案110。
在第23圖中，通孔116形成在金屬化圖案110上。通孔116可以延伸遠離背面重分佈結構106的最上層介電層(例如，介電層112)。可以使用類似於第3圖所述的方法和類似的材料來形成通孔116。
在第24圖中，藉由黏著劑118將積體電路晶片50(例如，第一積體電路晶片50A和第二積體電路晶片50B)黏合至散熱器170。在封裝區域100A和100B中的每一個中黏合期望類型和數量的積體電路晶片50。在所示的實施例中，多個積體電路晶片50彼此相鄰地黏合，包括分別在第一封裝區域100A和第二封裝區域100B中的第一積體電路晶片50A和第二積體電路晶片50B。第一積體電路晶片50A可以是邏輯裝置，例如CPU、GPU、SoC、微控制器等。第二積體電路晶片50B可以是記憶裝置，例如DRAM晶片、SRAM晶片、HMC模組、HBM模組等。在一些實施例中，積體電路晶片50A和50B可以是相同類型的晶片，例如SoC晶片。第一積體電路晶片50A和第二積體電路晶片50B可以在相同技術節點的過程中形成，或者可以在不同技術節點的過程中形成。舉例來說，第一積體電路晶片50A可以具有比第二積體電路晶片50B更先進的製程節點。積體電路晶片50A和50B可以具有不同的尺寸(例如，不同的高度和/或表面積)，或者可以具有相同的尺寸(例如，相同的高度和/或表面積)。第一封裝區域100A和第二封裝區域100B中的通孔116的可用空間可能會受到限制，特別是當積體電路晶片50包括諸如SoC等佔用空間較大的裝置時。當第一封裝區域100A和第二封裝區域100B具有可用於通孔116的有限空間時，使用背面重分佈結構106可以改進互連佈置(interconnect arrangement)。
黏著劑118位於積體電路晶片50的背面上，並將積體電路晶片50黏合至散熱器170。黏著劑118可以是高k聚合物(例如，高k DAF)、藉由回焊製程附接的金屬(例如，In、Sn等)、TIM、錫膏等。黏著劑118可以施加於積體電路晶片50的背面，也可以施加於背面重分佈結構106的上表面。舉例來說，在切割以分離積體電路晶片50之前，黏著劑118可以被施加到積體電路晶片50的背面。黏著劑118以具有相對較高的熱導率，以促進從晶片50至散熱器170的散熱。
在第26圖中，在各種組件上和周圍形成封裝劑120。形成之後，封裝劑120密封通孔116和積體電路晶片50。封裝劑120可以是模製化合物、環氧樹脂等。可以通過壓縮成型、傳遞成型等方式施加封裝劑120，且封裝劑120可以形成在載體基板102上方，使得通孔116 和/或積體電路晶片50被掩埋或覆蓋。封裝劑120進一步形成在積體電路晶片50之間的間隙區域中。封裝劑120可以以液體或半液體形式被施加，然後固化。
在封裝劑120上進行平坦化製程以暴露 通孔116 和晶片連接器66。平坦化製程還可去除通孔116、介電層68和/或晶片連接器66的材料，直到暴露出晶片連接器66和通孔116。在製程變化內，在平坦化製程之後，通孔116、晶片連接器66、介電層68和封裝劑120的頂表面實質上共平面。平坦化製程可以是，舉例來說， CMP、研磨製程等。在一些實施例中，舉例來說，如果通孔116和/或晶片連接器66已經暴露，則可以省略平坦化。
在第26圖中，正面重分佈結構122形成於封裝劑120、通孔116和積體電路晶片50的上方。正面重分佈結構122包含介電層124、128、132和136；以及金屬化圖案126、130和134。金屬化圖案可以被稱為重分佈層或重分佈線。以具有三層金屬化圖案的正面重分佈結構122為例。可以在正面重分佈結構122中形成更多或更少的介電層和金屬化圖案。正面重分佈結構122可以使用如第3圖中描述的製程和/或材料形成。
在第27圖中，形成UBM 138和導電連接器150以用於外部連接到正面重分佈結構122。UBM 138具有多個凸塊部分位於介電層136的主表面上並沿其延伸， 且具有通孔部分延伸穿過介電層136以物理性地和電性地耦合至金屬化圖案134。結果，UBM 138電性耦合到通孔116和積體電路晶片50。UBM 138可以由與金屬化圖案126相同的材料和相同的製程所形成。在一些實施例中， UBM 138的尺寸與金屬化圖案126、130和134的尺寸不同。
形成導電連接器150 於UBM 138上。導電連接器150可以是BGA連接器、焊料球、金屬柱、C4凸塊、微凸塊、ENEPIG形成的凸塊等。導電連接器150可以包括諸如焊料、銅、鋁、金、鎳、銀、鈀、錫等或其組合的導電材料。在一些實施例中，通過首先通過蒸發，電鍍，印刷，焊料轉移，焊球放置等形成焊料層來形成導電連接器150。一旦在結構上形成焊料層，就可以執行回焊以將材料成型為所需的凸塊形狀。在另一個實施例中，導電連接器150包括藉由濺射、印刷、電鍍、化學鍍、CVD等形成的金屬柱（例如銅柱）。金屬柱可以是無焊料的並且具有實質上垂直的側壁。在一些實施例中，在金屬柱的頂部上形成金屬蓋層。金屬蓋層可以包括鎳、錫、錫鉛、金、銀、鈀、銦、鎳-鈀-金、鎳-金等或它們的組合，並且可以通過電鍍製程形成。因此，形成第一封裝組件100，其包含背面重分佈結構106、散熱器170、通孔116、晶片50、封裝劑120、正面重分佈結構122、UBM 138和導電連接器150。
在第28圖中，進行載體基板剝離(de-bonding)，以使載體基板102從背面重分佈結構106，例如介電層108分離(或剝離)。根據一些實施例，剝離包括在釋放層104上投射諸如雷射光或UV光之類的光，使得釋放層104在光的熱量下分解並且可以去除載體基板102。然後將結構翻轉。
進一步在第28圖中，穿過介電層108形成開口115以暴露金屬化圖案111的多個部分。舉例來說，可以使用雷射鑽孔、蝕刻或類似的方式來形成開口115。
隨後，第二封裝組件200以與上述關於第7圖所述之類似的方式附接到第一封裝組件100。舉例來說，導電連接器延伸穿過介電層108中的開口，以將第一封裝組件100的金屬化圖案111電性連接到第二封裝組件200。散熱器170可以設置第一封裝組件100的晶片50與第二封裝組件200的基板202之間，以改善從晶片50到第二封裝組件200的散熱。
可以執行附加製程(例如，類似於上述關於第8圖、第12圖和第13圖描述)以達到第29圖的封裝470。封裝470可包括形成在第一封裝組件100的背面重分佈結構106內的散熱器170。藉由將散熱器170放置在晶片50與第二封裝組件200之間，可以改善散熱和裝置性能。
第30圖繪示出根據一些替代實施例之半導體封裝480的剖面示意圖。半導體封裝480類似於半導體封裝400，其中相同的附圖標記表示由相同製程形成的相同元件。 然而，半導體封裝480中的晶片50以堆疊配置彼此直接接合。在一些實施例中，可以通過上述混合接合製程將晶片50A直接接合至晶片50B。舉例來說，晶片50A的鈍化層68A可以通過介電質對介電質的鍵合直接接合到晶片50B的鈍化層68B，且晶片50A的晶片連接器66A可以通過金屬對金屬的鍵合直接接合到晶片50B的晶片連接器66B。此外，晶片50B可以包括延伸通過晶片50B的基板52的TSV 70。例如，可以使用混合接合配置將TSV 70直接接合到正面重分佈層122的接觸墊110B。
晶片50A和50B都熱連接到封裝480中的散熱器170。舉例來說，散熱器170可以通過薄膜168直接附接到晶片50A的基板52A。此外，熱通孔172可以形成在晶片50B的導電連接器66B上，並且熱通孔172可以將晶片50B熱連接至散熱器170。在一些實施例中，熱通孔172由與通孔116類似的材料並以類似的製程形成。在一些實施例中，熱通孔172可以是不與晶片50A和50B中的任何主動裝置電性連接的虛擬通孔(dummy via)。因此，可以通過散熱器170在封裝480中實現散熱，其中散熱器170熱連接到晶片50A 和50B。熱量也可以通過正面重分佈結構122從晶片50B消散。
根據一些實施例，封裝包括接合到積體電路(integrated circuit，IC)封裝組件的存儲器封裝組件，此存儲器封裝組件包括一個或多個IC晶片。在一些實施例中，在存儲器封裝組件與IC封裝組件之間設置具有較高熱導率的散熱器，以改善散熱。舉例來說，散熱器可以附接到IC晶片的背面，並且散熱器可以從IC晶片延伸到存儲器封裝。在其他實施例中，IC晶片可以直接連接到存儲器封裝，以提高散熱效率。因此，在半導體封裝的實施例中，熱量可以通過散熱器有效地從IC晶片散發到散熱器，也可以通過將IC晶片直接連接到存儲器封裝上而有效地散發。
在一些實施例中，一種半導體封裝包含第一封裝組件包含: 第一半導體晶片；第一封裝劑環繞第一半導體晶片；以及第一重分佈結構電性連接該第一半導體晶片。半導體封裝更包含第二封裝組件接合至第一封裝組件，其中第二封裝組件包含第二半導體晶片；散熱器位於第一半導體晶片與第二封裝組件之間；以及第二封裝劑位於第一封裝組件與第二封裝組件之間，其中第二封裝劑的熱導率低於散熱器的熱導率。可選擇地，在一些實施例中，散熱器的熱導率至少為149 W/m*K。可選擇地，在一些實施例中，散熱器接觸第二封裝組件的基板 。可選擇地，在一些實施例中，第二封裝劑在散熱器之頂表面與第二封裝組件之基板的底表面之間延伸。可選擇地，在一些實施例中，散熱器藉由一薄膜附接至第一半導體晶片的半導體基板。可選擇地，在一些實施例中，薄膜包含高介電常數聚合物、銦、錫、熱介面材料(TIM)或錫膏。可選擇地，在一些實施例中，第二散熱器設置於第一半導體晶片與第二封裝組件之間，且其中第二封裝劑位於散熱器與第二散熱器之間。  可選擇地，在一些實施例中，半導體封裝更包含一散熱蓋附接至第二封裝組件之基板的頂表面，其中第一封裝組件附接至第二封裝組件之基板的底表面。可選擇地，在一些實施例中，第二封裝劑沿著第二封裝組件的多個側壁設置。
在一些實施例中，一種半導體封裝包含第一封裝組件包含: 第一半導體晶片包含第一半導體基板；第一封裝劑環繞第一半導體晶片；以及第一重分佈結構電性連接第一半導體晶片。半導體封裝更包含第二封裝組件接合至第一封裝組件，其中第二封裝組件包含在第二半導體基板上的第二半導體晶片，且其中第一半導體基板藉由一薄膜直接附接至第二半導體基板；第二封裝劑位於第一封裝組件與第二封裝組件之間。可選擇地，在一些實施例中，第二封裝劑具有比第一半導體基板低的熱導率。可選擇地， 在一些實施例中，薄膜包含高介電常數聚合物、銦、錫、熱介面材料(TIM)或錫膏。可選擇地， 在一些實施例中，半導體封裝更包含一通孔位於第一封裝劑中，其中第一半導體晶片延伸高於通孔。可選擇地，在一些實施例中，第二封裝劑在第一半導體晶片之頂表面下延伸。
在一些實施例中，一種方法包含形成一重分佈結構，其中重分佈結構包含位於絕緣層中的第一接觸墊和第二接觸墊；形成一通孔於第二接觸墊上；將第一晶片接合至重分佈結構，其中第一晶片的介電層接觸絕緣層，且其中第一晶片的第三接觸墊接觸第一接觸墊；將一散熱器附接至與重分佈結構相對之第一晶片的表面；以及將包含第二晶片的封裝組件接合至通孔，其中散熱器位於第一晶片與封裝組件之間。可選擇地，在一些實施例中，方法更包含將通孔和第一晶片封裝於第一封裝劑中。可選擇地，在一些實施例中，方法更包含在散熱器周圍和在第一晶片與封裝組件之間分配第二封裝劑，其中散熱器具有比第二封裝劑高的熱導率。可選擇地，在一些實施例中，方法更包含在散熱器的頂表面與封裝組件的底表面之間分配第二封裝劑。可選擇地，在一些實施例中，接合封裝組件包含使散熱器接觸封裝組件。可選擇地， 在一些實施例中，將散熱器附接至與重分佈結構相對之第一晶片的表面包含使用一薄膜將散熱器附接至第一晶片的表面，且其中薄膜包含高介電常數聚合物、銦、錫、熱介面材料(TIM)或錫膏。
前文概述了若干實施例之特徵，使得熟習此項技藝者可較佳理解本揭露之各個實施例。熟習此項技藝者應瞭解，他們可容易地使用本揭示案之各個實施例作為設計或修改用於實現相同目的及/或達成本文中所介紹之實施例之相同優勢的其它製程及結構的基礎。熟習此項技藝者亦應認識到，此些等效構造不脫離本揭示案之各個實施例的精神及範疇，且他們可在不脫離本揭示案之各個實施例的精神及範疇的情況下在本文進行各種改變、代替及替換。
100:第一封裝區域 100A:封裝區域 100B:封裝區域 102:載體基板 104:釋放層 106:背面重分佈結構 108:介電層 110:金屬化圖案 110A:導電墊 110B:導電墊 111:金屬化圖案 112:介電層 113:開口 116:通孔 118:黏著劑 120:封裝劑 122:正面重分佈結構 124:介電層 126:金屬化圖案 128:介電層 130:金屬化圖案 132:介電層 134:金屬化圖案 136:介電層 138:UBM 150:導電連接器 152:導電連接器 154:薄膜 168:薄膜 170:散熱器 172:熱通孔 190:金屬化圖案 200:第二封裝組件 202:基板 204:接合墊 206:接合墊 208:導電通孔 210A:晶片 210B:晶片 212:引線接合 214:模製材料 250:封裝劑 252:框架 254:散熱蓋 300:封裝基板 302:核心基板 304:接合墊 306:阻焊劑 308:底部填充物 400:半導體封裝 420:半導體封裝 430:半導體封裝 440:半導體封裝 450:半導體封裝 460:半導體封裝 470:半導體封裝 480:半導體封裝 50:晶片 50A:第一積體電路晶片 50B:第二積體電路晶片 52:基板 52A:基板 54:裝置 56:層間介電質 58:導電栓塞 60:互連結構 62:焊墊 64:鈍化膜 66:晶片連接器 66A:晶片連接器 66B:導電連接器 68:介電層 68A:鈍化層 68B:鈍化層 70:TSV
當結合隨附諸圖閱讀時，得以自以下詳細描述最佳地理解本揭示案。應強調，根據行業上之標準實務，各種特徵並未按比例繪製且僅用於說明目的。事實上，為了論述清楚，可任意地增大或減小各種特徵之尺寸。 第1圖繪示根據一些實施例之積體電路晶片的剖面示意圖。 第2圖至第13圖繪示根據一些實施例之在形成半導體封裝過程中的中間步驟的剖面示意圖。 第14A圖、第14B圖和第14C圖繪示根據一些實施例之半導體封裝的剖面示意圖。 第15圖至第19圖繪示根據一些實施例之在形成半導體封裝過程中的中間步驟的剖面示意圖。 第20圖繪示根據一些實施例之半導體封裝的剖面示意圖。 第21圖至第29圖繪示根據一些實施例之在形成封裝組件過程中和裝置堆疊實現期間的中間步驟的剖面示意圖。 第30圖繪示根據一些實施例之半導體封裝的剖面示意圖。
100:第一封裝區域
116:通孔
120:封裝劑
122:正面重分佈結構
138:UBM
150:導電連接器
168:薄膜
170:散熱器
200:第二封裝組件
210A:晶片
210B:晶片
250:封裝劑
300:封裝基板
302:核心基板
304:接合墊
306:阻焊劑
308:底部填充物
400:半導體封裝
50:晶片

Claims (20)

  1. 一種半導體封裝，包含： 一第一封裝組件，包含: 一第一半導體晶片； 一第一封裝劑，環繞該第一半導體晶片；以及 一第一重分佈結構，電性連接該第一半導體晶片； 一第二封裝組件，接合至該第一封裝組件，其中該第二封裝組件包含一第二半導體晶片； 一散熱器，位於該第一半導體晶片與該第二封裝組件之間；以及 一第二封裝劑，位於該第一封裝組件與該第二封裝組件之間，其中該第二封裝劑的一熱導率低於該散熱器的一熱導率。
  2. 如請求項1所述之半導體封裝，其中該散熱器的該熱導率至少為149W/m*K。
  3. 如請求項1所述之半導體封裝，其中該散熱器接觸該第二封裝組件的一基板。
  4. 如請求項1所述之半導體封裝，其中該第二封裝劑在該散熱器之一頂表面與該第二封裝組件之一基板的一底表面之間延伸。
  5. 如請求項1所述之半導體封裝，其中該散熱器藉由一薄膜附接至該第一半導體晶片的一半導體基板。
  6. 如請求項5所述之半導體封裝，其中該薄膜包含一高介電常數聚合物、銦、錫、一熱介面材料(TIM)或一錫膏。
  7. 如請求項5所述之半導體封裝，其中一第二散熱器設置於該第一半導體晶片與該第二封裝組件之間，且其中該第二封裝劑位於該散熱器與該第二散熱器之間。
  8. 如請求項1所述之半導體封裝，更包含一散熱蓋附接至該第二封裝組件之一基板的一頂表面，其中該第一封裝組件附接至該第二封裝組件之該基板的一底表面。
  9. 如請求項1所述之半導體封裝，其中該第二封裝劑沿著該第二封裝組件的多個側壁設置。
  10. 一種半導體封裝，包含： 一第一封裝組件，包含: 一第一半導體晶片，包含一第一半導體基板； 一第一封裝劑，環繞該第一半導體晶片；以及 一第一重分佈結構，電性連接該第一半導體晶片； 一第二封裝組件，接合至該第一封裝組件，其中該第二封裝組件包含在一第二半導體基板上的一第二半導體晶片，且其中該第一半導體基板藉由一薄膜直接附接至該第二半導體基板； 一第二封裝劑，位於該第一封裝組件與該第二封裝組件之間。
  11. 如請求項10所述之半導體封裝，其中該第二封裝劑具有比該第一半導體基板低的一熱導率。
  12. 如請求項10所述之半導體封裝，其中該薄膜包含一高介電常數聚合物、銦、錫、一熱介面材料(TIM)或一錫膏。
  13. 如請求項10所述之半導體封裝，更包含一通孔位於該第一封裝劑中，其中該第一半導體晶片延伸高於該通孔。
  14. 如請求項10所述之半導體封裝，其中該第二封裝劑在該第一半導體晶片之一頂表面下延伸。
  15. 一種方法，包含: 形成一重分佈結構，其中該重分佈結構包含位於一絕緣層中的一第一接觸墊和一第二接觸墊； 形成一通孔於該第二接觸墊上； 將一第一晶片接合至該重分佈結構，其中該第一晶片的一介電層接觸該絕緣層，且其中該第一晶片的一第三接觸墊接觸該第一接觸墊； 將一散熱器附接至與該重分佈結構相對之該第一晶片的一表面；以及 將包含一第二晶片的一封裝組件接合至該通孔，其中該散熱器位於該第一晶片與該封裝組件之間。
  16. 如請求項15所述之方法，更包含將該通孔和該第一晶片封裝於一第一封裝劑中。
  17. 如請求項15所述之方法，更包含在該散熱器周圍和在該第一晶片與該封裝組件之間分配一第二封裝劑，其中該散熱器具有比該第二封裝劑高的一熱導率。
  18. 如請求項17所述之方法，更包含在該散熱器的一頂表面與該封裝組件的一底表面之間分配該第二封裝劑。
  19. 如請求項15所述之方法，其中接合該封裝組件包含使該散熱器接觸該封裝組件。
  20. 如請求項15所述之方法，其中將該散熱器附接至與該重分佈結構相對之該第一晶片的該表面包含使用一薄膜將該散熱器附接至該第一晶片的該表面，且其中該薄膜包含一高介電常數聚合物、銦、錫、一熱介面材料(TIM)或一錫膏。
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US20220028842A1 (en) 2022-01-27
KR102524244B1 (ko) 2023-04-20
CN113658944A (zh) 2021-11-16

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