TWI741837B - 積體電路封裝及其形成方法 - Google Patents

積體電路封裝及其形成方法 Download PDF

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TWI741837B
TWI741837B TW109135878A TW109135878A TWI741837B TW I741837 B TWI741837 B TW I741837B TW 109135878 A TW109135878 A TW 109135878A TW 109135878 A TW109135878 A TW 109135878A TW I741837 B TWI741837 B TW I741837B
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Taiwan
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die
power
power supply
rewiring structure
metallization pattern
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TW109135878A
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TW202117987A (zh
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余振華
王垂堂
張豐願
陳頡彥
張維麟
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台灣積體電路製造股份有限公司
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Priority claimed from US16/882,132 external-priority patent/US11532533B2/en
Application filed by 台灣積體電路製造股份有限公司 filed Critical 台灣積體電路製造股份有限公司
Publication of TW202117987A publication Critical patent/TW202117987A/zh
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Abstract

在一實施例中，一種裝置包括：處理器晶粒，包括電路 區塊，電路區塊包括具有第一技術節點的主動裝置；電源閘控晶粒，包括具有第二技術節點的功率半導體裝置，第二技術節點大於第一技術節點；以及第一重佈線結構，包括第一金屬化圖案，第一金屬化圖案包括電力供應源線及電力供應接地線，其中電路區塊的第一子集經由功率半導體裝置電性耦合至電力供應源線及電力供應接地線，且電路區塊的第二子集永久地電性耦合至電力供應源線及電力供應接地線。

Description

積體電路封裝及其形成方法
本發明實施例是關於積體電路封裝及其形成方法。
隨著半導體技術不斷演進，積體電路晶粒變得愈來愈小。此外，更多的功能被整合至晶粒中。因此，晶粒所需要的輸入/輸出(input/output，I/O)墊的數目已增加，而可用於I/O墊的面積已減小。I/O墊的密度隨著時間迅速上升，進而增大了晶粒封裝的難度。一些應用要求積體電路晶粒具有更強大的並行處理能力。封裝技術可用於多個晶粒的整合，從而使得達成更大程度的並行處理能力。
在一些封裝技術中，積體電路晶粒在被封裝之前自晶圓單體化。此種封裝技術的有利特徵是可形成扇出型封裝(fan-out package)，所述扇出型封裝使得晶粒上的I/O墊能夠被重佈線至更大的面積。因此可增加晶粒表面上的I/O墊的數目。
在一實施例中，一種積體電路封裝包括：處理器晶粒，包括電路區塊，所述電路區塊包括具有第一技術節點(technology node)的主動裝置；電源閘控晶粒(power gating die)，包括具有第二技術節點的功率半導體裝置，所述第二技術節點大於所述第 一技術節點；以及第一重佈線結構，包括第一金屬化圖案，所述第一金屬化圖案包括電力供應源線及電力供應接地線，其中所述電路區塊的第一子集經由所述功率半導體裝置電性耦合至所述電力供應源線及所述電力供應接地線，且所述電路區塊的第二子集永久地電性耦合至所述電力供應源線及所述電力供應接地線。
在一實施例中，一種積體電路封裝包括：處理器晶粒，包括電路區塊，所述電路區塊包括具有第一技術節點的主動裝置；電源閘控晶粒，藉由介電質對介電質結合及藉由金屬對金屬結合直接結合至所述處理器晶粒，所述電源閘控晶粒包括具有第二技術節點的功率半導體裝置，所述第二技術節點大於所述第一技術節點，所述功率半導體裝置電性耦合至所述電路區塊的第一子集；介電層，環繞所述電源閘控晶粒；第一導通孔，延伸穿過所述介電層，所述第一導通孔電性耦合至所述電路區塊的第二子集；以及第一重佈線結構，包括第一金屬化圖案，所述第一金屬化圖案包括連接至所述第一導通孔及所述電源閘控晶粒的電力供應源線；封裝基底；以及第一導電連接件，將所述封裝基底連接至所述第一重佈線結構的所述第一金屬化圖案。
在一實施例中，一種積體電路封裝的形成方法包括：將電源閘控晶粒結合至晶圓(wafer)，所述晶圓包括處理器晶粒，所述電源閘控晶粒與所述處理器晶粒包括間距(pitch)不同的主動裝置，所述電源閘控晶粒包括第一導通孔；在所述電源閘控晶粒周圍且在所述晶圓上形成介電層；在第一介電層中圖案化出開口，所述開口暴露出所述處理器晶粒的晶粒連接件；將導電材料鍍覆於所述開口中及所述晶粒連接件上；將所述導電材料平坦化 以在所述開口中形成第二導通孔，所述平坦化暴露出所述電源閘控晶粒的所述第一導通孔；以及鋸切所述介電層及所述晶圓以將所述處理器晶粒單體化。
10:處理器裝置
10F、20F:前側
12、22:半導體基底
12A:主動表面
12N:非主動表面
14、24:內連結構
16、16A、16B、26、728:晶粒連接件
18、28、104、318、522、618、714:介電層
20:電源閘控裝置
20B:後側
22S:開關裝置區
30、106、312、516、612、706、708:導通孔
100、300、400、500、600、700:積體電路封裝
102:晶圓
102A:裝置區
108、306、316、510、520、606、616、712、720:重佈線結構
110:介電層
112、310、320、514、524、610、620、716、724:金屬化圖案
114、322、324、526、622、624、718、726:導電連接件
200:封裝基底
202、406:結合墊
302、502、602、702:載體基底
302A、502A、602A、702A:封裝區
304、504、604、704:釋放層
308、512、608:介電層
314、506、518、614、710、732:包封體
402:基底
404:晶粒
410:模製材料
722:介電層
730:底部填充膠
結合附圖閱讀以下詳細說明，會最佳地理解本揭露的各個態樣。注意，根據行業中的標準慣例，各種特徵並非按比例繪製。事實上，為使論述清晰起見，可任意增大或減小各種特徵的尺寸。
圖1、圖2及圖3是根據一些實施例的用於形成積體電路封裝的製程期間的中間步驟的各種視圖。
圖4、圖5及圖6是根據一些實施例的用於形成實施積體電路封裝的系統的製程期間的中間步驟的剖視圖。
圖7是根據一些其他實施例的積體電路封裝及實施所述積體電路封裝的系統的剖視圖。
圖8、圖9、圖10、圖11、圖12、圖13、圖14、圖15及圖16是根據一些實施例的用於形成實施積體電路封裝的系統的製程期間的中間步驟的剖視圖。
圖17是根據一些其他實施例的積體電路封裝及實施所述積體電路封裝的系統的剖視圖。
圖18是根據一些其他實施例的積體電路封裝及實施所述積體電路封裝的系統的剖視圖。
圖19是根據一些其他實施例的積體電路封裝及實施所述積體電路封裝的系統的剖視圖。
圖20、圖21、圖22、圖23及圖24是根據一些實施例的用於形成積體電路封裝的製程期間的中間步驟的剖視圖。
圖25、圖26、圖27及圖28是根據一些實施例的用於形成實施積體電路封裝的系統的製程期間的中間步驟的剖視圖。
圖29、圖30、圖31、圖32、圖33及圖34是根據一些其他實施例的用於形成實施積體電路封裝的系統的製程期間的中間步驟的剖視圖。
圖35、圖36、圖37、圖38、圖39及圖40是根據一些其他實施例的用於形成積體電路封裝的製程期間的中間步驟的剖視圖。
圖41是根據一些其他實施例的積體電路封裝的剖視圖。
以下揭露內容提供諸多不同的實施例或實例以用於實施本發明的不同特徵。下文闡述組件及排列的具體實例以簡化本揭露。當然，這些僅為實例且不旨在進行限制。舉例而言，在以下說明中第一特徵形成於第二特徵「之上」或形成於第二特徵「上」可包括其中第一特徵與第二特徵被形成為直接接觸的實施例，且亦可包括其中第一特徵與第二特徵之間可形成有額外特徵使得所述第一特徵與所述第二特徵可不直接接觸的實施例。另外，本揭露可在各種實例中重複使用參考編號及/或字母。此種重複是出於簡潔及清晰的目的，而非自身指示所論述的各種實施例及/或配置之間的關係。
此外，為易於說明起見，本文中可使用例如「位於...之下(beneath)」、「位於...下方(below)」、「下部的(lower)」、「位 於...上方(above)」、「上部的(upper)」等空間相對性用語來闡述圖中所示的一個元件或特徵與另一(其他)元件或特徵的關係。除圖中所繪示的定向之外，所述空間相對性用語亦旨在囊括裝置在使用或操作中的不同定向。設備可具有其他定向(旋轉90度或處於其他定向)，且同樣地可對本文中所使用的空間相對性描述語加以相應地解釋。
根據一些實施例，形成具有處理器裝置及電源閘控裝置的積體電路封裝，處理器裝置與電源閘控裝置是分離的半導體裝置。電源閘控裝置形成有較處理器裝置大的主動裝置，且包括為處理器裝置提供電源閘控的功率半導體裝置。因此，具有大的技術節點的開關電晶體可用於電力輸送，從而允許減小所得的積體電路封裝的功耗。
圖1、圖2及圖3是根據一些實施例的用於形成積體電路封裝100的製程期間的中間步驟的剖視圖。藉由將半導體裝置堆疊於晶圓102上形成積體電路封裝100。說明將裝置堆疊於晶圓102的一個裝置區102A中，但應瞭解，晶圓102可具有任何數目的裝置區，且可將半導體裝置堆疊於每一裝置區中以形成積體電路封裝。半導體裝置可以是裸積體電路晶粒或經封裝晶粒。在所說明的實施例中，每一半導體裝置是裸積體電路晶粒。在其他實施例中，所說明的半導體裝置中的一或多者可以是被包封的經封裝晶粒。
在圖1中，獲得晶圓102。晶圓102包括位於裝置區102A中的處理器裝置10。將在後續處理中將處理器裝置10單體化以包括於積體電路封裝100中。處理器裝置10可以是任何可接受的處 理器或邏輯裝置，例如中央處理單元(central processing unit，CPU)、圖形處理單元(graphics processing unit，GPU)、算術邏輯單元(arithmetic logic unit，ALU)、系統晶片(system-on-a-chip，SoC)、應用處理器(application processor，AP)、影像訊號處理器(image signal processor，ISP)、數位訊號處理器(digital signal processor，DSP)、現場可程式化閘陣列(field programmable gate array，FPGA)、微控制器、人工智慧(artificial intelligence，AI)加速度計等。如下文進一步論述，處理器裝置10被形成為不包括電源閘控特徵。
可根據可適用的製造製程對處理器裝置10進行處理以形成積體電路。舉例而言，處理器裝置10包括經摻雜或未經摻雜的半導體基底12(例如矽)或絕緣體上半導體(semiconductor-on-insulator，SOI)基底的主動層。半導體基底12可包含其他半導體材料，例如：鍺；化合物半導體，包括碳化矽、鎵砷、磷化鎵、磷化銦、砷化銦及/或銻化銦；合金半導體，包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP及/或GaInAsP；或其組合。亦可使用其他基底，例如多層基底或梯度基底。半導體基底12具有主動表面12A及非主動表面12N。
可在半導體基底12的主動表面12A處形成裝置。所述裝置可以是主動裝置(例如電晶體、二極體等)、電容器、電阻器等。非主動表面12N可不具有裝置。層間介電質(inter-layer dielectric，ILD)位於半導體基底12的主動表面12A之上。ILD環繞且可覆蓋裝置。ILD可包括由以下材料形成的一或多個介電層，例如磷矽酸鹽玻璃(Phospho-Silicate Glass，PSG)、硼矽酸鹽 玻璃(Boro-Silicate Glass，BSG)、摻雜硼的磷矽酸鹽玻璃(Boron-Doped Phospho-Silicate Glass，BPSG)、未經摻雜的矽酸鹽玻璃(undoped Silicate Glass，USG)等。
內連結構14位於半導體基底12的主動表面12A之上。內連結構14對半導體基底12的主動表面12A處的裝置進行內連以形成積體電路。可藉由例如介電層中的金屬化圖案形成內連結構14。金屬化圖案包括形成於一或多個介電層中的金屬線及通孔。內連結構14的金屬化圖案電性耦合至半導體基底12的主動表面12A處的裝置。
晶粒連接件16位於處理器裝置10的前側10F處。晶粒連接件16可以是進行外部連接的導電柱、墊等。晶粒連接件16位於內連結構14中及/或上。晶粒連接件16可由金屬(例如銅、鋁等)形成，且可藉由例如鍍覆等形成。
介電層18位於處理器裝置10的前側10F處。介電層18位於內連結構14中及/或上。介電層18在側向上包封晶粒連接件16，且介電層18與處理器裝置10的側壁在側向上毗連(coterminous)。首先，介電層18可隱埋晶粒連接件16，以使得介電層18的最頂表面位於晶粒連接件16的最頂表面上方。介電層18可以是：聚合物，例如聚苯並噁唑(polybenzoxazole，PBO)、聚醯亞胺、苯並環丁烯(benzocyclobuten，BCB)系聚合物等；氮化物，例如氮化矽等；氧化物，例如氧化矽，PSG，BSG，BPSG等；類似物或其組合。可例如藉由旋轉塗佈、層壓、化學氣相沉積(chemical vapor deposition，CVD)等形成介電層18。在形成之後，可使用例如化學機械拋光(chemical-mechanical polish， CMP)製程、回蝕製程等或其組合將晶粒連接件16及介電層18平坦化。在平坦化之後，晶粒連接件16的表面及介電層18的表面是平坦的且在處理器裝置10的前側10F處暴露出。
處理器裝置10包括多個電路區塊。電路區塊是處理器裝置10的電路的邏輯區塊或邏輯單元。換言之，電路區塊包括處理器裝置10的電路的子集，其中電路區塊中的電路全部與同一域相關。電路區塊的實例包括算術電路區塊、記憶體電路區塊、DSP電路區塊等。
亦獲得電源閘控裝置20。電源閘控裝置20是處理器裝置10的電力輸送網路的一部分。具體而言，電源閘控裝置20為處理器裝置10的電路區塊中的一些或所有電路區塊提供電源閘控。電源閘控裝置20可在運行時間操作以接收控制訊號並因應於所述控制訊號而將處理器裝置10的電路區塊接通或關斷。舉例而言，處理器裝置10的電路區塊可在需要時接通且可不在處於使用中時關斷，因此減少未使用電路區塊洩漏的電力。因此，可減小處理器裝置10的功耗。此外，形成不包括電源閘控特徵的處理器裝置10使得能夠減小處理器裝置10的面積。舉例而言，將電源閘控特徵移動到專用電源閘控裝置20使得能夠將處理器裝置10的面積減小達20%。
可根據可適用的製造製程對電源閘控裝置20進行處理以形成積體電路。舉例而言，電源閘控裝置20包括半導體基底22、內連結構24、晶粒連接件26及介電層28，所述半導體基底22、內連結構24、晶粒連接件26及介電層28可分別類似於半導體基底12、內連結構14、晶粒連接件16及介電層18。電源閘控 裝置20的前側20F處暴露出晶粒連接件26及介電層28。電源閘控裝置20更包括導通孔30，導通孔30被形成為延伸至半導體基底22中。導通孔30電性耦合至內連結構24的金屬化圖案。
以形成導通孔30作為實例，可藉由例如蝕刻、銑削、雷射技術、其組合等在內連結構24及/或半導體基底22中形成凹陷部。可例如藉由使用氧化技術在所述凹陷部中形成薄的介電材料。可例如藉由CVD、原子層沉積(atomic layer deposition，ALD)、物理氣相沉積(physical vapor deposition，PVD)、熱氧化、其組合等在開口中共形地沉積薄的障壁層。障壁層可由氧化物、氮化物或氮氧化物(例如氮化鈦、氮氧化鈦、氮化鉭、氮氧化鉭、氮化鎢、其組合等)形成。可在障壁層之上及在開口中沉積導電材料。可藉由電化學鍍覆製程、CVD、ALD、PVD、其組合等形成導電材料。導電材料的實例是銅、鎢、鋁、銀、金、其組合等。藉由例如CMP自內連結構24的表面及/或半導體基底22的表面移除多餘導電材料及障壁層。障壁層的剩餘部分及導電材料的剩餘部分形成導通孔30。
在所說明的實施例中，電源閘控裝置20的後側20B處尚未暴露出導通孔30。而是，導通孔30隱埋於半導體基底22中。如下文進一步論述，將在後續處理中經由平坦化製程在電源閘控裝置20的後側20B處暴露出導通孔30。在暴露之後，導通孔30可被稱為基底穿孔或矽穿孔(through-substrate via或through-silicon via，TSV)。
電源閘控裝置20包括用以為處理器裝置10提供電源閘控的功率半導體裝置(例如，用於功率電子器件的半導體裝置)。 具體而言，電源閘控裝置20可包括開關電晶體、電源閘控控制器及電源閘控網路結構。電源閘控裝置20的功率半導體裝置可以是雙極裝置，例如絕緣閘雙極電晶體(insulated-gate bipolar transistor，IGBT)裝置等；或可以是功率金屬氧化物半導體場效應電晶體(Metal Oxide Semiconductor Field Effect Transistor，MOSFET)裝置，例如互補金屬氧化物半導體(complementary metal-oxide-semiconductor，CMOS)裝置、雙擴散金屬氧化物半導體(diffused metal-oxide-semiconductor，DMOS)裝置等。在一些實施例中，處理器裝置10與電源閘控裝置20是藉由不同的半導體製程技術形成，且具有間距不同的裝置(例如，主動裝置)。舉例而言，處理器裝置10可包括CMOS裝置，且電源閘控裝置20可包括IGBT裝置或DMOS裝置。半導體基底22的主動表面包括開關裝置區22S，開關裝置區22S包括開關電晶體。開關裝置區22S的開關電晶體連接至電力供應源(VDD)線(下文進一步論述)，且在被啟動時將VDD線電性耦合至處理器裝置10的電路區塊。同樣地，內連結構24的金屬化圖案可形成電源閘控網路結構中的一些或所有電源閘控網路結構。舉例而言，內連結構24可包括用於將VDD線自開關電晶體路由至處理器裝置10的電路區塊的金屬線及通孔。
內連結構24的金屬化圖案可形成電源閘控網路結構中的一些電源閘控網路結構、所有電源閘控網路結構，或者不形成電源閘控網路結構。在一些實施例中，電源閘控裝置20的內連結構24包括所有的電源閘控網路結構。在一些實施例中，電源閘控裝置20的內連結構24包括電源閘控網路結構中的一些電源閘控 網路結構，且處理器裝置10的內連結構14包括電源閘控網路結構中的一些電源閘控網路結構。在一些實施例中，電源閘控裝置20的內連結構24不包括電源閘控網路結構，且處理器裝置10的內連結構14包括所有的電源閘控網路結構。
開關電晶體的電力輸送效能可顯著地影響電源閘控裝置20的總體電力輸送效能。具體而言，具有大的技術節點的開關電晶體可適應較大的衝擊電流，且在處理器裝置10的電路區塊接通時具有較小的電壓降(例如，電壓電位降(IR drop))。類似地，具有大的技術節點的開關電晶體可具有較大的臨限值電壓，此使得開關電晶體能夠減少的電力洩漏。根據一些實施例，處理器裝置10具有技術節點較小(例如，裝置間距或間隔較小)的主動裝置，所述技術節點較小的主動裝置不適合於開關電晶體但適合於邏輯裝置，且電源閘控裝置20具有技術節點較大(例如，裝置間距或間隔較大)的主動裝置，所述技術節點較大的主動裝置不適合於邏輯裝置但適合於開關電晶體。舉例而言，處理器裝置10可具有技術節點處於約2奈米至約28奈米範圍中的主動裝置(例如，形成電路區塊)，且電源閘控裝置20可具有技術節點處於約3奈米至約90奈米範圍中的主動裝置(例如，功率半導體裝置)。形成主動裝置較處理器裝置10大的電源閘控裝置20使得處理器裝置10能夠被縮小至提供改良的邏輯裝置效能的較小技術節點，同時仍使得電源閘控裝置20能夠提供足夠的電力輸送效能。此外，形成具有較大的主動裝置的電源閘控裝置20使得能夠降低電源閘控裝置20的製造成本。
在圖2中，將電源閘控裝置20結合至處理器裝置10(例如，晶圓102)。藉由混合結合而以面對面方式直接結合處理器裝置10與電源閘控裝置20，以使得處理器裝置10的前側10F結合至電源閘控裝置20的前側20F。具體而言，經由介電質對介電質結合將處理器裝置10的介電層18結合至電源閘控裝置20的介電層28，而不使用任何黏合材料(例如，晶粒貼合膜)，且經由金屬對金屬結合將處理器裝置10的晶粒連接件16A的子集結合至電源閘控裝置20的晶粒連接件26，而不使用任何共晶材料(例如，焊料)。所述結合可包括預結合及退火。在預結合期間，施加小的按壓力以將電源閘控裝置20按壓成抵靠處理器裝置10(例如，晶圓102)。在低溫下實行預結合，且在預結合之後，介電層18與介電層28結合至彼此。然後，在後續退火步驟中提高結合強度，其中在高溫下對介電層18及28進行退火。在退火之後，形成結合(例如熔合結合)，從而將介電層18與介電層28結合。舉例而言，所述結合可以是介電層18的材料與介電層28的材料之間的共價鍵。晶粒連接件16A與晶粒連接件26一一對應地連接至彼此。晶粒連接件16A與晶粒連接件26可在預結合之後實體接觸，或可在退火期間發生膨脹而達到實體接觸。此外，在退火期間，晶粒連接件16A的材料與晶粒連接件26的材料(例如，銅)混雜，以使得亦形成金屬對金屬結合。因此，處理器裝置10與電源閘控裝置20之間所得的結合是包括介電質對介電質結合及金屬對金屬結合兩者的混合結合。
在混合結合之後，藉由直接結合將處理器裝置10電性耦合至電源閘控裝置20，經由所述直接結合實行控制傳訊及電源/ 接地傳訊。具體而言，處理器裝置10可經由所述直接結合將控制訊號發送至電源閘控裝置20，且可經由所述直接結合自電源閘控裝置20接收電源/接地訊號。可藉由使用直接結合來改良處理器裝置10與電源閘控裝置20之間的傳訊延時及內連頻寬。此外，亦可減小內連的阻抗且因此減小內連的功耗。如上文所述，內連結構24的金屬化圖案可形成電源閘控網路結構中的一些或所有電源閘控網路結構。在這些實施例中，電源閘控網路結構因此藉由直接結合連接至處理器裝置10，此可使得佈線能夠較其他類型的內連更簡單。在所示的實施例中，一個電源閘控裝置20結合至處理器裝置10。在另一實施例中，多個電源閘控裝置20結合至處理器裝置10。
在圖3中，形成環繞電源閘控裝置20的介電層104。可在放置電源閘控裝置20之後但在退火之前形成介電層104以完成混合結合，或可在退火之後形成介電層104。介電層104填充電源閘控裝置20與晶圓102的鄰近裝置區(未示出)中的其他裝置之間的間隙，因此保護半導體裝置。介電層104可以是：氧化物，例如氧化矽、PSG、BSG、BPSG等；氮化物，例如氮化矽等；聚合物，例如PBO、聚醯亞胺、BCB系聚合物等；包封體，例如模製化合物、環氧樹脂等；類似物或其組合。在一些實施例中，介電層104是氧化物，例如氧化矽。在一些實施例中，介電層104是使用CVD製程等沉積而成。
然後，形成延伸穿過介電層104的導通孔106。以形成導通孔106作為實例，在介電層104中圖案化出開口。可藉由可接受的製程進行圖案化，例如當介電層104是感光性材料時藉由 將介電層104暴露於光，或藉由使用例如非等向性蝕刻來蝕刻介電層104。開口會暴露出處理器裝置10的晶粒連接件16B的子集。在介電層104上及在晶粒連接件16B的由開口暴露出的部分上形成晶種層。在一些實施例中，所述晶種層是金屬層，所述金屬層可以是單層或包括由不同的材料形成的多個子層的複合層。在特定實施例中，所述晶種層包括鈦層及位於所述鈦層之上的銅層。可使用例如PVD等來形成晶種層。在晶種層上形成導電材料。可藉由鍍覆(例如，電鍍覆或無電鍍覆)等形成導電材料。導電材料可包括金屬，例如銅、鈦、鎢、鋁等。然後，移除晶種層的多餘部分及導電材料的多餘部分，其中所述多餘部分是上覆於介電層104上的部分。可藉由平坦化製程進行移除。對晶種層、導電材料、介電層104及電源閘控裝置20實行平坦化製程。所述移除會同時移除晶種層的多餘部分及導電材料的多餘部分且暴露出導通孔30。平坦化製程可以是例如CMP製程、研磨製程、回蝕製程、類似製程或其組合。晶種層及導電材料在開口中的剩餘部分形成導通孔106。在平坦化製程之後，介電層104的頂表面、導通孔106的頂表面、半導體基底22的頂表面及導通孔30的頂表面是平坦的。
圖4、圖5及圖6是根據一些實施例的用於形成實施積體電路封裝100的系統的製程期間的中間步驟的剖視圖。在此實施例中，積體電路封裝100被進一步處理成包括重佈線結構且被直接安裝至封裝基底。
在圖4中，在介電層104、導通孔106及電源閘控裝置20上形成重佈線結構108。重佈線結構108包括介電層110及位 於介電層110之中的金屬化圖案112(有時被稱為重佈線層或重佈線線路)。舉例而言，重佈線結構108可包括藉由相應的介電層110彼此隔開的多個金屬化圖案112。重佈線結構108的金屬化圖案112連接至導通孔106及電源閘控裝置20(例如，連接至導通孔30)。
在一些實施例中，介電層110由聚合物形成，所述聚合物可以是可使用微影罩幕來加以圖案化的感光性材料，例如PBO、聚醯亞胺、BCB系聚合物等。在其他實施例中，介電層110由以下材料形成：氮化物，例如氮化矽；氧化物，例如氧化矽、PSG、BSG、BPSG等。可藉由旋轉塗佈、層壓、CVD等或其組合形成介電層110。在形成每一介電層110之後，然後將介電層110圖案化以暴露出下伏的導電特徵，例如下伏金屬化圖案112的一些部分。圖案化可藉由可接受的製程進行，例如藉由在介電層110是感光性材料時將介電層暴露於光，或藉由使用例如非等向性蝕刻來進行蝕刻。若介電層110是感光性材料，則可在曝光之後對介電層110進行顯影。
金屬化圖案112各自包括導通孔及/或導電線。導通孔延伸穿過介電層110，且導電線沿著介電層110延伸。以形成金屬化圖案作為實例，在相應的下伏特徵之上形成晶種層(未示出)。舉例而言，當形成重佈線結構108的最底層時，晶種層可形成於介電層104、導通孔106、半導體基底22及導通孔30上，或者當形成重佈線結構108的中間層/最頂層時，晶種層可形成於相應的介電層110上及穿過相應的介電層110的開口中。在一些實施例中，所述晶種層是金屬層，所述金屬層可以是單層或包括由不同的材 料形成的多個子層的複合層。在一些實施例中，所述晶種層包括鈦層及位於所述鈦層之上的銅層。可使用例如PVD等沉積製程形成所述晶種層。然後，在晶種層上形成光阻並將所述光阻圖案化。可藉由旋轉塗佈等形成光阻且可將光阻暴露於光以進行圖案化。光阻的圖案對應於金屬化圖案。圖案化會形成穿過光阻以暴露出晶種層的開口。在光阻的開口中及在晶種層的暴露部分上形成導電材料。可藉由鍍覆(例如，電鍍覆或無電鍍覆等)形成導電材料。所述導電材料可包括金屬或金屬合金，例如銅、鈦、鎢、鋁、等或其組合。然後，移除光阻及晶種層的上面未形成導電材料的部分。可藉由可接受的灰化或剝除製程(例如使用氧電漿等)移除光阻。一旦光阻被移除，則例如藉由使用可接受的蝕刻製程(例如，藉由濕式蝕刻或乾式蝕刻)移除晶種層的暴露部分。晶種層的剩餘部分及導電材料形成重佈線結構108中的一層的金屬化圖案。
說明重佈線結構108作為實例。可藉由重複或省略上文所述的步驟來在重佈線結構108中形成較所說明的更多或更少的介電層110及金屬化圖案112。
重佈線結構108的金屬化圖案112包括電力供應源(VDD)線及電力供應接地(VSS)線。VDD線及VSS線連接至導通孔30及106。因此，電源閘控裝置20的開關裝置區22S藉由導通孔30電性耦合至VDD線及VSS線。處理器裝置10的電路區塊的第一子集經由電源閘控裝置20電性耦合至VDD線及VSS線。因此，電源閘控裝置20可接通及關斷電路區塊的第一子集。處理器裝置10的電路區塊的第二子集繞過電源閘控裝置20而經由導通孔106 電性耦合至VDD線及VSS線。因此，電路區塊的第二子集永久地電性耦合至電源及接地。永久地電性耦合至電源及接地的電路區塊始終接通，且不受電源閘控。
重佈線結構108的金屬化圖案112亦包括資料訊號線，所述資料訊號線藉由導通孔106電性耦合至處理器裝置10。舉例而言，導通孔106中的一些導通孔將處理器裝置10的輸入/輸出(I/O)連接耦合至重佈線結構108。因此，處理器裝置10可耦合至外部裝置。
在圖5中，形成連接至重佈線結構108的金屬化圖案112的導電連接件114。可將重佈線結構108的頂部介電層110圖案化以暴露出下伏金屬化圖案112的一些部分。在一些實施例中，可在開口中形成凸塊下金屬(under bump metallurgies，UBM)。在UBM上形成導電連接件114。導電連接件114可以是球柵陣列(ball grid array，BGA)連接件、焊料柱、金屬柱、受控塌陷晶片連接(controlled collapse chip connection，C4)凸塊、微凸塊、無電鍍鎳鈀浸金技術(electroless nickel-electroless palladium-immersion gold，ENEPIG)形成的凸塊等。導電連接件114可由金屬或金屬合金形成，例如焊料、銅、鋁、金、鎳、銀、鈀、錫等或其組合。在一些實施例中，首先經由一些常用方法(例如蒸鍍、電鍍覆、印刷、焊料轉移、植球等)形成焊料層來形成導電連接件114。一旦已在結構上形成焊料層，則可實行回焊以將材料塑形成所期望的凸塊形狀。在另一實施例中，導電連接件114是藉由濺鍍、印刷、電鍍覆、無電鍍覆、CVD等形成的金屬柱(例如，銅柱)。金屬柱可不具有焊料且具有實質上垂直的側壁。
在圖6中，藉由沿著切割道區(例如，在裝置區102A周圍)進行鋸切來實行單體化製程。單體化製程包括鋸切重佈線結構108、介電層104及晶圓102。單體化製程將裝置區102A(包括處理器裝置10)與晶圓102的鄰近裝置區(未示出)分離以形成包括處理器裝置10的積體電路封裝100。如上文所述，電源閘控裝置20以面對面方式直接結合至處理器裝置10，而不使用焊料。因此，所得的積體電路封裝100不具有焊料。在單體化之後，重佈線結構108(例如，介電層110)、介電層104及處理器裝置10在側向上毗連。
然後將積體電路封裝100倒置並使用導電連接件114貼合至封裝基底200。封裝基底200可由半導體材料(例如矽、鍺、金剛石等)製成。作為另外一種選擇，亦可使用化合物材料，例如矽鍺、碳化矽、鎵砷、砷化銦、磷化銦、碳化矽鍺、磷化鎵砷、磷化鎵銦、這些材料的組合等。另外，封裝基底200可以是SOI基底。通常，SOI基底包含一層半導體材料，例如磊晶矽、鍺、矽鍺、SOI、SGOI或其組合。在一個替代實施例中，封裝基底200基於絕緣芯，例如玻璃纖維加強型樹脂芯。一種示例性芯材料是玻璃纖維樹脂，例如FR4。芯材料的替代物包括雙馬來醯亞胺三嗪(bismaleimide-triazine，BT)樹脂，或作為另外一種選擇包括其他印刷電路板(printed circuit board，PCB)材料或膜。構成膜(例如，味之素構成膜(Ajinomoto build-up film，ABF))或其他層壓體可用於封裝基底200。
封裝基底200可包括主動裝置及被動裝置(未示出)。例如電晶體、電容器、電阻器、這些的組合等裝置可用於產生系 統的設計的結構要求及功能要求。可使用任何適合的方法形成所述裝置。
封裝基底200亦可包括金屬化層及通孔(未示出)以及位於所述金屬化層及通孔之上的結合墊202。金屬化層可形成於主動裝置及被動裝置之上，且被設計成對各種裝置進行連接以形成功能電路系統。金屬化層可由介電質(例如，低介電常數(low-k)介電材料)與導電材料(例如，銅)的交替層形成且可經由任何適合的製程(例如沉積、鑲嵌、雙鑲嵌等)形成，其中通孔對導電材料層進行內連。在一些實施例中，封裝基底200實質上不具有主動裝置及被動裝置。
對導電連接件114進行回焊以將重佈線結構108的UBM貼合至結合墊202。導電連接件114將封裝基底200(包括封裝基底200中的金屬化層)連接至積體電路封裝100(包括重佈線結構108的金屬化圖案112)。在一些實施例中，被動裝置(例如，表面安裝式裝置(surface mount device，SMD)，未示出)可在被安裝於封裝基底200上之前貼合至積體電路封裝100(例如，結合至結合墊202)。在這些實施例中，被動裝置可與導電連接件114結合至積體電路封裝100的同一表面。在一些實施例中，被動裝置(例如SMD，未示出)可貼合至封裝基底200，例如貼合至結合墊202。
導電連接件114在被回焊之前上面可形成有環氧助焊劑(未示出)，其中在將積體電路封裝100貼合至封裝基底200之後環氧助焊劑的環氧部分的至少一些保留下來。此剩餘的環氧部分可用作底部填充膠以減小應力且保護對導電連接件114進行回焊 所得的接頭。在一些實施例中，底部填充膠(未示出)可形成於積體電路封裝100與封裝基底200之間，從而環繞導電連接件114。可在貼合積體電路封裝100之後藉由毛細流動過程形成底部填充膠，或可在貼合積體電路封裝100之前藉由適合的沉積方法形成底部填充膠。
圖7是根據一些其他實施例的積體電路封裝100及實施積體電路封裝100的系統的剖視圖。此實施例類似於關於圖6所述的實施例，但處理器裝置10與電源閘控裝置20以面對背方式直接結合。因此，重佈線結構108的金屬化圖案112(例如，VDD線及VSS線)連接至晶粒連接件26，且藉由導通孔30電性耦合至處理器裝置10。
處理器裝置10與電源閘控裝置20藉由混合結合而以面對背方式直接結合，以使得處理器裝置10的前側10F結合至電源閘控裝置20的後側20B。具體而言，處理器裝置10的介電層18經由介電質對介電質結合而結合至電源閘控裝置20的半導體基底22，而不使用任何黏合材料(例如，晶粒貼合膜)，且處理器裝置10的晶粒連接件16A的子集經由金屬對金屬結合而結合至電源閘控裝置20的導通孔30，而不使用任何共晶材料(例如，焊料)。結合可包括預結合及退火。在預結合期間，施加小的按壓力以將電源閘控裝置20按壓成抵靠處理器裝置10。在低溫下實行預結合，且在預結合之後，介電層18與半導體基底22結合至彼此。在一些實施例中，在電源閘控裝置20的後側20B處(例如在半導體基底22上)形成氧化物(例如天然氧化物、熱氧化物等)，且所述氧化物用於結合。然後在後續退火步驟中提高結合強度，其 中在高溫下對介電層18及半導體基底22進行退火。在退火之後，形成結合(例如熔合結合)，從而結合介電層18與半導體基底22。舉例而言，所述結合可以是介電層18的材料與半導體基底22的材料之間的共價鍵。晶粒連接件16A與導通孔30一一對應地連接至彼此。晶粒連接件16A與導通孔30可在預結合之後實體接觸，或可在退火期間發生膨脹以達到實體接觸。此外，在退火期間，晶粒連接件16A的材料與導通孔30的材料(例如，銅)混雜，以使得亦形成金屬對金屬結合。因此，處理器裝置10與電源閘控裝置20之間所得的結合是包括介電質對介電質結合及金屬對金屬結合兩者的混合結合。
圖8、圖9、圖10、圖11、圖12、圖13、圖14、圖15及圖16是根據一些其他實施例的用於形成實施積體電路封裝100的系統的製程期間的中間步驟的剖視圖。在此實施例中，將積體電路封裝100單體化並包括於封裝組件中。說明將裝置封裝於一個封裝區302A中，但應瞭解，可同時形成任何數目的封裝區。將在後續處理中將封裝區302A單體化。經單體化的封裝組件可以是扇出型封裝，例如積體扇出型(integrated fan-out，InFO)封裝。然後，將扇出型封裝安裝至封裝基底。
在圖8中，提供載體基底302，且在載體基底302上形成釋放層304。載體基底302可以是玻璃載體基底、陶瓷載體基底等。載體基底302可以是晶圓，以使得多個封裝可同時形成於載體基底302上。釋放層304可由聚合物系材料形成，可將釋放層304與載體基底302一起自將在後續步驟中形成的上覆結構移除。在一些實施例中，釋放層304是在受熱時失去其黏合性質的 環氧樹脂系熱釋放材料，例如光熱轉換(light-to-heat-conversion，LTHC)釋放塗層。在其他實施例中，釋放層304可以是在暴露於紫外線(ultra-violet，UV)光時失去其黏合性質的UV膠。可以液體的形式施配釋放層304並將釋放層304固化，釋放層304可以是層壓至載體基底302上的層壓膜，或可以是類似的材料。釋放層304的頂表面可齊平且可具有高程度的平坦度。
在圖9中，可在釋放層304上形成重佈線結構306。重佈線結構306可以與關於圖4所述的重佈線結構108類似的方式且由類似的材料形成。重佈線結構306包括介電層308及金屬化圖案310(有時被稱為重佈線層或重佈線線路)。可在重佈線結構306中形成較所說明的更多或更少的介電層308及金屬化圖案310。重佈線結構306是可選的。在一些實施例中，在釋放層304上形成不具有金屬化圖案的介電層來代替重佈線結構306。
在圖10中，形成延伸穿過重佈線結構306的最頂部介電層308的導通孔312。因此，導通孔312連接至重佈線結構306的金屬化圖案310。導通孔312是可選的且可省略。舉例而言，在省略重佈線結構306的實施例中可(或可不)省略導通孔312。
以形成導通孔312作為實例，可在重佈線結構306的最頂部介電層308中形成開口。然後，在重佈線結構306之上(例如，在最頂部介電層308上及在金屬化圖案310的由最頂部介電層308中的開口暴露出的部分上)形成晶種層。在一些實施例中，所述晶種層是金屬層，所述金屬層可以是單層或包括由不同的材料形成的多個子層的複合層。在特定實施例中，所述晶種層包括鈦層及位於所述鈦層之上的銅層。可使用例如PVD等來形成晶種 層。在晶種層上形成光阻並將所述光阻圖案化。可藉由旋轉塗佈等形成光阻且將光阻暴露於光以進行圖案化。光阻的圖案對應於導通孔。圖案化會形成穿過光阻以暴露出晶種層的開口。在光阻的開口中及在晶種層的暴露部分上形成導電材料。導電材料可藉由鍍覆(例如，電鍍覆或無電鍍覆等)形成。導電材料可包括金屬，如銅、鈦、鎢、鋁等。移除光阻、及晶種層的上面未形成導電材料的部分。可藉由可接受的灰化或剝除製程(例如使用氧電漿等)移除光阻。一旦光阻被移除，則例如藉由使用可接受的蝕刻製程(例如，藉由濕式蝕刻或乾式蝕刻)移除晶種層的暴露部分。晶種層的剩餘部分及導電材料形成導通孔312。
在圖11中，將經單體化的積體電路封裝100放置在重佈線結構306(例如，最頂部介電層308)上。為形成經單體化的積體電路封裝100，獲得與關於圖3所述的中間結構類似的中間結構。藉由沿著切割道區(例如，在裝置區102A(參見圖3)周圍)進行鋸切來實行單體化製程。單體化製程包括鋸切介電層104及晶圓102。單體化製程將裝置區102A(包括處理器裝置10)與晶圓102的鄰近裝置區(未示出)分離以形成包括處理器裝置10的積體電路封裝100。如上文所述，電源閘控裝置20以面對面方式直接結合至處理器裝置10，而不使用焊料。因此，所得的積體電路封裝100不具有焊料。在單體化之後，介電層104與處理器裝置10在側向上毗連。
在圖12中，在導通孔312及積體電路封裝100上及周圍形成包封體314。在形成之後，包封體314包封導通孔312及積體電路封裝100。包封體314可以是模製化合物、環氧樹脂等。可 藉由壓縮模製、轉移模製等施加包封體314，且包封體314可形成於載體基底302之上以使得隱埋或覆蓋積體電路封裝100及/或導通孔312。可以液體或半液體形式施加包封體314且然後隨後將包封體314固化。在一些實施例中，包封體314不同於介電層104且包含與介電層104不同的材料。然後，可對包封體314實行平坦化製程以暴露出導通孔312及積體電路封裝100。平坦化製程可移除導通孔312的材料、包封體314的材料、介電層104的材料、導通孔106的材料、半導體基底22的材料及/或導通孔30的材料，直至暴露出導通孔30、106、312。在平坦化製程之後，平坦化組件的頂表面是共面的。平坦化製程可以是例如化學機械拋光(CMP)、研磨製程、回蝕等。在一些實施例中，舉例而言若導通孔30、106、312已暴露出，則可省略平坦化。
在圖13中，在包封體314、導通孔312及積體電路封裝100上形成重佈線結構316。可以與關於圖4所述的重佈線結構108類似的方式且由類似的材料形成重佈線結構316。重佈線結構316包括介電層318及金屬化圖案320(有時被稱為重佈線層或重佈線線路)。可在重佈線結構316中形成較所說明的更多或更少的介電層318及金屬化圖案320。重佈線結構316的金屬化圖案320連接至導通孔30、106、312。重佈線結構316的金屬化圖案320包括電力供應源(VDD)線、電力供應接地(VSS)線及資料訊號線，電力供應源(VDD)線、電力供應接地(VSS)線及資料訊號線以與關於圖4所述的方式類似的方式電性耦合至處理器裝置10及電源閘控裝置20。
在圖14中，形成連接至重佈線結構316的金屬化圖案320的導電連接件322。可以與關於圖5所述的導電連接件114類似的方式且由類似的材料形成導電連接件322。舉例而言，可在重佈線結構316的UBM上形成導電連接件322。
在圖15中，實行載體基底剝離以將載體基底302自重佈線結構306(例如，最底部介電層308)剝除(剝離)。根據一些實施例，剝離包括將光(例如，雷射光或UV光)投射於釋放層304上，以使得釋放層304在光的熱量下分解且可移除載體基底302。然後，可將結構倒置並放置於例如條帶上。
此外，穿過重佈線結構306的最底部介電層308形成導電連接件324。可穿過重佈線結構306的最底部介電層308形成開口，從而暴露出金屬化圖案310的部分。可例如使用雷射鑽孔、蝕刻等形成開口。導電連接件324形成於開口中，且連接至金屬化圖案310的暴露部分。可以與關於圖5所述的導電連接件114類似的方式且由類似的材料形成導電連接件324。
在圖16中，藉由沿著切割道區(例如，在封裝區302A周圍)進行鋸切來實行單體化製程。單體化製程包括鋸切重佈線結構306、316及包封體314。單體化製程將封裝區302A與鄰近封裝區(未示出)分離以形成積體電路封裝300。在單體化之後，重佈線結構306、316(例如，介電層308、318)與包封體314在側向上毗連。
可將另一積體電路封裝400貼合至積體電路封裝300以形成疊層封裝結構(package-on-package structure)。積體電路封裝400可以是記憶體封裝。可在將積體電路封裝300單體化之前或之 後將積體電路封裝400貼合至積體電路封裝300。積體電路封裝400包括基底402以及連接至基底402的一或多個晶粒404。在一些實施例中(未示出)，晶粒404的一或多個堆疊連接至基底402。基底402可由半導體材料(例如矽、鍺、金剛石等)製成。在一些實施例中，亦可使用化合物材料，例如矽鍺、碳化矽、鎵砷、砷化銦、磷化銦、碳化矽鍺、磷化鎵砷、磷化鎵銦、這些材料的組合等。另外，基底402可以是絕緣體上矽(silicon-on-insulator，SOI)基底。通常，SOI基底包含一層半導體材料，例如磊晶矽、鍺、矽鍺、SOI、絕緣體上矽鍺(silicon germanium on insulator，SGOI)或其組合。在一個替代實施例中，基底402基於絕緣芯，例如玻璃纖維加強型樹脂芯。一種示例性芯材料是玻璃纖維樹脂，例如FR4。芯材料的替代物包括雙馬來醯亞胺三嗪(BT)樹脂，或作為另外一種選擇，包括其他印刷電路板(PCB)材料或膜。構成膜(例如，味之素構成膜(ABF))或其他層壓體可用於基底402。
基底402可包括主動裝置及被動裝置(未示出)。熟習此項技術者將認識到，各種各樣的裝置(例如，電晶體、電容器、電阻器、這些的組合等)可用於產生積體電路封裝400的設計的結構要求及功能要求。可使用任何適合的方法形成裝置。基底402亦可包括金屬化層(未示出)及穿孔。金屬化層可形成於主動裝置及被動裝置之上且被設計成對各種裝置進行連接以形成功能電路系統。金屬化層可由介電質(例如，低介電常數介電材料)及導電材料(例如，銅)的交替層形成且可經由任何適合的製程(例如沉積、鑲嵌、雙鑲嵌等)形成，其中通孔對導電材料層進行內 連。在一些實施例中，基底402實質上不具有主動裝置及被動裝置。
基底402可在基底402的一側上具有結合墊406，以連接至導電連接件324。在一些實施例中，藉由在基底402的所述側上的介電層(未示出)中形成凹陷部(未示出)來形成結合墊406。凹陷部可被形成為使得結合墊406能夠嵌置至介電層中。在其他實施例中，當結合墊406可形成於介電層上時，省略凹陷部。在一些實施例中，結合墊406包括由銅、鈦、鎳、金、鈀等或其組合製成的薄晶種層(未示出)。可在薄晶種層之上沉積結合墊406的導電材料。可藉由電化學鍍覆製程、無電鍍覆製程、CVD、ALD、PVD等或其組合形成導電材料。在一實施例中，結合墊406的導電材料是銅、鎢、鋁、銀、金等或其組合。
在一實施例中，結合墊406是包括三個導電材料層(例如鈦層、銅層及鎳層)的UBM。舉例而言，結合墊406可由銅形成，可形成於鈦層(未示出)上且具有鎳飾面，所述鎳飾面可延長積體電路封裝400的儲放壽命，此在積體電路封裝400是記憶體裝置(例如，動態隨機存取記憶體(Dynamic Random Access Memory，DRAM)模組)時可特別有利。然而，熟習此項技術者應認識到，存在適合於形成結合墊406的諸多適合的材料及層的排列，例如鉻/鉻-銅合金/銅/金的排列、鈦/鈦鎢/銅的排列、或銅/鎳/金的排列。可用於結合墊406的任何適合的材料或材料層完全旨在包括於本申請案的範圍內。
在所說明的實施例中，晶粒404藉由導電凸塊連接至基底402，但可使用其他連接，例如打線結合。在一實施例中，晶粒 404是堆疊式記憶體晶粒。舉例而言，晶粒404可以是記憶體晶粒，例如低功率(low-power，LP)雙倍資料速率(double data rate，DDR)記憶體模組，例如LPDDR1、LPDDR2、LPDDR3、LPDDR4等。
可藉由模製材料410包封晶粒404及打線結合(當存在時)。可例如使用壓縮模製將模製材料410模製於晶粒404及打線結合上。在一些實施例中，模製材料410是模製化合物、聚合物、環氧樹脂、氧化矽填料材料等或其組合。可實行固化製程以將模製材料410固化；固化製程可以是熱固化、UV固化等或其組合。在一些實施例中，晶粒404隱埋於模製材料410中，且在將模製材料410固化之後，實行平坦化步驟(例如，研磨)以移除模製材料410的多餘部分且為積體電路封裝400提供實質上平坦的表面。
在形成積體電路封裝400之後，藉由導電連接件324將積體電路封裝400貼合至積體電路封裝300。可藉由對導電連接件324進行回焊來將導電連接件324連接至結合墊406。因此，晶粒404可經由導電連接件324、導通孔312及重佈線結構306、316電性耦合至積體電路封裝100。
在一些實施例中，在基底402的與晶粒404相對的一側上形成阻焊劑(未示出)。可將導電連接件324設置於阻焊劑中的開口中以連接至基底402中的導電特徵(例如，結合墊406)。阻焊劑可用於保護基底402的一些區域不受外部損壞。
在一些實施例中，導電連接件324在被回焊之前上面形成有環氧助焊劑(未示出)，其中在將積體電路封裝400貼合至重佈線結構306之後環氧助焊劑的環氧部分的至少一些保留下來。
在一些實施例中，底部填充膠(未示出)形成於重佈線結構306與基底402之間，從而環繞導電連接件324。底部填充膠可減小應力且保護對導電連接件324進行回焊所得的接頭。可在貼合積體電路封裝400之後藉由毛細流動過程形成底部填充膠，或可在貼合積體電路封裝400之前藉由適合的沉積方法形成底部填充膠。在形成有環氧助焊劑的實施例中，環氧助焊劑可用作底部填充膠。
然後，將疊層封裝結構倒置並使用導電連接件322貼合至封裝基底200。封裝基底200可類似於關於圖6所述的封裝基底200。舉例而言，封裝基底200可包括連接至導電連接件322的結合墊202。
圖17是根據一些其他實施例的積體電路封裝100及實施積體電路封裝100的系統的剖視圖。此實施例類似於關於圖16所述的實施例，但處理器裝置10與電源閘控裝置20以面對背方式直接結合，這類似於關於圖7所述的混合結合。因此，重佈線結構316的金屬化圖案320(例如，VDD線及VSS線)連接至晶粒連接件26，且藉由導通孔30電性耦合至處理器裝置10。
圖18是根據一些其他實施例的積體電路封裝100及實施積體電路封裝100的系統的剖視圖。此實施例類似於關於圖16所述的實施例，但省略了重佈線結構306、導通孔312及積體電路封裝400。
圖19是根據一些其他實施例的積體電路封裝100及實施積體電路封裝100的系統的剖視圖。此實施例類似於關於圖17所述的實施例，但省略了重佈線結構306、導通孔312及積體電路封裝400。
圖20、圖21、圖22、圖23及圖24是根據一些實施例的用於形成積體電路封裝500的製程期間的中間步驟的剖視圖。藉由堆疊各自包封於包封材料中的多個半導體裝置層來形成積體電路封裝500。說明將裝置封裝於一個封裝區502A中，但應瞭解，可同時形成任何數目的封裝區。將在後續處理中將封裝區502A單體化。經單體化的封裝組件可以是多重堆疊(multi-stacked，MUST)封裝。然後，將MUST封裝安裝至封裝基底。
在圖20中，提供載體基底502，且在載體基底502上形成釋放層504。可以與關於圖8所述的載體基底302類似的方式且由類似的材料形成載體基底502。可以與關於圖8所述的釋放層304類似的方式且由類似的材料形成釋放層504。然後，將與關於圖1所述的處理器裝置類似的處理器裝置10(例如，包括半導體基底12、內連結構14、晶粒連接件16及介電層18)放置於釋放層504上。
在圖21中，在處理器裝置10上及周圍形成包封體506。可以與關於圖12所述的包封體314類似的方式且由類似的材料形成包封體506。若需要，可對包封體506實行平坦化製程以暴露出晶粒連接件16。
在圖22中，在包封體506及處理器裝置10上形成重佈線結構510。可以與關於圖4所述的重佈線結構108類似的方式且 由類似的材料形成重佈線結構510。重佈線結構510包括介電層512及金屬化圖案514(有時被稱為重佈線層或重佈線線路)。可在重佈線結構510中形成較所說明的更多或更少的介電層512及金屬化圖案514。重佈線結構510的金屬化圖案514連接至處理器裝置10的晶粒連接件16。
在圖23中，形成延伸穿過重佈線結構510的最頂部介電層512的導通孔516。可以與關於圖10所述的導通孔312類似的方式且由類似的材料形成導通孔516。
將一或多個電源閘控裝置20放置於重佈線結構510(例如，最頂部介電層512)上。每一電源閘控裝置20可類似於關於圖1所述的電源閘控裝置(例如，包括半導體基底22、內連結構24、晶粒連接件26及介電層28)。電源閘控裝置20將經由MUST封裝的重佈線結構電性耦合至處理器裝置10，且因此不必形成導通孔30(參見圖1)。因此，可降低電源閘控裝置20的製造成本。
在圖24中，在電源閘控裝置20及導通孔516上及周圍形成包封體518。包封體518可以與關於圖12所述的包封體314類似的方式且由類似的材料形成。若需要，可對包封體518實行平坦化製程以暴露出導通孔516及晶粒連接件26。
圖25、圖26、圖27及圖28是根據一些實施例的用於形成實施積體電路封裝500的系統的製程期間的中間步驟的剖視圖。在此實施例中，積體電路封裝500被進一步處理成包括重佈線結構，且直接安裝至封裝基底。
在圖25中，在包封體518及電源閘控裝置20上形成重佈線結構520。可以與關於圖4所述的重佈線結構108類似的方式 且由類似的材料形成重佈線結構520。重佈線結構520包括介電層522及金屬化圖案524(有時被稱為重佈線層或重佈線線路)。可在重佈線結構520中形成較所說明的更多或更少的介電層522及金屬化圖案524。重佈線結構520的金屬化圖案524連接至導通孔516及電源閘控裝置20的晶粒連接件26。因此，處理器裝置10經由導通孔514及重佈線結構510的金屬化圖案524電性耦合至重佈線結構520的金屬化圖案524。
重佈線結構520的金屬化圖案524包括電性耦合至電源閘控裝置20的輸入端子的電力供應源(VDD)線、電力供應接地(VSS)線及資料訊號線。重佈線結構520的金屬化圖案524亦包括將導通孔516電性耦合至電源閘控裝置20的輸出端子的線。因此，處理器裝置10的電路區塊的第一子集經由電源閘控裝置20及導通孔516電性耦合至VDD線及VSS線。因此，可藉由電源閘控裝置20接通及關斷電路區塊的第一子集。處理器裝置10的電路區塊的第二子集繞過電源閘控裝置20而經由導通孔516電性耦合至VDD線及VSS線。因此，電路區塊的第二子集永久地電性耦合至電源及接地。電路區塊的第二子集可以是始終接通的必要電路區塊。資料訊號線電性耦合至處理器裝置10及電源閘控裝置20。處理器裝置10可經由資料訊號線將控制訊號發送至電源閘控裝置20，且可經由資料訊號線自電源閘控裝置20接收電源/接地訊號。
在圖26中，形成連接至重佈線結構520的金屬化圖案524的導電連接件526。可以與關於圖5所述的導電連接件114類似的方式且由類似的材料形成導電連接件526。
在圖27中，實行載體基底剝離以將載體基底502自重佈線結構510(例如，最底部介電層512)剝除(剝離)。根據一些實施例，剝離包括將光(例如，雷射光或UV光)投射於釋放層504上，以使得釋放層504在光的熱量下分解且可移除載體基底502。然後，可將結構倒置並放置於例如條帶上。
在圖28中，藉由沿著切割道區(例如，在封裝區502A周圍)進行鋸切來實行單體化製程。單體化製程包括鋸切重佈線結構510、520及包封體506、518。單體化製程將封裝區502A與鄰近封裝區(未示出)分離以形成積體電路封裝500。在單體化之後，重佈線結構510、520(例如，介電層512、522)與包封體506、518在側向上毗連。
然後，使用導電連接件526將積體電路封裝500貼合至封裝基底200。封裝基底200可類似於關於圖6所述的封裝基底200。舉例而言，封裝基底200可包括連接至導電連接件526的結合墊202。
圖29、圖30、圖31、圖32、圖33及圖34是根據一些實施例的用於形成實施積體電路封裝500的系統的製程期間的中間步驟的剖視圖。在此實施例中，將積體電路封裝500單體化並包括於封裝組件中。說明將裝置封裝於一個封裝區602A中，但應瞭解，可同時形成任何數目的封裝區。將在後續處理中將封裝區602A單體化。經單體化的封裝組件可以是扇出型封裝，例如積體扇出型(InFO)封裝。然後，將扇出型封裝安裝至封裝基底。
在圖29中，提供載體基底602，且在載體基底602上形成釋放層604。可以與關於圖8所述的載體基底302類似的方式且 由類似的材料形成載體基底602。可以與關於圖8所述的釋放層304類似的方式且由類似的材料形成釋放層604。
可在釋放層604上形成重佈線結構606。可以與關於圖4所述的重佈線結構108類似的方式且由類似的材料形成重佈線結構606。重佈線結構606包括介電層608及金屬化圖案610(有時被稱為重佈線層或重佈線線路)。可在重佈線結構606中形成較所說明的更多或更少的介電層608及金屬化圖案610。重佈線結構606是可選的。在一些實施例中，在釋放層604上形成不包括金屬化圖案的介電層來代替重佈線結構606。
在圖30中，形成延伸穿過重佈線結構606的最頂部介電層608的導通孔612。因此，導通孔612連接至重佈線結構606的金屬化圖案610。可以與關於圖10所述的導通孔312類似的方式且由類似的材料形成導通孔612。導通孔612是可選的，且可被省略。舉例而言，在省略重佈線結構606的實施例中可(或可不)省略導通孔612。
將經單體化的積體電路封裝500鄰近於導通孔612放置於重佈線結構606(例如，最頂部介電層608)上。為形成經單體化的積體電路封裝500，獲得與關於圖24所述的中間結構類似的中間結構。實行載體基底剝離以將中間結構自載體基底502(參見圖24)剝除(剝離)。然後，藉由沿著切割道區(例如，在封裝區502A(參見圖24)周圍)進行鋸切來實行單體化製程。單體化製程包括鋸切重佈線結構510及包封體506、518。單體化製程將封裝區502A與鄰近封裝區(未示出)分離以形成積體電路封裝500。在單體化之後，重佈線結構510(例如，介電層512)與包封體506、 518在側向上毗連。
在圖31中，在導通孔612及積體電路封裝500上及周圍形成包封體614。可以與關於圖12所述的包封體314類似的方式且由類似的材料形成包封體614。在一些實施例中，包封體614不同於包封體506、518且包含與包封體506、518不同的材料。若需要，可對包封體614實行平坦化製程以暴露出晶粒連接件26及導通孔516、612。
在圖32中，在包封體614、導通孔612及積體電路封裝500上形成重佈線結構616。可以與關於圖4所述的重佈線結構108類似的方式且由類似的材料形成重佈線結構616。重佈線結構616包括介電層618及金屬化圖案620(有時被稱為重佈線層或重佈線線路)。可在重佈線結構616中形成較所說明的更多或更少的介電層618及金屬化圖案620。重佈線結構616的金屬化圖案620連接至晶粒連接件26及導通孔516、612。重佈線結構616的金屬化圖案620包括電力供應源(VDD)線、電力供應接地(VSS)線及資料訊號線，電力供應源(VDD)線、電力供應接地(VSS)線及資料訊號線以與關於圖4所述的方式類似的方式電性耦合至處理器裝置10及電源閘控裝置20。
形成連接至重佈線結構616的金屬化圖案620的導電連接件622。可以與關於圖5所述的導電連接件114類似的方式且由類似的材料形成導電連接件622。舉例而言，可在重佈線結構616的UBM上形成導電連接件622。
在圖33中，實行載體基底剝離以將載體基底602自重佈線結構606(例如，最底部介電層608)剝除(剝離)。根據一 些實施例，剝離包括將光(例如，雷射光或UV光)投射於釋放層604上，以使得釋放層604在光的熱量下分解且可移除載體基底602。然後，可將結構倒置並放置於例如條帶上。
此外，形成重佈線結構606的最底部介電層608的導電連接件624。可穿過重佈線結構606的最底部介電層608形成開口，從而暴露出金屬化圖案610的部分。可例如使用雷射鑽孔、蝕刻等形成開口。在開口中形成導電連接件624，且導電連接件624連接至金屬化圖案610的暴露部分。可以與關於圖5所述的導電連接件114類似的方式且由類似的材料形成導電連接件624。
在圖34中，藉由沿著切割道區(例如，在封裝區602A周圍)進行鋸切來實行單體化製程。單體化製程包括鋸切重佈線結構606、616及包封體614。單體化製程將封裝區602A與鄰近封裝區(未示出)分離以形成積體電路封裝600。在單體化之後，重佈線結構606、616(例如，介電層608、618)與包封體614在側向上毗連。
可將另一積體電路封裝400貼合至積體電路封裝600以形成疊層封裝結構。積體電路封裝400可在積體電路封裝600被單體化之前或之後貼合至積體電路封裝600。積體電路封裝400可類似於關於圖16所述的積體電路封裝400。舉例而言，積體電路封裝400可包括連接至導電連接件624的結合墊406。
然後，將疊層封裝結構倒置並使用導電連接件622貼合至封裝基底200。封裝基底200可類似於關於圖6所述的封裝基底200。舉例而言，封裝基底200可包括連接至導電連接件622的結合墊202。
圖35、圖36、圖37、圖38、圖39及圖40是根據一些其他實施例的用於形成積體電路封裝700的製程期間的中間步驟的剖視圖。藉由將處理器裝置10及電源閘控裝置20單體化並將處理器裝置10及電源閘控裝置20包括於封裝組件中來形成積體電路封裝700。說明將裝置封裝於一個封裝區702A中，但應瞭解，可同時形成任何數目的封裝區。將在後續處理中將封裝區702A單體化。經單體化的封裝組件可以是扇出型封裝，例如積體扇出型(InFO)封裝。然後，將扇出型封裝安裝至封裝基底。
在圖35中，提供載體基底702，且在載體基底702上形成釋放層704。可以與關於圖8所述的載體基底302類似的方式且由類似的材料形成載體基底702。可以與關於圖8所述的釋放層304類似的方式且由類似的材料形成釋放層704。然後，在釋放層704上形成導通孔706，且導通孔706遠離釋放層704延伸。可以與關於圖10所述的導通孔312類似的方式且由類似的材料形成導通孔706。
然後，將與關於圖1所述的處理器裝置類似的處理器裝置10(例如，包括半導體基底12、內連結構14、晶粒連接件16及介電層18)鄰近於導通孔706而放置於釋放層704上。在此實施例中，處理器裝置10更包括被形成為延伸穿過半導體基底12的導通孔708。導通孔708電性耦合至內連結構14的金屬化圖案。
在圖36中，在導通孔706及處理器裝置10上及周圍形成包封體710。可以與關於圖12所述的包封體314類似的方式且由類似的材料形成包封體710。若需要，可對包封體710實行平坦化製程以暴露出晶粒連接件16及導通孔706。
在圖37中，在包封體710、導通孔706及處理器裝置10上形成重佈線結構712。可以與關於圖4所述的重佈線結構108類似的方式且由類似的材料形成重佈線結構712。重佈線結構712包括介電層714及金屬化圖案716(有時被稱為重佈線層或重佈線線路)。可在重佈線結構712中形成較所說明的更多或更少的介電層714及金屬化圖案716。重佈線結構712的金屬化圖案716連接至晶粒連接件16及導通孔706。
形成連接至重佈線結構712的金屬化圖案716的導電連接件718。可以與關於圖5所述的導電連接件114類似的方式且由類似的材料形成導電連接件718。舉例而言，可在重佈線結構712的UBM上形成導電連接件718。
在圖38中，實行載體基底剝離以將載體基底702自處理器裝置10剝除(剝離)。根據一些實施例，剝離包括將光(例如，雷射光或UV光)投射於釋放層704上，以使得釋放層704在光的熱量下分解且可移除載體基底702。然後，可將結構倒置並放置於例如條帶上。
在包封體710、導通孔706及處理器裝置10上形成重佈線結構720。可以與關於圖4所述的重佈線結構108類似的方式且由類似的材料形成重佈線結構720。重佈線結構720包括介電層722及金屬化圖案724(有時被稱為重佈線層或重佈線線路)。可在重佈線結構720中形成較所說明的更多或更少的介電層722及金屬化圖案724。重佈線結構720的金屬化圖案724連接至導通孔706、708。
在圖39中，利用導電連接件726將與關於圖1所述的 電源閘控裝置類似的電源閘控裝置20(例如，包括半導體基底22、內連結構24及晶粒連接件26)貼合至重佈線結構720。電源閘控裝置20將經由重佈線結構712、720(例如，金屬化圖案716、724)電性耦合至處理器裝置10，且因此不必形成導通孔30(參見圖1)。此外，電源閘控裝置20中亦可省略介電層28(參見圖1)。因此，可降低電源閘控裝置20的製造成本。
在一些實施例中，電源閘控裝置20貼合至導電凸塊，例如微凸塊。舉例而言，晶粒連接件728可被形成為延伸穿過重佈線結構720的最底部介電層722。以形成晶粒連接件728作為實例，可穿過重佈線結構720的最底部介電層722形成開口，從而暴露出金屬化圖案724的部分。可例如使用雷射鑽孔、蝕刻等形成開口。可在開口中鍍覆或沉積晶粒連接件728，且晶粒連接件728連接至金屬化圖案724的暴露部分。形成導電連接件726，從而連接相應的成對晶粒連接件26、728。可以與關於圖5所述的導電連接件114類似的方式且由類似的材料形成導電連接件726。在此實施例中，處理器裝置10的後側面向電源閘控裝置20的前側。
重佈線結構712的金屬化圖案716包括電力供應源(VDD)線、電力供應接地(VSS)線及資料訊號線。VDD線及VSS線的第一子集連接至處理器裝置10的晶粒連接件16。因此，處理器裝置10的電路區塊的第一子集繞過電源閘控裝置20而電性連接至重佈線結構712的VDD線及VSS線。因此，電路區塊的第一子集永久地電性耦合至電源及接地。電路區塊的第一子集可以是始終接通的必要電路區塊。所述VDD線及VSS線的第二子集經由導通孔706及重佈線結構720的金屬化圖案724電性耦合至電源 閘控裝置20的輸入端子。重佈線結構720的金屬化圖案724亦包括將處理器裝置10電性耦合至電源閘控裝置20的輸出端子的線。因此，處理器裝置10的電路區塊的第二子集經由電源閘控裝置20、重佈線結構720及導通孔706、708電性耦合至VDD線及VSS線。因此，電源閘控裝置20可接通及關斷電路區塊的第二子集。在一些實施例中，導通孔708中的一些導通孔連接至重佈線結構720的資料訊號線。資料訊號線電性耦合至處理器裝置10及電源閘控裝置20。處理器裝置10可經由資料訊號線將控制訊號發送至電源閘控裝置20，且可經由資料訊號線自電源閘控裝置20接收電源/接地訊號。
然後，在電源閘控裝置20與重佈線結構720之間形成底部填充膠730，從而環繞導電連接件726。可在貼合電源閘控裝置20之後藉由毛細流動過程形成底部填充膠730，或可在貼合電源閘控裝置20之前藉由適合的沉積方法形成底部填充膠730。
在電源閘控裝置20及底部填充膠730上及周圍形成包封體732。可以與關於圖12所述的包封體314類似的方式且由類似的材料形成包封體732。若需要，可對包封體710實行平坦化製程以暴露出電源閘控裝置20。
在圖40中，藉由沿著切割道區(例如，在封裝區702A周圍)進行鋸切來實行單體化製程。單體化製程包括鋸切重佈線結構712、720及包封體710、732。單體化製程將封裝區702A與鄰近封裝區(未示出)分離以形成積體電路封裝700。在單體化之後，重佈線結構712、720(例如，介電層714、722)與包封體710、732在側向上毗連。
然後，使用導電連接件718將積體電路封裝700貼合至封裝基底200。封裝基底200可類似於關於圖6所述的封裝基底200。舉例而言，封裝基底200可包括連接至導電連接件718的結合墊202。
圖41是根據一些其他實施例的積體電路封裝700的剖視圖。此實施例類似於關於圖40所述的實施例，但處理器裝置10的前側面向電源閘控裝置20的前側。因此，重佈線結構720的金屬化圖案724(例如，VDD線及VSS線)直接連接至晶粒連接件16。因此，導通孔706、708用於資料訊號線。
實施例可達成許多優點。形成電源閘控裝置20與處理器裝置10分離的積體電路封裝使得電源閘控裝置20能夠形成有較處理器裝置10大的主動裝置。因此，可使用技術節點大的開關電晶體來進行電力輸送。技術節點大的開關電晶體可適應較大的衝擊電流且在處理器裝置10的電路區塊接通時具有較小的電壓降(例如，IR降)，且亦具有較小的電力洩漏。因此，可減小所得的積體電路封裝的功耗。
亦可包括其他特徵及製程。舉例而言，可包括測試結構以輔助對三維(three-dimensional，3D)封裝或三維積體電路(three-dimensional integrated circuit，3DIC)裝置進行驗證測試。所述測試結構可包括例如形成於重佈線層中或基底上的測試墊(test pad)，以使得能對3D封裝或3DIC裝置進行測試、使用探針及/或探針卡(probe card)等。可對中間結構以及最終結構實行驗證測試。另外，本文中所揭露的結構及方法可與包含對已知良好晶粒(known good die)進行中間驗證的測試方法結合使用以提 高良率並降低成本。
在一實施例中，一種裝置包括：處理器晶粒，包括電路區塊，所述電路區塊包括具有第一技術節點的主動裝置；電源閘控晶粒，包括具有第二技術節點的功率半導體裝置，所述第二技術節點大於所述第一技術節點；以及第一重佈線結構，包括第一金屬化圖案，所述第一金屬化圖案包括電力供應源線及電力供應接地線，其中所述電路區塊的第一子集經由所述功率半導體裝置電性耦合至所述電力供應源線及所述電力供應接地線，且所述電路區塊的第二子集永久地電性耦合至所述電力供應源線及所述電力供應接地線。
在一些實施例中，所述裝置更包括：封裝基底；以及導電連接件，連接至所述封裝基底及所述第一重佈線結構的所述第一金屬化圖案。在所述裝置的一些實施例中，所述處理器晶粒與所述電源閘控晶粒藉由介電質對介電質結合及藉由金屬對金屬結合直接結合，且所述裝置更包括：導通孔，連接至所述處理器晶粒及所述第一重佈線結構的所述第一金屬化圖案；以及介電層，環繞所述導通孔及所述電源閘控晶粒，所述介電層及所述電源閘控晶粒各自設置於所述第一重佈線結構與所述處理器晶粒之間，所述第一重佈線結構、所述介電層及所述處理器晶粒在側向上毗連。在所述裝置的一些實施例中，所述處理器晶粒與所述電源閘控晶粒藉由介電質對介電質結合及藉由金屬對金屬結合直接結合，且所述裝置更包括：導通孔，連接至所述處理器晶粒及所述第一重佈線結構的所述第一金屬化圖案；介電層，環繞所述導通孔及所述電源閘控晶粒，所述介電層及所述電源閘控晶粒各自設 置於所述第一重佈線結構與所述處理器晶粒之間，所述介電層與所述處理器晶粒在側向上毗連；以及包封體，環繞所述處理器晶粒及所述介電層，所述包封體與所述第一重佈線結構在側向上毗連。在所述裝置的一些實施例中，所述第一重佈線結構的所述第一金屬化圖案連接至所述電源閘控晶粒，且所述裝置更包括：第二重佈線結構，設置於所述處理器晶粒與所述電源閘控晶粒之間，所述第二重佈線結構包括第二金屬化圖案，所述處理器晶粒連接至所述第二金屬化圖案；第一包封體，環繞所述電源閘控晶粒；導通孔，延伸穿過所述第一包封體，所述導通孔連接至所述第一重佈線結構的所述第一金屬化圖案及所述第二重佈線結構的所述第二金屬化圖案；以及第二包封體，環繞所述處理器晶粒，所述第二包封體、所述第二重佈線結構、所述第一包封體及所述第一重佈線結構在側向上毗連。在所述裝置的一些實施例中，所述第一重佈線結構的所述第一金屬化圖案連接至所述電源閘控晶粒，且所述裝置更包括：第二重佈線結構，設置於所述處理器晶粒與所述電源閘控晶粒之間，所述第二重佈線結構包括第二金屬化圖案，所述處理器晶粒連接至所述第二金屬化圖案；第一包封體，環繞所述電源閘控晶粒；導通孔，延伸穿過所述第一包封體，所述導通孔連接至所述第一重佈線結構的所述第一金屬化圖案及所述第二重佈線結構的所述第二金屬化圖案；第二包封體，環繞所述處理器晶粒，所述第二包封體、所述第二重佈線結構及所述第一包封體在側向上毗連；以及第三包封體，環繞所述第二包封體、所述第二重佈線結構及所述第一包封體，所述第三包封體與所述第一重佈線結構在側向上毗連。在所述裝置的一些實施例 中，所述第一重佈線結構的所述第一金屬化圖案連接至所述處理器晶粒，且所述裝置更包括：第二重佈線結構，設置於所述處理器晶粒與所述電源閘控晶粒之間，所述第二重佈線結構包括第二金屬化圖案，所述第二金屬化圖案連接至所述處理器晶粒及所述電源閘控晶粒；第一包封體，環繞所述處理器晶粒；導通孔，延伸穿過所述第一包封體，所述導通孔連接至所述第一重佈線結構的所述第一金屬化圖案及所述第二重佈線結構的所述第二金屬化圖案；以及第二包封體，環繞所述電源閘控晶粒，所述第二包封體、所述第一包封體、所述第二重佈線結構及所述第一重佈線結構在側向上毗連。在所述裝置的一些實施例中，所述電源閘控晶粒能夠在運行時間操作以自所述處理器晶粒接收控制訊號，且因應於所述控制訊號而將所述處理器晶粒的所述電路區塊的所述第一子集接通或關斷。在所述裝置的一些實施例中，所述處理器晶粒的所述主動裝置是互補金屬氧化物半導體裝置，且所述電源閘控晶粒的所述功率半導體裝置是絕緣閘雙極電晶體裝置或雙擴散金屬氧化物半導體裝置。
在一實施例中，一種裝置包括：處理器晶粒，包括電路區塊，所述電路區塊包括具有第一技術節點的主動裝置；電源閘控晶粒，藉由介電質對介電質結合及藉由金屬對金屬結合直接結合至所述處理器晶粒，所述電源閘控晶粒包括具有第二技術節點的功率半導體裝置，所述第二技術節點大於所述第一技術節點，所述功率半導體裝置電性耦合至所述電路區塊的第一子集；介電層，環繞所述電源閘控晶粒；第一導通孔，延伸穿過所述介電層，所述第一導通孔電性耦合至所述電路區塊的第二子集，以及第一 重佈線結構，包括第一金屬化圖案，所述第一金屬化圖案包括連接至所述第一導通孔及所述電源閘控晶粒的電力供應源線；封裝基底；以及第一導電連接件，將所述封裝基底連接至所述第一重佈線結構的所述第一金屬化圖案。
在所述裝置的一些實施例中，所述處理器晶粒、所述介電層及所述第一重佈線結構在側向上毗連。在所述裝置的一些實施例中，所述處理器晶粒與所述介電層在側向上毗連，且所述裝置更包括：包封體，環繞所述處理器晶粒及所述介電層，所述包封體與所述第一重佈線結構在側向上毗連。在一些實施例中，所述裝置更包括：第二重佈線結構，包括第二金屬化圖案，所述包封體設置於所述第一重佈線結構與所述第二重佈線結構之間；第二導通孔，延伸穿過所述包封體，所述第二導通孔連接至所述第二重佈線結構的所述第二金屬化圖案及所述第一重佈線結構的所述第一金屬化圖案；記憶體封裝；以及第二導電連接件，將所述記憶體封裝連接至所述第二重佈線結構的所述第二金屬化圖案。在所述裝置的一些實施例中，所述處理器晶粒的所述主動裝置是互補金屬氧化物半導體裝置，且所述電源閘控晶粒的所述功率半導體裝置是絕緣閘雙極電晶體裝置或雙擴散金屬氧化物半導體裝置。在所述裝置的一些實施例中，所述處理器晶粒與所述電源閘控晶粒以面對面方式直接結合。在所述裝置的一些實施例中，所述處理器晶粒與所述電源閘控晶粒以面對背方式直接結合。
在一實施例中，一種方法包括：將電源閘控晶粒結合至晶圓，所述晶圓包括處理器晶粒，所述電源閘控晶粒與所述處理器晶粒包括間距不同的主動裝置，所述電源閘控晶粒包括第一導 通孔；在所述電源閘控晶粒周圍且在所述晶圓上形成介電層；在第一介電層中圖案化出開口，所述開口暴露出所述處理器晶粒的晶粒連接件；將導電材料鍍覆於所述開口中及所述晶粒連接件上；將所述導電材料平坦化以在所述開口中形成第二導通孔，所述平坦化暴露出所述電源閘控晶粒的所述第一導通孔；以及鋸切所述介電層及所述晶圓以將所述處理器晶粒單體化。
在一些實施例中，在所述鋸切之前，所述方法更包括：在所述電源閘控晶粒、所述介電層及所述第二導通孔上形成重佈線結構，所述鋸切包括鋸切所述重佈線結構。在一些實施例中，在所述鋸切之後，所述方法更包括：利用包封體包封所述電源閘控晶粒及所述介電層；以及在所述包封體、所述電源閘控晶粒、所述介電層及所述第二導通孔上形成重佈線結構。在所述方法的一些實施例中，所述電源閘控晶粒包括技術節點較所述處理器晶粒大的主動裝置。
前述內容概述了數個實施例的特徵，以使熟習此項技術者可更佳地理解本揭露的各個態樣。熟習此項技術者應瞭解，他們可容易地使用本揭露作為設計或修改其他製程及結構的基礎來施行與本文中所介紹的實施例相同的目的及/或達成與本文中所介紹的實施例相同的優點。熟習此項技術者亦應意識到，這些等效構造並不背離本揭露的精神及範疇，而且他們可在不背離本揭露的精神及範疇的情況下對其作出各種改變、代替及變更。
100、300、400:積體電路封裝
200:封裝基底
202:結合墊
306、316:重佈線結構
312:導通孔
314:包封體
322、324:導電連接件
402:基底
404:晶粒
406:結合墊
410:模製材料

Claims (7)

  1. 一種積體電路封裝，包括：處理器晶粒，包括電路區塊，所述電路區塊包括具有第一技術節點的主動裝置；電源閘控晶粒，包括具有第二技術節點的功率半導體裝置，所述第二技術節點大於所述第一技術節點；以及第一重佈線結構，包括第一金屬化圖案，所述第一金屬化圖案包括電力供應源線及電力供應接地線，其中所述電路區塊的第一子集經由所述功率半導體裝置電性耦合至所述電力供應源線及所述電力供應接地線，且所述電路區塊的第二子集永久地電性耦合至所述電力供應源線及所述電力供應接地線，其中所述處理器晶粒與所述電源閘控晶粒藉由介電質對介電質結合及藉由金屬對金屬結合直接結合，且所述積體電路封裝更包括：導通孔，連接至所述處理器晶粒及所述第一重佈線結構的所述第一金屬化圖案；以及介電層，環繞所述導通孔及所述電源閘控晶粒，所述介電層及所述電源閘控晶粒各自設置於所述第一重佈線結構與所述處理器晶粒之間，所述第一重佈線結構、所述介電層及所述處理器晶粒在側向上毗連。
  2. 一種積體電路封裝，包括：處理器晶粒，包括電路區塊，所述電路區塊包括具有第一技術節點的主動裝置；電源閘控晶粒，包括具有第二技術節點的功率半導體裝置， 所述第二技術節點大於所述第一技術節點；以及第一重佈線結構，包括第一金屬化圖案，所述第一金屬化圖案包括電力供應源線及電力供應接地線，其中所述電路區塊的第一子集經由所述功率半導體裝置電性耦合至所述電力供應源線及所述電力供應接地線，且所述電路區塊的第二子集永久地電性耦合至所述電力供應源線及所述電力供應接地線，其中所述處理器晶粒與所述電源閘控晶粒藉由介電質對介電質結合及藉由金屬對金屬結合直接結合，且所述積體電路封裝更包括：導通孔，連接至所述處理器晶粒及所述第一重佈線結構的所述第一金屬化圖案；介電層，環繞所述導通孔及所述電源閘控晶粒，所述介電層及所述電源閘控晶粒各自設置於所述第一重佈線結構與所述處理器晶粒之間，所述介電層與所述處理器晶粒在側向上毗連；以及包封體，環繞所述處理器晶粒及所述介電層，所述包封體與所述第一重佈線結構在側向上毗連。
  3. 一種積體電路封裝，包括：處理器晶粒，包括電路區塊，所述電路區塊包括具有第一技術節點的主動裝置；電源閘控晶粒，包括具有第二技術節點的功率半導體裝置，所述第二技術節點大於所述第一技術節點；以及第一重佈線結構，包括第一金屬化圖案，所述第一金屬化圖案包括電力供應源線及電力供應接地線，其中所述電路區塊的第一子集經由所述功率半導體裝置電性耦合至所述電力供應源線及所述 電力供應接地線，且所述電路區塊的第二子集永久地電性耦合至所述電力供應源線及所述電力供應接地線，其中所述第一重佈線結構的所述第一金屬化圖案連接至所述電源閘控晶粒，且所述積體電路封裝更包括：第二重佈線結構，設置於所述處理器晶粒與所述電源閘控晶粒之間，所述第二重佈線結構包括第二金屬化圖案，所述處理器晶粒連接至所述第二金屬化圖案；第一包封體，環繞所述電源閘控晶粒；導通孔，延伸穿過所述第一包封體，所述導通孔連接至所述第一重佈線結構的所述第一金屬化圖案及所述第二重佈線結構的所述第二金屬化圖案；以及第二包封體，環繞所述處理器晶粒，所述第二包封體、所述第二重佈線結構、所述第一包封體及所述第一重佈線結構在側向上毗連。
  4. 一種積體電路封裝，包括：處理器晶粒，包括電路區塊，所述電路區塊包括具有第一技術節點的主動裝置；電源閘控晶粒，包括具有第二技術節點的功率半導體裝置，所述第二技術節點大於所述第一技術節點；以及第一重佈線結構，包括第一金屬化圖案，所述第一金屬化圖案包括電力供應源線及電力供應接地線，其中所述電路區塊的第一子集經由所述功率半導體裝置電性耦合至所述電力供應源線及所述電力供應接地線，且所述電路區塊的第二子集永久地電性耦合至所述電力供應源線及所述電力供應接地線， 其中所述第一重佈線結構的所述第一金屬化圖案連接至所述電源閘控晶粒，且所述積體電路封裝更包括：第二重佈線結構，設置於所述處理器晶粒與所述電源閘控晶粒之間，所述第二重佈線結構包括第二金屬化圖案，所述處理器晶粒連接至所述第二金屬化圖案；第一包封體，環繞所述電源閘控晶粒；導通孔，延伸穿過所述第一包封體，所述導通孔連接至所述第一重佈線結構的所述第一金屬化圖案及所述第二重佈線結構的所述第二金屬化圖案；第二包封體，環繞所述處理器晶粒，所述第二包封體、所述第二重佈線結構及所述第一包封體在側向上毗連；以及第三包封體，環繞所述第二包封體、所述第二重佈線結構及所述第一包封體，所述第三包封體與所述第一重佈線結構在側向上毗連。
  5. 一種積體電路封裝，包括：處理器晶粒，包括電路區塊，所述電路區塊包括具有第一技術節點的主動裝置；電源閘控晶粒，包括具有第二技術節點的功率半導體裝置，所述第二技術節點大於所述第一技術節點；以及第一重佈線結構，包括第一金屬化圖案，所述第一金屬化圖案包括電力供應源線及電力供應接地線，其中所述電路區塊的第一子集經由所述功率半導體裝置電性耦合至所述電力供應源線及所述電力供應接地線，且所述電路區塊的第二子集永久地電性耦合至所述電力供應源線及所述電力供應接地線， 其中所述第一重佈線結構的所述第一金屬化圖案連接至所述處理器晶粒，且所述積體電路封裝更包括：第二重佈線結構，設置於所述處理器晶粒與所述電源閘控晶粒之間，所述第二重佈線結構包括第二金屬化圖案，所述第二金屬化圖案連接至所述處理器晶粒及所述電源閘控晶粒；第一包封體，環繞所述處理器晶粒；導通孔，延伸穿過所述第一包封體，所述導通孔連接至所述第一重佈線結構的所述第一金屬化圖案及所述第二重佈線結構的所述第二金屬化圖案；以及第二包封體，環繞所述電源閘控晶粒，所述第二包封體、所述第一包封體、所述第二重佈線結構及所述第一重佈線結構在側向上毗連。
  6. 一種積體電路封裝，包括：處理器晶粒，包括電路區塊，所述電路區塊包括具有第一技術節點的主動裝置；電源閘控晶粒，藉由介電質對介電質結合及藉由金屬對金屬結合直接結合至所述處理器晶粒，所述電源閘控晶粒包括具有第二技術節點的功率半導體裝置，所述第二技術節點大於所述第一技術節點，所述功率半導體裝置電性耦合至所述電路區塊的第一子集；介電層，環繞所述電源閘控晶粒；第一導通孔，延伸穿過所述介電層，所述第一導通孔電性耦合至所述電路區塊的第二子集；以及第一重佈線結構，包括第一金屬化圖案，所述第一金屬化圖 案包括連接至所述第一導通孔及所述電源閘控晶粒的電力供應源線；封裝基底；以及第一導電連接件，將所述封裝基底連接至所述第一重佈線結構的所述第一金屬化圖案，其中所述處理器晶粒與所述介電層在側向上毗連，且所述積體電路封裝更包括：包封體，環繞所述處理器晶粒及所述介電層，所述包封體與所述第一重佈線結構在側向上毗連。
  7. 一種積體電路封裝的形成方法，包括：將電源閘控晶粒結合至晶圓，所述晶圓包括處理器晶粒，所述電源閘控晶粒與所述處理器晶粒包括間距不同的主動裝置，所述電源閘控晶粒包括第一導通孔；在所述電源閘控晶粒周圍且在所述晶圓上形成介電層；在第一介電層中圖案化出開口，所述開口暴露出所述處理器晶粒的晶粒連接件；將導電材料鍍覆於所述開口中及所述晶粒連接件上；將所述導電材料平坦化以在所述開口中形成第二導通孔，所述平坦化暴露出所述電源閘控晶粒的所述第一導通孔；以及鋸切所述介電層及所述晶圓以將所述處理器晶粒單體化。
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