TWI746306B - 封裝結構及其形成方法 - Google Patents

封裝結構及其形成方法 Download PDF

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TWI746306B
TWI746306B TW109143593A TW109143593A TWI746306B TW I746306 B TWI746306 B TW I746306B TW 109143593 A TW109143593 A TW 109143593A TW 109143593 A TW109143593 A TW 109143593A TW I746306 B TWI746306 B TW I746306B
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Taiwan
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die
integrated circuit
circuit die
connector
dielectric layer
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TW109143593A
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TW202125746A (zh
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余振華
劉仁福
曾明鴻
江宗憲
林彥良
黃子松
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台灣積體電路製造股份有限公司
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Abstract

在實施例中，一種封裝結構包括：第一積體電路晶粒，包括第一晶粒連接件；第一介電層，位於第一晶粒連接件上；第一導通孔，延伸穿過第一介電層，第一導通孔連接至第一晶粒連接件的第一子集；第二積體電路晶粒，利用第一可回焊連接件結合至第一晶粒連接件的第二子集；第一包封體，環繞第二積體電路晶粒及第一導通孔，第一包封體與第一積體電路晶粒在側向上毗連；第二導通孔，與第一積體電路晶粒相鄰；第二包封體，環繞第二導通孔、第一包封體及第一積體電路晶粒；以及第一重佈線結構，包括第一重佈線線，第一重佈線線連接至第一導通孔及第二導通孔。

Description

封裝結構及其形成方法
本發明實施例是有關於一種封裝結構及其形成方法。
隨著半導體技術不斷演進，積體電路晶粒變得愈來愈小。此外，更多的功能被整合至晶粒中。因此，晶粒所需要的輸入/輸出(input/output，I/O)接墊的數目增加，而可用於I/O接墊的面積減小。I/O接墊的密度隨著時間推移迅速上升，進而增大了進行晶粒封裝的難度。一些應用要求積體電路晶粒具有更強大的平行處理能力。封裝技術可用於多個晶粒的整合，從而使得達成更大程度的平行處理能力。
在一些封裝技術中，積體電路晶粒在被封裝之前自晶圓單體化。此種封裝技術的有利特徵是可形成扇出型封裝(fan-out package)，所述扇出型封裝使得晶粒上的I/O接墊能夠被重佈線至更大的面積。因此可增加晶粒表面上的I/O接墊的數目。
本申請的一些實施例提供一種封裝結構，包括：第一積體 電路晶粒，包括第一晶粒連接件；第一介電層，位於所述第一晶粒連接件上；第一導通孔，延伸穿過所述第一介電層，所述第一導通孔連接至所述第一晶粒連接件的第一子集；第二積體電路晶粒，利用第一可回焊連接件結合至所述第一晶粒連接件的第二子集；第一包封體，環繞所述第二積體電路晶粒及所述第一導通孔，所述第一包封體與所述第一積體電路晶粒在側向上毗連；第二導通孔，與所述第一積體電路晶粒相鄰；第二包封體，環繞所述第二導通孔、所述第一包封體及所述第一積體電路晶粒；以及第一重佈線結構，包括第一重佈線線，所述第一重佈線線連接至所述第一導通孔及所述第二導通孔。
此外，本申請的其他實施例提供一種封裝結構，包括：第一積體電路晶粒，包括鈍化後內連線(PPI)；介電層，位於所述鈍化後內連線上；第一導通孔，延伸穿過所述介電層，所述第一導通孔連接至所述鈍化後內連線；第二積體電路晶粒，包括半導體基底及晶粒連接件，所述半導體基底利用黏合劑結合至所述介電層；第一包封體，環繞所述第二積體電路晶粒及所述第一導通孔，所述第一包封體與所述第一積體電路晶粒在側向上毗連；第二導通孔，與所述第一積體電路晶粒相鄰；第二包封體，環繞所述第二導通孔、所述第一包封體及所述第一積體電路晶粒；以及第一重佈線結構，包括第一重佈線線，所述第一重佈線線連接至所述第一導通孔、所述晶粒連接件及所述第二導通孔。
另外，本申請的其他實施例提供一種形成封裝結構的方 法，包括：在第一積體電路晶粒上形成第一導通孔；利用第一可回焊連接件將第二積體電路晶粒結合至所述第一積體電路晶粒，所述第二積體電路晶粒與所述第一導通孔相鄰；利用第一模塑化合物包封所述第一導通孔及所述第二積體電路晶粒；將所述第一模塑化合物及所述第一積體電路晶粒單體化以形成晶粒堆疊；將所述晶粒堆疊與所述第二導通孔相鄰地放置；利用第二模塑化合物包封所述第二導通孔及所述晶粒堆疊；以及在所述第二模塑化合物及所述晶粒堆疊上形成第一重佈線結構，所述第一重佈線結構包括第一重佈線線，所述第一重佈線線連接至所述第一導通孔及所述第二導通孔。
100、500、700:晶粒堆疊
102:晶圓
102A:裝置區
110:第一積體電路晶粒/積體電路晶粒
110B、140B、170B:背側
110F、140F、170F:前側
112、142:半導體基底
112A:主動區
112N:非主動區
116、146、176:接觸接墊
118、130、148、156、178、208、212、242、246、250、254:介電層
120、150、180:鈍化層
122、122A、122B、122C、152、182:晶粒連接件
132、132A、132B、132C:開口
134、154、220:導通孔
140:第二積體電路晶粒/積體電路晶粒
158、168:黏合劑
160、160A、160B:可回焊連接件
162、312:底部填充膠
162A:第一底部填充膠/底部填充膠
162B:第二底部填充膠/底部填充膠
164、222:包封體
166:條帶
170:被動裝置
172:主要結構
200、300、600、800:積體電路封裝
202:載體基底
202A:封裝區
204:釋放層
206:背側重佈線結構/重佈線結構
210、244、248、252:金屬化圖案
224:障壁層
240:前側重佈線結構/重佈線結構
256:凸塊下金屬
258、262:導電連接件
260:整合式被動裝置
302:基底
304:晶粒
306、402:結合接墊
308:打線結合
310:模塑材料
400:封裝基底
結合附圖閱讀以下詳細說明，會最佳地理解本揭露的各個態樣。注意，根據行業中的標準慣例，各種特徵並非按比例繪製。事實上，為使論述清晰起見，可任意增大或減小各種特徵的尺寸。
圖1、圖2、圖3、圖4、圖5、圖6、圖7及圖8是根據一些實施例的用於形成晶粒堆疊的製程期間的中間步驟的剖視圖。
圖9、圖10、圖11、圖12、圖13、圖14、圖15、圖16、圖17及圖18A是根據一些實施例的用於形成實施晶粒堆疊的積體電路封裝的製程期間的中間步驟的剖視圖。
圖18B是根據一些其他實施例的實施晶粒堆疊的積體電路封裝的剖視圖。
圖19、圖20、圖21及圖22是根據一些其他實施例的用 於形成晶粒堆疊的製程期間的中間步驟的剖視圖。
圖23A是根據一些其他實施例的實施晶粒堆疊的積體電路封裝的剖視圖。
圖23B是根據一些其他實施例的實施晶粒堆疊的積體電路封裝的剖視圖。
圖24、圖25、圖26、圖27、圖28及圖29是根據一些其他實施例的用於形成晶粒堆疊的製程期間的中間步驟的剖視圖。
圖30是根據一些其他實施例的實施晶粒堆疊的積體電路封裝的剖視圖。
以下揭露內容提供諸多不同的實施例或實例以用於實施本發明的不同特徵。下文闡述組件及排列的具體實例以簡化本揭露。當然，該些僅為實例且不旨在進行限制。舉例而言，在以下說明中第一特徵形成於第二特徵「之上」或形成於第二特徵「上」可包括其中第一特徵與第二特徵被形成為直接接觸的實施例，且亦可包括其中第一特徵與第二特徵之間可形成有額外特徵使得所述第一特徵與所述第二特徵可不直接接觸的實施例。另外，本揭露可在各種實例中重複使用參考編號及/或字母。此種重複是出於簡潔及清晰的目的，而非自身指示所論述的各種實施例及/或配置之間的關係。
此外，為易於說明起見，本文中可使用例如「位於...之下(beneath)」、「位於...下方(below)」、「下部的(lower)」、「位於... 上方(above)」、「上部的(upper)」等空間相對性用語來闡述圖中所示的一個元件或特徵與另一(其他)元件或特徵的關係。除圖中所繪示的定向之外，所述空間相對性用語亦旨在囊括裝置在使用或操作中的不同定向。設備可具有其他定向(旋轉90度或處於其他定向)，且同樣地可對本文中所使用的空間相對性描述語加以相應地解釋。
根據一些實施例，形成包括多個積體電路晶粒的晶粒堆疊。所述晶粒堆疊是以面對面或背對面方式對晶粒進行堆疊而形成。可使用可回焊連接件或黏合劑來結合晶粒堆疊的積體電路晶粒。此結合技術無法使得晶粒連接件的節距如其他結合技術(諸如混合結合)一樣細小或無法使得輸入/輸出(I/O)連接件的計數如其他結合技術一樣大，然而，此結合技術使得能夠以較低的成本實行結合。當晶粒堆疊是低效能裝置時，可尤其期望以較低的成本形成晶粒堆疊。所得的晶粒堆疊可以是例如積體電路上系統(system-on-integrated circuit，SoIC)裝置。一旦形成，則可將SoIC裝置包括於積體電路封裝中。
圖1、圖2、圖3、圖4、圖5、圖6、圖7及圖8是根據一些實施例的用於形成晶粒堆疊100的製程期間的中間步驟的剖視圖。藉由在晶圓102上堆疊積體電路晶粒來形成晶粒堆疊100。說明晶圓102的一個裝置區102A中的積體電路晶粒的堆疊，但應瞭解，晶圓102可具有任何數目個裝置區，且可在每一裝置區中堆疊積體電路晶粒以形成晶粒堆疊。利用可回焊連接件以面對面 方式對晶粒堆疊100的積體電路晶粒進行直接結合。
在圖1中，形成或獲得晶圓102。晶圓102包括位於裝置區102A中的第一積體電路晶粒110。將在後續處理中將第一積體電路晶粒110單體化以將第一積體電路晶粒110包括於晶粒堆疊100中。第一積體電路晶粒110可以是任何可接受的處理器或邏輯裝置，諸如中央處理單元(central processing unit，CPU)、圖形處理單元(graphics processing unit，GPU)、算術邏輯單元(arithmetic logic unit，ALU)、系統晶片(system-on-a-chip，SoC)、應用處理器(application processor，AP)、影像訊號處理器(image signal processor，ISP)、數位訊號處理器(digital signal processor，DSP)、現場可程式化閘陣列(field programmable gate array，FPGA)、微控制器、人上智慧(artificial intelligence，AI)加速度計等。
根據可適用的製造製程對第一積體電路晶粒110進行處理以形成積體電路。舉例而言，第一積體電路晶粒110包括經過摻雜或未經摻雜的半導體基底112(諸如矽)或絕緣體上半導體(semiconductor-on-insulator，SOI)基底的有效層。半導體基底112可包含其他半導體材料，諸如：鍺；化合物半導體，包括碳化矽、鎵砷、磷化鎵、磷化銦、砷化銦及/或銻化銦；合金半導體，包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP及/或GaInAsP；或其組合。亦可使用其他基底，諸如多層基底或梯度基底。半導體基底112具有主動區112A及非主動區112N。
在半導體基底112的主動區112A處形成裝置。裝置可以 是主動裝置(例如電晶體、二極體等)、電容器、電阻器等。非主動區112N位於第一積體電路晶粒110的背側110B處，且可不包括裝置。在半導體基底112的主動區112A處形成內連結構。內連結構對半導體基底112的主動區112A處的裝置進行內連以形成積體電路。內連結構可由例如介電層中的金屬化圖案形成，且可藉由鑲嵌製程(諸如，單鑲嵌製程、雙鑲嵌製程等)來形成。金屬化圖案包括形成於一或多個介電層中的金屬線及通孔。內連結構的金屬化圖案電性耦合至位於半導體基底112的主動區112A處的裝置。
亦在半導體基底112的主動區112A之上形成接觸接墊116。接觸接墊116可以是鋁接墊、銅接墊等，且可藉由例如鍍覆、沈積等形成。在接觸接墊116周圍形成介電層118。介電層118可以是聚合物，諸如聚苯並噁唑(polybenzoxazole，PBO)、聚醯亞胺、苯並環丁烯(benzocyclobutene，BCB)系聚合物等；氮化物，諸如氮化矽等；氧化物，諸如氧化矽、磷矽酸鹽玻璃(phosphosilicate glass，PSG)、硼矽酸鹽玻璃(borosilicate glass，BSG)、摻雜硼的磷矽酸鹽玻璃(boron-doped phosphosilicate glass，BPSG)等；諸如此類或其組合。可例如藉由旋轉塗佈、層壓、沈積等形成介電層118。接觸接墊116及介電層118可以是內連結構的一部分，諸如內連結構的最頂層的一部分。
在接觸接墊116及半導體基底112上形成一或多個鈍化 層120。鈍化層120可由一或多種適合的介電材料形成，諸如氧化矽、氮化矽、低介電常數(low-k)電介質(諸如，摻雜碳的氧化物)、極低介電常數電介質(諸如，摻雜多孔碳的二氧化矽)、聚合物(諸如，聚醯亞胺、阻焊劑、PBO、BCB系聚合物)、模塑化合物等或其組合。鈍化層120可藉由旋轉塗佈、層壓、沈積等或其組合形成。
在接觸接墊116中的相應接觸接墊116上形成晶粒連接件122，且晶粒連接件122在第一積體電路晶粒110的前側110F處暴露出。晶粒連接件122可以是導電柱、凸塊、穿孔等，且可由諸如銅等金屬形成。晶粒連接件122連接(例如，實體地耦合且電性耦合)至接觸接墊116中的相應接觸接墊116，且電性耦合至第一積體電路晶粒110中的相應積體電路110。舉形成晶粒連接件122的實例，在鈍化層120中形成開口，且沿著鈍化層120及在穿過鈍化層120的開口中形成晶種層。可藉由可接受的光微影及蝕刻技術形成開口。在一些實施例中，晶種層是金屬層，所述金屬層可以是單層或包括由不同的材料形成的多個子層的複合層。在一些實施例中，晶種層包括鈦層及位於所述鈦層之上的銅層。可藉由沈積(諸如，物理氣相沈積(Physical Vapor Deposition，PVD)等)形成晶種層。在晶種層上形成光阻並將所述光阻圖案化。可藉由旋轉塗佈等形成光阻並可將光阻暴露於光以進行圖案化。光阻的圖案對應於晶粒連接件122。圖案化會形成穿過光阻的開口以暴露出晶種層。在光阻的開口中且在晶種層的暴露部分上形成導電材料。 可藉由鍍覆(諸如，電鍍覆或無電鍍覆)等形成導電材料。導電材料可包括金屬，諸如銅、鎳、鈦、鎢、鋁等。在一些實施例中，導電材料是包括由不同的材料形成的多個子層的複合層。舉例而言，導電材料可包括位於兩個銅層之間的鎳層。可藉由可接受的灰化或剝除製程(諸如，使用氧電漿等)移除光阻。一旦光阻被移除，則諸如藉由使用可接受的蝕刻製程(諸如，藉由濕式蝕刻或乾式蝕刻)移除晶種層的暴露部分。晶種層的剩餘部分及導電材料形成晶粒連接件122。
然後，對第一積體電路晶粒110實行電路探針(Circuit probe，CP)測試以探知第一積體電路晶粒110是否是已知良好晶粒(known good die，KGD)。使用探針測試第一積體電路晶粒110。探針藉由例如可回焊連接件連接至晶粒連接件122。僅是KGD的積體電路晶粒經受後續處理及封裝，且不封裝未通過CP測試的積體電路晶粒。測試可包括對第一積體電路晶粒110的功能性的測試，或可包括可基於第一積體電路晶粒110的設計而預期的已知開路或短路的測試。在測試完成之後，移除探針且可藉由例如蝕刻製程、化學機械拋光(chemical-mechanical polish，CMP)、研磨製程等移除晶粒連接件122上的任何多餘可回焊材料。
在圖2中，在晶圓102上(諸如，在晶粒連接件122及鈍化層120上)形成介電層130。在一些實施例中，介電層130是由聚合物(諸如，聚醯亞胺、PBO、BCB系聚合物等)形成。在其他實施例中，介電層130由氧化物(諸如，氧化矽、PSG、BSG、 BPSG等)、氮化物(諸如氮化矽)等形成。介電層130可藉由任何可接受的沈積製程(諸如，旋轉塗佈、化學氣相沈積(chemical vapor deposition，CVD)、層壓等或其組合)來形成。
然後，將介電層130圖案化以形成開口132，開口132暴露出晶粒連接件122的一些部分。可藉由可接受的製程來形成所述圖案化，諸如在介電層130是感光性材料時藉由將介電層130暴露於光，或者藉由使用例如各向異性蝕刻來進行蝕刻。若介電層130是感光性材料，則可在曝光之後對介電層130進行顯影。
開口132A的子集暴露出晶粒連接件122A的第一子集。開口132A中的每一者暴露出晶粒連接件122A中的相應晶粒連接件122A。如下文進一步論述，將在開口132A中的每一者中形成導通孔，且所述導通孔連接至晶粒連接件122A中的相應晶粒連接件122A。開口132B暴露出晶粒連接件122B的第二子集。具體而言，開口132B暴露出晶粒連接件122B中的多個晶粒連接件122B。如下文進一步論述，將在開口132B中放置積體電路晶粒，且積體電路晶粒連接至晶粒連接件122B。開口132B較開口132A中的每一者寬。舉例而言，開口132A可各自具有處於約10微米至約15微米範圍內的寬度，且開口132B可具有處於約3000微米至約6000微米範圍內的寬度。更寬的開口132B有助於容納積體電路晶粒。
在圖3中，在開口132A中形成導通孔134，導通孔134穿過介電層130且遠離晶圓102延伸。導通孔134連接至晶粒連 接件122A。舉形成導通孔134的實例，在介電層130之上且在晶粒連接件122A的由開口132A暴露出的部分之上形成晶種層。在一些實施例中，晶種層是金屬層，所述金屬層可以是單層或包括由不同的材料形成的多個子層的複合層。在特定實施例中，晶種層包括鈦層及位於所述鈦層之上的銅層。可使用例如PVD等形成晶種層。在晶種層上形成光阻並將所述光阻圖案化。可藉由旋轉塗佈等形成光阻並可將光阻暴露於光以進行圖案化。光阻的圖案對應於導通孔。圖案化會形成穿過光阻以暴露出晶種層的開口。在光阻的開口中且在晶種層的暴露部分上形成導電材料。可藉由鍍覆(諸如，電鍍覆或無電鍍覆)等形成導電材料。導電材料可包括金屬，如銅、鈦、鎢、鋁等。移除光阻且移除晶種層的上面未形成導電材料的部分。可藉由可接受的灰化或剝除製程(諸如，使用氧電漿等)移除光阻。一旦光阻被移除，則諸如藉由使用可接受的蝕刻製程(諸如，藉由濕式蝕刻或乾式蝕刻)移除晶種層的暴露部分。晶種層的剩餘部分及導電材料形成導通孔134。導通孔134可被形成為節距例如處於約40微米至約80微米範圍內。
在圖4中，形成或獲得第二積體電路晶粒140。第二積體電路晶粒140具有數種可能的功能，且具有與第一積體電路晶粒110不同的功能。在一些實施例中，第二積體電路晶粒140是類比裝置晶粒，諸如電力閘控(power gating)晶粒、電力管理積體電路(power management integrated circuit，PMIC)等。在一些實施例中，第二積體電路晶粒140是輸入/輸出(I/O)晶粒，諸如介面 晶粒、基底穿孔(through-substrate via，TSV)晶粒等。在一些實施例中，第二積體電路晶粒140是記憶體晶粒，諸如動態隨機存取記憶體(dynamic random access memory，DRAM)晶粒、靜態隨機存取記憶體(static random access memory，SRAM)晶粒、電阻式隨機存取記憶體(resistive random-access memory，RRAM)晶粒、磁阻式隨機存取記憶體(magnetoresistive random-access memory，MRAM)晶粒、相變隨機存取記憶體(phase-change random-access memory，PCRAM)晶粒等。在一些實施例中，第二積體電路晶粒140是另一處理器或邏輯裝置，諸如GPU、DSP等。
第二積體電路晶粒140可形成於晶圓中，晶圓可包括在後續步驟中被單體化以形成多個積體電路晶粒的不同的裝置區。當第二積體電路晶粒140包括主動裝置時，所述主動裝置可具有較第一積體電路晶粒110大的技術節點。根據可適用的製造製程對第二積體電路晶粒140進行處理以形成積體電路。舉例而言，第二積體電路晶粒140包括半導體基底142、接觸接墊146、介電層148、一或多個鈍化層150以及晶粒連接件152，所述半導體基底142、接觸接墊146、介電層148、一或多個鈍化層150以及晶粒連接件152可分別類似於第一積體電路晶粒110的半導體基底112、接觸接墊116、介電層118、鈍化層120及晶粒連接件122。晶粒連接件152在第二積體電路晶粒140的前側140F處暴露出。在將第二積體電路晶粒140單體化之後，半導體基底142、介電層148及鈍化層150在側向上毗連。第二積體電路晶粒140更包括被 形成為延伸至半導體基底142中的導通孔154。導通孔154諸如經由內連結構的金屬化圖案電性耦合至半導體基底142的裝置。
舉形成導通孔154的實例，可藉由例如蝕刻、銑削、雷射技術、其組合等在半導體基底142中形成凹陷。可諸如使用氧化技術在凹陷中形成薄的介電材料。可諸如藉由CVD、原子層沈積(atomic layer deposition，ALD)、物理氣相沈積(physical vapor deposition，PVD)、熱氧化、其組合等在開口中共形地沈積薄的障壁層。障壁層可由氧化物、氮化物或氮氧化物(諸如氮化鈦、氮氧化鈦、氮化鉭、氮氧化鉭、氮化鎢、其組合等)形成。可在障壁層之上且在開口中沈積導電材料。可藉由電化學鍍覆製程、CVD、ALD、PVD、其組合等形成導電材料。導電材料的實例是銅、鎢、鋁、銀、金、其組合等。藉由例如CMP自半導體基底142的表面移除多餘導電材料及障壁層。障壁層的剩餘部分及導電材料形成導通孔154。
根據一些實施例，第二積體電路晶粒140的背側140B處尚未暴露出導通孔154。而是，導通孔154隱埋於半導體基底142中。如下文進一步論述，將在後續處理中經由暴露製程在第二積體電路晶粒140的背側140B處暴露出導通孔154。在暴露出之後，導通孔154可被稱為TSV。
在圖5中，將第二積體電路晶粒140放置於開口132B中並結合至第一積體電路晶粒110(例如，晶圓102)。利用可回焊連接件160以面對面方式對第一積體電路晶粒110與第二積體電路 晶粒140進行直接結合，以使得第一積體電路晶粒110的前側110F結合至第二積體電路晶粒140的前側140F。可回焊連接件160可以是球柵陣列(ball grid array，BGA)連接件、焊球等。可回焊連接件160可由金屬或金屬合金(諸如，焊料、銅、鋁、金、鎳、銀、鈀、錫等或其組合)形成。在一些實施例中，首先經由諸如蒸鍍、電鍍覆、印刷、焊料轉移、植球等方法形成焊料層來形成可回焊連接件160。可回焊連接件160可首先形成於晶粒連接件122B或晶粒連接件152上。一旦已形成焊料層，則可實行回焊以將材料塑形成所期望的凸塊形狀。藉由使可回焊連接件160接觸晶粒連接件122B及晶粒連接件152並對可回焊連接件160進行回焊來將第一積體電路晶粒110與第二積體電路晶粒140結合。在回焊之後，晶粒連接件122B連接至晶粒連接件152。利用可回焊連接件160來對第一積體電路晶粒110與第二積體電路晶粒140進行結合使得能夠以較其他結合技術(諸如混合結合)低的成本實行結合。
在對可回焊連接件160進行回焊之前，可在可回焊連接件160上形成助焊劑(未繪示)。在一些實施例中，在可回焊連接件160被回焊之後，利用助焊劑清除製程移除助焊劑。可選地，在第一積體電路晶粒110與第二積體電路晶粒140之間形成底部填充膠162，從而環繞可回焊連接件160。可在將第一積體電路晶粒110與第二積體電路晶粒140結合之後藉由毛細流動製程形成底部填充膠162，或可在將第一積體電路晶粒110與第二積體電路晶 粒140結合之前藉由適合的沈積方法形成底部填充膠162。底部填充膠162填充開口132B，可沿著第二積體電路晶粒140的側壁延伸，且可沿著介電層130的頂表面的一部分延伸。
在圖6中，在導通孔134及第二積體電路晶粒140上及周圍形成包封體164。在形成之後，包封體164包封導通孔134及第二積體電路晶粒140。包封體164可以是模塑化合物、環氧樹脂等。可藉由壓縮模塑、轉移模塑等施加包封體164，且包封體164可形成於晶圓102之上，以使得導通孔134及/或第二積體電路晶粒140被隱埋或覆蓋。可以液體或半液體形式施加包封體164且然後隨後加以固化。如上文所述，底部填充膠162是可選的；當省略底部填充膠162時，包封體164可環繞且實體地接觸晶粒連接件122B、晶粒連接件152及可回焊連接件160中的每一者的側壁。此外，當省略底部填充膠162時，包封體164可延伸穿過介電層130。
在圖7中，對包封體164實行平坦化製程以暴露出導通孔134、及第二積體電路晶粒140的背側140B。平坦化製程可移除包封體164的材料、導通孔134的材料及/或半導體基底142的材料，直至暴露出導通孔134、及第二積體電路晶粒140的背側140B為止。在平坦化製程之後，被平坦化組件的頂表面是共面的。平坦化製程可以是例如化學機械拋光(CMP)、研磨製程、回蝕製程等。
在一些實施例中，平坦化製程包括將半導體基底142薄 化，這可有助於在後續處理中更容易地在第二積體電路晶粒140的背側140B處暴露出導通孔154。薄化製程可以是例如化學機械拋光(CMP)、研磨製程、回蝕製程等。即使當在此處理步驟處對半導體基底142進行薄化時，導通孔154仍隱埋於半導體基底142中。在平坦化製程之後，包封體164與介電層130可具有例如處於約30微米至約50微米範圍內(諸如，約50微米)的組合厚度。
可選地，可對半導體基底112進行薄化，這可有助於減小晶粒堆疊100的總厚度。薄化製程可以是例如化學機械拋光(CMP)、研磨製程、回蝕製程等，在第一積體電路晶粒110的背側110B處實行所述薄化製程。在薄化製程之後，半導體基底112可具有例如處於約100微米至約150微米範圍內(諸如，約130微)的厚度。
在圖8中，藉由沿著切割道區(例如，在裝置區102A周圍)進行切分來實行單體化製程。單體化製程包括切分晶圓102、介電層130及包封體164。單體化製程將晶圓102的裝置區102A(包括第一積體電路晶粒110)與相鄰的裝置區(未繪示)分離以形成包括第一積體電路晶粒110的晶粒堆疊100。在單體化之後，半導體基底112、介電層118、鈍化層120、介電層130及包封體164在側向上毗連。
在第一積體電路晶粒110的背側110B上形成黏合劑168。如下文進一步論述，黏合劑168將在後續處理中用於將晶粒堆疊100黏合至另一元件。黏合劑168可以是任何適合的黏合劑、環氧 樹脂、晶粒貼合膜(die attach film，DAF)等。在所示的實施例中，在進行單體化以分離第一積體電路晶粒110之前，將黏合劑168施加至第一積體電路晶粒110的背側110B(參見圖7)。在另一實施例中，直至稍後的處理步驟才施加黏合劑168。
在單體化之後，可將晶粒堆疊100放置於例如條帶166上。在將黏合劑168施加至第一積體電路晶粒110的背側110B(參見圖7)的實施例中，黏合劑168可用於將晶粒堆疊100黏合至條帶166。
圖9、圖10、圖11、圖12、圖13、圖14、圖15、圖16、圖17及圖18A是根據一些實施例的用於形成實施晶粒堆疊100的積體電路封裝的製程期間的中間步驟的剖視圖。將晶粒堆疊100封裝於積體電路封裝200中。說明將裝置封裝於一個封裝區202A中，但應瞭解，可同時形成任何數目個封裝區。將在後續處理中將封裝區202A單體化。被單體化的積體電路封裝200可以是扇出型封裝，諸如積體扇出型(integrated fan-out，InFO)封裝。然後，將被單體化的積體電路封裝200安裝至封裝基底以形成完整的系統。
在圖9中，提供載體基底202，且在載體基底202上形成釋放層204。載體基底202可以是玻璃載體基底、陶瓷載體基底等。載體基底202可以是晶圓，以使得可在載體基底202上同時形成多個封裝。釋放層204可由聚合物系材料形成，釋放層204可與載體基底202一起自將在後續步驟中形成的上覆結構被移除。在一些實施例中，釋放層204是在受熱時會失去其黏合性質的環 氧樹脂系熱釋放材料，諸如光熱轉換(light-to-heat-conversion，LTHC)釋放塗層。在其他實施例中，釋放層204可以是在暴露於紫外線(ultra-violet，UV)光時會失去其黏合性質的UV膠。可以液體形式施配釋放層204並將釋放層204固化，釋放層204可以是層壓至載體基底202上的層壓膜，或可以是諸如此類的材料。釋放層204的頂表面可以是平整的且可具有高程度的平坦度。
可以可選地在釋放層204上形成背側重佈線結構206。在所示的實施例中，背側重佈線結構206包括介電層208、金屬化圖案210(有時被稱為重佈線層或重佈線線)及介電層212。背側重佈線結構206是可選的。在一些實施例中，代替背側重佈線結構206，在釋放層204上形成不具有金屬化圖案的介電層。
在釋放層204上形成介電層208。介電層208的底表面可接觸釋放層204的頂表面。在一些實施例中，介電層208由聚合物(諸如PBO、聚醯亞胺、BCB系聚合物等)形成。在其他實施例中，介電層208由氮化物(諸如，氮化矽)、氧化物(諸如，氧化矽、磷矽酸鹽玻璃(PSG)、硼矽酸鹽玻璃(BSG)、摻雜硼的磷矽酸鹽玻璃(BPSG)等)等形成。介電層208可藉由任何可接受的沈積製程(諸如旋轉塗佈、CVD、層壓等或其組合)來形成。
在介電層208上形成金屬化圖案210。舉形成金屬化圖案210的實例，在介電層208之上形成晶種層。在一些實施例中，晶種層是金屬層，所述金屬層可以是單層或包括由不同的材料形成的多個子層的複合層。在一些實施例中，晶種層包括鈦層及位於所 述鈦層之上的銅層。可使用例如物理氣相沈積(PVD)等來形成晶種層。然後，在晶種層上形成光阻並將所述光阻圖案化。可藉由旋轉塗佈等形成光阻，並可將光阻暴露於光以進行圖案化。光阻的圖案對應於金屬化圖案210。圖案化會形成穿過光阻以暴露出晶種層的開口。在光阻的開口中且在晶種層的暴露部分上形成導電材料。可藉由鍍覆(諸如，電鍍覆或無電鍍覆)等形成導電材料。導電材料可包括金屬，如銅、鈦、鎢、鋁等。然後，移除光阻且移除晶種層的上面未形成導電材料的部分。可藉由可接受的灰化或剝除製程(諸如，使用氧電漿等)移除光阻。一旦光阻被移除，則諸如藉由使用可接受的蝕刻製程(諸如，藉由濕式蝕刻或乾式蝕刻)移除晶種層的暴露部分。晶種層的剩餘部分及導電材料形成金屬化圖案210。
在金屬化圖案210及介電層208上形成介電層212。在一些實施例中，介電層212由聚合物形成，所述聚合物可以是可使用微影罩幕圖案化的感光性材料，諸如PBO、聚醯亞胺、BCB等。在其他實施例中，介電層212由氮化物(諸如，氮化矽)、氧化物(諸如氧化矽、PSG、BSG、BPSG)等形成。可藉由旋轉塗佈、層壓、CVD等或其組合形成介電層212。
應瞭解，背側重佈線結構206可包括任何數目個介電層及金屬化圖案。若要形成更多的介電層及金屬化圖案，則可重複上文所論述的步驟及製程。金屬化圖案可包括導電線及導通孔。可在形成金屬化圖案期間藉由形成晶種層且在下伏的介電層的開口中 形成金屬化圖案的導電材料來形成導通孔。因此，導通孔可將各種導電線內連且電性耦合。
在圖10中，形成穿過背側重佈線結構206的最頂部介電層(例如，介電層212)且遠離載體基底202延伸的導通孔220。導通孔220連接至背側重佈線結構206的最頂部金屬化圖案(例如，金屬化圖案210)。導通孔220是可選的，且如下文進一步論述可被省略。舉例而言，在省略背側重佈線結構206的實施例中，可(或可不)省略導通孔220。舉形成導通孔220的實例，可將介電層212圖案化以形成暴露出金屬化圖案210的一些部分的開口。可藉由可接受的製程形成圖案化，諸如當介電層212是感光性材料時藉由將介電層212暴露於光，或藉由使用例如各向異性蝕刻進行蝕刻。若介電層212是感光性材料，則可在曝光之後對介電層212進行顯影。然後，在介電層212之上且在金屬化圖案210的由開口暴露出的部分之上形成晶種層。在一些實施例中，晶種層是金屬層，所述金屬層可以是單層或包括由不同的材料形成的多個子層的複合層。在特定實施例中，晶種層包括鈦層及位於所述鈦層之上的銅層。可使用例如PVD等形成晶種層。在晶種層上形成光阻並將所述光阻圖案化。可藉由旋轉塗佈等形成光阻並可將光阻暴露於光以進行圖案化。光阻的圖案對應於導通孔。圖案化會形成穿過光阻以暴露出晶種層的開口。在光阻的開口中且在晶種層的暴露部分上形成導電材料。可藉由鍍覆(諸如，電鍍覆或無電鍍覆)等形成導電材料。導電材料可包括金屬，如銅、鈦、鎢、鋁等。移 除光阻且移除晶種層的上面未形成導電材料的部分。可藉由可接受的灰化或剝除製程(諸如，使用氧電漿等)移除光阻。一旦光阻被移除，則諸如藉由使用可接受的蝕刻製程(諸如，藉由濕式蝕刻或乾式蝕刻)移除晶種層的暴露部分。晶種層的剩餘部分及導電材料形成導通孔220。
然後，與導通孔220相鄰地放置被單體化的晶粒堆疊100。當形成背側重佈線結構206時，可將晶粒堆疊100放置於背側重佈線結構206(例如，介電層212)上，或當省略背側重佈線結構206時，可將晶粒堆疊100放置於釋放層204上。使用黏合劑168將被單體化的晶粒堆疊100黏合至下伏的層(例如，介電層212或釋放層204)。在未對第一積體電路晶粒110的背側110B施加黏合劑168的實施例中，可替代地在載體基底202的表面之上(例如，在介電層212或釋放層204上)施加黏合劑168。
在圖11中，在各種組件上及周圍形成包封體222。在形成之後，包封體222包封導通孔220及晶粒堆疊100。包封體222可以是模塑化合物、環氧樹脂等。可藉由壓縮模塑、轉移模塑等施加包封體222，且包封體222形成於載體基底202之上，以使得導通孔220及/或晶粒堆疊100被隱埋或覆蓋。可以液體或半液體形式施加包封體222且然後隨後加以固化。在一些實施例中，包封體164、222包含不同的模塑材料。舉例而言，包封體222可由模塑化合物形成，且包封體164可由模塑底部填充膠(例如，具有粒徑較用於包封體222的模塑材料小的填料的模塑材料)形成。
圖12、圖13及圖14說明可對包封體222及晶粒堆疊100實行以暴露出導通孔134、154、220的平坦化製程。平坦化製程移除半導體基底142的材料、導通孔134、154、220的材料及/或包封體164、222的材料，直至暴露出導通孔134、154、220為止。在平坦化製程之後，經平坦特徵的頂表面是共面的。在平坦化之後，導通孔134延伸穿過包封體164(例如，導通孔134是穿孔)且導通孔220延伸穿過包封體222(例如，導通孔220是穿孔)。根據一些實施例，平坦化製程包括研磨製程、蝕刻製程及CMP製程的組合。圖12、圖13及圖14是可用於暴露出導通孔134、154、220的平坦化製程的實例。應瞭解，亦可使用其他平坦化製程。舉例而言，可使用研磨製程、蝕刻製程及/或CMP製程的其他組合以暴露出導通孔134、154、220。
在圖12中，對包封體222進行研磨以暴露出晶粒堆疊100，例如半導體基底142。可實行一或多次研磨製程，此舉亦可(或可不)暴露出導通孔220。亦可在研磨製程期間對半導體基底142進行薄化。在此處理步驟處將對導體基底142進行薄化可有助於降低在後續處理步驟中暴露出導通孔154的成本。在一些實施例中，實行第一研磨製程以暴露出半導體基底142，且實行第二研磨製程以對半導體基底142進行薄化，其中第二研磨製程是以較第一研磨製程小的移除速率實行。舉例而言，可利用具有第一表面粗糙度的第一研磨頭實行第一研磨製程，且可利用具有第二表面粗糙度的第二研磨頭實行第二研磨製程，其中第二表面粗糙度小 於第一表面粗糙度。以較緩慢的移除速率對半導體基底142進行薄化可有助於避免可損壞導通孔154的過度研磨。
在圖13中，對包封體222及半導體基底142進行研磨以暴露出導通孔154。可實行一或多次研磨製程，若導通孔220尚未被暴露出，則所述一或多次研磨製程亦會暴露出導通孔220。在一些實施例中，實行第三研磨製程以對半導體基底142進行薄化且暴露出導通孔154，其中所述第三研磨製程是以較關於圖12所論述的第一研磨製程及第二研磨製程小的移除速率實行。舉例而言，可利用表面粗糙度較在關於圖12所論述的第一研磨製程及第二研磨製程中所使用的研磨頭的表面粗糙度小的研磨頭實行第三研磨製程。繼續先前的實例，可利用具有第三表面粗糙度的第三研磨頭實行第三研磨製程，其中第三表面粗糙度小於關於圖12所論述的第一表面粗糙度及第二表面粗糙度。以較緩慢的移除速率暴露出導通孔154可有助於避免可損壞導通孔154的過度研磨。
在圖14中，可以可選地在導通孔154周圍形成障壁層224。障壁層224可有助於將導通孔154彼此電性隔離，因此避免短路。舉形成障壁層224的實例，可使半導體基底142凹陷以暴露出導通孔154的側壁部分。所述凹陷可藉由蝕刻製程(諸如，乾式蝕刻)來進行。然後，可在凹陷中形成障壁材料。障壁材料可以是介電材料，諸如低溫聚醯亞胺材料，但亦可利用任何其他適合的電介質(諸如PBO)、包封體、該些材料的組合等。可實行平坦化製程(諸如CMP、研磨或回蝕)以移除位於半導體基底142之上 的障壁材料的多餘部分。障壁材料的在凹陷中的剩餘部分形成障壁層224。在形成障壁層224之後，障壁層224在側向上由包封體164環繞。
在圖15中，在包封體222、導通孔220及晶粒堆疊100之上形成前側重佈線結構240。前側重佈線結構240包括介電層242、246、250、254及金屬化圖案244、248、252。金屬化圖案亦可被稱為重佈線層或重佈線線。前側重佈線結構240被舉例示出為具有三個金屬化圖案層。前側重佈線結構240中可形成更多或更少的介電層及金屬化圖案。若要形成更少的介電層及金屬化圖案，則可省略下文所論述的步驟及製程。若要形成更多的介電層及金屬化圖案，則可重複下文所論述的步驟及製程。
舉形成前側重佈線結構240的實例，可在包封體222、導通孔220及晶粒堆疊100上沈積介電層242。因此，障壁層224接觸介電層242。在一些實施例中，介電層242由可使用微影罩幕圖案化的感光性材料形成，諸如PBO、聚醯亞胺、BCB等。可藉由旋轉塗佈、層壓、CVD等或其組合形成介電層242。然後，將介電層242圖案化。圖案化會形成暴露出導通孔134、154、220的一些部分的開口。圖案化可藉由可接受的製程進行，諸如當介電層242是感光性材料時藉由將介電層242暴露於光，或藉由使用例如各向異性蝕刻進行蝕刻。若介電層242是感光性材料，則可在曝光之後對介電層242進行顯影。
然後，形成金屬化圖案244。金屬化圖案244包括位於介 電層242的主表面上且沿著介電層242的主表面延伸的線部分(亦被稱為導電線)。金屬化圖案244更包括延伸穿過介電層242以連接至導通孔134、154、220的通孔部分(亦被稱為導通孔)。舉形成金屬化圖案244的實例，在介電層242之上且在延伸穿過介電層242的開口中形成晶種層。在一些實施例中，晶種層是金屬層，所述金屬層可以是單層或包括由不同的材料形成的多個子層的複合層。在一些實施例中，晶種層包括鈦層及位於所述鈦層之上的銅層。可使用例如PVD等形成晶種層。然後，在晶種層上形成光阻並將所述光阻圖案化。可藉由旋轉塗佈等形成光阻並可將光阻暴露於光以進行圖案化。光阻的圖案對應於金屬化圖案244。圖案化會形成穿過光阻以暴露出晶種層的開口。然後，在光阻的開口中且在晶種層的暴露部分上形成導電材料。可藉由鍍覆(諸如，電鍍覆或無電鍍覆)等形成導電材料。導電材料可包括金屬，如銅、鈦、鎢、鋁等。導電材料與晶種層的下伏部分的組合形成金屬化圖案244。移除光阻且移除晶種層的上面未形成導電材料的部分。可藉由可接受的灰化或剝除製程(諸如，使用氧電漿等)移除光阻。一旦光阻被移除，則諸如藉由使用可接受的蝕刻製程(諸如，藉由濕式蝕刻或乾式蝕刻)移除晶種層的暴露部分。
然後，在金屬化圖案244及介電層242上沈積介電層246。可以與形成介電層242類似的方式且以類似的材料形成介電層246。
然後，形成金屬化圖案248。金屬化圖案248包括位於介 電層246的主表面上且沿著介電層246的主表面延伸的線部分。金屬化圖案248更包括延伸穿過介電層246以連接至金屬化圖案244的通孔部分。可以與形成金屬化圖案244類似的方式且以類似的材料形成金屬化圖案248。在一些實施例中，金屬化圖案248具有與金屬化圖案244不同的大小。舉例而言，金屬化圖案248的導電線及/或通孔可較金屬化圖案244的導電線及/或通孔寬或厚。此外，金屬化圖案248可被形成為節距較金屬化圖案244大。
然後，在金屬化圖案248及介電層246上沈積介電層250。可以與形成介電層242類似的方式且以類似的材料形成介電層250。
然後，形成金屬化圖案252。金屬化圖案252包括位於介電層250的主表面上且沿著介電層250的主表面延伸的線部分。金屬化圖案252更包括延伸穿過介電層250以連接至金屬化圖案248的通孔部分。可以與形成金屬化圖案244類似的方式且以類似的材料形成金屬化圖案252。金屬化圖案252是前側重佈線結構240的最頂部金屬化圖案。如此，前側重佈線結構240的所有中間金屬化圖案(例如，金屬化圖案244及248)設置於金屬化圖案252與晶粒堆疊100之間。在一些實施例中，金屬化圖案252具有與金屬化圖案244及248不同的大小。舉例而言，金屬化圖案252的導電線及/或通孔可較金屬化圖案244及248的導電線及/或通孔寬或厚。此外，金屬化圖案252的間距可被形成為較金屬化圖案248大。
然後，在金屬化圖案252及介電層250上沈積介電層254。可以與形成介電層242類似的方式且以類似的材料形成介電層254。
在圖16中，形成凸塊下金屬(under-bump metallurgy，UBM)256以用於外部連接至前側重佈線結構240。UBM 256具有位於介電層254的主表面上且沿著介電層254的主表面延伸的凸塊部分，且具有延伸穿過介電層254以連接至金屬化圖案252的通孔部分。因此，UBM 256電性耦合至導通孔134、154、220。UBM 256可由與金屬化圖案244類似的材料形成。在一些實施例中，UBM 256具有與金屬化圖案244、248、252不同的大小。
然後，在UBM 256上形成導電連接件258。導電連接件258可以是球柵陣列(ball grid array，BGA)連接件、焊球、金屬柱、受控塌陷晶片連接(controlled collapse chip connection，C4)凸塊、微凸塊、由無電鍍鎳鈀浸金技術(electroless nickel-electroless palladium-immersion gold technique，ENEPIG)形成的凸塊等。導電連接件258可包含導電材料，諸如焊料、銅、鋁、金、鎳、銀、鈀、錫等或其組合。在一些實施例中，藉由首先經由蒸鍍、電鍍覆、印刷、焊料轉移、植球等形成焊料層來形成導電連接件258。一旦已在結構上形成焊料層，則可實行回焊以將材料塑形成所期望的凸塊形狀。在另一實施例中，導電連接件258包括藉由濺鍍、印刷、電鍍覆、無電鍍覆、CVD等形成的金屬柱(諸如銅柱)。金屬柱可不含焊料且具有實質上垂直的側壁。在一些實施例中，在金屬 柱的頂部上形成金屬頂蓋層。金屬頂蓋層可包含鎳、錫、錫-鉛、金、銀、鈀、銦、鎳-鈀-金、鎳-金等或其組合且可藉由鍍覆製程形成。
可選地，利用導電連接件258的子集將一或多個整合式被動裝置(integrated passive device，IPD)260連接至UBM 256。IPD 260可以是表面安裝式裝置(surface mount device，SMD)、雙端子整合式被動裝置(IPD)、多端子IPD或其他類型的被動裝置。IPD 260可包括主要結構以及位於所述主要結構中的一或多個被動裝置。主要結構可以是例如半導體基底、包封體等。被動裝置可包括電容器、電阻器、電感器等或其組合，被動裝置可形成於主要結構中及/或形成於主要結構上。可藉由對導電連接件258進行回焊來將IPD 260連接至UBM 256。在一些實施例中(下文關於圖19至圖23B進一步論述)，晶粒堆疊100可包括結合至晶粒堆疊100中的晶粒的被動裝置，且因此可省略IPD 260。在一些實施例中，可在前側重佈線結構240的最頂部介電層(例如，介電層254)與IPD 260中的每一者之間形成底部填充膠(未示出)。
在圖17中，實行載體基底剝離以自背側重佈線結構206(例如，介電層208)拆除(剝離)載體基底202。根據一些實施例，剝離包括將光(諸如，雷射光或UV光)投射於釋放層204上，以使得釋放層204在光的熱量下分解，並可移除載體基底202。然後，可將結構倒置並放置於例如條帶上。
此外，穿過背側重佈線結構206的介電層208形成導電 連接件262。可穿過背側重佈線結構206的介電層208形成開口，從而暴露出金屬化圖案210的一些部分。可例如使用雷射鑽孔、蝕刻等形成開口。在開口中形成導電連接件262，且導電連接件262連接至金屬化圖案210的暴露部分。可以與形成導電連接件258類似的方式且以類似的材料形成導電連接件262。
在圖18A中，藉由沿著切割道區(例如，在封裝區202A周圍)進行切分來實行單體化製程。單體化製程包括切分重佈線結構206、240及包封體222。單體化製程將封裝區202A與相鄰的封裝區(未繪示)分離以形成積體電路封裝200。在單體化之後，重佈線結構206、240與包封體222在側向上毗連。
可將另一積體電路封裝300貼合至積體電路封裝200以形成疊層封裝結構(package-on-package structure)。積體電路封裝300可以是記憶體裝置。積體電路封裝300可在積體電路封裝200被單體化之前或之後貼合至積體電路封裝200。
積體電路封裝300包括基底302以及連接至基底302的一或多個晶粒304。在一些實施例中，晶粒304的一或多個堆疊連接至基底302。基底302可由半導體材料(諸如矽、鍺、金剛石等)製成。在一些實施例中，亦可使用化合物材料，諸如矽鍺、碳化矽、鎵砷、砷化銦、磷化銦、碳化矽鍺、磷化鎵砷、磷化鎵銦、該些材料的組合等。另外，基底302可以是絕緣體上矽(silicon-on-insulator，SOI)基底。通常，SOI基底包含一層半導體材料，諸如磊晶矽、鍺、矽鍺、SOI、絕緣體上矽鍺(silicon germanium on insulator，SGOI)或其組合。在另一實施例中，基底302基於絕緣芯體，諸如玻璃纖維加固樹脂芯體。一個示例性芯體材料是玻璃纖維樹脂，諸如FR4。其他芯體材料包括雙馬來醯亞胺三嗪(bismaleimide-triazine，BT)樹脂、其他印刷電路板(printed circuit board，PCB)材料或膜等。構成膜(諸如，味之素構成膜(Ajinomoto build-up film，ABF))或其他層壓體可用於基底302。
基底302可包括主動裝置及被動裝置(未示出)。熟習此項技術者應認識到，可使用各種各樣的裝置(諸如電晶體、電容器、電阻器、該些的組合等)來產生積體電路封裝300的設計的結構要求及功能要求。可使用任何適合的方法形成所述裝置。基底302亦可包括金屬化層(未示出)及穿孔。金屬化層可形成於主動裝置及被動裝置之上且被設計成連接各種裝置以形成功能電路系統。金屬化層可由交替的電介質(例如，低k介電材料)層及導電材料(例如，銅)層形成且可經由任何適合的製程(諸如沈積、鑲嵌、雙鑲嵌等)形成，其中通孔對導電材料層進行內連。在一些實施例中，基底302實質上不包括主動裝置及被動裝置。
基底302可在基底302的一側上具有連接至導電連接件262的結合接墊306。在一些實施例中，藉由在位於基底302的一側上的介電層(未示出)中形成凹陷(未示出)來形成結合接墊306。可形成凹陷以使得結合接墊306能夠嵌置至介電層中。在其他實施例中，當結合接墊306可形成於介電層上時，省略凹陷。在一些實施例中，結合接墊306包括由銅、鈦、鎳、金、鈀等或其組合製 成的薄晶種層(未示出)。可在薄晶種層之上沈積結合接墊306的導電材料。可藉由電化學鍍覆製程、無電鍍覆製程、CVD、ALD、PVD等或其組合形成導電材料。在實施例中，結合接墊306的導電材料是銅、鎢、鋁、銀、金等或其組合。
在實施例中，結合接墊306是包括三個導電材料層(諸如鈦層、銅層及鎳層)的UBM。舉例而言，結合接墊306可由銅形成，可形成於鈦層(未示出)上，且具有鎳飾面，所述鎳飾面可延長積體電路封裝300的儲放壽命，當積體電路封裝300是記憶體裝置(諸如DRAM模組)時，延長積體電路封裝300的儲放壽命可尤其有利。然而，熟習此項技術者應認識到，存在適合於形成結合接墊306的諸多適合的材料排列及層排列，諸如鉻/鉻-銅合金/銅/金排列、鈦/鈦鎢/銅排列、或銅/鎳/金排列。可用於結合接墊306的任何適合的材料或材料層完全旨在包括於本申請案的範疇內。
在所說明的實施例中，藉由打線結合308將晶粒304連接至基底302，但可使用諸如導電凸塊等其他連接。在實施例中，晶粒304是堆疊式記憶體晶粒。舉例而言，晶粒304可以是記憶體晶粒，諸如低功率(low-power，LP)雙倍資料速率(double data rate，DDR)記憶體模組，諸如LPDDR1、LPDDR2、LPDDR3、LPDDR4等。
可藉由模塑材料310包封晶粒304及打線結合308(當存在時)。可例如使用壓縮模塑將模塑材料310模塑於晶粒304及打線結合308上。在一些實施例中，模塑材料310是模塑化合物、 聚合物、環氧樹脂、氧化矽填料材料等或其組合。可實行固化製程以將模塑材料310固化；固化製程可以是熱固化、UV固化等或其組合。在一些實施例中，晶粒304隱埋於模塑材料310中，且在將模塑材料310固化之後，實行平坦化步驟(諸如研磨)，以移除模塑材料310的多餘部分且為積體電路封裝300提供實質上平坦的表面。
在形成積體電路封裝300之後，藉由導電連接件262將積體電路封裝300貼合至積體電路封裝200。可藉由對導電連接件262進行回焊將導電連接件262連接至結合接墊306。因此，晶粒304可經由導電連接件262、導通孔220及重佈線結構206、240電性耦合至晶粒堆疊100。
在一些實施例中，在基底302的與晶粒304相對的一側上形成阻焊劑(未示出)。導電連接件262可設置於阻焊劑中的開口中以連接至基底302中的導電特徵(例如，結合接墊306)。阻焊劑可用於保護基底302的區域不受外部損壞。
在一些實施例中，在對導電連接件262進行回焊之前，在導電連接件262上形成環氧助焊劑(未示出)，其中在積體電路封裝300貼合至重佈線結構206之後，環氧助焊劑的環氧部分中的至少一些保留下來。
在一些實施例中，底部填充膠312形成於重佈線結構206與基底302之間，且環繞導電連接件262。底部填充膠312可減小應力且保護由對導電連接件262進行回焊而得到的接頭。可在貼 合積體電路封裝300之後藉由毛細流動製程形成底部填充膠312，或者可在貼合積體電路封裝300之前藉由適合的沈積方法形成底部填充膠312。在形成環氧助焊劑的實施例中，環氧助焊劑可用作底部填充膠312。當底部填充膠312在貼合積體電路封裝300之前形成時，底部填充膠312與積體電路封裝200可在側向上毗連。
然後，使用導電連接件258將積體電路封裝200貼合至封裝基底400。封裝基底400可由半導體材料(諸如矽、鍺、金剛石等)製成。作為另外一種選擇，亦可使用化合物材料，諸如矽鍺、碳化矽、鎵砷、砷化銦、磷化銦、碳化矽鍺、磷化鎵砷、磷化鎵銦、該些材料的組合等。另外，封裝基底400可以是SOI基底。通常，SOI基底包含一層半導體材料，諸如磊晶矽、鍺、矽鍺、SOI、SGOI或其組合。在另一實施例中，封裝基底400基於絕緣芯體，諸如玻璃纖維加固樹脂芯體。一個示例性芯體材料是玻璃纖維樹脂，諸如FR4。芯體材料的替代物包括雙馬來醯亞胺三嗪(BT)樹脂，或作為另外一種選擇，包括其他印刷電路板(PCB)材料或膜。構成膜(諸如，味之素構成膜(ABF))或其他層壓體可用於封裝基底400。
封裝基底400可包括主動裝置及被動裝置(未繪示)。裝置(諸如電晶體、電容器、電阻器、該些裝置的組合等)可用於產生系統的設計的結構要求及功能要求。可使用任何適合的方法形成裝置。
封裝基底400亦可包括金屬化層及通孔(未繪示)以及位於金屬化層及通孔之上的結合接墊402。金屬化層可形成於主動 裝置及被動裝置之上且被設計成連接各種裝置以形成功能電路系統。金屬化層可由交替的電介質(例如，低k介電材料)層及導電材料(例如，銅)層形成且可經由任何適合的製程(諸如沈積、鑲嵌、雙鑲嵌等)形成，其中通孔對導電材料層進行內連。在一些實施例中，封裝基底400實質上不包括主動裝置及被動裝置。
對導電連接件258進行回焊以將UBM 256貼合至結合接墊402。導電連接件258將封裝基底400(包括封裝基底400中的金屬化層)連接至積體電路封裝200(包括重佈線結構240的金屬化圖案)。在一些實施例中，表面安裝式被動裝置(例如SMD，未繪示)可貼合至封裝基底400，例如貼合至結合接墊402。
在對導電連接件258進行回焊之前，可在導電連接件258上形成環氧助焊劑(未繪示)，其中在積體電路封裝200貼合至封裝基底400之後，環氧助焊劑的環氧部分中的至少一些保留下來。此剩餘環氧部分可用作底部填充膠以減小應力且保護由對導電連接件258進行回焊而得到的接頭。在一些實施例中，底部填充膠(未繪示)可形成於積體電路封裝200與封裝基底400之間，從而環繞導電連接件258。可在貼合積體電路封裝200之後藉由毛細流動製程形成底部填充膠，或可在貼合積體電路封裝200之前藉由適合的沈積方法形成底部填充膠。
圖18B是根據一些其他實施例的實施晶粒堆疊100的積體電路封裝的剖視圖。在此實施例中，自晶粒堆疊100省略底部填充膠162(參見圖5)。如上文關於圖5及圖6所述，當省略底 部填充膠162時，包封體164可環繞且實體地接觸晶粒連接件122B、晶粒連接件152及可回焊連接件160中的每一者的側壁。此外，當省略底部填充膠162時，包封體164可延伸穿過介電層130。
圖19、圖20、圖21及圖22是根據一些其他實施例的用於形成晶粒堆疊500的製程期間的中間步驟的剖視圖。在此實施例中，晶粒堆疊500的積體電路晶粒不具有TSV，這使得能夠使用較關於圖1至圖18B所論述的實施例厚的積體電路晶粒。因此，晶粒堆疊500中亦可包括其他類型的厚裝置(諸如IPD)。利用可回焊連接件以面對面方式對晶粒堆疊500的積體電路晶粒進行直接結合。說明晶圓102的一個裝置區102A中的積體電路晶粒的堆疊，但應瞭解，晶圓102可具有任何數目個裝置區，且積體電路晶粒可堆疊於每一裝置區中以形成晶粒堆疊。
在圖19中，形成或獲得與關於圖3所論述的中間結構類似的中間結構，但在圖19中介電層130被進一步圖案化成具有開口132C。如下文進一步論述，將在開口132C中放置被動裝置。開口132C暴露出晶粒連接件122C的第三子集，被動裝置將結合至晶粒連接件122C的所述第三子集。
形成或獲得與關於圖4所論述的第二積體電路晶粒140類似的第二積體電路晶粒140。在此實施例中，第二積體電路晶粒140不具有導通孔154(參見圖4)。如此，第二積體電路晶粒140可形成達更大的厚度而不會實質上提高製造成本。因此可增大晶粒堆疊500的總厚度，從而使得晶粒堆疊500能夠容納其他類型 的厚裝置，諸如被動裝置。
形成或獲得被動裝置170。被動裝置170可以是IPD，諸如雙端子整合式被動裝置(IPD)、多端子IPD或另一類型的被動裝置。被動裝置170可形成於晶圓中，晶圓可包括在後續步驟中被單體化以形成多個積體電路晶粒的不同的裝置區。根據可適用的製造製程對被動裝置170進行處理以形成被動電性組件。舉例而言，被動裝置170包括主要結構172及位於主要結構172中的一或多個被動裝置。主要結構172可以是例如半導體基底、包封體等。被動裝置可包括電容器、電阻器、電感器等或其組合，上述被動裝置可形成於主要結構172中及/或形成於主要結構172上。被動裝置170亦可包括接觸接墊176、介電層178、一或多個鈍化層180及晶粒連接件182，所述接觸接墊176、介電層178、一或多個鈍化層180及晶粒連接件182可分別類似於第一積體電路晶粒110的接觸接墊116、介電層118、鈍化層120及晶粒連接件122。晶粒連接件182在被動裝置170的前側170F處暴露出。在將被動裝置170單體化之後，主要結構172、介電層178及鈍化層180在側向上毗連。
在圖20中，將第二積體電路晶粒140放置於開口132B中且結合至第一積體電路晶粒110(例如，晶圓102)，且將被動裝置170放置於開口132C中且結合至第一積體電路晶粒110(例如，晶圓102)。所述結合可類似於關於圖5所論述的結合。具體而言，利用可回焊連接件160A的第一子集以面對面方式對第一積體電 路晶粒110與第二積體電路晶粒140進行直接結合，以使得第一積體電路晶粒110的前側110F結合至第二積體電路晶粒140的前側140F。藉由使可回焊連接件160A接觸晶粒連接件122B及晶粒連接件152並對可回焊連接件160A進行回焊來結合第一積體電路晶粒110與第二積體電路晶粒140。同樣地，亦利用可回焊連接件160B的第二子集以面對面方式對第一積體電路晶粒110與被動裝置170進行直接結合，以使得第一積體電路晶粒110的前側110F結合至被動裝置170的前側170F。藉由使可回焊連接件160B接觸晶粒連接件122C及晶粒連接件182並對可回焊連接件160B進行回焊來結合第一積體電路晶粒110與被動裝置170。利用可回焊連接件160結合第一積體電路晶粒110、第二積體電路晶粒140及被動裝置170使得能夠以較其他結合技術(諸如混合結合)低的成本實行結合。在一些實施例中，諸如藉由利用同一回焊製程對可回焊連接件160A、160B進行回焊來將第二積體電路晶粒140及被動裝置170同時結合至第一積體電路晶粒110。
底部填充膠162可選地形成於第一積體電路晶粒110與第二積體電路晶粒140及被動裝置170中的每一者之間，從而環繞可回焊連接件160A、160B。具體而言，第一底部填充膠162A形成於第一積體電路晶粒110與第二積體電路晶粒140之間，且第二底部填充膠162B形成於第一積體電路晶粒110與被動裝置170之間。可以與關於圖5所論述的方式類似的方式形成底部填充膠162A、162B。
然後，在導通孔134、第二積體電路晶粒140及被動裝置170上及周圍形成包封體164。可以與關於圖6所論述的方式類似的方式形成包封體164。在包封之後，結構的組件被隱埋或覆蓋。
在圖21中，對包封體164實行平坦化製程以暴露出導通孔134、第二積體電路晶粒140的背側140B及被動裝置170的背側170B。平坦化製程可類似於關於圖7所論述的平坦化製程。
在一些實施例中，平坦化製程包括對半導體基底142及主要結構172進行薄化。薄化製程可以是例如化學機械拋光(CMP)、研磨製程、回蝕製程等。在平坦化製程之後，包封體164與介電層130可具有例如處於約70微米至約180微米範圍內(諸如約100微米)的組合厚度。
可選地，可對半導體基底112進行薄化，這可有助於減小晶粒堆疊500的總厚度。薄化製程可以是例如化學機械拋光(CMP)、研磨製程、回蝕製程等，所述薄化製程是在第一積體電路晶粒110的背側110B處實行。在薄化製程之後，半導體基底112可具有例如處於約100微米至約150微米範圍內(諸如約130微米)的厚度。
在圖22中，藉由沿著切割道區(例如，在裝置區102A周圍)進行切分來實行單體化製程。所述單體化製程可類似於關於圖8所論述的單體化製程。單體化製程將晶圓102的裝置區102A(包括第一積體電路晶粒110)與相鄰的裝置區(未繪示)分離以形成晶粒堆疊500。然後，可將被單體化的晶粒堆疊500放置於例 如條帶166上。可選地在第一積體電路晶粒110的背側110B上形成黏合劑168。可以與關於圖8所論述的方式類似的方式形成黏合劑168。
圖23A是根據一些其他實施例的實施晶粒堆疊500的積體電路封裝的剖視圖。可使用與關於圖9至圖17所論述的製程類似的製程將晶粒堆疊500封裝於積體電路封裝600中。積體電路封裝600可以是扇出型封裝，諸如積體扇出型(InFO)封裝。可使用導電連接件262將另一積體電路封裝300貼合至積體電路封裝600以形成疊層封裝結構。積體電路封裝300可類似於關於圖18A所論述的積體電路封裝。然後，使用導電連接件258將積體電路封裝600貼合至封裝基底400以形成完整的系統。封裝基底400可類似於關於圖18A所論述的封裝基底。
如上文所述，晶粒堆疊500包括被動裝置，諸如被動裝置170(參見圖22)。如此，在此實施例中，可省略IPD 260(參見圖18A)。因此，積體電路封裝600可不具有安裝至前側重佈線結構240的被動裝置，諸如SMD。在另一實施例中，晶粒堆疊500可包括被動裝置且積體電路封裝600亦可包括SMD。
圖23B是根據一些其他實施例的實施晶粒堆疊500的積體電路封裝的剖視圖。在此實施例中，自晶粒堆疊500省略底部填充膠162(參見圖5)。如上文關於圖5及圖6所述，當省略底部填充膠162時，包封體164可環繞且實體地接觸晶粒連接件122B、晶粒連接件122C、晶粒連接件152、晶粒連接件182及可回焊連 接件160中的每一者的側壁。此外，當省略底部填充膠162時，包封體164可延伸穿過介電層130。
圖24、圖25、圖26、圖27、圖28及圖29是根據一些其他實施例的用於形成晶粒堆疊700的製程期間的中間步驟的剖視圖。在此實施例中，在不使用可回焊連接件的情況下以背對面方式對晶粒堆疊700的積體電路晶粒進行直接結合。說明晶圓102的一個裝置區102A中的積體電路晶粒的堆疊，但應瞭解，晶圓102可具有任何數目的裝置區，且積體電路晶粒可堆疊於每一裝置區中以形成晶粒堆疊。
在圖24中，形成或獲得晶圓102。晶圓102類似於關於圖1所論述的晶圓，但晶粒連接件122是鈍化後內連線(post passivation interconnect，PPI)。因此，晶粒連接件122包括延伸穿過鈍化層120的第一部分，且亦包括沿著鈍化層120延伸的第二部分。如下文進一步論述，使用是PPI的晶粒連接件使得更多的導通孔134能夠形成於晶粒堆疊700中。
在圖25中，在晶圓102上(諸如在晶粒連接件122及鈍化層120上)形成介電層130。可以與關於圖2所論述的方式類似的方式形成介電層130。然後，形成穿過介電層130而遠離晶圓102延伸的導通孔134。可以與關於圖3所論述的方式類似的方式形成導通孔134。由於晶粒連接件122是PPI，因此晶粒連接件122可有助於重新分配跨越晶粒堆疊700的面積的由導通孔134引發的應力。因此，與在關於圖3及圖19所論述的實施例中相比，可 在晶粒堆疊700中形成更多的導通孔134。當形成更多的導通孔134時，導通孔134可具有較關於圖3及圖19所論述的導通孔134細小的節距。舉例而言，導通孔134可被形成為節距處於約40微米至約80微米範圍內。
在圖26中，形成或獲得第二積體電路晶粒140。第二積體電路晶粒140類似於關於圖4所論述的第二積體電路晶粒140，但圖26的第二積體電路晶粒140不具有導通孔154(參見圖4)，且圖26的第二積體電路晶粒140包括位於前側140F處且覆蓋晶粒連接件152的另一介電層156。第二積體電路晶粒140的背側140B在導通孔134之中放置於介電層130上，且利用黏合劑158結合至介電層130。黏合劑158形成於第二積體電路晶粒140的背側140B上。黏合劑158可以是任何適合的黏合劑、環氧樹脂、晶粒貼合膜(DAF)等。在所示的實施例中，在進行單體化以將第二積體電路晶粒140分離之前將黏合劑158施加至第二積體電路晶粒140的背側140B。
利用黏合劑158以背對面方式對第一積體電路晶粒110與第二積體電路晶粒140進行直接結合。可以較其他結合技術(諸如混合結合)低的成本實行此結合。由於晶粒的定向，將使用導通孔134來將第一積體電路晶粒110與第二積體電路晶粒140電性耦合。因此，晶粒堆疊700可需要較晶粒堆疊100(參見圖8)或晶粒堆疊500(參見圖22)多的導通孔134來容納第一積體電路晶粒110的I/O連接件。如上文所述，由於晶粒連接件122是PPI， 因此可在晶粒堆疊700中形成更多的導通孔134且可實現背對面結合。
在圖27中，在導通孔134及第二積體電路晶粒140上及周圍形成包封體164。可以與關於圖6所論述的方式類似的方式形成包封體164。
在圖28中，對包封體164及介電層156實行平坦化製程以暴露出第二積體電路晶粒140的導通孔134及晶粒連接件152。平坦化製程可類似於關於圖7所論述的平坦化製程。在平坦化製程之後，介電層156的剩餘部分環繞晶粒連接件152。
可選地，可對半導體基底112進行薄化，這可有助於減小晶粒堆疊500的總厚度。薄化製程可以是例如化學機械拋光(CMP)、研磨製程、回蝕製程等，所述薄化製程是在第一積體電路晶粒110的背側110B處實行。在薄化製程之後，半導體基底112可具有例如處於約50微米至約90微米範圍中(諸如約70微米)的厚度。
在圖29中，藉由沿著切割道區(例如，在裝置區102A周圍)進行切分來實行單體化製程。單體化製程可類似於關於圖8所論述的單體化製程。單體化製程將晶圓102的裝置區102A(包括第一積體電路晶粒110)與相鄰的裝置區(未繪示)分離以形成晶粒堆疊700。然後，可將被單體化的晶粒堆疊700放置於例如條帶166上。可選地，在第一積體電路晶粒110的背側110B上形成黏合劑168。可以與關於圖8所論述的方式類似的方式形成黏合劑 168。
圖30是根據一些其他實施例的實施晶粒堆疊700的積體電路封裝的剖視圖。可使用與關於圖9至圖17所論述的製程類似的製程將晶粒堆疊700封裝於積體電路封裝800中。積體電路封裝800可以是扇出型封裝，諸如積體扇出型(InFO)封裝。前側重佈線結構240的金屬化圖案將第一積體電路晶粒110與第二積體電路晶粒140電性耦合。在一些實施例中，晶粒堆疊700不具有被動裝置。在該些實施例中，IPD 260可連接至UBM 256。IPD 260可類似於關於圖16所論述的IPD 260。可使用導電連接件262將另一積體電路封裝300貼合至積體電路封裝800以形成疊層封裝結構。積體電路封裝300可類似於關於圖18A所論述的積體電路封裝300。然後，使用導電連接件258將積體電路封裝800貼合至封裝基底400以形成完整的系統。封裝基底400可類似於關於圖18A所論述的封裝基底400。
實施例可達成若干優點。藉由利用可回焊連接件或黏合劑對積體電路晶粒110、140進行結合來形成晶粒堆疊100、500、700可使得能夠以較其他結合技術(諸如混合結合)低的成本實行結合。當晶粒堆疊是低效能裝置時，可尤其期望以較低的成本形成晶粒堆疊100、500、700。此外，儘管混合結合可使得晶粒堆疊100、500、700能夠具有更細小的晶粒連接件節距或更大的輸入/輸出(I/O)連接件計數，但在晶粒堆疊是低效能裝置時，該些特徵可能並不必要。一些實施例亦可使得能夠以低成本方式將被動裝置 包括於積體電路封裝中。
亦可包括其他特徵及製程。舉例而言，可包括測試結構以輔助對三維(three-dimensional，3D)封裝或三維積體電路(three-dimensional integrated circuit，3DIC)裝置進行驗證測試。所述測試結構可包括例如形成於重佈線層中或基底上的測試接墊(test pad)，以使得能對3D封裝或3DIC進行測試、使用探針及/或探針卡(probe card)等。可對中間結構以及最終結構實行驗證測試。另外，本文中所揭露的結構及方法可與包含對已知良好晶粒進行中間驗證的測試方法結合使用以提高良率並降低成本。
在實施例中，一種結構包括：第一積體電路晶粒，包括第一晶粒連接件；第一介電層，位於所述第一晶粒連接件上；第一導通孔，延伸穿過所述第一介電層，所述第一導通孔連接至所述第一晶粒連接件的第一子集；第二積體電路晶粒，利用第一可回焊連接件結合至所述第一晶粒連接件的第二子集；第一包封體，環繞所述第二積體電路晶粒及所述第一導通孔，所述第一包封體與所述第一積體電路晶粒在側向上毗連；第二導通孔，與所述第一積體電路晶粒相鄰；第二包封體，環繞所述第二導通孔、所述第一包封體及所述第一積體電路晶粒；以及第一重佈線結構，包括第一重佈線線，所述第一重佈線線連接至所述第一導通孔及所述第二導通孔。
在一些實施例中，所述結構更包括：底部填充膠，環繞所述第一可回焊連接件及所述第一晶粒連接件的所述第二子集中的每一者，所述底部填充膠延伸穿過所述第一介電層。在所述結構 的一些實施例中，所述第一包封體具有環繞所述第一可回焊連接件及所述第一晶粒連接件的所述第二子集中的每一者的第一部分，所述第一包封體的所述第一部分延伸穿過所述第一介電層。在所述結構的一些實施例中，所述第二積體電路晶粒包括：基底穿孔(TSV)，所述第一重佈線結構的所述第一重佈線線連接至所述TSV；以及障壁層，環繞所述TSV，所述障壁層接觸所述第一重佈線結構的第二介電層。在所述結構的一些實施例中，所述第二積體電路晶粒不具有TSV，且所述結構更包括：被動裝置，利用第二可回焊連接件結合至所述第一晶粒連接件的第三子集，所述第一包封體環繞所述被動裝置。在所述結構的一些實施例中，所述第一包封體包含第一模塑材料，所述第二包封體包含第二模塑材料，且所述第一模塑材料不同於所述第二模塑材料。在所述結構的一些實施例中，所述第一模塑材料包含粒徑小於所述第二模塑材料的填料。在一些實施例中，所述結構更包括：第二重佈線結構，包括第二重佈線線，所述第二重佈線線連接至所述第二導通孔；記憶體裝置，連接至所述第二重佈線結構的所述第二重佈線線；以及封裝基底，連接至所述第一重佈線結構的所述第一重佈線線。在一些實施例中，所述結構更包括：表面安裝式被動裝置，連接至所述第一重佈線結構的所述第一重佈線線。
根據本發明的一些實施例，其中：所述的封裝結構，更包括：底部填充膠，環繞所述第一可回焊連接件及所述第一晶粒連接件的所述第二子集中的每一者，所述底部填充膠延伸穿過所述 第一介電層。
根據本發明的一些實施例，其中：其中所述第一包封體具有環繞所述第一可回焊連接件及所述第一晶粒連接件的所述第二子集中的每一者的第一部分，所述第一包封體的所述第一部分延伸穿過所述第一介電層。
根據本發明的一些實施例，其中：其中所述第二積體電路晶粒包括：基底穿孔(TSV)，所述第一重佈線結構的所述第一重佈線線連接至所述基底穿孔；以及障壁層，環繞所述基底穿孔，所述障壁層接觸所述第一重佈線結構的第二介電層。
根據本發明的一些實施例，其中：其中所述第二積體電路晶粒不具有基底穿孔，所述結構更包括：被動裝置，利用第二可回焊連接件結合至所述第一晶粒連接件的第三子集，所述第一包封體環繞所述被動裝置。
根據本發明的一些實施例，其中：其中所述第一包封體包含第一模塑材料，所述第二包封體包含第二模塑材料，且所述第一模塑材料不同於所述第二模塑材料。
根據本發明的一些實施例，其中：其中所述第一模塑材料包含粒徑小於所述第二模塑材料的填料。
根據本發明的一些實施例，其中：所述的封裝結構，更包括：第二重佈線結構，包括第二重佈線線，所述第二重佈線線連接至所述第二導通孔；記憶體裝置，連接至所述第二重佈線結構的所述第二重佈線線；以及封裝基底，連接至所述第一重佈線結構的 所述第一重佈線線。
根據本發明的一些實施例，其中：所述的封裝結構，更包括：表面安裝式被動裝置，連接至所述第一重佈線結構的所述第一重佈線線。
在實施例中，一種結構包括：第一積體電路晶粒，包括鈍化後內連線(PPI)；介電層，位於所述PPI上；第一導通孔，延伸穿過所述介電層，所述第一導通孔連接至所述PPI；第二積體電路晶粒，包括半導體基底及晶粒連接件，所述半導體基底利用黏合劑結合至所述介電層；第一包封體，環繞所述第二積體電路晶粒及所述第一導通孔，所述第一包封體與所述第一積體電路晶粒在側向上毗連；第二導通孔，與所述第一積體電路晶粒相鄰；第二包封體，環繞所述第二導通孔、所述第一包封體及所述第一積體電路晶粒；以及第一重佈線結構，包括第一重佈線線，所述第一重佈線線連接至所述第一導通孔、所述晶粒連接件及所述第二導通孔。
在所述結構的一些實施例中，所述第一包封體包含第一模塑材料，所述第二包封體包含第二模塑材料，且所述第一模塑材料不同於所述第二模塑材料。在所述結構的一些實施例中，所述第一模塑材料包含粒徑小於所述第二模塑材料的填料。在一些實施例中，所述結構更包括：第二重佈線結構，包括第二重佈線線，所述第二重佈線線連接至所述第二導通孔；記憶體裝置，連接至所述第二重佈線結構的所述第二重佈線線；以及封裝基底，連接至所述第一重佈線結構的所述第一重佈線線。在一些實施例中，所述結構 更包括：表面安裝式被動裝置，連接至所述第一重佈線結構的所述第一重佈線線。
根據本發明的一些實施例，其中：其中所述第一包封體包含第一模塑材料，所述第二包封體包含第二模塑材料，且所述第一模塑材料不同於所述第二模塑材料。
根據本發明的一些實施例，其中：其中所述第一模塑材料包含粒徑小於所述第二模塑材料的填料。
根據本發明的一些實施例，其中：所述的封裝結構，更包括：第二重佈線結構，包括第二重佈線線，所述第二重佈線線連接至所述第二導通孔；記憶體裝置，連接至所述第二重佈線結構的所述第二重佈線線；以及封裝基底，連接至所述第一重佈線結構的所述第一重佈線線。
根據本發明的一些實施例，其中：所述的封裝結構，更包括：表面安裝式被動裝置，連接至所述第一重佈線結構的所述第一重佈線線。
在實施例中，一種方法包括：在第一積體電路晶粒上形成第一導通孔；利用第一可回焊連接件將第二積體電路晶粒結合至所述第一積體電路晶粒，所述第二積體電路晶粒與所述第一導通孔相鄰；利用第一模塑化合物包封所述第一導通孔及所述第二積體電路晶粒；將所述第一模塑化合物及所述第一積體電路晶粒單體化以形成晶粒堆疊；將所述晶粒堆疊與所述第二導通孔相鄰地放置，利用第二模塑化合物包封所述第二導通孔及所述晶粒堆 疊；以及在所述第二模塑化合物及所述晶粒堆疊上形成第一重佈線結構，所述第一重佈線結構包括第一重佈線線，所述第一重佈線線連接至所述第一導通孔及所述第二導通孔。
在所述方法的一些實施例中，所述第一積體電路晶粒包括第一晶粒連接件，所述第二積體電路晶粒包括第二晶粒連接件，且所述將所述第二積體電路晶粒結合至所述第一積體電路晶粒包括：在所述第一積體電路晶粒上沈積介電層；將所述介電層圖案化成具有第一開口，所述第一開口暴露出所述第一晶粒連接件的第一子集；將所述第二積體電路晶粒放置於所述第一開口中；以及利用所述第一可回焊連接件將所述第二晶粒連接件連接至所述第一晶粒連接件的所述第一子集。在一些實施例中，所述方法更包括：將所述介電層圖案化成具有第二開口，所述第二開口暴露出所述第一晶粒連接件的第二子集；將被動裝置放置於所述第二開口中，所述被動裝置包括第三晶粒連接件；以及利用第二可回焊連接件將所述第三晶粒連接件連接至所述第一晶粒連接件的所述第二子集。在所述方法的一些實施例中，所述第二積體電路晶粒包括半導體基底及延伸穿過所述半導體基底的基底穿孔(TSV)，且所述方法更包括：在利用所述第二模塑化合物包封所述第二導通孔及所述晶粒堆疊之後，將所述第二模塑化合物平坦化，其中所述第一導通孔、所述第二導通孔及所述TSV在所述平坦化之後被暴露出。在所述方法的一些實施例中，所述平坦化包括：利用第一研磨製程對所述第二模塑化合物進行薄化，以暴露出所述半導體基底；利用 第二研磨製程對所述半導體基底進行薄化，所述第二研磨製程具有較所述第一研磨製程小的移除速率；以及利用第三研磨製程對所述半導體基底進行薄化，以暴露出所述基底穿孔，所述第三研磨製程具有較所述第二研磨製程小的移除速率。在一些實施例中，所述方法更包括：在所述第三研磨製程之後，使所述半導體基底凹陷以暴露出所述基底穿孔的側壁部分；以及圍繞所述TSV的所述側壁部分沈積障壁層。
根據本發明的一些實施例，其中：其中所述第一積體電路晶粒包括第一晶粒連接件，所述第二積體電路晶粒包括第二晶粒連接件，且所述將所述第二積體電路晶粒結合至所述第一積體電路晶粒包括：在所述第一積體電路晶粒上沈積介電層；將所述介電層圖案化成具有第一開口，所述第一開口暴露出所述第一晶粒連接件的第一子集；將所述第二積體電路晶粒放置於所述第一開口中；以及利用所述第一可回焊連接件將所述第二晶粒連接件連接至所述第一晶粒連接件的所述第一子集。
根據本發明的一些實施例，其中：所述的方法，更包括：將所述介電層圖案化成具有第二開口，所述第二開口暴露出所述第一晶粒連接件的第二子集；將被動裝置放置於所述第二開口中，所述被動裝置包括第三晶粒連接件；以及利用第二可回焊連接件將所述第三晶粒連接件連接至所述第一晶粒連接件的所述第二子集。
根據本發明的一些實施例，其中：其中所述第二積體電路晶粒包括半導體基底及延伸穿過所述半導體基底的基底穿孔(TSV)，且所述方法更包括：在利用所述第二模塑化合物包封所述第二導通孔及所述晶 粒堆疊之後，將所述第二模塑化合物平坦化，其中所述第一導通孔、所述第二導通孔及所述基底穿孔在所述平坦化之後被暴露出。
根據本發明的一些實施例，其中：所述的方法，其中所述平坦化包括：利用第一研磨製程對所述第二模塑化合物進行薄化，以暴露出所述半導體基底；利用第二研磨製程對所述半導體基底進行薄化，所述第二研磨製程具有較所述第一研磨製程小的移除速率；以及利用第三研磨製程對所述半導體基底進行薄化，以暴露出所述基底穿孔，所述第三研磨製程具有較所述第二研磨製程小的移除速率。
根據本發明的一些實施例，其中：所述的方法，更包括：在所述第三研磨製程之後，使所述半導體基底凹陷以暴露出所述基底穿孔的側壁部分；以及圍繞所述基底穿孔的所述側壁部分沈積障壁層。
前述內容概述了數個實施例的特徵，以使熟習此項技術者可更佳地理解本揭露的各個態樣。熟習此項技術者應瞭解，他們可容易地使用本揭露作為設計或修改其他製程及結構的基礎來施行與本文中所介紹的實施例相同的目的及/或達成與本文中所介紹的實施例相同的優點。熟習此項技術者亦應意識到，該些等效構造並不背離本揭露的精神及範疇，而且他們可在不背離本揭露的精神及範疇的情況下對其作出各種改變、代替及變更。
100:晶粒堆疊
220:導通孔
312:底部填充膠
222:包封體
200、300:積體電路封裝
206:背側重佈線結構/重佈線結構
240:前側重佈線結構/重佈線結構
256:凸塊下金屬
258、262:導電連接件
260:整合式被動裝置
302:基底
304:晶粒
306、402:結合接墊
308:打線結合
310:模塑材料
400:封裝基底

Claims (10)

  1. 一種封裝結構，包括：第一積體電路晶粒，包括第一晶粒連接件；第一介電層，位於所述第一晶粒連接件上；第一導通孔，延伸穿過所述第一介電層，所述第一導通孔連接至所述第一晶粒連接件的第一子集；第二積體電路晶粒，利用第一可回焊連接件結合至所述第一晶粒連接件的第二子集；第一包封體，環繞所述第二積體電路晶粒及所述第一導通孔；第二導通孔，與所述第一積體電路晶粒相鄰；第二包封體，環繞所述第二導通孔、所述第一包封體及所述第一積體電路晶粒；第一重佈線結構，包括第一重佈線線，所述第一重佈線線連接至所述第一導通孔及所述第二導通孔；第二重佈線結構設置於所述第一積體電路晶粒的背側；以及黏合劑設置於所述第一積體電路晶粒的所述背側，且所述黏合劑位於所述第一積體電路晶粒與所述第二重佈線結構之間，其中所述黏合劑、所述第一包封體與所述第一積體電路晶粒在側向上毗連。
  2. 如請求項1所述的封裝結構，更包括：底部填充膠，環繞所述第一可回焊連接件及所述第一晶粒連接件的所述第二子集中的每一者，所述底部填充膠延伸穿過所述 第一介電層。
  3. 如請求項1所述的封裝結構，其中所述第一包封體具有環繞所述第一可回焊連接件及所述第一晶粒連接件的所述第二子集中的每一者的第一部分，所述第一包封體的所述第一部分延伸穿過所述第一介電層。
  4. 如請求項1所述的封裝結構，其中所述第二積體電路晶粒包括：基底穿孔(TSV)，所述第一重佈線結構的所述第一重佈線線連接至所述基底穿孔；以及障壁層，環繞所述基底穿孔，所述障壁層接觸所述第一重佈線結構的第二介電層。
  5. 如請求項1所述的封裝結構，其中所述第二積體電路晶粒不具有基底穿孔，所述結構更包括：被動裝置，利用第二可回焊連接件結合至所述第一晶粒連接件的第三子集，所述第一包封體環繞所述被動裝置。
  6. 一種封裝結構，包括：第一積體電路晶粒，包括鈍化後內連線(PPI)；介電層，位於所述鈍化後內連線上；第一導通孔，延伸穿過所述介電層，所述第一導通孔連接至所述鈍化後內連線；第二積體電路晶粒，包括半導體基底及晶粒連接件，所述半導體基底利用第一黏合劑結合至所述介電層； 第一包封體，環繞所述第二積體電路晶粒及所述第一導通孔，所述第一包封體與所述第一積體電路晶粒在側向上毗連；第二導通孔，與所述第一積體電路晶粒相鄰；第二包封體，環繞所述第二導通孔、所述第一包封體及所述第一積體電路晶粒；第一重佈線結構，包括第一重佈線線，所述第一重佈線線連接至所述第一導通孔、所述晶粒連接件及所述第二導通孔，第二重佈線結構設置於所述第一積體電路晶粒的背側；以及第二黏合劑設置於所述第一積體電路晶粒的所述背側，且所述第二黏合劑位於所述第一積體電路晶粒與所述第二重佈線結構之間，其中所述第二黏合劑、所述第一包封體與所述第一積體電路晶粒在側向上毗連。
  7. 如請求項1或6所述的封裝結構，其中所述第一包封體包含第一模塑材料，所述第二包封體包含第二模塑材料，且所述第一模塑材料不同於所述第二模塑材料。
  8. 如請求項1或6所述的封裝結構，更包括：所述第二重佈線結構，包括第二重佈線線，所述第二重佈線線連接至所述第二導通孔；記憶體裝置，連接至所述第二重佈線結構的所述第二重佈線線；以及封裝基底，連接至所述第一重佈線結構的所述第一重佈線線。
  9. 一種形成封裝結構的方法，包括：在第一積體電路晶粒上形成第一導通孔；利用第一可回焊連接件將第二積體電路晶粒結合至所述第一積體電路晶粒，所述第二積體電路晶粒與所述第一導通孔相鄰；利用第一模塑化合物包封所述第一導通孔及所述第二積體電路晶粒；將所述第一模塑化合物及所述第一積體電路晶粒單體化以形成晶粒堆疊；將所述晶粒堆疊放置於第二重佈線結構上，且所述晶粒堆疊與所述第二導通孔相鄰地放置，其中所述晶粒堆疊的背側透過黏合劑黏合至所述第二重佈線結構，且所述黏合劑位於所述晶粒堆疊與所述第二重佈線結構之間，其中所述黏合劑、所述第一包封體與所述晶粒堆疊在側向上毗連；利用第二模塑化合物包封所述第二導通孔及所述晶粒堆疊；以及在所述第二模塑化合物及所述晶粒堆疊上形成第一重佈線結構，所述第一重佈線結構包括第一重佈線線，所述第一重佈線線連接至所述第一導通孔及所述第二導通孔。
  10. 如請求項9所述的方法，其中所述第一積體電路晶粒包括第一晶粒連接件，所述第二積體電路晶粒包括第二晶粒連接件，且所述將所述第二積體電路晶粒結合至所述第一積體電路晶粒包括： 在所述第一積體電路晶粒上沈積介電層；將所述介電層圖案化成具有第一開口，所述第一開口暴露出所述第一晶粒連接件的第一子集；將所述第二積體電路晶粒放置於所述第一開口中；以及利用所述第一可回焊連接件將所述第二晶粒連接件連接至所述第一晶粒連接件的所述第一子集。
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Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10460987B2 (en) * 2017-05-09 2019-10-29 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor package device with integrated antenna and manufacturing method thereof
US11264362B2 (en) * 2020-05-28 2022-03-01 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structure and method of fabricating the same
US11521931B2 (en) * 2020-06-16 2022-12-06 Intel Corporation Microelectronic structures including bridges
US11373972B2 (en) 2020-06-16 2022-06-28 Intel Corporation Microelectronic structures including bridges
US11923307B2 (en) 2020-06-16 2024-03-05 Intel Corporation Microelectronic structures including bridges
US11791274B2 (en) 2020-06-16 2023-10-17 Intel Corporation Multichip semiconductor package including a bridge die disposed in a cavity having non-planar interconnects
US11804441B2 (en) 2020-06-16 2023-10-31 Intel Corporation Microelectronic structures including bridges
US11887962B2 (en) 2020-06-16 2024-01-30 Intel Corporation Microelectronic structures including bridges
US11637055B2 (en) * 2020-08-03 2023-04-25 Advanced Semiconductor Engineering, Inc. Semiconductor device package
DE102020122323A1 (de) * 2020-08-26 2022-03-03 Infineon Technologies Ag Chip mit chip-pad und zugehörigem lotflussmittel-ausgasungsgraben
US11894357B2 (en) * 2020-09-10 2024-02-06 Sj Semiconductor (Jiangyin) Corporation System-level packaging structure and method for LED chip
TWI756094B (zh) * 2021-03-31 2022-02-21 力成科技股份有限公司 封裝結構及其製造方法
US20230063261A1 (en) * 2021-08-30 2023-03-02 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and manufacturing method thereof

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160049385A1 (en) * 2014-08-15 2016-02-18 Taiwan Semiconductor Manufacturing Company, Ltd. Packages and methods of manufacture thereof
US20190214347A1 (en) * 2018-01-10 2019-07-11 Powertech Technology Inc. Semiconductor package and manufacturing method thereof

Family Cites Families (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8759964B2 (en) 2007-07-17 2014-06-24 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer level package structure and fabrication methods
US8097489B2 (en) * 2009-03-23 2012-01-17 Stats Chippac, Ltd. Semiconductor device and method of mounting pre-fabricated shielding frame over semiconductor die
EP2557597A4 (en) 2010-04-07 2014-11-26 Shimadzu Corp RADIATION DETECTOR AND METHOD FOR MANUFACTURING SAME
US9048233B2 (en) 2010-05-26 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Package systems having interposers
US8361842B2 (en) 2010-07-30 2013-01-29 Taiwan Semiconductor Manufacturing Company, Ltd. Embedded wafer-level bonding approaches
US8884431B2 (en) 2011-09-09 2014-11-11 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods and structures for semiconductor devices
US9064879B2 (en) 2010-10-14 2015-06-23 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods and structures using a die attach film
US8829676B2 (en) 2011-06-28 2014-09-09 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structure for wafer level package
US8816404B2 (en) * 2011-09-16 2014-08-26 Stats Chippac, Ltd. Semiconductor device and method of forming stacked semiconductor die and conductive interconnect structure through an encapsulant
US9000584B2 (en) 2011-12-28 2015-04-07 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor device with a molding compound and a method of forming the same
US8680647B2 (en) 2011-12-29 2014-03-25 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with passive devices and methods of forming the same
US9991190B2 (en) * 2012-05-18 2018-06-05 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging with interposer frame
US8703542B2 (en) 2012-05-18 2014-04-22 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer-level packaging mechanisms
US8809996B2 (en) 2012-06-29 2014-08-19 Taiwan Semiconductor Manufacturing Company, Ltd. Package with passive devices and method of forming the same
US9030010B2 (en) 2012-09-20 2015-05-12 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging devices and methods
US8785299B2 (en) 2012-11-30 2014-07-22 Taiwan Semiconductor Manufacturing Company, Ltd. Package with a fan-out structure and method of forming the same
US8803306B1 (en) 2013-01-18 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out package structure and methods for forming the same
US8778738B1 (en) 2013-02-19 2014-07-15 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor devices and packaging devices and methods
US9378982B2 (en) * 2013-01-31 2016-06-28 Taiwan Semiconductor Manufacturing Company, Ltd. Die package with openings surrounding end-portions of through package vias (TPVs) and package on package (PoP) using the die package
US8970023B2 (en) * 2013-02-04 2015-03-03 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and methods of forming same
US9263511B2 (en) 2013-02-11 2016-02-16 Taiwan Semiconductor Manufacturing Co., Ltd. Package with metal-insulator-metal capacitor and method of manufacturing the same
US9048222B2 (en) 2013-03-06 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating interconnect structure for package-on-package devices
US9368460B2 (en) 2013-03-15 2016-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out interconnect structure and method for forming same
US8877554B2 (en) 2013-03-15 2014-11-04 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor devices, methods of packaging semiconductor devices, and PoP devices
US9570322B2 (en) * 2014-11-26 2017-02-14 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit packages and methods of forming same
US9984998B2 (en) * 2016-01-06 2018-05-29 Taiwan Semiconductor Manufacturing Company, Ltd. Devices employing thermal and mechanical enhanced layers and methods of forming same
US10269702B2 (en) * 2016-01-29 2019-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Info coil structure and methods of manufacturing same
US10541226B2 (en) * 2016-07-29 2020-01-21 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and method of forming the same
US10224254B2 (en) * 2017-04-26 2019-03-05 Powertech Technology Inc. Package process method including disposing a die within a recess of a one-piece material
US10510718B2 (en) * 2017-08-28 2019-12-17 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and manufacturing method thereof
US10510650B2 (en) 2018-02-02 2019-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacturing semiconductor device packaging structure having through interposer vias and through substrate vias

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160049385A1 (en) * 2014-08-15 2016-02-18 Taiwan Semiconductor Manufacturing Company, Ltd. Packages and methods of manufacture thereof
US20190214347A1 (en) * 2018-01-10 2019-07-11 Powertech Technology Inc. Semiconductor package and manufacturing method thereof

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