CN112687670B - 集成电路结构及其形成方法 - Google Patents

集成电路结构及其形成方法 Download PDF

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Publication number
CN112687670B
CN112687670B CN202011106428.6A CN202011106428A CN112687670B CN 112687670 B CN112687670 B CN 112687670B CN 202011106428 A CN202011106428 A CN 202011106428A CN 112687670 B CN112687670 B CN 112687670B
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processor device
dielectric layer
shared memory
integrated circuit
conductive via
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CN112687670A (zh
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余振华
张维麟
王垂堂
陈颉彦
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

在实施例中，一种结构包括：图形处理器器件；无源器件，耦合至图形处理器器件，该无源器件直接面对面地接合至图形处理器器件；共享存储器器件，耦合至图形处理器器件，共享存储器器件直接面对面地接合至图形处理器器件；中央处理器器件，耦合至共享存储器器件，中央处理器器件直接背对背地接合至共享存储器器件，中央处理器器件和图形处理器器件的每个具有比共享存储器器件小的技术节点的有源器件；以及再分布结构，耦合至中央处理器器件、共享存储器器件、无源器件和图形处理器器件。本发明的实施例还涉及集成电路结构及其形成方法。

Description

集成电路结构及其形成方法
技术领域
本发明的实施例涉及集成电路结构及其形成方法。
背景技术
随着半导体技术的不断发展，集成电路管芯变得越来越小。此外，更多功能正在集成到管芯中。因此，管芯所需的输入/输出(I/O)焊盘的数量增大，而可用于I/O焊盘的面积减小。I/O焊盘的密度随着时间迅速提高，增加了管芯封装的难度。一些应用要求更大的集成电路管芯的并行处理能力。封装技术可以用于集成多个管芯，允许更大程度的并行处理能力。
在一些封装技术中，集成电路管芯是在封装之前从晶圆分割出来的。这种封装技术的优点是可以形成扇出封装件，这允许将管芯上的I/O焊盘再分布到更大的区域。管芯的表面上的I/O焊盘的数量因此可以增加。
发明内容
本发明的实施例提供了一种集成电路结构，包括：第一处理器器件，具有前侧；共享存储器器件，具有前侧和与前侧相对的后侧，所述共享存储器器件的前侧通过金属至金属接合和电介质至电介质接合接合至所述第一处理器器件的前侧；第一介电层，横向地围绕所述共享存储器器件；第一导电通孔，延伸穿过所述第一介电层；第二处理器器件，具有前侧和与前侧相对的后侧，所述第一导电通孔将所述第一处理器器件的前侧连接至所述第二处理器器件的后侧，所述第二处理器器件的后侧通过金属至金属接合接合至所述第一导电通孔和所述共享存储器器件的后侧，所述第二处理器器件的后侧通过电介质至电介质接合接合至所述第一介电层，所述第一处理器器件和所述第二处理器器件的每个是不同类型的处理器器件；以及第一再分布结构，连接至所述第二处理器器件的前侧。
本发明的另一实施例提供了一种集成电路结构，包括：图形处理器器件；无源器件，耦合至所述图形处理器器件，所述无源器件直接面对面地接合至所述图形处理器器件；共享存储器器件，耦合至所述图形处理器器件，所述共享存储器器件直接面对面地接合至所述图形处理器器件；中央处理器器件，耦合至所述共享存储器器件，所述中央处理器器件直接背对背地接合至所述共享存储器器件，所述中央处理器器件和所述图形处理器器件的每个具有比所述共享存储器器件小的技术节点的有源器件；以及再分布结构，耦合至所述中央处理器器件、所述共享存储器器件、所述无源器件和所述图形处理器器件。
本发明的又一实施例提供了一种形成集成电路结构的方法，包括：将共享存储器器件接合至第一处理器器件；在所述共享存储器器件周围形成第一介电层；形成延伸穿过所述第一介电层的第一导电通孔，所述第一导电通孔连接至所述第一处理器器件；将第二处理器器件接合至所述第一导电通孔、所述第一介电层和所述共享存储器器件，所述第一处理器器件和所述第二处理器器件的每个是不同类型的处理器器件；在所述第二处理器器件周围形成第二介电层；形成延伸穿过所述第二介电层的第二导电通孔，所述第二导电通孔连接至所述共享存储器器件；形成延伸穿过所述第一介电层和所述第二介电层的第三导电通孔，所述第三导电通孔连接至所述第一处理器器件；以及在所述第二导电通孔、所述第三导电通孔、所述第二介电层和所述第二处理器器件上形成再分布结构。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本发明的各个方面。应该强调，根据工业中的标准实践，各个部件未按比例绘制并且仅用于说明的目的。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1A、图1B、图1C和图1D是根据一些实施例的半导体器件的截面图。
图2A、图2B、图2C和图2D是根据一些实施例的集成电路封装件的各种视图。
图3A、图3B、图4A、图4B、图5A、图5B、图6A、图6B、图7A、图7B、图8A和图8B是根据一些实施例的在形成集成电路封装件的工艺期间的中间步骤的截面图。
图9A和图9B是根据一些实施例的集成电路封装件的截面图。
图10和图11是根据一些实施例的在形成实现集成电路封装件的系统的工艺期间的中间步骤的截面图。
图12、图13、图14、图15和图16是根据一些实施例的在形成用于实现集成电路封装件的系统的工艺期间的中间步骤的截面图。
图17是根据一些实施例的实现集成电路封装件的系统的截面图。
具体实施方式
以下公开提供了许多用于实现本发明的不同特征的不同的实施例或实例。下面描述了组件和布置的具体实施例或实例以简化本发明。当然，这些仅是实例而不旨在限制。例如，在以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成附加部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可以在各个示例中重复参考数字和/或字母。该重复是为了简单和清楚的目的，并且其本身不指示讨论的各个实施例和/或配置之间的关系。
此外，为了便于描述，本文中可以使用诸如“在…下方”、“在…下面”、“下部”、“在…上面”、“上部”等的间距关系术语，以描述如图中所示的一个元件或部件与另一元件或部件的关系。除了图中所示的方位外，间距关系术语旨在包括器件在使用或操作工艺中的不同方位。装置可以以其它方式定位(旋转90度或在其它方位)，并且在本文中使用的间距关系描述符可以同样地作相应地解释。
根据一些实施例，集成电路封装件包括夹在两种不同类型的处理器器件之间的存储器器件，所述两种不同类型的处理器器件诸如是图形处理单元和中央处理单元。在操作期间，两个处理器器件共享存储器器件。半导体器件通过混合接合而接合。如下面进一步描述的，可以通过混合接合的直接连接而不是通过再分布结构的数据信号线来完成集成电路封装件的半导体器件之间的数据信令。虽然集成电路封装件可以形成有再分布结构，但是通过混合接合使管芯互连允许减少再分布结构中的数据信号线的数量。
图1A至图1D是根据一些实施例的半导体器件的截面图。具体地，图1A、图1B、图1C和图1D分别示出了第一处理器器件20、第二处理器器件40、存储器器件60和无源器件80。将在随后的处理中封装半导体器件以形成集成电路封装件，诸如片上系统(SoIC)器件。每个半导体器件可以是裸集成电路管芯或封装管芯。在所示的实施例中，每个半导体器件是裸集成电路管芯。在其他实施例中，一个或多个所示的半导体器件可以是密封的封装管芯。
参考图1A，第一处理器器件20可以是任何可接受的处理器或逻辑器件，诸如图形处理单元(GPU)、中央处理单元(CPU)、片上系统(SoC)、应用处理器(AP)、数字信号处理(DSP)、现场可编程门阵列(FPGA)、微控制器、人工智能(AI)加速器等。可以根据适用的制造工艺来处理第一处理器器件20以形成集成电路。例如，第一处理器器件20包括半导体衬底22，诸如掺杂或未掺杂的硅或者绝缘体上半导体(SOI)衬底的有源层。半导体衬底22可以包括诸如锗的其他半导体材料；化合物半导体，包括碳化硅、砷化镓、磷化镓、磷化铟、砷化铟和/或锑化铟；合金半导体，包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP；或它们的组合。也可以使用其他衬底，诸如多层或梯度衬底。半导体衬底22具有有源表面22A和无源表面22N。
可以在半导体衬底22的有源表面22A处形成器件。该器件可以是有源器件(例如，晶体管、二极管等)、电容器、电阻器等。无源表面22N可以没有器件。层间电介质(ILD)位于半导体衬底22的有源表面22A上方。ILD围绕并且可以覆盖器件。ILD可以包括由诸如磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、硼掺杂的磷硅酸盐玻璃(BPSG)、未掺杂的硅酸盐玻璃(USG)等的材料形成的一个或多个介电层。
互连结构24位于半导体衬底22的有源表面22A上方。互连结构24互连半导体衬底22的有源表面22A处的器件以形成集成电路。互连结构24可以由例如介电层中的金属化图案形成。金属化图案包括形成在一个或多个介电层中的金属线和通孔。互连结构24的金属化图案电连接至半导体衬底22的有源表面22A处的器件。
管芯连接件28位于第一处理器器件20的前侧20F处。管芯连接件28可以是形成外部连接的导电柱、焊盘等。管芯连接件28位于互连结构24中和/或上，并且可以由诸如铜、铝等的金属形成。管芯连接件28可以通过例如镀等形成。
介电层30位于第一处理器器件20的前侧20F处，诸如位于互连结构24上。介电层30横向密封管芯连接件28，并且介电层30与第一处理器器件20的侧壁横向共末端。最初，介电层30可以掩埋管芯连接件28，使得介电层30的最顶部表面位于管芯连接件28的最顶部表面之上。介电层30可以是聚合物，诸如PBO、聚酰亚胺、BCB等；氮化物，诸如氮化硅等；氧化物，诸如氧化硅、PSG、BSG、BPSG等；等或它们的组合。介电层30可以例如通过旋涂、层压、化学气相沉积(CVD)等形成。在形成之后，可以使用例如化学机械抛光(CMP)工艺、回蚀刻工艺等或它们的组合来平坦化管芯连接件28和介电层30。在平坦化之后，管芯连接件28和介电层30的表面是齐平的，并且在第一处理器器件20的前侧20F处暴露。
参考图1B，第二处理器器件40可以是任何可接受的处理器或逻辑器件，诸如中央处理单元(CPU)、图形处理单元(GPU)、片上系统(SoC)、应用处理器(AP)、数字信号处理(DSP)、现场可编程门阵列(FPGA)、微控制器、人工智能(AI)加速器等。可以根据适用的制造工艺来处理第二处理器器件40以形成集成电路。例如，第二处理器器件40包括半导体衬底42，该半导体衬底42具有有源表面42A和无源表面42N。半导体衬底42可以类似于半导体衬底22。第二处理器器件40还包括位于第二处理器器件40的前侧40F处的互连结构44。互连结构44可以类似于互连结构24。第二处理器器件40还包括导电通孔46，该导电通孔46形成为在半导体衬底42的有源表面42A和无源表面42N之间延伸。导电通孔46有时也称为衬底通孔或硅通孔(TSV)。导电通孔46物理和电连接至互连结构44的金属化图案。
作为形成导电通孔46的示例，可以通过例如蚀刻、研磨、激光技术、它们的组合等在半导体衬底42中形成凹槽。可以诸如通过使用氧化技术在凹槽中形成薄介电材料。可以诸如通过CVD、原子层沉积(ALD)、物理气相沉积(PVD)、热氧化、它们的组合等，将薄的阻挡层共形地沉积在半导体衬底42的有源表面42A上方和开口中。阻挡层可以由氧化物、氮化物或氮氧化物形成，诸如氮化钛、氮氧化钛、氮化钽、氮氧化钽、氮化钨、它们的组合等。可以将导电材料沉积在阻挡层上方和开口中。可以通过电化学镀工艺、CVD、ALD、PVD、它们的组合等形成导电材料。导电材料的示例是铜、钨、铝、银、金、它们的组合等。通过例如CMP从半导体衬底42的有源表面42A去除过量的导电材料和阻挡层。阻挡层和导电材料的剩余部分形成导电通孔46。
在半导体衬底42的无源表面42N上形成管芯连接件48和介电层50。管芯连接件48可以由与管芯连接件28类似的材料并且通过与管芯连接件28类似的方法形成。管芯连接件48物理连接至导电通孔46，并且通过导电通孔46电连接至第二处理器器件40的集成电路。介电层50可以由与介电层30类似的材料和类似的方法形成。在形成管芯连接件48和介电层50之前，可以研磨半导体衬底42的无源表面42N以暴露导电通孔46。在形成之后，可以使用例如CMP工艺、回蚀刻工艺等或它们的组合来平坦化管芯连接件48和介电层50。在平坦化之后，管芯连接件48和介电层50的表面是齐平的，并且在第二处理器器件40的后侧40B处暴露。
参考图1C，存储器器件60可以是任何可接受的存储器器件，诸如动态随机存取存储器(DRAM)器件、静态随机存取存储器(SRAM)器件、电阻式随机存取存储器(RRAM)器件、磁阻随机存取存储器(MRAM)器件、相变随机存取存储器(PCRAM)器件等。可以根据适用的制造工艺来处理存储器器件60以形成集成电路。例如，存储器器件60包括半导体衬底62，该半导体衬底62具有有源表面62A和无源表面62N。半导体衬底62可以类似于半导体衬底22。存储器器件60还包括互连结构64、管芯连接件68和介电层70，它们可以分别类似于互连结构24、导电通孔46、管芯连接件28和介电层30。管芯连接件68和介电层70在存储器器件60的前侧60F处暴露。
存储器器件60还包括导电通孔66。在所示的实施例中，导电通孔66尚未在存储器器件60的后侧60B处暴露。相反，导电通孔66被掩埋在半导体衬底62中。如下面进一步讨论的，在随后的处理中，导电通孔66将通过平坦化工艺在存储器器件60的后侧60B处暴露。
参考图1D，无源器件80可以是任何可接受的无源器件，诸如集成无源器件(IPD)、电源管理集成电路(PMIC)、集成调压器(IVR)等。可以根据适用的制造工艺来处理无源器件80以形成集成电路。例如，无源器件80包括半导体衬底82，半导体衬底82可以类似于半导体衬底22，但是还包括无源器件(例如，电阻器、电容器、电感器等)并且没有有源器件(例如，晶体管、二极管等)。无源器件80还包括互连结构84、管芯连接件88和介电层90，它们可以分别类似于互连结构24、管芯连接件28和介电层30。管芯连接件88和介电层90在无源器件80的前侧80F处暴露。
无源器件80还包括导电通孔86，导电通孔86可以类似于导电通孔46。在所示的实施例中，导电通孔86尚未在无源器件80的后侧80B处暴露。导电通孔86被掩埋在半导体衬底82中。如下文进一步讨论的，导电通孔86将在随后的处理中通过平坦化工艺在无源器件80的后侧80B处暴露。
可以对第一处理器器件20、第二处理器器件40、存储器器件60和/或无源器件80执行芯片探针(CP)测试，以确定该器件是否是已知良好管芯(KGD)。因此，只有属于KGD的器件才经受后续处理并且被封装，而未通过CP测试的器件则不经受后续处理并且不被封装。
图2A至图2D是根据一些实施例的集成电路封装件100的各种视图。集成电路封装件100包括通过例如混合接合而接合在一起的器件的堆叠件。集成电路封装件100可以是异构器件，诸如集成芯片上系统(SoIC)器件。下面将参考图3A至图8B进一步描述用于形成集成电路封装件100的工艺。
图2A和图2B是集成电路封装件100的截面图。图2C是三维图，示出了集成电路封装件100的半导体器件之间的电连接。图2D是集成电路封装件100的的顶视图，示出半导体器件的定位。图2A沿着图2C和图2D中的参考横截面A-A示出，并且图2B沿着图2C和图2D中的参考横截面B-B示出。横截面B-B垂直于横截面A-A。为了图示清楚，第一处理器器件20、第二处理器器件40、存储器器件60和无源器件80的一些部件未在图2A和图2B中标记，而是分别在图1A、图1B、图1C和图1D中标记。此外，为了图示清楚，从图2C和图2D中省略了一些部件。
集成电路封装件100包括第一处理器器件20、第二处理器器件40、存储器器件60和可选的无源器件80。根据一些实施例，第一处理器器件20和第二处理器器件40是不同类型的处理器器件。例如，第一处理器器件20可以是图形处理器器件，而第二处理器器件40可以是中央处理器器件。此外，存储器器件60电耦合至第一处理器器件20和第二处理器器件40中的每个，并且包括由一个或两个处理器器件使用的存储器。例如，存储器器件60可以是共享存储器器件，诸如共享3级(L3)高速缓存、嵌入式DRAM(eDRAM)等。使用单独的存储器器件60代替包括具有第一处理器器件20和/或第二处理器器件40的存储器，可以允许增加集成电路封装件100中的存储器的总量而不显著增加处理器器件的制造成本。此外，形成没有存储器的第一处理器器件20和/或第二处理器器件40允许在处理器器件中包括更多的处理单元(例如，核)，而基本上不增加处理器器件的占用面积。
第一处理器器件20、第二处理器器件40和存储器器件60可以具有不同技术节点的有源器件。具体地，第一处理器器件20和第二处理器器件40的每个可以具有比存储器器件60小的技术节点的有源器件。例如，第一处理器器件20和第二处理器器件40的每个可以包括7nm技术节点的有源器件，并且存储器器件60可以包括16nm技术节点的有源器件。以更大的技术节点形成存储器器件60允许降低存储器器件60的制造成本。
集成电路封装件100还包括再分布结构102(下面进一步描述)。再分布结构102包括介电层中的金属化图案。再分布结构102的金属化图案电耦合至集成电路封装件100的半导体器件。具体地，再分布结构102的金属化图案包括电源源线(VDD)和电源接地线(VSS)，它们与第一处理器器件20、第二处理器器件40、存储器器件60和无源装置80中的每个电耦合以形成用于半导体器件的电力输送网络。在无源器件80是PMIC的实施例中，它也可以是第一处理器器件20的电力输送网络的一部分。在一些实施例中，第一处理器器件20具有其自己的PMIC，并且不连接至无源器件80。
再分布结构102的金属化图案还包括直接连接至第二处理器器件40的前侧40F的数据信号线。在第二处理器器件40是中央处理器器件的实施例中，将第二处理器器件40的前侧40F直接连接到再分布结构102的金属化图案可以帮助增加到中央处理器器件的输入/输出(I/O)连接的数量。此外，再分布结构102的金属化图案可以将热量从第二处理器器件40传导走，这在第二处理器器件40是具有大散热的器件(诸如中央处理器器件)时尤其有利。
如以下进一步描述的，集成电路封装件100的半导体器件之间的数据信令可以通过半导体器件之间的直接连接(例如，金属至金属接合)而不是通过再分布结构102的数据信号线来实现。因此，可以减少再分布结构102中的数据信号线的数量。
介电层(下面进一步描述)位于集成电路封装件100的一些半导体器件周围，从而保护半导体器件。导电通孔(下面进一步描述)延伸穿过介电层，从而允许集成电路封装件100的半导体器件的互连。具体地，第一介电层104横向地围绕存储器器件60和无源器件80，并且第一导电通孔106延伸穿过第一介电层104。第一导电通孔106将第一处理器器件20的前侧20F连接至第二处理器器件40的后侧40B。类似地，第二介电层108横向围绕第二处理器器件40，并且第二导电通孔110延伸穿过第二介电层108。第二导电通孔110将再分布结构102连接至存储器器件60的后侧60B和无源器件80的后侧80B。一些导电通孔延伸穿过多个介电层。具体地，第三导电通孔112延伸穿过第一介电层104和第二介电层108两者。第三导电通孔112将再分布结构102连接至第一处理器器件20的前侧20F。在一些实施例中，第二导电通孔110和第三导电通孔112电耦合至再分布结构102的电源源线(VDD)和电源接地线(VSS)，并且提供至集成电路封装件100的半导体器件的电源和接地连接。在一些实施例中，第二导电通孔110和第三导电通孔112中的一些也电耦合至再分布结构102的数据信号线。
集成电路封装件100的半导体器件可以具有不同的尺寸，使得它们不会同心地彼此重叠，从而为连接至导电通孔106、110、112和再分布结构102提供了足够的空间。具体地，半导体器件的宽度在不同的截面图中可以不同。
在第一平面(例如，图2A所示的横截面)中，存储器器件60比第二处理器器件40窄，并且在第二平面(例如，图2B中所示的横截面)中，存储器器件60比第二处理器器件40宽。例如，参考图2D，存储器器件60可以具有宽度W1和W2，并且第二处理器器件40可以具有宽度W3和W4，其中宽度W1大于宽度W3，并且宽度W2小于宽度W4。
在第一平面(例如，图2A所示的横截面)中，无源器件80比第二处理器器件40窄，并且在第二平面(例如，图2B中所示的横截面)中，无源器件80比第二处理器器件40宽。例如，参考图2D，无源器件80可以具有宽度W5和W6，其中宽度W5大于宽度W3，并且宽度W6小于宽度W4。
在第一平面(例如，图2A中所示的横截面)和第二平面(例如，图2B中所示的横截面)中，第一处理器器件20比第二处理器器件40、存储器器件60和无源器件80宽。例如，参考图2D，第一处理器器件20可以具有宽度W7和W8，其中宽度W7大于宽度W1、W3和W5中的每个，并且宽度W8大于宽度W2、W4和W6中的每个。
存储器器件60设置在第一处理器器件20和第二处理器器件40之间，并且接合至两个处理器器件。第一处理器器件20直接面对面地接合至存储器器件60。例如，第一处理器器件20的前侧20F可以通过混合接合(例如，通过金属至金属接合和电介质至电介质接合)接合至存储器器件60的前侧60F。第二处理器器件40直接背对背接合至存储器器件60。例如，第二处理器器件40的后侧40B可以通过混合接合(例如，通过金属至金属接合和电介质至电介质接合)接合至存储器器件60的后侧60B。第二处理器器件40也接合至集成电路封装件100的其他部件。具体地，第二处理器器件40直接接合至第一介电层104的部分和一些第一导电通孔106。例如，第二处理器器件40的后侧40B可以通过电介质至电介质接合而接合至第一介电层104的一部分，并且第二处理器器件40的后侧40B也可以通过金属至金属接合而接合至一些第一导电通孔106。
在包括无源器件80的实施例中，无源器件80接合至第一处理器器件20。无源器件80直接面对面地接合至第一处理器器件20。例如，无源器件80的前侧80F可以通过混合接合(例如，通过金属至金属接合以及通过电介质至电介质接合)接合至第一处理器器件20的前侧20F。无源器件80横向地设置在第二处理器器件40的占用区域的外部，并且未接合至第二处理器器件40。
在封装之后，第一处理器器件20和第二处理器器件40可以通过多个部件互连。第一处理器器件20和第二处理器器件40可以通过第一导电通孔106直接通信。此外，由于直接接合产生的互连，第一处理器器件20和第二处理器器件40可以通过存储器器件60间接通信。具体地，第一处理器器件20和第二处理器器件40可以通过互连结构64和存储器器件60的导电通孔66进行通信。半导体器件之间的数据信令是通过这些互连来执行的，这些互连短于再分布结构102的再分布线。因此，可以减小集成电路封装件100的半导体器件之间的数据信令的延迟和互连带宽。此外，还可以减小连接的阻抗并因此减小连接的功耗。
图3A至图8B是根据一些实施例的在形成集成电路封装件100的工艺期间的中间步骤的截面图。图3A、图4A、图5A、图6A、图7A和图8A是沿着图2C和图2D中的参考横截面A-A的截面图。图3B、图4B、图5B、图6B、图7B和图8B是沿着图2C和图2D中的参考横截面B-B的截面图。集成电路封装件100是通过在未分割的晶圆120上堆叠器件而形成的。示出了在晶圆120的一个器件区域120A中堆叠器件，但是应当理解，晶圆120可以具有任何数量的器件区域，并且器件可以堆叠在每个器件区域中。
在图3A和图3B中，获得晶圆120。晶圆120包括位于器件区域120A中的第一处理器器件20。这样，晶圆120的器件区域120A具有与第一处理器器件20类似的部件。第一处理器器件20将在随后的处理中被分割(见图8A和图8B)，以包括在集成电路封装件100中。
存储器器件60接合至第一处理器器件20(例如，至晶圆120)。第一处理器器件20和存储器器件60通过混合接合以面对面的方式直接接合，其中第一处理器器件20的介电层30通过电介质至电介质接合而接合至存储器器件60的介电层70，而无需使用任何粘合剂材料(例如，管芯附接膜)，并且其中第一处理器器件20的管芯连接件28通过金属至金属接合而接合至存储器器件60的管芯连接件68，而无需使用任何共晶材料(例如，焊料)。
接合可以包括预接合和退火。在预接合期间，施加小的压力以将第一处理器器件20和存储器器件60彼此按压。在诸如室温的低温下，诸如在约15℃至约30℃的范围内的温度下执行预接合，并且在预接合之后，将介电层30和70彼此接合。然后在随后的退火步骤中提高接合强度，在该退火步骤中，在高温下(诸如在约100℃至约450℃范围内的温度)对介电层30和70进行退火。在退火之后，形成直接接合，诸如熔融接合，以接合介电层30和70。例如，接合可以是介电层30的材料和介电层70的材料之间的共价键。管芯连接件28和68以一一对应的方式彼此物理和电连接。管芯连接件28和68可以在预接合之后物理接触，或者可以在退火期间膨胀以物理接触。此外，在退火期间，管芯连接件28和68的材料(例如，铜)混合，使得也形成金属至金属接合。因此，第一处理器器件20与存储器器件60之间的所得接合为混合接合，其包括电介质至电介质接合和金属至金属接合。
无源器件80可选地接合至第一处理器器件20(例如，至晶圆120)。第一处理器器件20和无源器件80通过混合接合以面对面的方式直接接合，其中第一处理器器件20的介电层30通过电介质至电介质接合而接合至无源器件80的介电层90，而无需使用任何粘合剂材料(例如，管芯附接膜)，并且其中，第一处理器器件20的管芯连接件28通过金属至金属接合而接合至无源器件80的管芯连接件88，而无需使用任何共晶材料(例如，焊料)。混合接合可以类似于如上所述的第一处理器器件20和存储器器件60的接合。
在图4A和图4B中，围绕存储器器件60和无源器件80形成第一介电层104。可以在放置存储器器件60和无源器件80之后但在完成混合接合的退火之前形成第一介电层104，或者可以在退火后形成第一介电层104。第一介电层104填充存储器器件60和无源器件80之间的间隙，从而保护半导体器件。第一介电层104可以是氧化物，诸如氧化硅、PSG、BSG、BPSG等；氮化物，诸如氮化硅等；聚合物，诸如聚苯并恶唑(PBO)、聚酰亚胺、苯并环丁烯(BCB)等；密封剂，诸如模塑料、环氧树脂等；等或它们的组合。在一些实施例中，第一介电层104是氧化物，诸如氧化硅。
然后，形成第一导电通孔106以延伸穿过第一介电层104。作为形成第一导电通孔106的示例，在第一介电层104中图案化开口。图案化可以通过可接受的工艺进行，诸如当第一介电层104是光敏材料时，通过将第一介电层104暴露于光，或者通过使用例如各向异性蚀刻来蚀刻第一介电层104。开口暴露第一处理器器件20的管芯连接件28。在第一介电层104上以及管芯连接件28的由开口暴露的部分上形成晶种层。在一些实施例中，晶种层是金属层，其可以是单层或包括由不同材料形成的多个子层的复合层。在特定实施例中，晶种层包括钛层和位于钛层上方的铜层。可以使用例如PVD等形成晶种层。在晶种层上形成导电材料。可以通过诸如电镀或化学镀等的镀来形成导电材料。导电材料可以包括金属，诸如铜、钛、钨、铝等。然后去除晶种层和导电材料的过量部分，其中过量部分是位于第一介电层104上面的部分。可以通过平坦化工艺去除。对晶种层、导电材料、第一介电层104以及半导体衬底62和82执行平坦化工艺。该去除同时去除晶种层和导电材料的过量部分，并且暴露出导电通孔66和86。平坦化工艺可以例如是CMP工艺、研磨工艺、回蚀刻工艺等或它们的组合。开口中的晶种层和导电材料的剩余部分形成第一导电通孔106。在平坦化工艺之后，第一介电层104、第一导电通孔106、半导体衬底62和82以及导电通孔66和86的顶面是齐平的。
在图5A和图5B中，第二处理器器件40接合至存储器器件60、第一导电通孔106和第一介电层104。第二处理器器件40和存储器器件60通过混合接合以背对背的方式直接接合。因为第二处理器器件40和存储器器件60不同心地彼此重叠，所以第一导电通孔106和第一介电层104的一些部分参与了混合接合。具体地，第二处理器器件40的介电层50通过电介质至电介质接合而接合至第一介电层104的部分，而不使用任何粘合剂材料(例如，管芯附接膜)。同样地，第二处理器器件40的管芯连接件48通过金属至金属接合而接合至第一导电通孔106和存储器器件60的导电通孔66，而无需使用任何共晶材料(例如，焊料)。混合接合可以类似于如上所述的第一处理器器件20和存储器器件60的接合。因为第一介电层104参与混合接合，所以即使没有暴露存储器器件60的介电部件，也可以形成到第二处理器器件40的强电介质至电介质接合。
在图6A和图6B中，围绕第二处理器器件40形成第二介电层108。可以在放置第二处理器器件40之后但是在退火以完成混合接合之前形成第二介电层108，或者可以在退火之后形成第二介电层108。第二介电层108可以由与第一介电层104类似的材料并且通过与第一介电层104类似的方法形成。在一些实施例中，第二介电层108是诸如氧化硅的氧化物。
然后，形成第二导电通孔110以延伸穿过第二介电层108并且连接至导电通孔66和86。第二导电通孔110可以由与第一导电通孔106类似的材料和类似的方法形成。然后，形成第三导电通孔112以延伸穿过第一介电层104和第二介电层108并且连接至管芯连接件28。第三导电通孔112可以由与第一导电通孔106类似的材料和类似的方法形成，除了可以穿过第一介电层104和第二介电层108图案化用于第三导电通孔112的开口之外。在一些实施例中，第二导电通孔110和第三导电通孔112同时形成。在第二导电通孔110和/或第三导电通孔112的形成期间，可以执行平坦化工艺。在平坦化工艺之后，第二介电层108、第二导电通孔110、第三导电通孔112和第二处理器器件40的顶面是齐平的。
在图7A和图7B中，再分布结构102形成在第二介电层108、第二导电通孔110、第三导电通孔112和第二处理器器件40上。再分布结构102包括多个介电层、金属化图案和通孔。例如，再分布结构102可以被图案化为通过相应的介电层彼此分隔开的多个离散的金属化图案。在一些实施例中，介电层由聚合物形成，该聚合物可以是光敏材料，诸如PBO、聚酰亚胺、BCB等，可以使用光刻掩模来图案化。在其他实施例中，介电层由以下材料形成：氮化物，诸如氮化硅；氧化物，诸如氧化硅、PSG、BSG、BPSG；等。介电层可以通过旋涂、层压、CVD等或它们的组合来形成。在形成之后，图案化介电层以暴露下面的导电部件。例如，图案化底部介电层以暴露互连结构44的金属化图案的部分，并且图案化中间介电层以暴露下面的金属化图案的部分。可以通过可接受的工艺进行图案化，诸如当介电层是光敏材料时通过将介电层暴露于光，或者通过使用例如各向异性蚀刻来进行蚀刻。如果介电层是光敏材料，则可以在曝光之后显影介电层。
形成沿着和穿过每个介电层延伸的金属化图案。晶种层(未示出)形成在每个相应的介电层上方以及穿过相应的介电层的开口中。在一些实施例中，晶种层是金属层，其可以是单层或包括由不同材料形成的多个子层的复合层。在一些实施例中，晶种层包括钛层和位于钛层上方的铜层。可以使用诸如PVD等的沉积工艺来形成晶种层。然后在晶种层上形成光刻胶并且图案化光刻胶。可以通过旋涂等形成光刻胶，并且可以将光刻胶曝光以用于图案化。光刻胶的图案对应于金属化图案。图案化形成穿过光刻胶的开口以暴露出晶种层。在光刻胶的开口中和晶种层的暴露部分上形成导电材料。可以通过诸如电镀或化学镀等的镀来形成导电材料。导电材料可以包括金属或金属合金，诸如铜、钛、钨、铝等或它们的组合。然后，去除光刻胶和晶种层的其上未形成导电材料的部分。可以通过可接受的灰化或剥离工艺，诸如使用氧等离子体等，来去除光刻胶。一旦去除了光刻胶，就去除晶种层的暴露部分，诸如通过使用可接受的蚀刻工艺，诸如通过湿或干蚀刻。晶种层和导电材料的剩余部分形成用于再分布结构102的一层的金属化图案。
再分布结构102示出为示例。通过重复或省略上述步骤，可以在再分布结构102中形成比图示更多或更少的介电层和金属化图案。
在图8A和图8B中，通过沿着划线区域(例如在器件区域120A周围)进行锯切来执行分割工艺。分割工艺包括锯切再分布结构102、第一介电层104、第二介电层108和晶圆120。分割工艺将器件区域120A(包括第一处理器器件20)与晶圆120的相邻器件区域(未示出)分隔开，以形成包括第一处理器器件20的集成电路封装件100。存储器器件60以面对面的方式接合至第一处理器器件20，并且存储器器件60以背对背的方式接合至第二处理器器件40，无需使用焊料。因此，所得到的集成电路封装件100没有焊料。在分割之后，再分布结构102、第一介电层104、第二介电层108和第一处理器器件20横向共末端。
图9A和图9B是根据一些实施例的集成电路封装件100的截面图。沿着图2C和图2D中的参考横截面A-A示出了图9A。沿着图2C和图2D中的参考横截面B-B示出图9B。在该实施例中，第一处理器器件20不是裸露的集成电路管芯，而是封装的管芯。可以通过获得包括第一处理器器件20的晶圆，锯切晶圆以分割第一处理器器件20，然后用密封剂32密封第一处理器器件20来形成第一处理器器件20。然后可以在密封的第一处理器器件20上堆叠集成电路封装件100的其他半导体器件。
图10和图11是根据一些实施例的在形成实现集成电路封装件100的系统的工艺期间的中间步骤的截面图。图10和图11是沿着图2C和图2D中的参考横截面B-B示出的。在该实施例中，集成电路封装件100直接安装到封装衬底。
在图10中，导电连接件114形成为物理地并且电连接至再分布结构102。导电连接件114可以在分割集成电路封装件100之前或之后形成。可以图案化再分布结构102的顶部介电层以暴露出下面的金属化图案的部分。在一些实施例中，可以在开口中形成凸块下金属(UBM)。导电连接件114形成在UBM上。导电连接件114可以是球栅阵列(BGA)连接件、焊球、金属柱、可控塌陷芯片连接(C4)凸块、微凸块、化学镀镍钯浸金技术(ENEPIG)形成的凸块等。导电连接件114可以由金属或金属合金形成，诸如焊料、铜、铝、金、镍、银、钯、锡等或它们的组合。在一些实施例中，通过最初使用诸如蒸发、电镀、印刷、焊料转移、球放置等的常用方法形成一层焊料来形成导电连接件114。一旦在结构上形成焊料层，就可以执行回流以将材料成形为所需的凸块形状。在另一个实施例中，导电连接件114是通过溅射、印刷、电镀、化学镀、CVD等形成的金属柱(诸如铜柱)。金属柱可以是无焊料的并且具有基本垂直的侧壁。导电连接件114电耦合至再分布结构102的金属化图案。
在图11中，将集成电路封装件100翻转并且使用导电连接件114连接至封装衬底200。封装衬底200可以由诸如硅、锗、金刚石等的半导体材料制成。可选地，也可以使用诸如硅锗、碳化硅、砷化镓、砷化铟、磷化铟、碳化硅锗、磷砷化镓、磷化铟镓、它们的组合等的化合物。另外，封装衬底200可以是SOI衬底。通常，SOI衬底包括诸如外延硅、锗、硅锗、SOI、SGOI或它们的组合的半导体材料层。在一个可选实施例中，封装衬底200基于诸如玻璃纤维增强树脂芯的绝缘芯。一种示例芯材料是玻璃纤维树脂，诸如FR4。芯材的替代材料包括双马来酰亚胺三嗪(BT)树脂，或者可选地其他印刷电路板(PCB)材料或膜。诸如味之素堆积膜(ABF)的堆积膜或其他层压件可以用于封装衬底200。
封装衬底200可以包括有源和无源器件(未示出)。诸如晶体管、电容器、电阻器、这些的组合等的器件可以用于生成系统的设计的结构和功能要求。可以使用任何合适的方法来形成器件。
封装衬底200还可以包括金属化层和通孔(未示出)以及位于金属化层和通孔上方的接合焊盘202。金属化层可以形成在有源和无源器件上方，并且设计为连接各种器件以形成功能电路。金属化层可以由电介质(例如低k介电材料)和导电材料(例如铜)的交替层形成，具有将导电材料层互连的通孔，并且可以通过任何合适的工艺(诸如沉积、镶嵌、双镶嵌等)形成。在一些实施例中，封装衬底200基本上没有有源和无源器件。
使导电连接件114回流，以将再分布结构102的UBM附接至接合焊盘202。导电连接件114将包括封装衬底200中的金属化层的封装衬底200电和/或物理连接至集成电路封装件100。在一些实施例中，无源器件(例如，表面安装器件(SMD)，未示出)可以在安装到封装衬底200上之前附接至集成电路封装件100(例如，接合至接合焊盘202)。在这样的实施例中，无源器件可以与导电连接件114接合至集成电路封装件100的同一表面上。在一些实施例中，无源器件(例如，SMD，未示出)可以附接至封装衬底200，例如，至接合焊盘202。
在导电连接件114回流之前，可以在其上形成环氧焊剂(未示出)，其中在集成电路封装件100附接至封装衬底200之后剩余环氧焊剂的环氧部分中的至少一些。该剩余的环氧树脂部分可以用作底部填充物，以减小应力并保护由导电连接件114回流产生的接头。在一些实施例中，底部填充物(未示出)可以形成在集成电路封装件100和封装衬底200之间，围绕导电连接件114。底部填充物可以在附接集成电路封装件100之后通过毛细管流动工艺形成，或者可以在附接集成电路封装件100之前通过适当的沉积方法形成。
图12至图16是根据一些其他实施例的在形成用于实现集成电路封装件100的系统的工艺期间的中间步骤的截面图。沿着图2C和图2D中的参考横截面B-B示出了图12至图16。在该实施例中，集成电路封装件100被分割并且被包括在封装组件中。示出了一个封装区域302A中的器件的封装，但是应当理解，可以同时形成任何数量的封装区域。封装区域302A将在后续处理中被分割。分割的封装组件可以是扇出封装件，诸如集成扇出(InFO)封装件。然后将扇出封装件安装至封装衬底。
在图12中，提供了载体衬底302，并且在载体衬底302上形成释放层304。载体衬底302可以是玻璃载体衬底、陶瓷载体衬底等。载体衬底302可以是晶圆，使得可以在载体衬底302上同时形成多个封装件。释放层304可以由基于聚合物的材料形成，释放层304可以与载体衬底302一起从将在后续步骤中形成的上面的结构去除。在一些实施例中，释放层304是基于环氧树脂的热释放材料，其在加热时失去其粘合性，诸如光热转换(LTHC)释放涂层。在其他实施例中，释放层304可以是紫外线(UV)胶，当暴露于UV光时其失去粘合性。释放层304可以以液体的形式分配并固化，可以是层压到载体衬底302上的层压膜等。释放层304的顶面可以是齐平的并且可以具有高度的平面度。
可以在释放层304上形成再分布结构306。可以以与关于图7A和图7B描述的再分布结构102类似的方式和类似的材料形成再分布结构306。再分布结构306包括介电层和金属化图案(有时称为再分布层或再分布线)。在再分布结构306中可以形成比图示更多或更少的介电层和金属化图案。再分布结构306是可选的。在一些实施例中，代替再分布结构306，在释放层304上形成没有金属化图案的介电层。
在图13中，形成导电通孔308，其延伸穿过再分布结构306的最顶部介电层。因此，导电通孔308连接至再分布结构306的金属化图案。导电通孔308是可选的，并且可以省略。例如，在省略再分布结构306的实施例中，可以(或可以不)省略导电通孔308。
作为形成导电通孔308的示例，可以在再分布结构306的最顶部介电层中形成开口。然后在再分布结构306上方(例如在再分布的最顶部介电层上和由开口暴露的再分布结构306的金属化图案的部分上)形成晶种层。在一些实施例中，晶种层是金属层，其可以是单层或包括由不同材料形成的多个子层的复合层。在特定实施例中，晶种层包括钛层和位于钛层上方的铜层。可以使用例如PVD等形成晶种层。在晶种层上形成光刻胶并且图案化光刻胶。可以通过旋涂等形成光刻胶，并且可以将光刻胶曝光以用于图案化。光刻胶的图案对应于导电通孔。图案化形成穿过光刻胶的开口以暴露出晶种层。在光刻胶的开口中和晶种层的暴露部分上形成导电材料。可以通过诸如电镀或化学镀等的镀来形成导电材料。导电材料可以包括金属，例如铜、钛、钨、铝等。去除光刻胶和晶种层的其上未形成导电材料的部分。可以通过可接受的灰化或剥离工艺，诸如使用氧等离子体等，来去除光刻胶。一旦去除了光刻胶，就去除晶种层的暴露部分，诸如通过使用可接受的蚀刻工艺，诸如通过湿或干蚀刻。晶种层和导电材料的剩余部分形成导电通孔308。
将分割的集成电路封装件100放置在再分布结构306上。在所示的实施例中，获得了与关于图8A和图8B所述的结构类似的结构。在另一个实施例中，获得类似于关于图9A和图9B描述的结构。如上所述，在集成电路封装件100中，器件彼此接合而不使用焊料。因此，分割的集成电路封装件100没有焊料。
在图14中，密封剂310形成在集成电路封装件100周围。密封剂310横向地围绕集成电路封装件100。密封剂310可以是模塑料、环氧树脂等。可以通过压缩模制、传递模制等来施加密封剂310，并且可以以液体或半液体形式来施加密封剂310，然后进行固化。
在一些实施例中，密封剂310形成在集成电路封装件100上方，使得再分布结构102被掩埋或覆盖。可以对密封剂310执行平坦化工艺以暴露集成电路封装件100。平坦化工艺可以去除密封剂310的材料，直到暴露出再分布结构102。在平坦化工艺之后，密封剂310和再分布结构102的顶面是共面的。平坦化工艺可以是例如CMP工艺、研磨工艺、回蚀刻工艺等或它们的组合。在其他实施例中，密封剂310未形成在集成电路封装件100上方，并且不需要平坦化工艺来暴露集成电路封装件100。
然后在密封剂310和再分布结构102上形成再分布结构312。再分布结构312可以以与关于图7A和图7B描述的再分布结构102类似的方式和类似的材料形成。再分布结构312包括介电层和金属化图案(有时称为再分布层或再分布线)。在再分布结构306中可以形成比所示出的更多或更少的介电层和金属化图案。再分布结构312的底部介电层与密封剂310和再分布结构102的顶部介电层物理接触。再分布结构312的金属化图案电耦合至再分布结构102的金属化图案。
导电连接件314形成为物理地并且电连接至再分布结构312的金属化图案。导电连接件314可以以与关于图10描述的导电连接件114类似的方式和类似的材料形成。
在图15中，执行载体衬底脱粘以将载体衬底302与再分布结构306(例如，再分布结构306的最底部介电层)分离(脱粘)。根据一些实施例，脱粘包括将诸如激光或UV光的光投射在释放层304上，使得释放层304在光的热量下分解，并且可以去除载体衬底302。然后可以将该结构翻转并放置在例如胶带上。
此外，穿过再分布结构306的最底部介电层形成导电连接件316。可以穿过再分布结构306的最底部介电层形成开口，暴露再分布结构306的金属化图案的部分。例如，可以使用激光钻孔、蚀刻等来形成开口。导电连接件316形成在开口中，并且连接至再分布结构306的金属化图案的暴露部分。导电连接件316可以以与关于图10描述的导电连接件114类似的方式和类似的材料形成。
在图16中，通过沿着划线区域(例如在封装区域302A周围)进行锯切来执行分割工艺。分割工艺包括锯切再分布结构306、312和密封剂310。分割工艺将封装区域302A与相邻的封装区域(未示出)分离以形成集成电路封装件300。在分割之后，再分布结构306、312和密封剂310横向共末端。
另一个集成电路封装件400可以附接至集成电路封装件300以形成叠层封装结构。集成电路封装件400可以是存储器封装件。集成电路封装件400可以在分割集成电路封装件300之前或之后附接至集成电路封装件300。集成电路封装件400包括衬底402和连接至衬底402的一个或多个管芯404。在一些实施例(未示出)中，一个或多个管芯404的堆叠件连接至衬底402。衬底402可以由半导体材料制成，诸如硅、锗、金刚石等。在一些实施例中，也可以使用诸如硅锗、碳化硅、砷化镓、砷化铟、磷化铟、碳化硅锗、磷砷化镓、磷化镓铟、它们的组合等的化合物材料。另外，衬底402可以是绝缘体上硅(SOI)衬底。通常，SOI衬底包括半导体材料层，诸如外延硅、锗、硅锗、SOI、绝缘体上硅锗(SGOI)或它们的组合。在一个可选实施例中，衬底402基于绝缘芯，诸如玻璃纤维增强树脂芯。一种示例芯材料是玻璃纤维树脂，诸如FR4。芯材料的替代材料包括双马来酰亚胺三嗪(BT)树脂，或者可选地其他印刷电路板(PCB)材料或膜。诸如味之素堆积膜(ABF)的堆积膜或其他层压件可以用于衬底402。
衬底402可以包括有源和无源器件(未示出)。如本领域的普通技术人员将认识到的，诸如晶体管、电容器、电阻器、它们的组合等的各种各样的器件可以用于生成集成电路封装件400的设计的结构和功能要求。可以使用任何合适的方法来形成器件。衬底402还可以包括金属化层(未示出)和通孔。金属化层可以形成在有源和无源器件上方，并且设计为连接各种器件以形成功能电路。金属化层可以由电介质(例如低k介电材料)和导电材料(例如铜)的交替层形成，其中通孔将导电材料层互连，并且可以通过任何合适的工艺(诸如沉积、镶嵌、双镶嵌等)形成。在一些实施例中，衬底402基本上没有有源和无源器件。
衬底402可以具有位于衬底402的一侧上的焊盘406，以连接至导电连接件316。在一些实施例中，接合焊盘406是通过在衬底402的该侧上的介电层(未示出)中形成凹槽(未示出)而形成的。凹陷可以形成为允许接合焊盘406嵌入介电层中。在其他实施例中，由于可以在介电层上形成接合焊盘406，因此省略了凹槽。在一些实施例中，接合焊盘406包括由铜、钛、镍、金、钯等或它们的组合制成的薄晶种层(未示出)。接合焊盘406的导电材料可以沉积在薄晶种层上方。可以通过电化学镀工艺、化学镀工艺、CVD、ALD、PVD等或它们的组合来形成导电材料。在实施例中，接合焊盘406的导电材料为铜、钨、铝、银、金等或它们的组合。
在实施例中，接合焊盘406是UBM，UBM包括三层导电材料，诸如钛层、铜层和镍层。例如，接合焊盘406可以由铜形成，可以形成在钛层(未示出)上，并且具有镍镀层，这可以提高集成电路封装件400的保存期限，当集成电路封装件400是诸如DRAM模块的存储器器件时，这可以是特别有利的。然而，本领域普通技术人员将认识到，存在许多合适的材料和层的布置，诸如铬/铬-铜合金/铜/金的布置、钛/钛钨/铜的布置或铜/镍/金的布置，它们适于形成接合焊盘406。可以用于接合焊盘406的任何合适的材料或材料层完全旨在包括在本申请的范围内。
在所示的实施例中，管芯404通过导电凸块连接至衬底402，但是可以使用其他连接，诸如线接合。在实施例中，管芯404是堆叠的存储器管芯。例如，管芯404可以是诸如低功率(LP)双倍数据速率(DDR)存储器模块的存储器管芯，诸如LPDDR1、LPDDR2、LPDDR3、LPDDR4等。
管芯404和线接合(如果存在的话)可以由模制材料410密封。模制材料410可以例如使用压缩模制而模制在管芯404和线接合上。在一些实施例中，模制材料410是模塑料、聚合物、环氧树脂、氧化硅填充材料等或它们的组合。可以执行固化工艺以固化模制材料410；固化工艺可以是热固化、UV固化等或它们的组合。在一些实施例中，管芯404被掩埋在模制材料410中，并且在模制材料410固化之后，执行诸如研磨的平坦化步骤以去除模制材料410的过量部分并且为集成电路封装件400提供基本平坦的表面。
在形成集成电路封装件400之后，通过导电连接件316将集成电路封装件400附接至集成电路封装件300。可以通过回流导电连接件316来将导电连接件316连接至接合焊盘406。管芯404因此可以通过导电连接件316、导电通孔308和再分布结构306、312电耦合至集成电路封装件100。
在一些实施例中，在衬底402的与管芯404相对的一侧上形成阻焊剂(未示出)。导电连接件316可以设置在阻焊剂中的开口中以连接至衬底402中的导电部件(例如，接合焊盘406)。阻焊剂可以用于保护衬底402的区域免受外部损坏。
在一些实施例中，导电连接件316在其回流之前在其上形成有环氧助焊剂(未示出)，并且在集成电路封装件400附接至再分布结构306之后剩余环氧助焊剂的至少一些环氧部分。
在一些实施例中，底部填充物(未示出)形成在再分布结构306和衬底402之间，并且围绕导电连接件316。底部填充物可以减小应力并保护由导电连接件316的回流产生的接头。底部填充物可以在附接集成电路封装件400之后通过毛细管流动工艺形成，或者可以在附接集成电路封装件400之前通过适当的沉积方法形成。在形成环氧助焊剂的实施例中，它可以用作底部填充物。
然后，将叠层封装结构翻转并且使用导电连接件314附接至封装衬底200。封装衬底200可以类似于关于图11描述的封装衬底200。例如，衬底200可以包括连接至导电连接件314的接合焊盘202。
图17是根据一些其他实施例的实现集成电路封装件100的系统的截面图。沿着图2C和图2D中的参考横截面B-B示出了图17。在该实施例中，形成了类似于图16的集成电路封装件300，但是省略了再分布结构306、导电通孔308、导电连接件316和集成电路封装件400。
实施例可以实现优点。通过混合接合将管芯互连允许减少集成电路封装件的再分布结构中的数据信号线的数量。通过使用集成到集成电路封装中的无源器件，也可以简化电源输送和路由。使用单独的存储器器件而不是包括具有集成电路封装件的处理器器件的存储器器件，可以允许增加集成电路封装件中的存储器的总量而不显著增加处理器器件的制造成本。此外，形成没有存储器的集成电路封装件的处理器器件允许在处理器器件中包括更多的处理单元(例如，核)，而基本上不增加处理器器件的占用面积。因此可以减小集成电路封装件的占用面积和制造成本。
也可以包括其他部件和工艺。例如，可以包括测试结构以辅助3D封装或3DIC器件的验证测试。测试结构可以包括例如形成在再分布层中或衬底上的测试焊盘，测试焊盘允许使用探针和/或探针卡等测试3D封装或3DIC。验证测试可以对中间结构以及最终结构执行。另外，本文公开的结构和方法可以与结合了已知良管芯的中间验证的测试方法结合使用，以增加产量并降低成本。
在实施例中，一种结构包括：第一处理器器件，具有前侧；共享存储器器件，具有前侧和与前侧相对的后侧，该共享存储器器件的前侧通过金属至金属接合和电介质至电介质接合接合至第一处理器器件的前侧；第一介电层，横向地围绕共享存储器器件；第一导电通孔，延伸穿过第一介电层；第二处理器器件，具有前侧和与前侧相对的后侧，第一导电通孔将第一处理器器件的前侧连接至第二处理器器件的后侧，第二处理器器件的后侧通过金属至金属接合接合至第一导电通孔和共享存储器器件的后侧，第二处理器器件的后侧通过电介质至电介质接合接合至第一介电层，第一处理器器件和第二处理器器件是不同类型的处理器器件；以及第一再分布结构，连接至第二处理器器件的前侧。
在一些实施例中，该结构还包括：第二介电层，横向地围绕第二处理器器件；以及第二导电通孔，延伸穿过第二介电层，第二导电通孔将第一再分布结构连接至共享存储器器件的后侧；以及第三导电通孔，延伸穿过第一介电层和第二介电层，第三导电通孔将第一再分布结构连接至第一处理器器件的前侧。在一些实施例中，第一再分布结构包括电源源线和电源接地线，第二导电通孔和第三导电通孔的每个电耦合至电源源线和电源接地线。在一些实施例中，共享存储器器件包括衬底通孔(TSV)，第二处理器器件通过TSV和第一导电通孔电耦合至第一处理器器件。在一些实施例中，该结构还包括：无源器件，具有前侧和与该前侧相对的后侧，该无源器件的前侧通过金属至金属接合和电介质至电介质接合接合至第一处理器器件的前侧；第二介电层，横向地围绕第二处理器器件；以及第二导电通孔，延伸穿过第二介电层，第二导电通孔将第一再分布结构连接至无源器件的后侧。在一些实施例中，第一处理器器件是图形处理单元(GPU)，第二处理器器件是中央处理单元(CPU)，并且无源器件是用于GPU的电源管理集成电路(PMIC)。在一些实施例中，该结构还包括：密封剂，横向地围绕共享存储器器件、第一处理器器件、第二处理器器件和第一再分布结构；以及第二再分布结构，与密封剂接触，第二再分布结构连接至第一再分布结构。在一些实施例中，该结构还包括：封装衬底；以及导电连接件，将封装衬底连接至第二再分布结构。在一些实施例中，该结构还包括：封装衬底；以及导电连接件，将封装衬底连接至第一再分布结构。在一些实施例中，第一处理器器件和第二处理器器件具有比共享存储器器件小的技术节点的有源器件。
在实施例中，一种结构包括：图形处理器器件；无源器件，耦合至图形处理器器件，该无源器件直接面对面地接合至图形处理器器件；共享存储器器件，耦合至图形处理器器件，共享存储器器件直接面对面地接合至图形处理器器件；中央处理器器件，耦合至共享存储器器件，中央处理器器件直接背对背地接合至共享存储器器件，中央处理器器件和图形处理器器件的每个具有比共享存储器器件小的技术节点的有源器件；以及再分布结构，耦合至中央处理器器件、共享存储器器件、无源器件和图形处理器器件。
在一些实施例中，共享存储器器件在第一平面中比中央处理器器件窄，并且共享存储器器件在第二平面中比中央处理器器件宽，第一平面垂直于第二平面。在一些实施例中，图形处理器器件在第一平面和第二平面中比中央处理器器件和共享存储器器件宽。
在实施例中，一种方法包括：将共享存储器器件接合至第一处理器器件；在共享存储器器件周围形成第一介电层；形成延伸穿过第一介电层的第一导电通孔，第一导电通孔连接至第一处理器器件；将第二处理器器件接合至第一导电通孔、第一介电层和共享存储器器件，第一处理器器件和第二处理器器件的每个是不同类型的处理器器件；在第二处理器器件周围形成第二介电层；形成延伸穿过第二介电层的第二导电通孔，第二导电通孔连接至共享存储器器件；形成延伸穿过第一介电层和第二介电层的第三导电通孔，第三导电通孔连接至第一处理器器件；以及在第二导电通孔、第三导电通孔、第二介电层和第二处理器器件上形成再分布结构。
在一些实施例中，该方法还包括：获得包括第一处理器器件的晶圆，其中将共享存储器器件接合至第一处理器器件包括将共享存储器器件接合至晶圆；以及在形成再分布结构之后，锯切晶圆、第一介电层、第二介电层和再分布结构。在一些实施例中，该方法还包括：在将共享存储器器件接合至第一处理器器件之前：获得包括第一处理器器件的晶圆；锯切晶圆以分割第一处理器器件；以及密封第一处理器器件。在一些实施例中，形成第一导电通孔包括：在第一介电层中图案化第一开口，第一开口暴露第一处理器器件的管芯连接件；在第一开口中镀导电材料；以及平坦化导电材料和第一介电层，第一开口中的导电材料的剩余部分形成第一导电通孔。在一些实施例中，形成第二导电通孔包括：在第二介电层中图案化第二开口，第二开口暴露共享存储器器件的管芯连接件；在第二开口中镀导电材料；以及平坦化导电材料和第二介电层，第二开口中的导电材料的剩余部分形成第二导电通孔。在一些实施例中，形成第一介电层包括在无源器件周围形成第一介电层，并且其中第二导电通孔的子集连接至无源器件。在一些实施例中，第一处理器器件是图形处理单元(GPU)，第二处理器器件是中央处理单元(CPU)，并且无源器件是用于GPU的电源管理集成电路(PMIC)。
本发明概述了若干实施例的特征，使得本领域人员可以更好地理解本发明的方面。本领域人员应该理解，它们可以容易地使用本发明作为基底来设计或修改用于实施与本文所介绍实施例相同的目的和/或实现相同优势的其它工艺和结构。本领域技术人员也应该意识到，这种等同配置并且不面向远离本发明的精神和范围，并且在不面向远离本发明的精神和范围的情况下，本文中它们可以做出多种变化、替换以及改变。

Claims (20)

1.一种集成电路结构，包括：
第一处理器器件，具有前侧；
共享存储器器件，具有前侧和与前侧相对的后侧，所述共享存储器器件的前侧通过金属至金属接合和电介质至电介质接合接合至所述第一处理器器件的前侧；
第一介电层，横向地围绕所述共享存储器器件；
第一导电通孔，延伸穿过所述第一介电层；
第二处理器器件，具有前侧和与前侧相对的后侧，所述第一导电通孔将所述第一处理器器件的前侧连接至所述第二处理器器件的后侧，所述第二处理器器件的后侧通过金属至金属接合接合至所述第一导电通孔和所述共享存储器器件的后侧，所述第二处理器器件的后侧通过电介质至电介质接合接合至所述第一介电层，所述第一处理器器件和所述第二处理器器件的每个是不同类型的处理器器件；以及
第一再分布结构，连接至所述第二处理器器件的前侧。
2.根据权利要求1所述的集成电路结构，还包括：
第二介电层，横向地围绕所述第二处理器器件；
第二导电通孔，延伸穿过所述第二介电层，所述第二导电通孔将所述第一再分布结构连接至所述共享存储器器件的后侧；以及
第三导电通孔，延伸穿过所述第一介电层和所述第二介电层，所述第三导电通孔将所述第一再分布结构连接至所述第一处理器器件的前侧。
3.根据权利要求2所述的集成电路结构，其中，所述第一再分布结构包括电源源线和电源接地线，所述第二导电通孔和所述第三导电通孔的每个电耦合至所述电源源线和所述电源接地线。
4.根据权利要求1所述的集成电路结构，其中，所述共享存储器器件包括衬底通孔，所述第二处理器器件通过所述衬底通孔和所述第一导电通孔电耦合至所述第一处理器器件。
5.根据权利要求1所述的集成电路结构，还包括：
无源器件，具有前侧和与前侧相对的后侧，所述无源器件的前侧通过金属至金属接合和电介质至电介质接合接合至所述第一处理器器件的前侧；
第二介电层，横向地围绕所述第二处理器器件；以及
第二导电通孔，延伸穿过所述第二介电层，所述第二导电通孔将所述第一再分布结构连接至所述无源器件的后侧。
6.根据权利要求5所述的集成电路结构，其中，所述第一处理器器件是图形处理单元，所述第二处理器器件是中央处理单元，并且所述无源器件是用于图形处理单元的电源管理集成电路。
7.根据权利要求1所述的集成电路结构，还包括：
密封剂，横向地围绕所述共享存储器器件、所述第一处理器器件、所述第二处理器器件和所述第一再分布结构；以及
第二再分布结构，与所述密封剂接触，所述第二再分布结构连接至所述第一再分布结构。
8.根据权利要求7所述的集成电路结构，还包括：
封装衬底；以及
导电连接件，将所述封装衬底连接至所述第二再分布结构。
9.根据权利要求1所述的集成电路结构，还包括：
封装衬底；以及
导电连接件，将所述封装衬底连接至所述第一再分布结构。
10.根据权利要求1所述的集成电路结构，其中，所述第一处理器器件和所述第二处理器器件具有比所述共享存储器器件小的技术节点的有源器件。
11.一种集成电路结构，包括：
图形处理器器件；
无源器件，耦合至所述图形处理器器件，所述无源器件直接面对面地接合至所述图形处理器器件；
共享存储器器件，耦合至所述图形处理器器件，所述共享存储器器件直接面对面地接合至所述图形处理器器件；
中央处理器器件，耦合至所述共享存储器器件，所述中央处理器器件直接背对背地接合至所述共享存储器器件，所述中央处理器器件和所述图形处理器器件的每个具有比所述共享存储器器件小的技术节点的有源器件；以及
再分布结构，耦合至所述中央处理器器件、所述共享存储器器件、所述无源器件和所述图形处理器器件。
12.根据权利要求11所述的集成电路结构，其中，所述共享存储器器件在第一平面中比所述中央处理器器件窄，并且所述共享存储器器件在第二平面中比所述中央处理器器件宽，所述第一平面垂直于所述第二平面。
13.根据权利要求12所述的集成电路结构，其中，所述图形处理器器件在所述第一平面和所述第二平面中比所述中央处理器器件和所述共享存储器器件宽。
14.一种形成集成电路结构的方法，包括：
将共享存储器器件接合至第一处理器器件；
在所述共享存储器器件周围形成第一介电层；
形成延伸穿过所述第一介电层的第一导电通孔，所述第一导电通孔连接至所述第一处理器器件；
将第二处理器器件接合至所述第一导电通孔、所述第一介电层和所述共享存储器器件，所述第一处理器器件和所述第二处理器器件的每个是不同类型的处理器器件；
在所述第二处理器器件周围形成第二介电层；
形成延伸穿过所述第二介电层的第二导电通孔，所述第二导电通孔连接至所述共享存储器器件；
形成延伸穿过所述第一介电层和所述第二介电层的第三导电通孔，所述第三导电通孔连接至所述第一处理器器件；以及
在所述第二导电通孔、所述第三导电通孔、所述第二介电层和所述第二处理器器件上形成再分布结构。
15.根据权利要求14所述的方法，还包括：
获得包括所述第一处理器器件的晶圆，其中，将所述共享存储器器件接合至所述第一处理器器件包括将所述共享存储器器件接合至所述晶圆；以及
在形成所述再分布结构之后，锯切所述晶圆、所述第一介电层、所述第二介电层和所述再分布结构。
16.根据权利要求14所述的方法，还包括：在将所述共享存储器器件接合至所述第一处理器器件之前：
获得包括所述第一处理器器件的晶圆；
锯切所述晶圆以分割所述第一处理器器件；以及
密封所述第一处理器器件。
17.根据权利要求14所述的方法，其中，形成所述第一导电通孔包括：
在所述第一介电层中图案化第一开口，所述第一开口暴露所述第一处理器器件的管芯连接件；
在所述第一开口中镀导电材料；以及
平坦化所述导电材料和所述第一介电层，所述第一开口中的所述导电材料的剩余部分形成所述第一导电通孔。
18.根据权利要求17所述的方法，其中，形成所述第二导电通孔包括：
在所述第二介电层中图案化第二开口，所述第二开口暴露所述共享存储器器件的管芯连接件；
在所述第二开口中镀所述导电材料；以及
平坦化所述导电材料和所述第二介电层，所述第二开口中的所述导电材料的剩余部分形成所述第二导电通孔。
19.根据权利要求14所述的方法，还包括：
将无源器件接合至所述第一处理器器件，其中，形成所述第一介电层包括在所述无源器件周围形成所述第一介电层，并且其中，所述第二导电通孔的子集连接至所述无源器件。
20.根据权利要求19所述的方法，其中，所述第一处理器器件是图形处理单元，所述第二处理器器件是中央处理单元，并且所述无源器件是用于图形处理单元的电源管理集成电路。
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