CN113808959A - 封装结构的制造方法 - Google Patents

封装结构的制造方法 Download PDF

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Publication number
CN113808959A
CN113808959A CN202110650402.6A CN202110650402A CN113808959A CN 113808959 A CN113808959 A CN 113808959A CN 202110650402 A CN202110650402 A CN 202110650402A CN 113808959 A CN113808959 A CN 113808959A
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Prior art keywords
die
dummy
dummy structure
wafer
structures
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CN202110650402.6A
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Inventor
陈明发
叶松峯
刘醇鸿
史朝文
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

提供一种封装结构及其制作方法。所述方法包括：通过混合结合将第一管芯及第二管芯结合到晶片的第一管芯区中的所述晶片；将第一虚设结构结合到所述第一管芯区中的所述晶片及所述晶片的第一切割道；以及沿所述第一切割道使所述晶片及所述第一虚设结构单体化，以形成堆叠集成电路(IC)结构。

Description

封装结构的制造方法
技术领域
本公开实施例涉及一种封装结构及其制造方法。
背景技术
由于对集成电路(integrated circuit，IC)的开发，半导体行业已因各种电子组件(即晶体管、二极管、电阻器、电容器等)集成密度的不断提升而经历连续快速成长。最重要的是，集成密度的这些提升是源自最小特征大小的不断减小，而使得更多的组件能够集成到给定面积中。
这些集成度提升本质上是从二维(two-dimensional，2D)层面来说，原因在于集成组件所占据的面积主要位于半导体晶片的表面上。密度的增加及集成电路的面积的相应减小一般来说超出了将集成电路芯片直接结合到衬底上的能力。中介层(interposer)可用来将球接触面积从芯片重布线到中介层的更大面积。此外，中介层已可包含多个芯片的三维(three-dimensional，3D)封装。还已开发出其他封装来并入三维方面。
发明内容
本公开实施例提出一种封装结构的制造方法，其特征在于包括：通过混合结合将第一管芯及第二管芯结合到晶片的第一管芯区中的所述晶片；将第一虚设结构结合到所述第一管芯区中的所述晶片及所述晶片的第一切割道；以及沿所述第一切割道使所述晶片及所述第一虚设结构单体化，以形成堆叠集成电路结构。
本公开实施例一种封装结构的制造方法，其特征在于包括：将第一管芯及第二管芯结合到晶片的管芯区中的所述晶片；将第一虚设结构结合到所述管芯区中的所述晶片，以覆盖在所述管芯区的多个拐角上方；以及将所述晶片单体化以形成堆叠集成电路(IC)结构。
本公开实施例一种封装结构，包括：底部管芯；第一管芯，结合到所述底部管芯的第一侧；第二管芯，结合到所述底部管芯的所述第一侧；包封体，侧向包封所述第一管芯及所述第二管芯；以及第一虚设结构，结合到所述底部管芯的所述第一侧，其中所述第一虚设结构的侧壁与所述底部管芯的第一侧壁共面。
附图说明
结合附图阅读以下详细说明，会最好地理解本发明的各个方面。应注意，根据本行业中的标准惯例，各种特征并非按比例绘制。事实上，为论述清晰起见，可任意增大或减小各种特征的尺寸。
图1A到图1H是示出根据本公开一些实施例的一种形成三维集成电路(three-dimensional integrated circuit，3DIC)结构的方法的示意性剖视图。
图2A到图6A示出根据一些实施例的图1B所示晶片级管芯结构的俯视图。
图2B到图6B示出根据一些实施例的从图2A到图6A所示晶片级管芯结构单体化的个别3DIC结构的俯视图。
图3C、图4C、图4D、图4E、图4F、图5C及图6C示出根据一些其他实施例的个别3DIC结构的俯视图。
图7A到图7E示出根据一些实施例的形成封装的剖视图。
图8示出根据一些实施例的用于形成3DIC结构的工艺流程。
具体实施方式
以下公开内容提供用于实施所提供主题的不同特征的许多不同的实施例或实例。以下阐述组件及排列的具体实例以简化本公开。当然，这些仅为实例而非旨在进行限制。举例来说，在以下说明中，在第一特征上方或第一特征上形成第二特征可包括其中第二特征与第一特征被形成为直接接触的实施例，且也可包括其中第二特征与第一特征之间可形成附加特征从而使得第二特征与第一特征可不直接接触的实施例。另外，本公开可在各种实例中重复参考编号和/或字母。此种重复使用是为了简明及清晰起见，且自身并不指示所讨论的各种实施例和/或配置之间的关系。
此外，为易于说明，本文中可能使用例如“在…之下(beneath)”、“在…下方(below)”、“下部的(lower)”、“在…上(on)”、“在…上方(above)”、“上部的(upper)”等空间相对性用语来阐述图中所示一个元件或特征与另一(其他)元件或特征的关系。除了图中所绘示的取向以外，所述空间相对性用语还旨在囊括装置在使用或操作中的不同取向。设备可以其他方式取向(旋转90度或处于其他取向)，且本文所用的空间相对性描述语可同样相应地作出解释。
本公开也可包括其他特征及工艺。举例来说，可包括测试结构以帮助对3D封装或3DIC装置进行验证测试。所述测试结构可例如包括在重布线层中或在衬底上形成的测试焊盘(test pad)，以便能够对3D封装或3DIC进行测试、对探针和/或探针卡(probe card)进行使用等。可对中间结构以及最终结构执行验证测试。另外，可将本文中所公开的结构及方法与包括对已知良好管芯进行中间验证的测试方法结合使用，以提高良率并降低成本。
图1A到图1H是示出根据本公开一些实施例的一种形成3DIC结构的方法的示意性剖视图。图8所示的工艺流程也示意性地反映了图1A到图1H所示的步骤。
进一步参照图1A，提供具有多个集成电路(IC)管芯104的晶片100。根据本公开的一些实施例，IC管芯104可以是逻辑管芯(例如，中央处理器、图形处理单元、系统芯片、微控制器等)、存储器管芯(例如，动态随机存取存储器(dynamic random access memory，DRAM)管芯、静态随机存取存储器(static random access memory，SRAM)管芯等)、功率管理管芯(例如，功率管理集成电路(power management integrated circuit，PMIC)管芯)、射频(radio frequency，RF)管芯、传感器管芯、微机电系统(micro-electro-mechanical-system，MEMS)管芯、信号处理管芯(例如，数字信号处理(digital signal processing，DSP)管芯)、前端管芯(例如，模拟前端(analog front-end，AFE)管芯)等或其组合。此外，在一些实施例中，IC管芯104可以是不同的大小(例如，不同的高度和/或表面积)，并且在其他实施例中，IC管芯104可以是相同的大小(例如，相同的高度和/或表面积)。
晶片100包括衬底105及位于衬底105上方的结合结构120。在一些实施例中，衬底105可由硅形成，但其也可由其他III族、IV族和/或V族元素或化合物(例如，硅、锗、镓、砷及其组合)形成。衬底105也可以是绝缘体上硅(silicon-on-insulator，SOI)的形式。SOI衬底可包括形成在绝缘体层(例如，掩埋氧化物和/或类似物)上方的半导体材料(例如，硅、锗和/或类似物)层，所述绝缘体层形成在半导体(例如，硅)衬底上。此外，可使用的其他衬底包括多层式衬底、梯度衬底、混合取向衬底、其任意组合和/或类似物。
在一些实施例中，衬底105可包括从衬底105的前侧表面向衬底105的后侧表面延伸的穿孔(through via，TV)109。在一些实施例中，TV 109可通过在衬底105中形成开口并用合适的导电材料填充开口形成。在一些实施例中，开口可使用合适的光刻及蚀刻方法来形成。可利用物理气相沉积(physical vapor deposition，PVD)、原子层沉积(atomiclayer deposition，ALD)、电化学镀覆、无电镀覆或其组合等用铜、铜合金、银、金、钨、钽、铝、其组合等来填充开口。在一些实施例中，在用合适的导电材料填充开口之前可在开口中形成衬垫层和/或粘合剂层。在一些其他实施例中，衬底105可不包括穿孔(TV)109，并且可在后续工艺中形成介电穿孔(through dielectric via，TDV)。TDV形成在结合结构120上的顶部管芯周围的介电层中，以连接到结合结构120的结合焊盘123。
晶片100还可包括一个或多个集成电路装置、互连结构114、接触焊盘115及位于衬底105与结合结构120之间的介电层117。集成电路装置可以是有源和/或无源装置。一个或多个有源和/或无源装置可形成在衬底105上和/或衬底105中。在一些实施例中，一个或多个有源和/或无源装置可包括各种n型金属氧化物半导体(NMOS)和/或p型金属氧化物半导体(PMOS)装置，例如晶体管、电容器、电阻器、二极管、光电二极管、熔丝和/或类似物。互连结构114形成在衬底105及一个或多个有源和/或无源装置上方。互连结构114可在衬底105上形成的一个或多个集成电路装置之间提供电连接。互连结构114可包括多个介电层(例如，层间介电(inter-layer dielectric，ILD)层/金属间介电层(inter-metaldielectric，IMD)层)及介电层111内的互连件113(例如，导线及通孔)。介电层111可由例如低介电常数介电材料(例如，磷硅酸盐玻璃(phosphosilicate glass，PSG)、硼磷硅酸盐玻璃(borophosphosilicate glass，BPSG)、氟硅酸盐玻璃(fluorosilicate glass，FSG)、SiOxCy、旋涂玻璃、旋涂聚合物、硅碳材料、其化合物、其复合物、其组合等)形成。在一些实施例中，互连件113可包含铜、铜合金、银、金、钨、钽、铝、其组合等。
接触焊盘115形成在互连结构114上方。接触焊盘115可通过互连件113电耦合到一个或多个有源和/或无源装置。在一些实施例中，接触焊盘115可包含导电材料，例如铝、铜、钨、银、金、其组合等。
介电层117形成在互连结构114及接触焊盘115上方。在一些实施例中，介电层117可包含一层或多层不可光图案化的绝缘材料，例如氮化硅、氧化硅、磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(borosilicate glass，BSG)、掺杂有硼的磷硅酸盐玻璃(boron-dopedphosphosilicate galss，BPSG)、其组合等。在其他实施例中，介电层可包含一层或多层可光图案化的绝缘材料，例如聚苯并恶唑(polybenzoxazole，PBO)、聚酰亚胺(polyimide，PI)、苯并环丁烯(benzocyclobutene，BCB)、其组合等。在一些实施例中，使用化学机械抛光(chemical mechanical polishing，CMP)工艺、研磨工艺、蚀刻工艺、其组合等来平坦化介电层。
参照图1A，在介电层117上形成结合结构120。结合结构120包括形成在介电层117上的绝缘层119及形成在绝缘层119中的结合焊盘123。在一些实施例中，结合结构120还包括形成在绝缘层119中的虚设焊盘125。结合焊盘123与形成在介电层117中的通孔121直接电接触，以电连接到互连件113。
在一些实施例中，绝缘层119可包括一层或多层不可光图案化的绝缘材料，例如氮化硅、氧化硅、磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、掺杂有硼的磷硅酸盐玻璃(BPSG)、其组合等，并且可使用化学气相沉积(chemical vapor deposition，CVD)、PVD、ALD、旋涂工艺、其组合等形成。在一些实施例中，使用CMP工艺、研磨工艺、蚀刻工艺、其组合等来平坦化绝缘层119。在一些实施例中，绝缘层119与下伏介电层可包含相同的材料。在其他实施例中，绝缘层119与下伏介电层可包含不同的材料。
在一些实施例中，结合焊盘123、虚设焊盘125及通孔121可包含例如铝、铜、钨、银、金、其组合等导电材料。在一些实施例中，可使用例如PVD、ALD、电化学镀覆、无电镀覆、其组合等在互连结构上方形成导电材料。随后，使用合适的光刻及蚀刻方法图案化导电材料以形成接触焊盘。结合焊盘123、虚设焊盘125及通孔121可使用例如镶嵌工艺、双镶嵌工艺、其组合等形成在绝缘层119中。在一些实施例中，结合焊盘123、虚设焊盘125及绝缘层119被平坦化，使得结合焊盘123及虚设焊盘125的最顶部表面实质上与绝缘层119的最顶部表面齐平或共面。
参照图1B，将装置管芯204及装置管芯304结合到晶片100的第一侧，以开始形成晶片级管芯结构1000。所述相应的工艺在图8所示的工艺流程中被示出为步骤S10。装置管芯204可以是逻辑管芯(例如，中央处理器、图形处理单元、系统芯片、微控制器等)、存储器管芯(例如，动态随机存取存储器(DRAM)管芯、静态随机存取存储器(SRAM)管芯等)、功率管理管芯(例如，功率管理集成电路(PMIC)管芯)、射频(RF)管芯、传感器管芯、微机电系统(MEMS)管芯、信号处理管芯(例如，数字信号处理(DSP)管芯)、前端管芯(例如，模拟前端(AFE)管芯)等或其组合。此外，在一些实施例中，装置管芯204可以是不同的大小(例如，不同的高度和/或表面积)，并且在其他实施例中，装置管芯可以是相同的大小(例如，相同的高度和/或表面积)。
装置管芯304包括一个或多个存储器管芯，例如存储器管芯(例如，DRAM管芯、SRAM管芯、高带宽存储器(High-Bandwidth Memory，HBM)管芯、混合存储器立方体(HybridMemory Cube，HMC)管芯等)的堆叠。在存储器管芯堆叠实施例中，装置管芯304可包括存储器管芯及存储器控制器两者，例如四个或八个存储器管芯与存储器控制器的堆叠。此外，在一些实施例中，装置管芯304可以是不同的大小(例如，不同的高度和/或表面积)，并且在其他实施例中，装置管芯304可以是相同的大小(例如，相同的高度和/或表面积)。
装置管芯204可包括衬底205、一个或多个有源和/或无源装置(图中未示出)、互连结构214、接触焊盘215、介电层217、通孔221及结合结构220。结合结构220包括结合焊盘223、虚设焊盘225及绝缘层219。装置管芯304可包括衬底305、一个或多个有源和/或无源装置(图中未示出)、互连结构314、接触焊盘315、介电层317、通孔321及结合结构320。结合结构320包括结合焊盘323、虚设焊盘325及绝缘层319。
在一些实施例中，装置管芯204及304的衬底205及305、互连结构214及314、接触焊盘215及315、介电层217及317、通孔221及321、以及结合结构220及320的材料及形成方法可类似于晶片100的衬底105、互连结构114、接触焊盘115、介电层117、通孔121及结合结构120，且因此在此不再予以赘述。
装置管芯204及304与晶片100可通过混合结合来结合。举例来说，将结合焊盘223及323结合到IC管芯(或称为底部管芯)104的结合焊盘123，并且通过金属到金属的直接结合将虚设焊盘225及325结合到IC管芯104的虚设焊盘125。根据本公开的一些实施例，金属到金属的直接结合是铜到铜的直接结合。结合焊盘223及323的大小可大于、等于或小于相应结合焊盘123的大小。虚设焊盘225及325的大小可大于、等于或小于相应虚设结合焊盘125的大小。此外，通过介电质到介电质的结合(其可为例如产生Si-O-Si结合的熔融结合)将绝缘层219及319结合到绝缘层119。为实现混合结合，首先通过将装置管芯204及304轻压抵靠IC管芯104而将装置管芯204及304预结合到绝缘层119、结合焊盘223及虚设焊盘225。然后执行退火以引起结合焊盘223及323以及虚设焊盘225及325中的金属与对应的上覆结合焊盘123及虚设焊盘125的金属的相互扩散。
参照图1B，将虚设结构404结合到晶片100的绝缘层119，使得每个装置管芯204及每个装置管芯304被夹在相邻的虚设结构404之间。所述相应工艺在图8所示的工艺流程中被示出为步骤S20。使用图1B中的虚设管芯404的数量进行例示。每个IC管芯104可具有一个或多个虚设结构404。此外，相邻的IC管芯104可共享虚设结构404。虚设结构404可由块状材料405制成。在一些实施例中，虚设结构404可包含与IC管芯104的衬底105相同的材料。在一些实施例中，虚设结构404可不包括有源和/或无源装置，并且可不对所得的IC封装提供额外的电功能。在一些实施例中，每个虚设结构404可包括位于块状材料405的一侧上的绝缘层419。在一些实施例中，绝缘层419可使用与绝缘层119类似的材料及方法形成，并且在此不再予以赘述。在一些实施例中，绝缘层419与绝缘层119可包含相同的材料。在其他实施例中，绝缘层419与绝缘层119可包含不同的材料。
在一些实施例中，通过将绝缘层419结合到绝缘层119，虚设结构404的前侧表面404a结合到IC管芯104的前侧表面104a。在一些实施例中，可使用直接结合方法(例如，熔融结合方法)将绝缘层419结合到绝缘层119。在一些实施例中，在将绝缘层419结合到绝缘层119之前，可对绝缘层419及绝缘层119执行表面处理工艺。在其他实施例中，可使用其他合适的结合方法或使用粘合剂将绝缘层419结合到绝缘层119。在一些实施例中，可在将虚设结构404结合到晶片100之后执行退火工艺以加强结合。
图2A示出根据一些实施例的图1B所示晶片级管芯结构1000的俯视图。在一些实施例中，晶片100被切割道9及11分成管芯区113i(其中i＝1、…、N，其中N是管芯区的总数)。在一些实施例中，切割道9垂直于切割道11。在此类实施例中，管芯区113i(其中i＝1、…、N)在俯视图中具有平行四边形形状。在一些实施例中，管芯区113i(其中i＝1、…、N)在俯视图中具有矩形形状。在其他实施例中，切割道9及切割道11形成不同于90度的角度。
参照图2A，将虚设结构404放置在管芯区113i中并与相应切割道11的一部分交叠，使得虚设结构404在被相应切割道11分开的管芯区113i(其中i＝1、…、N)的子集之间共享。在一些实施例中，虚设结构404被放置在由装置管芯204及304以及切割道9及11包围的区域中，并且延伸到邻近的装置管芯204。每个切割道11被多个分隔开的虚设结构404交叠。举例来说，虚设结构404在俯视图中具有矩形形状。
图3A示出根据替代实施例的图1B所示晶片级管芯结构1000的俯视图。在图3A所示的实施例中，虚设结构404包括彼此分开的虚设结构4041与虚设结构4042。在一些实施例中，在俯视图中，虚设结构4041具有矩形形状，并且虚设结构4042具有环形形状。
虚设结构4042放置在每个管芯区113i中的装置管芯204及304以及虚设结构4041周围。虚设结构4042放置在管芯区113i中，并且不覆盖切割道9及11。虚设结构4042被设置在相应的切割道9及11的两侧上彼此相邻。虚设结构4041放置在由装置管芯204及304以及虚设结构4042包围的区域中。
图4A示出根据替代实施例的图1B所示晶片级管芯结构1000的俯视图。在图4A所示的实施例中，虚设结构404包括彼此分开的虚设结构4041、4042、4043及4044。在一些实施例中，在俯视图中，虚设结构4041、4043及4044具有不同大小的矩形形状，并且虚设结构4042具有环形形状。虚设结构4041类似于图2A所示实施例的虚设结构4041，且在此不再予以赘述。
在一些管芯区113i(例如，管芯区1131、1133、1137及1139)中，虚设结构4042放置在装置管芯204及304以及虚设结构4041周围。管芯区1131与1137在第一方向D1上被管芯区1134分开，并且管芯区1131与1133在第二方向D2上被管芯区1132分开。
虚设结构4042放置在管芯区113i中并与对应切割道9及11的一部分交叠，使得虚设结构4042在被相应切割道9及11分开的管芯区113i(其中i＝1、…、N)的子集之间共享。举例来说，虚设结构4042由管芯区1131与1134(由对应的切割道11分开)共享，并且也由管芯区1131与1132(由对应的切割道9分开)共享。
在一些实施例中，虚设结构4043设置在在第一方向D1上相邻的两个虚设结构4042之间。虚设结构4043可形成沿第一方向D1延伸并在第二方向D2上排列的断开的虚设结构。虚设结构4043放置在一些管芯区113i中，并与对应的切割道9的一部分交叠，使得虚设结构4043在被相应切割道9分开的管芯区113i(其中i＝1、…、N)的子集之间共享。
在一些实施例中，虚设结构4044设置在在第二方向D2上相邻的两个虚设结构4042之间。虚设结构4044可形成沿第二方向D2延伸并在第一方向D1上排列的断开的虚设结构。虚设结构4044形成在一些管芯区113i中，并与对应的切割道11的一部分交叠，使得虚设结构4044在被相应切割道11分开的管芯区113i(其中i＝1、…、N)的子集之间共享。
换句话说，每个切割道9被多个虚设结构4042及多个虚设结构4043交叠，并且每个切割道11被多个虚设结构4042及多个虚设结构4044交叠。
图5A示出根据替代实施例的图1B所示晶片级管芯结构1000的俯视图。在图5A所示的实施例中，虚设结构404包括彼此分开的虚设结构4041、虚设结构4042及虚设结构4043。装置管芯204及304以及虚设结构4041被虚设结构4042及4043包围。在一些实施例中，虚设结构4041、4042及4043在俯视图中具有矩形形状。虚设结构4041类似于图3A所示实施例的虚设结构4041，且在此不再予以赘述。
虚设结构4042可形成沿第二方向D2延伸并在第一方向D1上排列的断开的虚设结构。虚设结构4042形成在管芯区113i中，以覆盖在IC管芯104的拐角上方，并暴露出相应的切割道9及11。虚设结构4043可形成沿第一方向D1延伸并在第二方向D2上排列的断开的虚设结构。虚设结构4043形成在管芯区113i中，并暴露出相应的切割道9及11。在第一方向上的两个相邻虚设结构4042插入在两个相邻的虚设结构4043之间。在第二方向D2上的虚设结构4042彼此相邻，并且在其之间没有插入虚设结构4043。
图6A示出根据替代实施例的图1B所示晶片级管芯结构1000的俯视图。图1B是沿图6A的线I-I’截取的剖视图。在图6A所示的实施例中，虚设结构404包括彼此分开的虚设结构4041、虚设结构4042及虚设结构4043。在一些实施例中，虚设结构4041、4042及4043在俯视图中具有不同大小的矩形形状。虚设结构4041类似于图3A所示实施例的虚设结构4041，且在此不再予以赘述。
虚设结构4042形成在管芯区113i中且与整个相应切割道11交叠，并且在被相应切割道11分开的管芯区113i(其中i＝1、…、N)的子集之间共享。在一些实施例中，虚设结构4042可形成沿第二方向D2延伸的连续结构，使得每个切割道11被相应的单个连续虚设结构4042交叠。在一些实施例中，通过形成与切割道11交叠的虚设结构4042，可减少形成个别IC封装的时间。举例来说，用于形成个别IC封装的时间可减少在执行单体化工艺之前在晶片100的每个管芯区内放置及结合个别(芯片级或管芯级)虚设结构所需的时间。因此，在IC封装的生产期间，每小时晶片(wafer per hour，WPH)产量可增加，且生产成本可降低。
虚设结构4043形成在管芯区113i中，并与相应切割道9的一部分交叠，使得虚设结构4043在被相应切割道9分开的管芯区113i(其中i＝1、…、N)的子集之间共享。在一些实施例中，虚设结构4043可形成沿第一方向D1延伸的断开的虚设结构，使得每个切割道9被多个虚设结构4043交叠。
放置在切割道9和/或切割道11中或邻近切割道9和/或切割道11的虚设结构404可有助于防止在封装的单体化(参见图1H)期间及之后的翘曲。虚设结构404可有助于减少翘曲的一种方式是在实际单体化工艺期间为封装提供支撑。虚设结构404可防止翘曲的另一种方式是减小IC管芯104与随后形成的包封体127(如果存在的话)之间的热膨胀系数(coefficient of thermal expansion，CTE)失配(参见图1C)，因为虚设结构404具有与IC管芯104相似的CTE，并且其减少了封装中必需的包封体127的量。
参照图1B，执行薄化工艺以薄化装置管芯204及304以及虚设结构404。在一些实施例中，可使用CMP工艺、研磨工艺、蚀刻工艺、其组合等来薄化装置管芯204及304以及虚设结构404。在薄化工艺之后，虚设结构404具有例如在100微米到150微米范围内的厚度T1。厚度T1是指虚设结构404的前侧表面404a与虚设结构404的后侧表面404b之间的距离。为简洁起见，未在图1C到图1H中示出衬底105与绝缘层119之间、衬底205与绝缘层219之间、以及衬底305与绝缘层319之间的层、焊盘及元件。
参照图1C，在装置管芯204及304以及虚设结构404上方并围绕装置管芯204及304以及虚设结构404形成包封体127。在一些实施例中，包封体127可包含一层或多层不可光图案化的绝缘材料，例如氮化硅、氧化硅、磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、掺杂有硼的磷硅酸盐玻璃(BPSG)、其组合等，并且可使用CVD、PVD、ALD、旋涂工艺、其组合等形成。在其他实施例中，包封体127可包含一层或多层可光图案化的绝缘材料，例如聚苯并恶唑(PBO)、聚酰亚胺(PI)、苯并环丁烯(BCB)、其组合等，并且可使用旋涂工艺等形成。此种可光图案化的绝缘材料可使用与光刻胶材料类似的光刻方法来图案化。在其他实施例中，包封体127可包含模制化合物，例如环氧树脂、树脂、可模制聚合物、其组合等。模制化合物可在实质上为液体的情况下施加，且然后可例如在环氧树脂或树脂中通过化学反应固化。在其他实施例中，模制化合物可以是紫外线(ultraviolet，UV)或热固化聚合物，所述聚合物作为能够设置在装置管芯204及304以及虚设结构404周围及之间的凝胶或延展性固体来施加。
参照图1C，将包封体127及装置管芯204及304以及虚设结构404平坦化，使得装置管芯204及304以及虚设结构404的后侧表面实质上与包封体127的最顶部表面齐平或共面。在一些实施例中，平坦化工艺可包括CMP工艺、研磨工艺、蚀刻工艺、其组合等。在平坦化工艺之后，虚设结构404具有例如40微米到150微米范围内的厚度T2。厚度T2指的是虚设结构404的前侧表面404a与虚设结构404的后侧表面404c之间的距离。
参照图1D，将图1C的结构翻转并通过释放层(图中未示出)贴合到载体129。载体129可包含合适的绝缘材料，例如玻璃。对衬底105的后侧执行薄化工艺以薄化衬底105，直到TV 109被暴露出。薄化工艺可包括蚀刻工艺、研磨工艺等、或其组合。在一些实施例中，薄化工艺暴露出IC管芯104的TV 109，使得TV 109的被暴露出的表面实质上与衬底105的后侧表面105b齐平或共面。在一些实施例中，在薄化工艺之后，IC管芯104的厚度T3在20微米到30微米的范围内。厚度T3指的是IC管芯104的前侧表面104a到IC管芯104的后侧表面104b之间的距离。
参照图1E，在IC管芯104的后侧表面104b上方形成重布线结构131，并且使用所述重布线结构131将IC管芯104的集成电路装置(如果存在的话)和/或TV 109电连接在一起和/或电连接到外部装置。重布线结构131可包括一个或多个介电层133及位于一个或多个介电层133中的相应金属化图案135。金属化图案135有时被称为重布线走线(RDL)。介电层133可包含氧化硅、氮化硅、碳化硅、氮氧化硅、低介电常数介电材料，例如PSG、BPSG、FSG、SiOxCy、旋涂玻璃、旋涂聚合物、硅碳材料、其化合物、其复合物、其组合等。可通过所属领域中已知的任何合适的方法(例如，旋涂、CVD、等离子体增强化学气相沉积(PECVD)、高密度等离子体化学气相沉积(HDP-CVD)等)来沉积介电层133。金属化图案135包括导线及导通孔。可例如通过使用光刻技术在介电层133上沉积及图案化光刻胶材料以暴露出将成为金属化图案135的介电层133的一些部分而在介电层133中形成金属化图案135。可使用例如各向异性干蚀刻工艺等蚀刻工艺在介电层133中生成对应于介电层133的被暴露出的部分的凹陷和/或开口。凹陷和/或开口可衬有扩散阻挡层并填充以导电材料。扩散阻挡层可包括由ALD等沉积的一层或多层TaN、Ta、TiN、Ti、CoW等，且导电材料可包括由CVD、PVD等沉积的铜、铝、钨、银及其组合等。可例如通过使用CMP来移除介电层上的任何过量的扩散阻挡层和/或导电材料。
在重布线结构131上方形成介电层137。介电层137可包括单个层或多个层。介电层137可包含氧化硅、氮化硅、氮氧化硅、USG、TEOS、聚合物或其组合。所述聚合物包含感光性材料，例如聚苯并恶唑(PBO)、聚酰亚胺(PI)、苯并环丁烯(BCB)、其组合等。介电层137的形成方法包括合适的制作技术，例如旋转涂布、化学气相沉积(CVD)、等离子体增强化学气相沉积(PECVD)、层叠等。
此后，在介电层137中形成多个开口(图中未示出)，以暴露出重布线结构131的顶表面的一些部分。开口的形成方法可包括光刻及蚀刻工艺、激光钻孔工艺或其组合。
在开口36中及RDL 34上形成多个导电焊盘(UBM)139。导电焊盘139可由金属或金属合金(例如，铝、铜、镍或其合金)形成，并且可通过双镶嵌工艺、PVD、电镀或其组合形成。导电焊盘139贯穿介电层137以与重布线结构131的顶表面电接触。在一些实施例中，导电焊盘139的顶表面实质上与介电层137的顶表面共面，但本公开不限于此。在一些其他实施例中，导电焊盘139从介电层137的顶表面突出并延伸跨越所述顶表面。
导电焊盘139可包括晶种层及导电材料(图中未示出)。在一些实施例中，晶种层包括使用例如PVD等形成的钛层及位于所述钛层上方的铜层。在晶种层上方形成导电材料。导电材料可通过例如电镀或无电镀覆等镀覆形成。导电材料可包括金属，如铜、钛、钨、铝等。
在导电焊盘(UBM)139上形成电连接件141，并且通过重布线结构131将电连接件141电耦合到TV 109。电连接件141可被称为管芯连接件141。电连接件141形成在重布线结构131的顶表面处。在一些实施例中，电连接件141是焊球和/或凸块，例如球栅阵列(ballgrid array，BGA)球、受控塌陷芯片连接(controlled collapse chip connection，C4)微凸块、化镍浸金(electroless nickel/immersion gold，ENIG)形成的凸块、无电镀镍钯浸金技术(electroless nickel-electroless palladium-immersion gold technique，ENEPIG)形成的凸块等。电连接件141可包含导电材料，例如焊料、铜、铝、金、镍、银、钯、锡等、或其组合。在一些实施例中，电连接件141通过首先由例如蒸镀、电镀、印刷、焊料转移、植球等此类常用方法形成焊料层来形成。一旦已在结构上形成了焊料层，便可执行回焊，以将材料成形为期望的凸块形状。
在另一实施例中，电连接件141是通过溅镀、印刷、电镀、无电镀覆、CVD等形成的金属柱(例如，铜柱)。金属柱可以是无焊料的，并且具有实质上垂直的侧壁。在一些实施例中，在电连接件141的顶部上形成导电顶盖143。导电顶盖143可包含镍、锡、锡-铅、金、银、钯、铟、镍-钯-金、镍-金等或其组合，并且可通过镀覆工艺形成。
在一些实施例中，在导电焊盘(UBM)139上形成电连接件141之前，可在介电层137上形成绝缘层138。绝缘层138可包含一层或多层不可光图案化的绝缘材料，例如氮化硅、氧化硅、磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、掺杂有硼的磷硅酸盐玻璃(BPSG)、其组合等，并且可使用CVD、PVD、ALD、旋涂工艺、其组合等形成。在其他实施例中，绝缘层145可包含一层或多层可光图案化的绝缘材料，例如聚苯并恶唑(PBO)、聚酰亚胺(PI)、苯并环丁烯(BCB)、其组合等，并且可使用旋涂工艺等形成。此种可光图案化的绝缘材料可使用与光刻胶材料类似的光刻方法来图案化。此后，在绝缘层138中形成多个开口(图中未示出)以暴露出导电焊盘(UBM)139的一些部分，且然后在开口中形成电连接件141。开口的形成方法可包括光刻及蚀刻工艺、激光钻孔工艺或其组合。
参照图1F，然后对晶片1000执行芯片探测工艺或其他合适的芯片测试工艺，以识别已知良好管芯及不良管芯。在芯片探测工艺之后，移除导电顶盖143。此后，在电连接件141及重布线结构131上形成绝缘层145。在一些实施例中，绝缘层145及绝缘层138可包含相同的材料或不同的材料。在一些实施例中，使用CMP工艺、研磨工艺、蚀刻工艺、其组合等来平坦化绝缘层145。
此后，将晶片1000贴合到载体147，且然后执行载体剥离以从晶片1000分离(或“剥离”)载体129。
参照图1G及图1H，将晶片1000贴合到框架149，且然后从晶片1000移除载体147。沿切割道9及11将晶片1000单体化(参见图2A到图6A)，以形成个别3DIC结构1004。所述相应工艺在图8所示的工艺流程中被示出为步骤S30。在一些实施例中，可例如通过锯切、激光烧蚀、蚀刻、其组合等将晶片1000单体化成个别3DIC结构(或称为堆叠结构)1004。
参照图1H，此种单体化工艺还将虚设结构404单体化，并形成用于相应3DIC结构1004的个别(芯片级或管芯级)虚设结构404’。每个3DIC结构1004包括IC管芯104、装置管芯204及304、以及位于装置管芯204和/或装置管芯304旁边的虚设结构404’。3DIC结构1004还包括包封装置管芯204及304的包封体127。虚设结构404’的侧壁SW4与IC管芯104的侧壁SW1对齐。虚设结构404’的侧壁SW4实质上与IC管芯104的侧壁SW1齐平或共面。
如上所述，虚设结构404可减小IC管芯104与包封体127之间的热膨胀系数(CTE)失配，因为虚设结构404具有与IC管芯104相似的CTE，并且其减少了封装中必需的包封体127的体积。因此，虚设结构404’有助于减少由IC管芯104上的厚包封体引起的应力及翘曲，并减轻IC管芯104侧壁裂纹问题。在一些实施例中，装置管芯204及304以及虚设结构404’的面积之和对IC管芯104的面积的比率大于75％，包封体127的面积对IC管芯104的面积的比率小于25％。举例来说，装置管芯204及304以及虚设结构404’的面积之和对IC管芯104的面积的比率在75％到99％的范围内，且包封体127的面积对IC管芯104的面积的比率在1％到25％的范围内。
图2B示出根据一些实施例的从图2A所示晶片级管芯结构1000单体化的个别3DIC结构1004的俯视图。此种单体化工艺还将虚设结构404单体化，并形成用于相应3DIC结构1004的个别(芯片级或管芯级)虚设结构404’。每个3DIC结构1004包括IC管芯104、装置管芯204及304、以及位于IC管芯104上的两个虚设结构404’。
每个虚设结构404’具有沿第一方向D1的长度W4及沿第二方向D2的长度H4。第一方向D1垂直于第二方向D2。虚设结构404’的长度H4小于IC管芯104的长度H1。虚设结构404’的长度H4可等于、大于或小于装置管芯204的长度H2。在一些实施例中，长度H4对长度H3与H2之差(ΔH＝|H3-H2|，绝对值)的比率R2(R2＝H4/ΔH)大于10％、100％、200％、300％或400％。举例来说，比率R2介于500％到10％的范围内。
IC管芯104的长度W1大于装置管芯304的长度W3。装置管芯304的长度W3大于装置管芯204的长度W2。虚设结构404’设置在装置管芯204的旁边。虚设结构404’的长度W4小于装置管芯304的长度W3。虚设结构404’的长度W4可等于、大于或小于装置管芯204的长度W2。在一些实施例中，长度W4对长度W3与W2之差(ΔW＝W3-W2)的比率R1(R1＝W4/ΔW)大于10％、50％、70％、100％、200％、300％或400％。举例来说，比率R1介于500％到10％的范围内。
管芯204的四个侧壁及装置管芯304的四个侧壁被包封体127包围。虚设结构404’被包封体127部分包围。在一些实施例中，每个虚设结构404’的三个侧壁被包封体127包围，并且每个虚设结构404’的一个侧壁SW4被包封体127暴露出。虚设结构404’的侧壁SW4与IC管芯104的侧壁SW1及位于装置管芯304旁边的包封体127的侧壁SWe对齐。虚设结构404’的侧壁SW4实质上与IC管芯104的侧壁SW1及位于装置管芯304旁边的包封体127的侧壁SWe齐平或共面。
图3B示出根据一些实施例的从图3A所示晶片级管芯结构1000单体化的个别3DIC结构1004的俯视图。在沿切割道9及11将晶片级管芯结构1000单体化之后，虚设结构4041及4042保留在个别3DIC结构1004中。每个3DIC结构1004包括IC管芯104、以及位于IC管芯104上的装置管芯204及304、两个虚设结构4041及一个虚设结构4042。虚设结构4041与4042彼此分开。在一些实施例中，在俯视图中，虚设结构4041具有矩形形状，并且虚设结构4042具有矩形环形形状。
虚设结构4041设置在装置管芯204的旁边。每个虚设结构4041具有沿第一方向D1的长度W41及沿第二方向D2的长度H41。第一方向D1垂直于第二方向D2。虚设结构4041的长度H41小于IC管芯104的长度H1。虚设结构4041的长度H41可等于、大于或小于装置管芯204的长度H2。在一些实施例中，长度H41对长度H3与长度H2之差(ΔH＝H3-H2)的比率R12(R12＝H41/ΔH)大于10％。举例来说，比率R12介于10％到500％的范围内。
IC管芯104的长度W1大于装置管芯304的长度W3。装置管芯204的长度W3大于装置管芯204的长度W2。虚设结构4041的长度W41小于装置管芯304的长度W3。虚设结构4041的长度W41可等于、大于或小于装置管芯204的长度W2。在一些实施例中，长度W41对长度W3与W2之差(ΔW＝W3-W2)的比率R11(R11＝W4/ΔW)大于10％。举例来说，比率R11介于10％到500％的范围内。
虚设结构4042包围装置管芯204及304以及虚设结构4041。虚设结构4042包括两个部分P1及两个部分P2。每个部分P1具有沿第一方向D1的长度L1，且每个部分P2具有沿第二方向D2的长度L2。第一方向D1垂直于第二方向D2。在一些实施例中，虚设结构4042的部分P1的长度L1可等于IC管芯104的长度W1，并且虚设结构4042的部分P2的长度L2可等于IC管芯104的长度H1。
每个部分P1具有宽度H42，且虚设结构4042的每个部分P2具有宽度W42。在一些实施例中，虚设结构4042的部分P1的宽度H42大于虚设结构4042与装置管芯204之间的包封体127的宽度H7。虚设结构4042的部分P2的宽度W42大于虚设结构4042与装置管芯304之间的包封体127的宽度W7。宽度W42可与宽度H42相同或不同。
包封体127填充在虚设结构4042内。管芯204的四个侧壁、装置管芯304的四个侧壁及虚设结构4041的四个侧壁被包封体127包围。后续工艺中的包封体127及包封体142(参见图7C)被虚设结构4042分开。
在一些实施例中，虚设结构4042的四个侧壁SW42分别与IC管芯104的四个侧壁SW1对齐。虚设结构4042的四个侧壁SW42分别实质上与IC管芯104的四个侧壁SW1齐平或共面。此外，相应3DIC结构1004的IC管芯104的四个拐角C被虚设结构4042覆盖。
图4B示出根据一些实施例的从图4A所示管芯区1131、1132、1134及1135中的晶片级管芯结构1000单体化的个别3DIC结构1004的俯视图。此种单体化工艺还将虚设结构4042/4043/4044单体化，并分别形成个别(芯片级或管芯级)虚设结构40421、40422、40423、40424/40431、40432/40441及40442。虚设结构40421、40422、40423、40424、40431、40432、40441及40442设置在不同的区中，且因此管芯区1131、1132、1134及1135中的3DIC结构1004具有不同的结构。
管芯区1131中的3DIC结构1004包括IC管芯104、以及位于IC管芯104上的装置管芯204及304、两个虚设结构4041及一个虚设结构40421。在一些实施例中，在俯视图中，虚设结构4041具有矩形形状，并且虚设结构40421具有矩形环形形状。装置管芯204及304以及虚设结构4041被包封体127及虚设结构40421包围。虚设结构4041及40421的配置类似于图3B所示实施例的虚设结构4041及4042的配置，并且在此不再予以赘述。
管芯区1132中的3DIC结构1004包括装置管芯204及304、两个虚设结构4041、两个虚设结构40422及两个虚设结构40441。虚设结构4041、40422及40441在俯视图中具有矩形形状。装置管芯204及304以及虚设结构4041被包封体127及虚设结构40422及40441包围。虚设结构4041的配置类似于图3B所示实施例的虚设结构4041的配置，并且在此不再予以赘述。
虚设结构40422沿第一方向D1延伸，并且虚设结构40441沿第二方向D2延伸。虚设结构40422具有沿第一方向D1的长度W422，并且虚设结构40441具有沿第二方向D2的长度H441。在一些实施例中，虚设结构40422沿第一方向D1的长度W422可等于IC管芯104沿第二方向D2的长度W1，并且虚设结构40441沿第二方向D2的长度H441可小于IC管芯104沿第二方向D2的长度H1。
在第一方向D1上，两个虚设结构40422的两个侧壁SW4221与IC管芯104的两个侧壁SW1对齐。在第二方向D2上，两个虚设结构40441的两个侧壁SW441与IC管芯104的另外两个侧壁SW1对齐。虚设结构40422的每个侧壁SW4221实质上与IC管芯104的侧壁SW1齐平或共面。虚设结构40441的每个侧壁SW441实质上与包封体127的两个侧壁SWe、虚设结构40422的两个侧壁SW4222齐平或共面，并且实质上与IC管芯104的侧壁SW1齐平或共面。管芯区1132中相应3DIC结构1004的IC管芯104的四个拐角C上面覆盖有两个虚设结构40422。
管芯区1134中的3DIC结构1004包括装置管芯204及304、两个虚设结构4041、两个虚设结构40431及两个虚设结构40423。虚设结构4041、40431及40423在俯视图中具有矩形形状。装置管芯204及304以及虚设结构4041被包封体127及虚设结构40431及40423包围。虚设结构4041的配置类似于图3B所示实施例的虚设结构4041的配置，并且在此不再予以赘述。
虚设结构40431沿第一方向D1延伸，并且虚设结构40423沿第二方向D2延伸。虚设结构40431具有沿第一方向D1的长度W431，并且虚设结构40423具有沿第二方向D2的长度H423。在一些实施例中，虚设结构40431的长度W431可小于IC管芯104的长度W1，并且虚设结构40423的长度H423可等于IC管芯104的长度H1。
在第一方向D1上，两个虚设结构40431的两个侧壁SW431与IC管芯104的两个侧壁SW1对齐。在第二方向D2上，两个虚设结构40423的两个侧壁SW4231与IC管芯104的另外两个侧壁SW1对齐。虚设结构40431的每个侧壁SW431实质上与包封体127的两个侧壁SWe、虚设结构40423的两个侧壁SW4232齐平或共面，并实质上与IC管芯104的侧壁SW1齐平或共面。虚设结构40423的每个侧壁SW4231实质上与IC管芯104的另一侧壁SW1齐平或共面。管芯区1132中相应3DIC结构1004的IC管芯104的四个拐角C上面覆盖有两个虚设结构40423。
管芯区1135中的3DIC结构1004包括装置管芯204及304、两个虚设结构4041、两个虚设结构40432以及两个虚设结构40442及40424。虚设结构4041、40432、40442及40424在俯视图中具有矩形形状。装置管芯204及304以及虚设结构4041被包封体127及虚设结构40432、40442及40424包围。虚设结构4041的配置类似于图3B所示实施例的虚设结构4041的配置，并且在此不再予以赘述。
虚设结构40432沿第一方向D1延伸，并且虚设结构40442沿第二方向D2延伸。虚设结构40432具有沿第一方向D1的长度W432，并且虚设结构40442具有沿第二方向D2的长度H442。在一些实施例中，虚设结构40432的长度W432可小于IC管芯104的长度W1，并且虚设结构40442的长度H442可小于IC管芯104的长度H1。管芯区1132中的相应3DIC结构1004的IC管芯104的四个拐角C上面覆盖有四个虚设结构40424。
在第一方向D1上，两个虚设结构40432的两个侧壁SW432与IC管芯104的两个侧壁SW1对齐。在第二方向D2上，虚设结构40442的两个侧壁SW4422与IC管芯104的另外两个侧壁SW1对齐。虚设结构40432的每个侧壁SW432实质上与包封体127的两个侧壁SWe、两个虚设结构40442的两个侧壁SW4242齐平或共面，并且实质上与IC管芯104的侧壁SW1齐平或共面。虚设结构40442的每个侧壁SW4422实质上与包封体127的两个侧壁SWe、虚设结构40424的两个侧壁SW4241齐平或共面，并且实质上与IC管芯104的另一侧壁SW1齐平或共面。
对于管芯区1131中的3DIC结构1004来说，包封体127被虚设结构404’侧向包裹，并且不被虚设结构404’暴露出。对于管芯区1132、1134及1135中的3DIC结构1004来说，大部分包封体127被虚设结构404’包裹，且包封体127的一小部分被虚设结构404’暴露出。换句话说，包封体127的被暴露出的侧壁SWe的面积小于虚设结构404’的被暴露出的侧壁的面积。
图5B示出根据一些实施例的从图5A所示晶片级管芯结构1000单体化的个别3DIC结构1004的俯视图。在沿切割道9及11将晶片级管芯结构1000单体化之后，虚设结构4041、4042及4043保留在个别3DIC结构1004中。每个3DIC结构1004包括装置管芯204及304、两个虚设结构4041、两个虚设结构4042及两个虚设结构4043。虚设结构4041、4042及4043在俯视图中具有矩形形状。装置管芯204及304以及虚设结构4041被包封体127及虚设结构4042及4043包围。虚设结构4041、4042及4043的配置类似于图4B所示实施例的虚设结构4041、40431及40423的配置，并且在此不再予以赘述。
图6B示出根据一些实施例的从图6A所示晶片级管芯结构1000单体化的个别3DIC结构1004的俯视图。在沿切割道9及11将晶片级管芯结构1000单体化之后，虚设结构4041被保留。此种单体化工艺还将虚设结构4042及4043单体化。虚设结构4042形成个别虚设结构40421及40422，且虚设结构4043形成个别虚设结构40431及40432。虚设结构40421与40422可具有相同的大小或不同的大小。虚设结构40431与40432可具有相同的大小或不同的大小。虚设结构4041、40421、40422、40431及40432的配置类似于图4B所示实施例的虚设结构4041、40431及40423的配置，并且在此不再予以赘述。
在一些实施例中，虚设结构404’中的一者可沿第一方向D1或/和第二方向D2与其他虚设结构404’合并在同一管芯区113i中。举例来说，如图3C、图4C、图4D、图4E、图4F、图5C及图6C所示，图3B到图6B所示的虚设结构4041可沿第一方向D1或第二方向D2与其他虚设结构404’合并在同一管芯区113i中，并且在所述虚设结构之间没有界面。
放置在IC管芯104的拐角和/或边缘上方的虚设结构404’可有助于防止在封装单体化期间及之后的翘曲。此外，虚设结构404’可藉由减小IC管芯104与包封体127之间的热膨胀系数(CTE)失配而防止翘曲，因为虚设结构404’具有与IC管芯104相似的CTE，并且其减少了封装中所需的包封体127的量。
图7A到图7E示出根据一些实施例的形成封装的剖视图。
参照图7A，提供载体衬底102，并且在载体衬底102上形成释放层124。载体衬底102可以是玻璃载体衬底、陶瓷载体衬底等。载体衬底102可以是晶片，使得可同时在载体衬底102上形成多个封装。释放层124可由聚合物系材料形成，其可与载体衬底102一起从将在后续步骤中形成的上覆结构移除。在一些实施例中，释放层124是在被加热时失去其粘合性质的环氧树脂系热释放材料，例如光-热转换(light-to-heat-conversion，LTHC)释放涂层。在其他实施例中，释放层124可以是紫外线(ultra-violet，UV)胶，其在暴露于UV光时失去其粘合性质。释放层124可作为液体分配并固化，可以是层叠在载体衬底102上的层叠膜，或者可以是类似物。释放层124的顶表面可以是齐平的，并且可具有高的平坦度。
在释放层124上形成介电层108。在一些实施例中，介电层108由例如聚苯并恶唑(PBO)、聚酰亚胺、苯并环丁烯(BCB)等聚合物形成。在其他实施例中，介电层108由以下形成：氮化物，例如氮化硅；氧化物，例如氧化硅；磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、掺杂有硼的磷硅酸盐玻璃(BPSG)等；或类似物。可通过例如旋转涂布、化学气相沉积(CVD)、层叠等或其组合等任何可接受的沉积工艺来形成介电层108。
参照图7A，在释放层124上形成导电柱116。作为形成导电柱116的实例，在释放层124上方形成晶种层。在一些实施例中，晶种层是金属层，所述金属层可以是单个层或包括由不同材料形成的多个子层的复合层。举例来说，晶种层包括钛层及位于钛层上方的铜层。晶种层可使用例如PVD等形成。在晶种层上形成光刻胶并将光刻胶图案化。光刻胶可通过旋转涂布等形成，并且可被曝光以进行图案化。图案化形成穿过光刻胶的开口，以暴露出晶种层。导电材料形成在光刻胶的开口中及晶种层的被暴露出的部分上。导电材料可通过例如电镀或无电镀覆等镀覆形成。导电材料可包括金属，如铜、钛、钨、铝等。移除光刻胶以及晶种层的上面没有形成导电材料的部分。可例如使用氧等离子体等通过可接受的灰化或剥除工艺来移除光刻胶。一旦光刻胶被移除，便例如使用可接受的蚀刻工艺(例如，通过湿法蚀刻或干法蚀刻)移除晶种层的被暴露出的部分。晶种层及导电材料的剩余部分形成导电柱116。
参照图7B，通过粘合剂128将3DIC结构1004粘合到介电层108。粘合剂128位于3DIC结构1004的后侧表面上，并将3DIC结构1004粘合到释放层124。粘合剂128可以是任何合适的粘合剂、环氧树脂、管芯贴合膜(die attach film，DAF)等。
参照图7B，在各种组件上形成包封体142。在形成之后，以包封体142侧向包封导电柱116及3DIC结构1004。在一些实施例中，包封体142包括模制化合物、模制底层填充材料、例如环氧树脂等树脂、其组合等。在一些其他实施例中，包封体142包含感光性材料，例如聚苯并恶唑(PBO)、聚酰亚胺(PI)、苯并环丁烯(BCB)、其组合等，所述材料可易于通过曝光及显影工艺或激光钻孔工艺被图案化。在替代实施例中，包封体142包含氮化物(例如，氮化硅)、氧化物(例如，氧化硅)、磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、掺杂有硼的磷硅酸盐玻璃(BPSG)、其组合等。
在一些实施例中，包封体142包含复合材料，所述复合材料包括基材(例如，聚合物)以及位于基材中的多种填充剂。填充剂可以是单一元素、化合物(例如，氮化物、氧化物)或其组合。举例来说，填充剂可包括氧化硅、氧化铝、氮化硼、铝氧化物、二氧化硅等。填充剂的横截面形状可以是圆形、椭圆形或任何其他形状。在一些实施例中，填充剂是球形颗粒等。填充剂的横截面形状可以是圆形、椭圆形或任何其他形状。在一些实施例中，填充剂包括固体填充剂，但本公开不限于此。在一些实施例中，一小部分填充剂可以是中空填充剂。
包封体142可通过压缩模制、转移模制(transfer molding)、旋转涂布、层叠、沉积或类似工艺来施加，并且可形成在载体衬底102上方，使得导电柱116和/或3DIC结构1004被掩埋或覆盖。然后将包封体142固化。导电柱116穿透包封体142，并且导电柱116有时被称为穿孔116或集成扇出型穿孔(through integrated fan-out via，TIV)116。
参照图7C，然后对包封体142执行平坦化工艺，以移除包封体142的一部分，使得穿孔116及管芯连接件141的顶表面被暴露出。在其中穿孔116的顶表面与3DIC结构1004的前侧表面不共面(如图7B所示)的一些实施例中，穿孔116的一些部分或/和介电材料140的一些部分也可通过平坦化工艺被移除。在一些实施例中，穿孔116、管芯连接件141、介电材料140及包封体142的顶表面在平坦化工艺之后实质上共面。平坦化工艺可以是例如化学机械抛光(CMP)、研磨工艺等。在一些实施例中，举例来说，如果穿孔116及管芯连接件141已被暴露出，那么可省略平坦化。
参照图7D，在穿孔116、包封体142及3DIC结构1004的前侧表面上方形成前侧重布线结构144。前侧重布线结构144包括：介电层146、150、154及158；金属化图案148、152及156；以及凸块下金属(under bump metallurgy，UBM)160。金属化图案也可被称为重布线层或重布线走线。前侧重布线结构144被示出作为实例。可在前侧重布线结构144中形成更多或更少的介电层及金属化图案。如果将形成更少的介电层及金属化图案，那么可省略以下论述的步骤及工艺。如果将形成更多的介电层及金属化图案，那么可重复以下论述的步骤及工艺。
作为形成前侧重布线结构144的实例，在包封体142、穿孔116及管芯连接件141上沉积介电层146。在一些实施例中，介电层146由感光性材料(例如，PBO、聚酰亚胺、BCB等)形成，所述材料可使用光刻掩模来图案化。介电层146可通过旋转涂布、层叠、CVD等或其组合来形成。然后，将介电层146图案化。图案化形成暴露出穿孔116及管芯连接件141的一些部分的开口。图案化可通过可接受的工艺进行，例如当介电层146是感光性材料时通过将介电层146曝光，或者通过使用例如各向异性蚀刻进行蚀刻。如果介电层146是感光性材料，那么介电层146可在曝光后显影。
然后形成金属化图案148。金属化图案148包括位于介电层146的顶表面上并沿所述顶表面延伸的导线CL。金属化图案148还包括延伸穿过介电层146以物理及电连接到穿孔116及3DIC结构1004的导通孔V。导通孔V及导线CL的侧壁可以是直的或倾斜的。在一些实施例中，导通孔V具有倾斜的侧壁，并且朝着3DIC结构1004逐渐变细。为形成金属化图案148，在介电层146上方及延伸穿过介电层146的开口中形成晶种层。在一些实施例中，晶种层是金属层，所述金属层可以是单个层或包括由不同材料形成的多个子层的复合层。在一些实施例中，晶种层包括钛层及位于钛层上方的铜层。晶种层可使用例如PVD等形成。然后在晶种层上形成光刻胶并将光刻胶图案化。光刻胶可通过旋转涂布等形成，并且可被曝光以进行图案化。光刻胶的图案对应于金属化图案148。图案化形成穿过光刻胶的开口，以暴露出晶种层。然后在光刻胶的开口中及晶种层的被暴露出的部分上形成导电材料。导电材料可通过例如电镀或无电镀覆等镀覆形成。导电材料可包括金属，如铜、钛、钨、铝等。导电材料与晶种层的下伏部分的组合形成金属化图案148。移除光刻胶以及晶种层的上面没有形成导电材料的部分。可例如使用氧等离子体等通过可接受的灰化或剥除工艺来移除光刻胶。一旦光刻胶被移除，便例如使用可接受的蚀刻工艺(例如，通过湿法蚀刻或干法蚀刻)移除晶种层的被暴露出的部分。
交替形成介电层150、154、158及金属化图案152、156。介电层150、154及158可以类似于介电层146的方式形成，并且可由与介电层146相同的材料形成。金属化图案152及156可包括位于下伏介电层上的导线CL及分别延伸穿过下伏介电层的导通孔V。金属化图案152及156可以类似于金属化图案148的方式形成，并且可由与金属化图案148相同的材料形成。UBM 160视情况形成在介电层158上并延伸穿过介电层158。UBM 160可以类似于金属化图案148的方式形成，并且可由与金属化图案148相同的材料形成。
参照图7D，在UBM 160上形成导电连接件162。导电连接件162可以是球栅阵列(BGA)连接件、焊球、金属柱、受控塌陷芯片连接(C4)凸块、微凸块、无电镀镍钯浸金技术(ENEPIG)形成的凸块等。导电连接件162包括通过溅镀、印刷、电镀、无电镀覆、CVD等形成的金属柱(例如，铜柱)。金属柱可以是无焊料的，并且具有实质上垂直的侧壁。在一些实施例中，在金属柱的顶部上形成金属顶盖层。金属顶盖层可包含镍、锡、锡-铅、金、银、钯、铟、镍-钯-金、镍-金等或其组合，并且可通过镀覆工艺形成。在另一实施例中，导电连接件162可包含导电材料，例如焊料、铜、铝、金、镍、银、钯、锡等、或其组合。在一些实施例中，导电连接件162通过首先由例如蒸镀、电镀、印刷、焊料转移、植球等此类常用方法形成焊料层来形成。一旦已在结构上形成了焊料层，便可执行回焊工艺，以将材料成形为期望的凸块形状。
参照图7D及图7E，执行载体衬底剥离以从介电层108分离(或“剥离”)载体衬底102，以形成InFO封装166。根据一些实施例，剥离包括将例如激光或UV光等光投射到释放层124上，使得释放层124在光的热量下分解，并且载体衬底102可被移除。然后，将InFO封装166翻转并放置在胶带(图中未示出)上。
参照图7E，可将顶部封装500结合到InFO封装166。顶部封装500包括衬底502及耦合到衬底502的一个或多个堆叠管芯(或管芯)508。衬底502可由例如硅、锗、金刚石等半导体材料制成。在一些实施例中，也可使用化合物材料，例如硅锗、碳化硅、砷化镓、砷化铟、磷化铟、硅锗碳化物、磷化镓砷、磷化镓铟、其组合等。另外，衬底502可以是SOI衬底。一般来说，SOI衬底包括半导体材料(例如，外延硅、锗、硅锗、SOI、绝缘体上硅锗(SGOI)或其组合)层。在一个替代实施例中，衬底502基于绝缘芯，例如玻璃纤维增强树脂芯。芯材的一个实例是玻璃纤维树脂，例如FR4。芯材的替代物包括双马来酰亚胺-三嗪(bismaleimide-triazine，BT)树脂，或作为另一选择，包括其他印刷电路板(printed circuit board，PCB)材料或膜。可将例如味之素积层膜(Ajinomoto build-up film，ABF)等积层膜或其他层叠体用于衬底502。
衬底502可包括有源及无源装置(图中未示出)。如所属领域中的普通技术人员将认识到，可使用例如晶体管、电容器、电阻器、其组合等各种各样的装置来产生顶部封装500的设计的结构及功能要求。可使用任何合适的方法来形成装置。
衬底502还可包括金属化层(图中未示出)及穿孔506。金属化层可形成在有源及无源装置上方，并且被设计成连接各种装置以形成功能电路系统。金属化层可由交替的介电质(例如，低介电常数介电材料)层及导电材料(例如，铜)层(其中通孔互连各导电材料层)形成，并且可通过任何合适的工艺(例如，沉积、镶嵌、双镶嵌等)形成。在一些实施例中，衬底502实质上不具有有源装置及无源装置。
衬底502可在衬底502的第一侧上具有结合焊盘503以耦合到堆叠管芯508，并且在衬底502的第二侧上具有结合焊盘504以耦合到导电连接件168，其中衬底502的第二侧与第一侧相对。在一些实施例中，通过在衬底502的第一侧及第二侧上的介电层(图中未示出)中形成凹陷(图中未示出)来形成结合焊盘503及504。可形成凹陷以允许结合焊盘503及504嵌入介电层中。在其他实施例中，由于结合焊盘503及504可形成在介电层上，因此省略了凹陷。在一些实施例中，结合焊盘503及504包括由铜、钛、镍、金、钯等或其组合制成的薄晶种层(图中未示出)。结合焊盘503及504的导电材料可沉积在薄晶种层上方。所述导电材料可通过电化学镀覆工艺、无电镀覆工艺、CVD、ALD、PVD等或其组合来形成。在实施例中，结合焊盘503及504的导电材料是铜、钨、铝、银、金等、或其组合。在实施例中，结合焊盘503及504是使用与较早结合UBM 160描述的相同或相似工艺形成的UBM。
在所示实施例中，通过引线结合510将堆叠管芯508耦合到衬底502，但也可使用其他连接，例如导电凸块。在实施例中，堆叠管芯508是堆叠存储器管芯。举例来说，堆叠存储器管芯508可包括低功率(low-power，LP)双倍数据速率(double data rate，DDR)存储器模块，例如LPDDR1、LPDDR2、LPDDR3、LPDDR4或类似存储器模块。
在一些实施例中，可由模制材料512包封堆叠管芯508及引线结合510。模制材料512可例如使用压缩模制而被模制在堆叠管芯508及引线结合510上。在一些实施例中，模制材料512是模制化合物、聚合物、环氧树脂、氧化硅填充剂材料等或其组合。可执行固化步骤来固化模制材料512，其中固化可以是热固化、UV固化等或其组合。
在一些实施例中，将堆叠管芯508及引线结合510埋置在模制材料512中，并且在固化模制材料512之后，执行平坦化步骤(例如，研磨)以移除模制材料512的多余部分，并且为顶部封装500提供实质上平面的表面。
在形成顶部封装500之后，通过导电连接件168及结合焊盘504将顶部封装500结合到InFO封装166。在一些实施例中，堆叠存储器管芯508可通过引线结合510、结合焊盘503及504、穿孔506、导电连接件168及穿孔116耦合到3DIC结构1004。
导电连接件168可类似于上述连接件68，并且在此不再予以赘述，但导电连接件168与68不必相同。在一些实施例中，在结合导电连接件168之前，用例如免清洗助焊剂(non-clean flux)等助焊剂(图中未示出)对导电连接件168进行涂布。可将导电连接件168浸入助焊剂中，或者可将助焊剂喷射到导电连接件168上。
在一些实施例中，导电连接件168在被回焊之前可在其上形成有环氧树脂助焊剂(图中未示出)，其中在将顶部封装500贴合到InFO封装166之后，环氧树脂助焊剂的至少一些环氧树脂部分存留。此存留的环氧树脂部分可充当底部填充材料，以减少应力并保护由回焊导电连接件168产生的接头。在一些实施例中，可在顶部封装500与InFO封装166之间且围绕导电连接件168形成底部填充材料170。底部填充材料170可在贴合顶部封装500之后通过毛细流动工艺(capillary flow process)形成，或者可在贴合顶部封装500之前通过合适的沉积方法形成。
顶部封装500与InFO封装166之间的结合可以是焊料结合或直接金属对金属(例如，铜对铜或锡对锡)的结合。在实施例中，通过回焊工艺将顶部封装500结合到InFO封装166。在此回焊工艺期间，导电连接件168与结合焊盘504及穿孔116接触，以将顶部封装500物理及电耦合到InFO封装166。
所公开的封装结构的实施例包括位于管芯区中或者进一步位于切割道区中的虚设结构。所述虚设结构可允许对包封体的比率进行更多控制，且因此可减少应力及由热膨胀系数(CTE)失配引起的翘曲。
根据本公开的一些实施例，一种封装结构的制造方法包括：通过混合结合将第一管芯及第二管芯结合到晶片的第一管芯区中的所述晶片；将第一虚设结构结合到所述第一管芯区中的所述晶片及所述晶片的第一切割道；以及沿所述第一切割道使所述晶片及所述第一虚设结构单体化，以形成堆叠集成电路(IC)结构。
根据本公开的一些实施例，所述第一虚设结构被结合在由所述晶片的所述第一管芯、所述第二管芯、所述第一切割道及第二切割道包围的区域中，并且延伸到第二管芯区。
根据本公开的一些实施例，所述第一虚设结构从所述晶片的所述第一管芯区延伸到第二管芯区。
根据本公开的一些实施例，所述第一虚设结构与所述晶片的所述第一切割道及第二切割道交叠，并且所述第一切割道与所述第二切割道沿着不同的方向。
根据本公开的一些实施例，所述的方法，还包括：将第二虚设结构结合到所述第二管芯区中的所述晶片及所述晶片的所述第一切割道；以及将第三虚设结构结合到第三区中的所述晶片及所述晶片的所述第二切割道。
根据本公开的一些实施例，所述第一虚设结构在俯视图中具有矩形形状或环形形状。
根据本公开的一些实施例，所述第一虚设结构是虚设管芯，并且所述虚设管芯包括硅衬底及位于所述硅衬底上的第一绝缘层。
根据本公开的一些实施例，所述晶片包括具有第二绝缘层的第三管芯，并且所述第一虚设结构通过熔融结合所述第一绝缘层与所述第二绝缘层而结合到所述第三管芯，并且所述混合结合包括金属到金属的直接结合及介电质到介电质的结合。
根据本公开的替代实施例，一种封装结构的制造方法包括：将第一管芯及第二管芯结合到晶片的管芯区中的所述晶片；将第一虚设结构结合到所述管芯区中的所述晶片，以覆盖在所述管芯区的多个拐角上方；以及将所述晶片单体化以形成堆叠集成电路(IC)结构。
根据本公开的一些实施例，所述第一虚设结构是虚设管芯，并且所述虚设管芯包括硅衬底及位于所述硅衬底上的第一绝缘层。
根据本公开的一些实施例，所述晶片包括：具有第二绝缘层的第三管芯，并且所述第一虚设结构通过熔融结合所述第一绝缘层与所述第二绝缘层而结合到所述第三管芯，且所述第一管芯及所述第二管芯通过混合结合而结合到所述第三管芯，并且所述混合结合包括金属到金属的直接结合及介电质到介电质的结合。
根据本公开的一些实施例，所述第一虚设结构在俯视图中具有矩形形状或环形形状。
根据本公开的一些实施例，所述的方法还包括：将第二虚设结构结合到所述管芯区中的所述晶片，其中所述第一虚设结构邻近所述晶片的第一切割道，而所述第二虚设结构邻近所述晶片的第二切割道，并且所述第一切割道与所述第二切割道是沿着不同的方向。根据本公开的一些实施例，一种封装结构包括：底部管芯；第一管芯，结合到所述底部管芯的第一侧；第二管芯，结合到所述底部管芯的所述第一侧；包封体，侧向包封所述第一管芯及所述第二管芯；以及第一虚设管芯，结合到所述底部管芯的所述第一侧，其中所述第一虚设管芯的侧壁与所述底部管芯的第一侧壁共面。
根据本公开的一些实施例，所述第一虚设结构在俯视图中具有矩形形状或环形形状。
根据本公开的一些实施例，所述第一虚设结构覆盖在所述底部管芯的多个拐角上方。
根据本公开的一些实施例，所述包封体位于所述第一虚设结构内并被所述第一虚设结构包围。
根据本公开的一些实施例，所述的封装结构还包括：第二虚设结构，结合到所述底部管芯的所述第一侧，其中所述第一虚设结构与所述第二虚设结构沿着不同的方向，并且所述第二虚设结构的侧壁与所述底部管芯的第二侧壁共面。
根据本公开的一些实施例，所述包封体邻接所述第一虚设结构及所述第二虚设结构。
根据本公开的一些实施例，所述的封装结构还包括：穿孔，延伸穿过所述底部管芯，所述第一管芯及所述第二管芯电耦合到所述穿孔；重布线结构，位于所述底部管芯的第二侧上，所述第二侧与所述第一侧相对；以及多个电连接件，位于所述重布线结构上，所述多个电连接件通过所述重布线结构电耦合到所述穿孔。
[符号的说明]
9、11：切割道
102：载体衬底
104：IC管芯
104a：IC管芯的前侧表面
104b：IC管芯的后侧表面
105：衬底
105b：衬底的后侧表面
108：介电层
109：穿孔(TV)
111：介电层
113：互连件
1131、1132、1133、1134、1135、1136、1137、1138、1139、113i：管芯区
114：互连结构
115：接触焊盘
116：导电柱/穿孔/集成扇出型穿孔(TIV)
117：介电层
119：绝缘层
120：结合结构
121：通孔
123：结合焊盘
124：释放层
125：虚设焊盘/虚设结合焊盘
127：包封体
128：粘合剂
129：载体
131：重布线结构
133：介电层
135：金属化图案
137：介电层
138：绝缘层
139：导电焊盘(UBM)
141：电连接件/管芯连接件
142：包封体
143：导电顶盖
144：前侧重布线结构
145：绝缘层
146：介电层
147：载体
148：金属化图案
149：框架
150：介电层
152：金属化图案
154：介电层
156：金属化图案
158：介电层
160：凸块下金属(UBM)
162：导电连接件
166：InFO封装
168：导电连接件
170：底部填充材料
204：装置管芯
205：衬底
214：互连结构
215：接触焊盘
217：介电层
219：绝缘层
220：结合结构
221：通孔
223：结合焊盘
225：虚设焊盘
304：装置管芯
305：衬底
314：互连结构
315：接触焊盘
317：介电层
319：绝缘层
320：结合结构
321：通孔
323：结合焊盘
325：虚设焊盘
404：虚设结构/虚设管芯
404’、4041、4042、4043、4044、40421、40422、40423、40424、40431、40432、40441、40442：虚设结构
404a：虚设结构的前侧表面
404b、404c：虚设结构的后侧表面
405：块状材料
419：绝缘层
500：顶部封装
502：衬底
503、504：结合焊盘
506：穿孔
508：堆叠管芯/堆叠存储器管芯
510：引线结合
512：模制材料
1000：晶片级管芯结构/晶片
1004：3DIC结构
C：拐角
CL：导线
D1：第一方向
D2：第二方向
H1、H2、H3、H4、H41、H423、H441、H442：长度
H7、H42：宽度
I-I’：线
L1：长度
P1、P2：虚设结构的部分
S10、S20、S30：步骤
SW1：IC管芯的侧壁
SW4、SW42、SW4221、SW4222、SW4231、SW4232、SW4241、SW4242、SW431、SW432、SW441、SW442：虚设结构的侧壁
SWe：包封体的侧壁
T1、T2、T3：厚度
V：导通孔
W1：IC管芯的长度
W2：装置管芯的长度
W3：装置管芯的长度
W4：虚设结构的长度
W7：包封体的宽度
W41：虚设结构的长度
W42：虚设结构的宽度
W422、W431、W432：虚设结构的长度

Claims (1)

1.一种封装结构的制造方法，其特征在于包括：
通过混合结合将第一管芯及第二管芯结合到晶片的第一管芯区中的所述晶片；
将第一虚设结构结合到所述第一管芯区中的所述晶片及所述晶片的第一切割道；以及
沿所述第一切割道使所述晶片及所述第一虚设结构单体化，以形成堆叠集成电路结构。
CN202110650402.6A 2020-06-15 2021-06-10 封装结构的制造方法 Pending CN113808959A (zh)

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