TW202201583A - 封裝結構的製造方法 - Google Patents

封裝結構的製造方法 Download PDF

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TW202201583A
TW202201583A TW110121577A TW110121577A TW202201583A TW 202201583 A TW202201583 A TW 202201583A TW 110121577 A TW110121577 A TW 110121577A TW 110121577 A TW110121577 A TW 110121577A TW 202201583 A TW202201583 A TW 202201583A
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Taiwan
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wafer
dummy
structures
die
layer
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TW110121577A
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English (en)
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陳明發
葉松峯
劉醇鴻
史朝文
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台灣積體電路製造股份有限公司
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Abstract

提供一種封裝結構及其製造方法。所述方法包括：通過混合結合將第一晶片及第二晶片結合到晶片的第一晶片區中的所述晶片；將第一虛設結構結合到所述第一晶片區中的所述晶片及所述晶片的第一切割道；以及沿所述第一切割道使所述晶片及所述第一虛設結構單體化，以形成堆疊積體電路（IC）結構。

Description

封裝結構的製造方法
本發明實施例是有關於一種封裝結構及其製造方法。
由於對積體電路（integrated circuit，IC）的開發，半導體行業已因各種電子元件（即電晶體、二極體、電阻器、電容器等）積體密度的不斷提升而經歷連續快速成長。最重要的是，積體密度的這些提升是源自最小特徵大小的不斷減小，而使得更多的元件能夠整合到給定面積中。
積集度提升本質上是從二維（two-dimensional，2D）層面來說，原因在於積體元件所佔據的面積主要位於半導體晶片的表面上。密度的增加以及積體電路的面積的相應減小通常超出了將積體電路晶片直接結合到基底上的能力。中介層（interposer）可用來將球接觸面積從晶片重佈線到更大面積的中介層。此外，中介層可包含多個晶片的三維（three-dimensional，3D）封裝。還已開發出其他封裝來併入三維方面。
本揭露的一些實施例提出一種封裝結構的製造方法包括：通過混合結合將第一晶片及第二晶片結合到晶片的第一晶片區中的所述晶片；將第一虛設結構結合到所述第一晶片區中的所述晶片及所述晶片的第一切割道；以及沿所述第一切割道使所述晶片及所述第一虛設結構單體化，以形成堆疊積體電路（IC）結構。
本揭露的一些實施例提出一種封裝結構的製造方法包括：通過混合結合將第一晶片及第二晶片結合到晶片的第一晶片區中的所述晶片；將第一虛設結構結合到所述第一晶片區中的所述晶片及所述晶片的第一切割道；以及沿所述第一切割道使所述晶片及所述第一虛設結構單體化，以形成堆疊積體電路（IC）結構。
本揭露的一些實施例提出一種封裝結構包括：底部晶片；第一晶片，結合到所述底部晶片的第一側；第二晶片，結合到所述底部晶片的所述第一側；包封體，側向包封所述第一晶片及所述第二晶片；以及第一虛設晶片，結合到所述底部晶片的所述第一側，其中所述第一虛設晶片的側壁與所述底部晶片的第一側壁共面。
以下揭露內容提供用於實施所提供主題的不同特徵的許多不同的實施例或實例。以下闡述元件及排列的具體實例以簡化本揭露。當然，這些僅為實例而非旨在進行限制。舉例來說，在以下說明中，在第一特徵上方或第一特徵上形成第二特徵可包括其中第二特徵與第一特徵被形成為直接接觸的實施例，且也可包括其中第二特徵與第一特徵之間可形成附加特徵從而使得第二特徵與第一特徵可不直接接觸的實施例。另外，本揭露可在各種實例中重複參考編號和/或字母。此種重複使用是為了簡明及清晰起見，且自身並不指示所討論的各種實施例和/或配置之間的關係。
此外，為易於說明，本文中可能使用例如“在…之下（beneath）”、“在…下方（below）”、“下部的（lower）”、“在…上（on）”、“在…上方（above）”、“上部的（upper）”等空間相對性用語來闡述圖中所示一個元件或特徵與另一（其他）元件或特徵的關係。除了圖中所繪示的取向以外，所述空間相對性用語還旨在囊括裝置在使用或操作中的不同取向。設備可以其他方式取向（旋轉90度或處於其他取向），且本文所用的空間相對性描述語可同樣相應地作出解釋。
本揭露也可包括其他特徵及製程。舉例來說，可包括測試結構以説明對3D封裝或3DIC裝置進行驗證測試。所述測試結構可例如包括在重佈線層中或在基底上形成的測試墊（test pad），以便能夠對3D封裝或3DIC進行測試、對探針和/或探針卡（probe card）進行使用等。可對中間結構以及最終結構執行驗證測試。另外，可將本文中所揭露的結構及方法與包括對已知良好晶片進行中間驗證的測試方法結合使用，以提高良率並降低成本。
圖1A到圖1H是示出根據本揭露一些實施例的一種形成3DIC結構的方法的示意性剖視圖。圖8所示的製程流程也示意性地反映了圖1A到圖1H所示的步驟。
進一步參照圖1A，提供具有多個積體電路（IC）晶片104的晶片100。根據本揭露的一些實施例，IC晶片104可以是邏輯晶片（例如，中央處理器、圖形處理單元、系統晶片、微控制器等）、記憶體晶片（例如，動態隨機存取記憶體（dynamic random access memory，DRAM）晶片、靜態隨機存取記憶體（static random access memory，SRAM）晶片等）、功率管理晶片（例如，功率管理積體電路（power management integrated circuit，PMIC）晶片）、射頻（radio frequency，RF）晶片、感測器晶片、微機電系統（micro-electro-mechanical-system，MEMS）晶片、訊號處理晶片（例如，數位訊號處理（digital signal processing，DSP）晶片）、前端晶片（例如，模擬前端（analog front-end，AFE）晶片）等或其組合。此外，在一些實施例中，IC晶片104可以是不同的大小（例如，不同的高度和/或表面積），並且在其他實施例中，IC晶片104可以是相同的大小（例如，相同的高度和/或表面積）。
晶片100包括基底105及位於基底105上方的結合結構120。在一些實施例中，基底105可由矽形成，但其也可由其他III族、IV族和/或V族元素或化合物（例如，矽、鍺、鎵、砷及其組合）形成。基底105也可以是絕緣體上矽（silicon-on-insulator，SOI）的形式。SOI基底可包括形成在絕緣體層（例如，掩埋氧化物和/或類似物）上方的半導體材料（例如，矽、鍺和/或類似物）層，所述絕緣體層形成在半導體（例如，矽）基底上。此外，可使用的其他基底包括多層式基底、梯度基底、混合取向基底、其任意組合和/或類似物。
在一些實施例中，基底105可包括從基底105的前側表面向基底105的後側表面延伸的穿孔（through via，TV）109。在一些實施例中，TV 109可通過在基底105中形成開口並用合適的導電材料填充開口形成。在一些實施例中，開口可使用合適的微影及蝕刻方法來形成。可利用物理氣相沉積（PVD）、原子層沉積（ALD）、電化學鍍覆、無電鍍覆或其組合等用銅、銅合金、銀、金、鎢、鉭、鋁、其組合等來填充開口。在一些實施例中，在用合適的導電材料填充開口之前可在開口中形成襯墊層和/或粘合劑層。在一些其他實施例中，基底105可不包括穿孔（TV）109，並且可在後續製程中形成介電穿孔（through dielectric via，TDV）。TDV形成在結合結構120上的頂部晶片周圍的介電層中，以連接到結合結構120的結合墊123。
晶片100還可包括一個或多個積體電路裝置、互連結構114、接觸墊115及位於基底105與結合結構120之間的介電層117。積體電路裝置可以是主動和/或被動裝置。一個或多個主動和/或被動裝置可形成在基底105上和/或基底105中。在一些實施例中，一個或多個主動和/或被動裝置可包括各種n型金屬氧化物半導體（NMOS）和/或p型金屬氧化物半導體（PMOS）裝置，例如電晶體、電容器、電阻器、二極體、光電二極體、熔絲和/或類似物。互連結構114形成在基底105及一個或多個主動和/或被動裝置上方。互連結構114可在基底105上形成的一個或多個積體電路裝置之間提供電連接。互連結構114可包括多個介電層（例如，層間介電（inter-layer dielectric，ILD）層/金屬間介電層（inter-metal dielectric，IMD）層）及介電層111內的互連件113（例如，導線及通孔）。介電層111可由例如低介電常數介電材料（例如，磷矽酸鹽玻璃（PSG）、硼磷矽酸鹽玻璃（BPSG）、氟矽酸鹽玻璃（fluorosilicate glass，FSG）、SiOx Cy 、旋塗玻璃、旋塗聚合物、矽碳材料、其化合物、其複合物、其組合等）形成。在一些實施例中，互連件113可包含銅、銅合金、銀、金、鎢、鉭、鋁、其組合等。
接觸墊115形成在互連結構114上方。接觸墊115可通過互連件113電耦合到一個或多個主動和/或被動裝置。在一些實施例中，接觸墊115可包含導電材料，例如鋁、銅、鎢、銀、金、其組合等。
介電層117形成在互連結構114及接觸墊115上方。在一些實施例中，介電層117可包含一層或多層不可光圖案化的絕緣材料，例如氮化矽、氧化矽、磷矽酸鹽玻璃（PSG）、硼矽酸鹽玻璃（BSG）、摻雜有硼的磷矽酸鹽玻璃（BPSG）、其組合等。在其他實施例中，介電層可包含一層或多層可光圖案化的絕緣材料，例如聚苯並啞唑（PBO）、聚醯亞胺（polyimide，PI）、苯並環丁烯（BCB）、其組合等。在一些實施例中，使用化學機械研磨（CMP）製程、研磨製程、蝕刻製程、其組合等來平坦化介電層。
參照圖1A，在介電層117上形成結合結構120。結合結構120包括形成在介電層117上的絕緣層119及形成在絕緣層119中的結合墊123。在一些實施例中，結合結構120還包括形成在絕緣層119中的虛設墊125。結合墊123與形成在介電層117中的通孔121直接電接觸，以電連接到互連件113。
在一些實施例中，絕緣層119可包括一層或多層不可光圖案化的絕緣材料，例如氮化矽、氧化矽、磷矽酸鹽玻璃（PSG）、硼矽酸鹽玻璃（BSG）、摻雜有硼的磷矽酸鹽玻璃（BPSG）、其組合等，並且可使用化學氣相沉積（CVD）、PVD、ALD、旋塗製程、其組合等形成。在一些實施例中，使用CMP製程、研磨製程、蝕刻製程、其組合等來平坦化絕緣層119。在一些實施例中，絕緣層119與下伏介電層可包含相同的材料。在其他實施例中，絕緣層119與下伏介電層可包含不同的材料。
在一些實施例中，結合墊123、虛設墊125及通孔121可包含例如鋁、銅、鎢、銀、金、其組合等導電材料。在一些實施例中，可使用例如PVD、ALD、電化學鍍覆、無電鍍覆、其組合等在互連結構上方形成導電材料。隨後，使用合適的微影及蝕刻方法圖案化導電材料以形成接觸墊。結合墊123、虛設墊125及通孔121可使用例如鑲嵌製程、雙鑲嵌製程、其組合等形成在絕緣層119中。在一些實施例中，結合墊123、虛設墊125及絕緣層119被平坦化，使得結合墊123及虛設墊125的最頂部表面實質上與絕緣層119的最頂部表面齊平或共面。
參照圖1B，將裝置晶片204及裝置晶片304結合到晶片100的第一側，以開始形成晶圓級晶片結構1000。所述相應的製程在圖8所示的製程流程中被示出為步驟S10。裝置晶片204可以是邏輯晶片（例如，中央處理器、圖形處理單元、系統晶片、微控制器等）、記憶體晶片（例如，動態隨機存取記憶體（DRAM）晶片、靜態隨機存取記憶體（SRAM）晶片等）、功率管理晶片（例如，功率管理積體電路（PMIC）晶片）、射頻（RF）晶片、感測器晶片、微機電系統（MEMS）晶片、訊號處理晶片（例如，數位訊號處理（DSP）晶片）、前端晶片（例如，模擬前端（AFE）晶片）等或其組合。此外，在一些實施例中，裝置晶片204可以是不同的大小（例如，不同的高度和/或表面積），並且在其他實施例中，裝置晶片可以是相同的大小（例如，相同的高度和/或表面積）。
裝置晶片304包括一個或多個記憶體晶片，例如記憶體晶片（例如，DRAM晶片、SRAM晶片、高頻寬記憶體（High-Bandwidth Memory，HBM）晶片、混合記憶體立方體（Hybrid Memory Cube，HMC）晶片等）的堆疊。在記憶體晶片堆疊實施例中，裝置晶片304可包括記憶體晶片及記憶體控制器兩者，例如四個或八個記憶體晶片與記憶體控制器的堆疊。此外，在一些實施例中，裝置晶片304可以是不同的大小（例如，不同的高度和/或表面積），並且在其他實施例中，裝置晶片304可以是相同的大小（例如，相同的高度和/或表面積）。
裝置晶片204可包括基底205、一個或多個主動和/或被動裝置（圖中未示出）、互連結構214、接觸墊215、介電層217、通孔221及結合結構220。結合結構220包括結合墊223、虛設墊225及絕緣層219。裝置晶片304可包括基底305、一個或多個主動和/或被動裝置（圖中未示出）、互連結構314、接觸墊315、介電層317、通孔321及結合結構320。結合結構320包括結合墊323、虛設墊325及絕緣層319。
在一些實施例中，裝置晶片204及304的基底205及305、互連結構214及314、接觸墊215及315、介電層217及317、通孔221及321、以及結合結構220及320的材料及形成方法可類似於晶片100的基底105、互連結構114、接觸墊115、介電層117、通孔121及結合結構120，且因此在此不再予以贅述。
裝置晶片204及304與晶片100可通過混合結合來結合。舉例來說，將結合墊223及323結合到IC晶片（或稱為底部晶片）104的結合墊123，並且通過金屬到金屬的直接結合將虛設墊225及325結合到IC晶片104的虛設墊125。根據本揭露的一些實施例，金屬到金屬的直接結合是銅到銅的直接結合。結合墊223及323的大小可大於、等於或小於相應結合墊123的大小。虛設墊225及325的大小可大於、等於或小於相應虛設結合墊125的大小。此外，通過介電質到介電質的結合（其可為例如產生Si-O-Si結合的熔融結合）將絕緣層219及319結合到絕緣層119。為實現混合結合，首先通過將裝置晶片204及304輕壓抵靠IC晶片104而將裝置晶片204及304預結合到絕緣層119、結合墊223及虛設墊225。然後執行退火以引起結合墊223及323以及虛設墊225及325中的金屬與對應的上覆結合墊123及虛設墊125的金屬的相互擴散。
參照圖1B，將虛設結構404結合到晶片100的絕緣層119，使得每個裝置晶片204及每個裝置晶片304被夾在相鄰的虛設結構404之間。所述相應製程在圖8所示的製程流程中被示出為步驟S20。使用圖1B中的虛設晶片404的數量進行例示。每個IC晶片104可具有一個或多個虛設結構404。此外，相鄰的IC晶片104可共用虛設結構404。虛設結構404可由塊狀材料405製成。在一些實施例中，虛設結構404可包含與IC晶片104的基底105相同的材料。在一些實施例中，虛設結構404可不包括主動和/或被動裝置，並且可不對所得的IC封裝提供額外的電功能。在一些實施例中，每個虛設結構404可包括位於塊狀材料405的一側上的絕緣層419。在一些實施例中，絕緣層419可使用與絕緣層119類似的材料及方法形成，並且在此不再予以贅述。在一些實施例中，絕緣層419與絕緣層119可包含相同的材料。在其他實施例中，絕緣層419與絕緣層119可包含不同的材料。
在一些實施例中，通過將絕緣層419結合到絕緣層119，虛設結構404的前側表面404a結合到IC晶片104的前側表面104a。在一些實施例中，可使用直接結合方法（例如，熔融結合方法）將絕緣層419結合到絕緣層119。在一些實施例中，在將絕緣層419結合到絕緣層119之前，可對絕緣層419及絕緣層119執行表面處理製程。在其他實施例中，可使用其他合適的結合方法或使用粘合劑將絕緣層419結合到絕緣層119。在一些實施例中，可在將虛設結構404結合到晶片100之後執行退火製程以加強結合。
圖2A示出根據一些實施例的圖1B所示晶圓級晶片結構1000的俯視圖。在一些實施例中，晶片100被切割道9及11分成晶片區113i （其中i=1、…、N，其中N是晶片區的總數）。在一些實施例中，切割道9垂直於切割道11。在此類實施例中，晶片區113i （其中i=1、…、N）在俯視圖中具有平行四邊形形狀。在一些實施例中，晶片區113i （其中i=1、…、N）在俯視圖中具有矩形形狀。在其他實施例中，切割道9及切割道11形成不同於90度的角度。
參照圖2A，將虛設結構404放置在晶片區113i 中並與相應切割道11的一部分交疊，使得虛設結構404在被相應切割道11分開的晶片區113i （其中i=1、…、N）的子集之間共用。在一些實施例中，虛設結構404被放置在由裝置晶片204及304以及切割道9及11包圍的區域中，並且延伸到鄰近的裝置晶片204。每個切割道11被多個分隔開的虛設結構404交疊。舉例來說，虛設結構404在俯視圖中具有矩形形狀。
圖3A示出根據替代實施例的圖1B所示晶圓級晶片結構1000的俯視圖。在圖3A所示的實施例中，虛設結構404包括彼此分開的虛設結構4041 與虛設結構4042 。在一些實施例中，在俯視圖中，虛設結構4041 具有矩形形狀，並且虛設結構4042 具有環形形狀。
虛設結構4042 放置在每個晶片區113i 中的裝置晶片204及304以及虛設結構4041 周圍。虛設結構4042 放置在晶片區113i 中，並且不覆蓋切割道9及11。虛設結構4042 被設置在相應的切割道9及11的兩側上彼此相鄰。虛設結構4041 放置在由裝置晶片204及304以及虛設結構4042 包圍的區域中。
圖4A示出根據替代實施例的圖1B所示晶圓級晶片結構1000的俯視圖。在圖4A所示的實施例中，虛設結構404包括彼此分開的虛設結構4041 、4042 、4043 及4044 。在一些實施例中，在俯視圖中，虛設結構4041 、4043 及4044 具有不同大小的矩形形狀，並且虛設結構4042 具有環形形狀。虛設結構4041 類似於圖2A所示實施例的虛設結構4041 ，且在此不再予以贅述。
在一些晶片區113i （例如，晶片區1131 、1133 、1137 及1139 ）中，虛設結構4042 放置在裝置晶片204及304以及虛設結構4041 周圍。晶片區1131 與1137 在第一方向D1上被晶片區1134 分開，並且晶片區1131 與1133 在第二方向D2上被晶片區1132 分開。
虛設結構4042 放置在晶片區113i 中並與對應切割道9及11的一部分交疊，使得虛設結構4042 在被相應切割道9及11分開的晶片區113i （其中i=1、…、N）的子集之間共用。舉例來說，虛設結構4042 由晶片區1131 與1134 （由對應的切割道11分開）共用，並且也由晶片區1131 與1132 （由對應的切割道9分開）共用。
在一些實施例中，虛設結構4043 設置於在第一方向D1上相鄰的兩個虛設結構4042 之間。虛設結構4043 可形成沿第一方向D1延伸並在第二方向D2上排列的斷開的虛設結構。虛設結構4043 放置在一些晶片區113i 中，並與對應的切割道9的一部分交疊，使得虛設結構4043 在被相應切割道9分開的晶片區113i （其中i=1、…、N）的子集之間共用。
在一些實施例中，虛設結構4044 設置在在第二方向D2上相鄰的兩個虛設結構4042 之間。虛設結構4044 可形成沿第二方向D2延伸並在第一方向D1上排列的斷開的虛設結構。虛設結構4044 形成在一些晶片區113i 中，並與對應的切割道11的一部分交疊，使得虛設結構4044 在被相應切割道11分開的晶片區113i （其中i=1、…、N）的子集之間共用。
換句話說，每個切割道9被多個虛設結構4042 及多個虛設結構4043 交疊，並且每個切割道11被多個虛設結構4042 及多個虛設結構4044 交疊。
圖5A示出根據替代實施例的圖1B所示晶圓級晶片結構1000的俯視圖。在圖5A所示的實施例中，虛設結構404包括彼此分開的虛設結構4041 、虛設結構4042 及虛設結構4043 。裝置晶片204及304以及虛設結構4041 被虛設結構4042 及4043 包圍。在一些實施例中，虛設結構4041 、4042 及4043 在俯視圖中具有矩形形狀。虛設結構4041 類似於圖3A所示實施例的虛設結構4041 ，且在此不再予以贅述。
虛設結構4042 可形成沿第二方向D2延伸並在第一方向D1上排列的斷開的虛設結構。虛設結構4042 形成在晶片區113i 中，以覆蓋在IC晶片104的轉角上方，並暴露出相應的切割道9及11。虛設結構4043 可形成沿第一方向D1延伸並在第二方向D2上排列的斷開的虛設結構。虛設結構4043 形成在晶片區113i 中，並暴露出相應的切割道9及11。在第一方向上的兩個相鄰虛設結構4042 插入在兩個相鄰的虛設結構4043 之間。在第二方向D2上的虛設結構4042 彼此相鄰，並且在其之間沒有插入虛設結構4043 。
圖6A示出根據替代實施例的圖1B所示晶圓級晶片結構1000的俯視圖。圖1B是沿圖6A的線I-I’截取的剖視圖。在圖6A所示的實施例中，虛設結構404包括彼此分開的虛設結構4041 、虛設結構4042 及虛設結構4043 。在一些實施例中，虛設結構4041 、4042 及4043 在俯視圖中具有不同大小的矩形形狀。虛設結構4041 類似於圖3A所示實施例的虛設結構4041 ，且在此不再予以贅述。
虛設結構4042 形成在晶片區113i 中且與整個相應切割道11交疊，並且在被相應切割道11分開的晶片區113i （其中i=1、…、N）的子集之間共用。在一些實施例中，虛設結構4042 可形成沿第二方向D2延伸的連續結構，使得每個切割道11被相應的單個連續虛設結構4042 交疊。在一些實施例中，通過形成與切割道11交疊的虛設結構4042 ，可減少形成個別IC封裝的時間。舉例來說，用於形成個別IC封裝的時間可減少在執行單體化製程之前在晶片100的每個晶片區內放置及結合個別（晶圓級或晶片級）虛設結構所需的時間。因此，在IC封裝的生產期間，每小時晶片（wafer per hour，WPH）產量可增加，且生產成本可降低。
虛設結構4043 形成在晶片區113i 中，並與相應切割道9的一部分交疊，使得虛設結構4043 在被相應切割道9分開的晶片區113i （其中i=1、…、N）的子集之間共用。在一些實施例中，虛設結構4043 可形成沿第一方向D1延伸的斷開的虛設結構，使得每個切割道9被多個虛設結構4043 交疊。
放置在切割道9和/或切割道11中或鄰近切割道9和/或切割道11的虛設結構404可有助於防止在封裝的單體化（參見圖1H）期間及之後的翹曲。虛設結構404可有助於減少翹曲的一種方式是在實際單體化製程期間為封裝提供支撐。虛設結構404可防止翹曲的另一種方式是減小IC晶片104與隨後形成的包封體127（如果存在的話）之間的熱膨脹係數（coefficient of thermal expansion，CTE）失配（參見圖1C），因為虛設結構404具有與IC晶片104相似的CTE，並且其減少了封裝中必需的包封體127的量。
參照圖1B，執行薄化製程以薄化裝置晶片204及304以及虛設結構404。在一些實施例中，可使用CMP製程、研磨製程、蝕刻製程、其組合等來薄化裝置晶片204及304以及虛設結構404。在薄化製程之後，虛設結構404具有例如在100微米到150微米範圍內的厚度T1。厚度T1是指虛設結構404的前側表面404a與虛設結構404的後側表面404b之間的距離。為簡潔起見，未在圖1C到圖1H中示出基底105與絕緣層119之間、基底205與絕緣層219之間、以及基底305與絕緣層319之間的層、墊及元件。
參照圖1C，在裝置晶片204及304以及虛設結構404上方並圍繞裝置晶片204及304以及虛設結構404形成包封體127。在一些實施例中，包封體127可包含一層或多層不可光圖案化的絕緣材料，例如氮化矽、氧化矽、磷矽酸鹽玻璃（PSG）、硼矽酸鹽玻璃（BSG）、摻雜有硼的磷矽酸鹽玻璃（BPSG）、其組合等，並且可使用CVD、PVD、ALD、旋塗製程、其組合等形成。在其他實施例中，包封體127可包含一層或多層可光圖案化的絕緣材料，例如聚苯並啞唑（PBO）、聚醯亞胺（PI）、苯並環丁烯（BCB）、其組合等，並且可使用旋塗製程等形成。此種可光圖案化的絕緣材料可使用與光阻材料類似的微影方法來圖案化。在其他實施例中，包封體127可包含模製化合物，例如環氧樹脂、樹脂、可模製聚合物、其組合等。模製化合物可在實質上為液體的情況下施加，且然後可例如在環氧樹脂或樹脂中通過化學反應固化。在其他實施例中，模製化合物可以是紫外線（ultraviolet，UV）或熱固化聚合物，所述聚合物作為能夠設置在裝置晶片204及304以及虛設結構404周圍及之間的凝膠或延展性固體來施加。
參照圖1C，將包封體127及裝置晶片204及304以及虛設結構404平坦化，使得裝置晶片204及304以及虛設結構404的後側表面實質上與包封體127的最頂部表面齊平或共面。在一些實施例中，平坦化製程可包括CMP製程、研磨製程、蝕刻製程、其組合等。在平坦化製程之後，虛設結構404具有例如40微米到150微米範圍內的厚度T2。厚度T2指的是虛設結構404的前側表面404a與虛設結構404的後側表面404c之間的距離。
參照圖1D，將圖1C的結構翻轉並通過釋放層（圖中未示出）貼合到載體129。載體129可包含合適的絕緣材料，例如玻璃。對基底105的後側執行薄化製程以薄化基底105，直到TV 109被暴露出。薄化製程可包括蝕刻製程、研磨製程等、或其組合。在一些實施例中，薄化製程暴露出IC晶片104的TV 109，使得TV 109的被暴露出的表面實質上與基底105的後側表面105b齊平或共面。在一些實施例中，在薄化製程之後，IC晶片104的厚度T3在20微米到30微米的範圍內。厚度T3指的是IC晶片104的前側表面104a到IC晶片104的後側表面104b之間的距離。
參照圖1E，在IC晶片104的後側表面104b上方形成重佈線結構131，並且使用所述重佈線結構131將IC晶片104的積體電路裝置（如果存在的話）和/或TV 109電連接在一起和/或電連接到外部裝置。重佈線結構131可包括一個或多個介電層133及位於一個或多個介電層133中的相應金屬化圖案135。金屬化圖案135有時被稱為重佈線走線（RDL）。介電層133可包含氧化矽、氮化矽、碳化矽、氮氧化矽、低介電常數介電材料，例如PSG、BPSG、FSG、SiOx Cy 、旋塗玻璃、旋塗聚合物、矽碳材料、其化合物、其複合物、其組合等。可通過所屬領域中已知的任何合適的方法（例如，旋塗、CVD、電漿增強化學氣相沉積（PECVD）、高密度電漿化學氣相沉積（HDP-CVD）等）來沉積介電層133。金屬化圖案135包括導線及導通孔。可例如通過使用微影技術在介電層133上沉積及圖案化光阻材料以暴露出將成為金屬化圖案135的介電層133的一些部分而在介電層133中形成金屬化圖案135。可使用例如各向異性幹蝕刻製程等蝕刻製程在介電層133中生成對應於介電層133的被暴露出的部分的凹陷和/或開口。凹陷和/或開口可襯有擴散阻擋層並填充以導電材料。擴散阻擋層可包括由ALD等沉積的一層或多層TaN、Ta、TiN、Ti、CoW等，且導電材料可包括由CVD、PVD等沉積的銅、鋁、鎢、銀及其組合等。可例如通過使用CMP來移除介電層上的任何過量的擴散阻擋層和/或導電材料。
在重佈線結構131上方形成介電層137。介電層137可包括單個層或多個層。介電層137可包含氧化矽、氮化矽、氮氧化矽、USG、TEOS、聚合物或其組合。所述聚合物包含感光性材料，例如聚苯並啞唑（PBO）、聚醯亞胺（PI）、苯並環丁烯（BCB）、其組合等。介電層137的形成方法包括合適的製造技術，例如旋轉塗布、化學氣相沉積（CVD）、電漿增強化學氣相沉積（PECVD）、層疊等。
此後，在介電層137中形成多個開口（圖中未示出），以暴露出重佈線結構131的頂表面的一些部分。開口的形成方法可包括微影及蝕刻製程、雷射鑽孔製程或其組合。
在開口36中及RDL 34上形成多個導電墊（UBM）139。導電墊139可由金屬或金屬合金（例如，鋁、銅、鎳或其合金）形成，並且可通過雙鑲嵌製程、PVD、電鍍或其組合形成。導電墊139貫穿介電層137以與重佈線結構131的頂表面電接觸。在一些實施例中，導電墊139的頂表面實質上與介電層137的頂表面共面，但本揭露不限於此。在一些其他實施例中，導電墊139從介電層137的頂表面突出並延伸跨越所述頂表面。
導電墊139可包括晶種層及導電材料（圖中未示出）。在一些實施例中，晶種層包括使用例如PVD等形成的鈦層及位於所述鈦層上方的銅層。在晶種層上方形成導電材料。導電材料可通過例如電鍍或無電鍍覆等鍍覆形成。導電材料可包括金屬，如銅、鈦、鎢、鋁等。
在導電墊（UBM）139上形成電性連接件141，並且通過重佈線結構131將電性連接件141電耦合到TV 109。電性連接件141可被稱為晶片連接件141。電性連接件141形成在重佈線結構131的頂表面處。在一些實施例中，電性連接件141是焊球和/或凸塊，例如球柵陣列（ball grid array，BGA）球、受控塌陷晶片連接（controlled collapse chip connection，C4）微凸塊、化鎳浸金（electroless nickel/immersion gold，ENIG）形成的凸塊、無電鍍鎳鈀浸金技術（electroless nickel-electroless palladium-immersion gold technique，ENEPIG）形成的凸塊等。電性連接件141可包含導電材料，例如焊料、銅、鋁、金、鎳、銀、鈀、錫等、或其組合。在一些實施例中，電性連接件141通過首先由例如蒸鍍、電鍍、印刷、焊料轉移、植球等此類常用方法形成焊料層來形成。一旦已在結構上形成了焊料層，便可執行回焊，以將材料成形為期望的凸塊形狀。
在另一實施例中，電性連接件141是通過濺鍍、印刷、電鍍、無電鍍覆、CVD等形成的金屬柱（例如，銅柱）。金屬柱可以是無焊料的，並且具有實質上垂直的側壁。在一些實施例中，在電性連接件141的頂部上形成導電頂蓋143。導電頂蓋143可包含鎳、錫、錫-鉛、金、銀、鈀、銦、鎳-鈀-金、鎳-金等或其組合，並且可通過鍍覆製程形成。
在一些實施例中，在導電墊（UBM）139上形成電性連接件141之前，可在介電層137上形成絕緣層138。絕緣層138可包含一層或多層不可光圖案化的絕緣材料，例如氮化矽、氧化矽、磷矽酸鹽玻璃（PSG）、硼矽酸鹽玻璃（BSG）、摻雜有硼的磷矽酸鹽玻璃（BPSG）、其組合等，並且可使用CVD、PVD、ALD、旋塗製程、其組合等形成。在其他實施例中，絕緣層145可包含一層或多層可光圖案化的絕緣材料，例如聚苯並啞唑（PBO）、聚醯亞胺（PI）、苯並環丁烯（BCB）、其組合等，並且可使用旋塗製程等形成。此種可光圖案化的絕緣材料可使用與光阻材料類似的微影方法來圖案化。此後，在絕緣層138中形成多個開口（圖中未示出）以暴露出導電墊（UBM）139的一些部分，且然後在開口中形成電性連接件141。開口的形成方法可包括微影及蝕刻製程、雷射鑽孔製程或其組合。
參照圖1F，然後對晶片1000執行晶片探測製程或其他合適的晶片測試製程，以識別已知良好晶片及不良晶片。在晶片探測製程之後，移除導電頂蓋143。此後，在電性連接件141及重佈線結構131上形成絕緣層145。在一些實施例中，絕緣層145及絕緣層138可包含相同的材料或不同的材料。在一些實施例中，使用CMP製程、研磨製程、蝕刻製程、其組合等來平坦化絕緣層145。
此後，將晶片1000貼合到載體147，且然後執行載體剝離以從晶片1000分離（或“剝離”）載體129。
參照圖1G及圖1H，將晶片1000貼合到框架149，且然後從晶片1000移除載體147。沿切割道9及11將晶片1000單體化（參見圖2A到圖6A），以形成個別3DIC結構1004。所述相應製程在圖8所示的製程流程中被示出為步驟S30。在一些實施例中，可例如通過鋸切、雷射燒蝕、蝕刻、其組合等將晶片1000單體化成個別3DIC結構（或稱為堆疊結構）1004。
參照圖1H，此種單體化製程還將虛設結構404單體化，並形成用於相應3DIC結構1004的個別（晶圓級或晶片級）虛設結構404’。每個3DIC結構1004包括IC晶片104、裝置晶片204及304、以及位於裝置晶片204和/或裝置晶片304旁邊的虛設結構404’。3DIC結構1004還包括包封裝置晶片204及304的包封體127。虛設結構404’的側壁SW4與IC晶片104的側壁SW1對齊。虛設結構404’的側壁SW4實質上與IC晶片104的側壁SW1齊平或共面。
如上所述，虛設結構404可減小IC晶片104與包封體127之間的熱膨脹係數（CTE）失配，因為虛設結構404具有與IC晶片104相似的CTE，並且其減少了封裝中必需的包封體127的體積。因此，虛設結構404’有助於減少由IC晶片104上的厚包封體引起的應力及翹曲，並減輕IC晶片104側壁裂紋問題。在一些實施例中，裝置晶片204及304以及虛設結構404’的面積之和對IC晶片104的面積的比率大於75%，包封體127的面積對IC晶片104的面積的比率小於25%。舉例來說，裝置晶片204及304以及虛設結構404’的面積之和對IC晶片104的面積的比率在75%到99%的範圍內，且包封體127的面積對IC晶片104的面積的比率在1%到25%的範圍內。
圖2B示出根據一些實施例的從圖2A所示晶圓級晶片結構1000單體化的個別3DIC結構1004的俯視圖。此種單體化製程還將虛設結構404單體化，並形成用於相應3DIC結構1004的個別（晶圓級或晶片級）虛設結構404’。每個3DIC結構1004包括IC晶片104、裝置晶片204及304、以及位於IC晶片104上的兩個虛設結構404’。
每個虛設結構404’具有沿第一方向D1的長度W4及沿第二方向D2的長度H4。第一方向D1垂直於第二方向D2。虛設結構404’的長度H4小於IC晶片104的長度H1。虛設結構404’的長度H4可等於、大於或小於裝置晶片204的長度H2。在一些實施例中，長度H4對長度H3與H2之差（ΔH=|H3-H2|，絕對值）的比率R2（R2=H4/ΔH）大於10%、100%、200%、300%或400%。舉例來說，比率R2介於500%到10%的範圍內。
IC晶片104的長度W1大於裝置晶片304的長度W3。裝置晶片304的長度W3大於裝置晶片204的長度W2。虛設結構404’設置在裝置晶片204的旁邊。虛設結構404’的長度W4小於裝置晶片304的長度W3。虛設結構404’的長度W4可等於、大於或小於裝置晶片204的長度W2。在一些實施例中，長度W4對長度W3與W2之差（ΔW=W3-W2）的比率R1（R1=W4/ΔW）大於10%、50%、70%、100%、200%、300%或400%。舉例來說，比率R1介於500%到10%的範圍內。
晶片204的四個側壁及裝置晶片304的四個側壁被包封體127包圍。虛設結構404’被包封體127部分包圍。在一些實施例中，每個虛設結構404’的三個側壁被包封體127包圍，並且每個虛設結構404’的一個側壁SW4被包封體127暴露出。虛設結構404’的側壁SW4與IC晶片104的側壁SW1及位於裝置晶片304旁邊的包封體127的側壁SWe對齊。虛設結構404’的側壁SW4實質上與IC晶片104的側壁SW1及位於裝置晶片304旁邊的包封體127的側壁SWe齊平或共面。
圖3B示出根據一些實施例的從圖3A所示晶圓級晶片結構1000單體化的個別3DIC結構1004的俯視圖。在沿切割道9及11將晶圓級晶片結構1000單體化之後，虛設結構4041 及4042 保留在個別3DIC結構1004中。每個3DIC結構1004包括IC晶片104、以及位於IC晶片104上的裝置晶片204及304、兩個虛設結構4041 及一個虛設結構4042 。虛設結構4041 與4042 彼此分開。在一些實施例中，在俯視圖中，虛設結構4041 具有矩形形狀，並且虛設結構4042 具有矩形環形形狀。
虛設結構4041 設置在裝置晶片204的旁邊。每個虛設結構4041 具有沿第一方向D1的長度W41及沿第二方向D2的長度H41。第一方向D1垂直於第二方向D2。虛設結構4041 的長度H41小於IC晶片104的長度H1。虛設結構4041 的長度H41可等於、大於或小於裝置晶片204的長度H2。在一些實施例中，長度H41對長度H3與長度H2之差（ΔH=H3-H2）的比率R12（R12=H41/ΔH）大於10%。舉例來說，比率R12介於10%到500%的範圍內。
IC晶片104的長度W1大於裝置晶片304的長度W3。裝置晶片204的長度W3大於裝置晶片204的長度W2。虛設結構4041 的長度W41小於裝置晶片304的長度W3。虛設結構4041 的長度W41可等於、大於或小於裝置晶片204的長度W2。在一些實施例中，長度W41對長度W3與W2之差（ΔW=W3-W2）的比率R11（R11=W4/ΔW）大於10%。舉例來說，比率R11介於10%到500%的範圍內。
虛設結構4042 包圍裝置晶片204及304以及虛設結構4041 。虛設結構4042 包括兩個部分P1及兩個部分P2。每個部分P1具有沿第一方向D1的長度L1，且每個部分P2具有沿第二方向D2的長度L2。第一方向D1垂直於第二方向D2。在一些實施例中，虛設結構4042 的部分P1的長度L1可等於IC晶片104的長度W1，並且虛設結構4042 的部分P2的長度L2可等於IC晶片104的長度H1。
每個部分P1具有寬度H42，且虛設結構4042 的每個部分P2具有寬度W42。在一些實施例中，虛設結構4042 的部分P1的寬度H42大於虛設結構4042 與裝置晶片204之間的包封體127的寬度H7。虛設結構4042 的部分P2的寬度W42大於虛設結構4042 與裝置晶片304之間的包封體127的寬度W7。寬度W42可與寬度H42相同或不同。
包封體127填充在虛設結構4042 內。晶片204的四個側壁、裝置晶片304的四個側壁及虛設結構4041 的四個側壁被包封體127包圍。後續製程中的包封體127及包封體142（參見圖7C）被虛設結構4042 分開。
在一些實施例中，虛設結構4042 的四個側壁SW42分別與IC晶片104的四個側壁SW1對齊。虛設結構4042 的四個側壁SW42分別實質上與IC晶片104的四個側壁SW1齊平或共面。此外，相應3DIC結構1004的IC晶片104的四個轉角C被虛設結構4042 覆蓋。
圖4B示出根據一些實施例的從圖4A所示晶片區1131 、1132 、1134 及1135 中的晶圓級晶片結構1000單體化的個別3DIC結構1004的俯視圖。此種單體化製程還將虛設結構4042 /4043 /4044 單體化，並分別形成個別（晶圓級或晶片級）虛設結構40421 、40422 、40423 、40424 /40431 、40432 /40441 及40442 。虛設結構40421 、40422 、40423 、40424 、40431 、40432 、40441 及40442 設置在不同的區中，且因此晶片區1131 、1132 、1134 及1135 中的3DIC結構1004具有不同的結構。
晶片區1131 中的3DIC結構1004包括IC晶片104、以及位於IC晶片104上的裝置晶片204及304、兩個虛設結構4041 及一個虛設結構40421 。在一些實施例中，在俯視圖中，虛設結構4041 具有矩形形狀，並且虛設結構40421 具有矩形環形形狀。裝置晶片204及304以及虛設結構4041 被包封體127及虛設結構40421 包圍。虛設結構4041 及40421 的配置類似於圖3B所示實施例的虛設結構4041 及4042 的配置，並且在此不再予以贅述。
晶片區1132 中的3DIC結構1004包括裝置晶片204及304、兩個虛設結構4041 、兩個虛設結構40422 及兩個虛設結構40441 。虛設結構4041 、40422 及40441 在俯視圖中具有矩形形狀。裝置晶片204及304以及虛設結構4041 被包封體127及虛設結構40422 及40441 包圍。虛設結構4041 的配置類似於圖3B所示實施例的虛設結構4041 的配置，並且在此不再予以贅述。
虛設結構40422 沿第一方向D1延伸，並且虛設結構40441 沿第二方向D2延伸。虛設結構40422 具有沿第一方向D1的長度W422，並且虛設結構40441 具有沿第二方向D2的長度H441。在一些實施例中，虛設結構40422 沿第一方向D1的長度W422可等於IC晶片104沿第二方向D2的長度W1，並且虛設結構40441 沿第二方向D2的長度H441可小於IC晶片104沿第二方向D2的長度H1。
在第一方向D1上，兩個虛設結構40422 的兩個側壁SW4221與IC晶片104的兩個側壁SW1對齊。在第二方向D2上，兩個虛設結構40441 的兩個側壁SW441與IC晶片104的另外兩個側壁SW1對齊。虛設結構40422 的每個側壁SW4221實質上與IC晶片104的側壁SW1齊平或共面。虛設結構40441 的每個側壁SW441實質上與包封體127的兩個側壁SWe、虛設結構40422 的兩個側壁SW4222齊平或共面，並且實質上與IC晶片104的側壁SW1齊平或共面。晶片區1132 中相應3DIC結構1004的IC晶片104的四個轉角C上面覆蓋有兩個虛設結構40422 。
晶片區1134 中的3DIC結構1004包括裝置晶片204及304、兩個虛設結構4041 、兩個虛設結構40431 及兩個虛設結構40423 。虛設結構4041 、40431 及40423 在俯視圖中具有矩形形狀。裝置晶片204及304以及虛設結構4041 被包封體127及虛設結構40431 及40423 包圍。虛設結構4041 的配置類似於圖3B所示實施例的虛設結構4041 的配置，並且在此不再予以贅述。
虛設結構40431 沿第一方向D1延伸，並且虛設結構40423 沿第二方向D2延伸。虛設結構40431 具有沿第一方向D1的長度W431，並且虛設結構40423 具有沿第二方向D2的長度H423。在一些實施例中，虛設結構40431 的長度W431可小於IC晶片104的長度W1，並且虛設結構40423 的長度H423可等於IC晶片104的長度H1。
在第一方向D1上，兩個虛設結構40431 的兩個側壁SW431與IC晶片104的兩個側壁SW1對齊。在第二方向D2上，兩個虛設結構40423 的兩個側壁SW4231與IC晶片104的另外兩個側壁SW1對齊。虛設結構40431 的每個側壁SW431實質上與包封體127的兩個側壁SWe、虛設結構40423 的兩個側壁SW4232齊平或共面，並實質上與IC晶片104的側壁SW1齊平或共面。虛設結構40423 的每個側壁SW4231實質上與IC晶片104的另一側壁SW1齊平或共面。晶片區1132 中相應3DIC結構1004的IC晶片104的四個轉角C上面覆蓋有兩個虛設結構40423 。
晶片區1135 中的3DIC結構1004包括裝置晶片204及304、兩個虛設結構4041 、兩個虛設結構40432 以及兩個虛設結構40442 及40424 。虛設結構4041 、40432 、40442 及40424 在俯視圖中具有矩形形狀。裝置晶片204及304以及虛設結構4041 被包封體127及虛設結構40432 、40442 及40424 包圍。虛設結構4041 的配置類似於圖3B所示實施例的虛設結構4041 的配置，並且在此不再予以贅述。
虛設結構40432 沿第一方向D1延伸，並且虛設結構40442 沿第二方向D2延伸。虛設結構40432 具有沿第一方向D1的長度W432，並且虛設結構40442 具有沿第二方向D2的長度H442。在一些實施例中，虛設結構40432 的長度W432可小於IC晶片104的長度W1，並且虛設結構40442 的長度H442可小於IC晶片104的長度H1。晶片區1132 中的相應3DIC結構1004的IC晶片104的四個轉角C上面覆蓋有四個虛設結構40424 。
在第一方向D1上，兩個虛設結構40432 的兩個側壁SW432與IC晶片104的兩個側壁SW1對齊。在第二方向D2上，虛設結構40442 的兩個側壁SW4422與IC晶片104的另外兩個側壁SW1對齊。虛設結構40432 的每個側壁SW432實質上與包封體127的兩個側壁SWe、兩個虛設結構40442 的兩個側壁SW4242齊平或共面，並且實質上與IC晶片104的側壁SW1齊平或共面。虛設結構40442 的每個側壁SW4422實質上與包封體127的兩個側壁SWe、虛設結構40424 的兩個側壁SW4241齊平或共面，並且實質上與IC晶片104的另一側壁SW1齊平或共面。
對於晶片區1131 中的3DIC結構1004來說，包封體127被虛設結構404’側向包裹，並且不被虛設結構404’暴露出。對於晶片區1132 、1134 及1135 中的3DIC結構1004來說，大部分包封體127被虛設結構404’包裹，且包封體127的一小部分被虛設結構404’暴露出。換句話說，包封體127的被暴露出的側壁SWe的面積小於虛設結構404’的被暴露出的側壁的面積。
圖5B示出根據一些實施例的從圖5A所示晶圓級晶片結構1000單體化的個別3DIC結構1004的俯視圖。在沿切割道9及11將晶圓級晶片結構1000單體化之後，虛設結構4041 、4042 及4043 保留在個別3DIC結構1004中。每個3DIC結構1004包括裝置晶片204及304、兩個虛設結構4041 、兩個虛設結構4042 及兩個虛設結構4043 。虛設結構4041 、4042 及4043 在俯視圖中具有矩形形狀。裝置晶片204及304以及虛設結構4041 被包封體127及虛設結構4042 及4043 包圍。虛設結構4041 、4042 及4043 的配置類似於圖4B所示實施例的虛設結構4041 、40431 及40423 的配置，並且在此不再予以贅述。
圖6B示出根據一些實施例的從圖6A所示晶圓級晶片結構1000單體化的個別3DIC結構1004的俯視圖。在沿切割道9及11將晶圓級晶片結構1000單體化之後，虛設結構4041 被保留。此種單體化製程還將虛設結構4042 及4043 單體化。虛設結構4042 形成個別虛設結構40421 及40422 ，且虛設結構4043 形成個別虛設結構40431 及40432 。虛設結構40421 與40422 可具有相同的大小或不同的大小。虛設結構40431 與40432 可具有相同的大小或不同的大小。虛設結構4041 、40421 、40422 、40431 及40432 的配置類似於圖4B所示實施例的虛設結構4041 、40431 及40423 的配置，並且在此不再予以贅述。
在一些實施例中，虛設結構404’中的一者可沿第一方向D1或/和第二方向D2與其他虛設結構404’合併在同一晶片區113i 中。舉例來說，如圖3C、圖4C、圖4D、圖4E、圖4F、圖5C及圖6C所示，圖3B到圖6B所示的虛設結構4041 可沿第一方向D1或第二方向D2與其他虛設結構404’合併在同一晶片區113i 中，並且在所述虛設結構之間沒有介面。
放置在IC晶片104的轉角和/或邊緣上方的虛設結構404’可有助於防止在封裝單體化期間及之後的翹曲。此外，虛設結構404’可藉由減小IC晶片104與包封體127之間的熱膨脹係數（CTE）失配而防止翹曲，因為虛設結構404’具有與IC晶片104相似的CTE，並且其減少了封裝中所需的包封體127的量。
圖7A到圖7E示出根據一些實施例的形成封裝的剖視圖。
參照圖7A，提供載體基底102，並且在載體基底102上形成釋放層124。載體基底102可以是玻璃載體基底、陶瓷載體基底等。載體基底102可以是晶片，使得可同時在載體基底102上形成多個封裝。釋放層124可由聚合物系材料形成，其可與載體基底102一起從將在後續步驟中形成的上覆結構移除。在一些實施例中，釋放層124是在被加熱時失去其粘合性質的環氧樹脂系熱釋放材料，例如光-熱轉換（light-to-heat-conversion，LTHC）釋放塗層。在其他實施例中，釋放層124可以是紫外線（ultra-violet，UV）膠，其在暴露于UV光時失去其粘合性質。釋放層124可作為液體分配並固化，可以是層疊在載體基底102上的層疊膜，或者可以是類似物。釋放層124的頂表面可以是齊平的，並且可具有高的平坦度。
在釋放層124上形成介電層108。在一些實施例中，介電層108由例如聚苯並啞唑（PBO）、聚醯亞胺、苯並環丁烯（BCB）等聚合物形成。在其他實施例中，介電層108由以下形成：氮化物，例如氮化矽；氧化物，例如氧化矽；磷矽酸鹽玻璃（PSG）、硼矽酸鹽玻璃（BSG）、摻雜有硼的磷矽酸鹽玻璃（BPSG）等；或類似物。可通過例如旋轉塗布、化學氣相沉積（CVD）、層疊等或其組合等任何可接受的沉積製程來形成介電層108。
參照圖7A，在釋放層124上形成導電柱116。作為形成導電柱116的實例，在釋放層124上方形成晶種層。在一些實施例中，晶種層是金屬層，所述金屬層可以是單個層或包括由不同材料形成的多個子層的複合層。舉例來說，晶種層包括鈦層及位於鈦層上方的銅層。晶種層可使用例如PVD等形成。在晶種層上形成光阻並將光阻圖案化。光阻可通過旋轉塗布等形成，並且可被曝光以進行圖案化。圖案化形成穿過光阻的開口，以暴露出晶種層。導電材料形成在光阻的開口中及晶種層的被暴露出的部分上。導電材料可通過例如電鍍或無電鍍覆等鍍覆形成。導電材料可包括金屬，如銅、鈦、鎢、鋁等。移除光阻以及晶種層的上面沒有形成導電材料的部分。可例如使用氧電漿等通過可接受的灰化或剝除製程來移除光阻。一旦光阻被移除，便例如使用可接受的蝕刻製程（例如，通過濕式蝕刻法或幹式蝕刻法）移除晶種層的被暴露出的部分。晶種層及導電材料的剩餘部分形成導電柱116。
參照圖7B，通過粘合劑128將3DIC結構1004粘合到介電層108。粘合劑128位於3DIC結構1004的後側表面上，並將3DIC結構1004粘合到釋放層124。粘合劑128可以是任何合適的粘合劑、環氧樹脂、晶片貼合膜（die attach film，DAF）等。
參照圖7B，在各種元件上形成包封體142。在形成之後，以包封體142側向包封導電柱116及3DIC結構1004。在一些實施例中，包封體142包括模製化合物、模製底層填充材料、例如環氧樹脂等樹脂、其組合等。在一些其他實施例中，包封體142包含感光性材料，例如聚苯並啞唑（PBO）、聚醯亞胺（PI）、苯並環丁烯（BCB）、其組合等，所述材料可易於通過曝光及顯影製程或雷射鑽孔製程被圖案化。在替代實施例中，包封體142包含氮化物（例如，氮化矽）、氧化物（例如，氧化矽）、磷矽酸鹽玻璃（PSG）、硼矽酸鹽玻璃（BSG）、摻雜有硼的磷矽酸鹽玻璃（BPSG）、其組合等。
在一些實施例中，包封體142包含複合材料，所述複合材料包括基材（例如，聚合物）以及位於基材中的多種填充劑。填充劑可以是單一元素、化合物（例如，氮化物、氧化物）或其組合。舉例來說，填充劑可包括氧化矽、氧化鋁、氮化硼、鋁氧化物、二氧化矽等。填充劑的橫截面形狀可以是圓形、橢圓形或任何其他形狀。在一些實施例中，填充劑是球形顆粒等。填充劑的橫截面形狀可以是圓形、橢圓形或任何其他形狀。在一些實施例中，填充劑包括固體填充劑，但本揭露不限於此。在一些實施例中，一小部分填充劑可以是中空填充劑。
包封體142可通過壓縮模製、轉移模製（transfer molding）、旋轉塗布、層疊、沉積或類似製程來施加，並且可形成在載體基底102上方，使得導電柱116和/或3DIC結構1004被掩埋或覆蓋。然後將包封體142固化。導電柱116穿透包封體142，並且導電柱116有時被稱為穿孔116或集成扇出型穿孔（through integrated fan-out via，TIV）116。
參照圖7C，然後對包封體142執行平坦化製程，以移除包封體142的一部分，使得穿孔116及晶片連接件141的頂表面被暴露出。在其中穿孔116的頂表面與3DIC結構1004的前側表面不共面（如圖7B所示）的一些實施例中，穿孔116的一些部分或/和介電材料140的一些部分也可通過平坦化製程被移除。在一些實施例中，穿孔116、晶片連接件141、介電材料140及包封體142的頂表面在平坦化製程之後實質上共面。平坦化製程可以是例如化學機械研磨（CMP）、研磨製程等。在一些實施例中，舉例來說，如果穿孔116及晶片連接件141已被暴露出，那麼可省略平坦化。
參照圖7D，在穿孔116、包封體142及3DIC結構1004的前側表面上方形成前側重佈線結構144。前側重佈線結構144包括：介電層146、150、154及158；金屬化圖案148、152及156；以及凸塊下金屬（under bump metallurgy，UBM）160。金屬化圖案也可被稱為重佈線層或重佈線走線。前側重佈線結構144被示出作為實例。可在前側重佈線結構144中形成更多或更少的介電層及金屬化圖案。如果將形成更少的介電層及金屬化圖案，那麼可省略以下論述的步驟及製程。如果將形成更多的介電層及金屬化圖案，那麼可重複以下論述的步驟及製程。
作為形成前側重佈線結構144的實例，在包封體142、穿孔116及晶片連接件141上沉積介電層146。在一些實施例中，介電層146由感光性材料（例如，PBO、聚醯亞胺、BCB等）形成，所述材料可使用微影罩幕來圖案化。介電層146可通過旋轉塗布、層疊、CVD等或其組合來形成。然後，將介電層146圖案化。圖案化形成暴露出穿孔116及晶片連接件141的一些部分的開口。圖案化可通過可接受的製程進行，例如當介電層146是感光性材料時通過將介電層146曝光，或者通過使用例如各向異性蝕刻進行蝕刻。如果介電層146是感光性材料，那麼介電層146可在曝光後顯影。
然後形成金屬化圖案148。金屬化圖案148包括位於介電層146的頂表面上並沿所述頂表面延伸的導線CL。金屬化圖案148還包括延伸穿過介電層146以物理及電連接到穿孔116及3DIC結構1004的導通孔V。導通孔V及導線CL的側壁可以是直的或傾斜的。在一些實施例中，導通孔V具有傾斜的側壁，並且朝著3DIC結構1004逐漸變細。為形成金屬化圖案148，在介電層146上方及延伸穿過介電層146的開口中形成晶種層。在一些實施例中，晶種層是金屬層，所述金屬層可以是單個層或包括由不同材料形成的多個子層的複合層。在一些實施例中，晶種層包括鈦層及位於鈦層上方的銅層。晶種層可使用例如PVD等形成。然後在晶種層上形成光阻並將光阻圖案化。光阻可通過旋轉塗布等形成，並且可被曝光以進行圖案化。光阻的圖案對應於金屬化圖案148。圖案化形成穿過光阻的開口，以暴露出晶種層。然後在光阻的開口中及晶種層的被暴露出的部分上形成導電材料。導電材料可通過例如電鍍或無電鍍覆等鍍覆形成。導電材料可包括金屬，如銅、鈦、鎢、鋁等。導電材料與晶種層的下伏部分的組合形成金屬化圖案148。移除光阻以及晶種層的上面沒有形成導電材料的部分。可例如使用氧電漿等通過可接受的灰化或剝除製程來移除光阻。一旦光阻被移除，便例如使用可接受的蝕刻製程（例如，通過濕式蝕刻法或幹式蝕刻法）移除晶種層的被暴露出的部分。
交替形成介電層150、154、158及金屬化圖案152、156。介電層150、154及158可以類似於介電層146的方式形成，並且可由與介電層146相同的材料形成。金屬化圖案152及156可包括位於下伏介電層上的導線CL及分別延伸穿過下伏介電層的導通孔V。金屬化圖案152及156可以類似於金屬化圖案148的方式形成，並且可由與金屬化圖案148相同的材料形成。UBM 160視情況形成在介電層158上並延伸穿過介電層158。UBM 160可以類似於金屬化圖案148的方式形成，並且可由與金屬化圖案148相同的材料形成。
參照圖7D，在UBM 160上形成導電性連接件162。導電性連接件162可以是球柵陣列（BGA）連接件、焊球、金屬柱、受控塌陷晶片連接（C4）凸塊、微凸塊、無電鍍鎳鈀浸金技術（ENEPIG）形成的凸塊等。導電性連接件162包括通過濺鍍、印刷、電鍍、無電鍍覆、CVD等形成的金屬柱（例如，銅柱）。金屬柱可以是無焊料的，並且具有實質上垂直的側壁。在一些實施例中，在金屬柱的頂部上形成金屬頂蓋層。金屬頂蓋層可包含鎳、錫、錫-鉛、金、銀、鈀、銦、鎳-鈀-金、鎳-金等或其組合，並且可通過鍍覆製程形成。在另一實施例中，導電性連接件162可包含導電材料，例如焊料、銅、鋁、金、鎳、銀、鈀、錫等、或其組合。在一些實施例中，導電性連接件162通過首先由例如蒸鍍、電鍍、印刷、焊料轉移、植球等此類常用方法形成焊料層來形成。一旦已在結構上形成了焊料層，便可執行回焊製程，以將材料成形為期望的凸塊形狀。
參照圖7D及圖7E，執行載體基底剝離以從介電層108分離（或“剝離”）載體基底102，以形成InFO封裝166。根據一些實施例，剝離包括將例如雷射或UV光等光投射到釋放層124上，使得釋放層124在光的熱量下分解，並且載體基底102可被移除。然後，將InFO封裝166翻轉並放置在膠帶（圖中未示出）上。
參照圖7E，可將頂部封裝500結合到InFO封裝166。頂部封裝500包括基底502及耦合到基底502的一個或多個堆疊晶片（或晶片）508。基底502可由例如矽、鍺、金剛石等半導體材料製成。在一些實施例中，也可使用化合物材料，例如矽鍺、碳化矽、砷化鎵、砷化銦、磷化銦、矽鍺碳化物、磷化鎵砷、磷化鎵銦、其組合等。另外，基底502可以是SOI基底。一般來說，SOI基底包括半導體材料（例如，磊晶矽、鍺、矽鍺、SOI、絕緣體上矽鍺（SGOI）或其組合）層。在一個替代實施例中，基底502基於絕緣芯，例如玻璃纖維增強樹脂芯。芯材的一個實例是玻璃纖維樹脂，例如FR4。芯材的替代物包括雙馬來醯亞胺-三嗪（bismaleimide-triazine，BT）樹脂，或作為另一選擇，包括其他印刷電路板（printed circuit board，PCB）材料或膜。可將例如味之素積層膜（Ajinomoto build-up film，ABF）等積層膜或其他層疊體用於基底502。
基底502可包括主動及被動裝置（圖中未示出）。如所屬領域中的普通技術人員將認識到，可使用例如電晶體、電容器、電阻器、其組合等各種各樣的裝置來產生頂部封裝500的設計的結構及功能要求。可使用任何合適的方法來形成裝置。
基底502還可包括金屬化層（圖中未示出）及穿孔506。金屬化層可形成在主動及被動裝置上方，並且被設計成連接各種裝置以形成功能電路系統。金屬化層可由交替的介電質（例如，低介電常數介電材料）層及導電材料（例如，銅）層（其中通孔互連各導電材料層）形成，並且可通過任何合適的製程（例如，沉積、鑲嵌、雙鑲嵌等）形成。在一些實施例中，基底502實質上不具有主動裝置及被動裝置。
基底502可在基底502的第一側上具有結合墊503以耦合到堆疊晶片508，並且在基底502的第二側上具有結合墊504以耦合到導電性連接件168，其中基底502的第二側與第一側相對。在一些實施例中，通過在基底502的第一側及第二側上的介電層（圖中未示出）中形成凹陷（圖中未示出）來形成結合墊503及504。可形成凹陷以允許結合墊503及504嵌入介電層中。在其他實施例中，由於結合墊503及504可形成在介電層上，因此省略了凹陷。在一些實施例中，結合墊503及504包括由銅、鈦、鎳、金、鈀等或其組合製成的薄晶種層（圖中未示出）。結合墊503及504的導電材料可沉積在薄晶種層上方。所述導電材料可通過電化學鍍覆製程、無電鍍覆製程、CVD、ALD、PVD等或其組合來形成。在實施例中，結合墊503及504的導電材料是銅、鎢、鋁、銀、金等、或其組合。在實施例中，結合墊503及504是使用與較早結合UBM 160描述的相同或相似製程形成的UBM。
在所示實施例中，通過引線結合510將堆疊晶片508耦合到基底502，但也可使用其他連接，例如導電凸塊。在實施例中，堆疊晶片508是堆疊記憶體晶片。舉例來說，堆疊記憶體晶片508可包括低功率（low-power，LP）雙倍數據速率（double data rate，DDR）記憶體模組，例如LPDDR1、LPDDR2、LPDDR3、LPDDR4或類似記憶體模組。
在一些實施例中，可由模製材料512包封堆疊晶片508及引線結合510。模製材料512可例如使用壓縮模製而被模製在堆疊晶片508及引線結合510上。在一些實施例中，模製材料512是模製化合物、聚合物、環氧樹脂、氧化矽填充劑材料等或其組合。可執行固化步驟來固化模製材料512，其中固化可以是熱固化、UV固化等或其組合。
在一些實施例中，將堆疊晶片508及引線結合510埋置在模製材料512中，並且在固化模製材料512之後，執行平坦化步驟（例如，研磨）以移除模製材料512的多餘部分，並且為頂部封裝500提供實質上平面的表面。
在形成頂部封裝500之後，通過導電性連接件168及結合墊504將頂部封裝500結合到InFO封裝166。在一些實施例中，堆疊記憶體晶片508可通過引線結合510、結合墊503及504、穿孔506、導電性連接件168及穿孔116耦合到3DIC結構1004。
導電性連接件168可類似於上述連接件68，並且在此不再予以贅述，但導電性連接件168與68不必相同。在一些實施例中，在結合導電性連接件168之前，用例如免清洗助焊劑（non-clean flux）等助焊劑（圖中未示出）對導電性連接件168進行塗布。可將導電性連接件168浸入助焊劑中，或者可將助焊劑噴射到導電性連接件168上。
在一些實施例中，導電性連接件168在被回焊之前可在其上形成有環氧樹脂助焊劑（圖中未示出），其中在將頂部封裝500貼合到InFO封裝166之後，環氧樹脂助焊劑的至少一些環氧樹脂部分存留。此存留的環氧樹脂部分可充當底部填充材料，以減少應力並保護由回焊導電性連接件168產生的接頭。在一些實施例中，可在頂部封裝500與InFO封裝166之間且圍繞導電性連接件168形成底部填充材料170。底部填充材料170可在貼合頂部封裝500之後通過毛細流動製程（capillary flow process）形成，或者可在貼合頂部封裝500之前通過合適的沉積方法形成。
頂部封裝500與InFO封裝166之間的結合可以是焊料結合或直接金屬對金屬（例如，銅對銅或錫對錫）的結合。在實施例中，通過回焊製程將頂部封裝500結合到InFO封裝166。在此回焊製程期間，導電性連接件168與結合墊504及穿孔116接觸，以將頂部封裝500物理及電耦合到InFO封裝166。
所揭露的封裝結構的實施例包括位於晶片區中或者進一步位於切割道區中的虛設結構。所述虛設結構可允許對包封體的比率進行更多控制，且因此可減少應力及由熱膨脹係數（CTE）失配引起的翹曲。
根據本揭露的一些實施例，一種封裝結構的製造方法包括：通過混合結合將第一晶片及第二晶片結合到晶片的第一晶片區中的所述晶片；將第一虛設結構結合到所述第一晶片區中的所述晶片及所述晶片的第一切割道；以及沿所述第一切割道使所述晶片及所述第一虛設結構單體化，以形成堆疊積體電路（IC）結構。
根據本揭露的一些實施例，所述第一虛設結構從所述晶片的所述第一晶片區延伸到第二晶片區。根據本揭露的一些實施例，所述第一虛設結構與所述晶片的所述第一切割道及第二切割道交疊，並且所述第一切割道與所述第二切割道沿著不同的方向。根據本揭露的一些實施例，封裝結構的製造方法更包括：將第二虛設結構結合到所述第二晶片區中的所述晶片及所述晶片的所述第一切割道；以及將第三虛設結構結合到第三區中的所述晶片及所述晶片的所述第二切割道。根據本揭露的一些實施例，所述第一虛設結構在俯視圖中具有矩形形狀或環形形狀。根據本揭露的一些實施例，所述第一虛設結構是虛設晶片，並且所述虛設晶片包括矽基底及位於所述矽基底上的第一絕緣層。根據本揭露的一些實施例，所述晶片包括具有第二絕緣層的第三晶片，並且所述第一虛設結構通過熔融結合所述第一絕緣層與所述第二絕緣層而結合到所述第三晶片，並且所述混合結合包括金屬到金屬的直接結合及介電質到介電質的結合。
根據本揭露的替代實施例，一種封裝結構的製造方法包括：將第一晶片及第二晶片結合到晶片的晶片區中的所述晶片；將第一虛設結構結合到所述晶片區中的所述晶片，以覆蓋在所述晶片區的多個轉角上方；以及將所述晶片單體化以形成堆疊積體電路（IC）結構。
根據本揭露的一些實施例，所述第一虛設結構是虛設晶片，並且所述虛設晶片包括矽基底及位於所述矽基底上的第一絕緣層。根據本揭露的一些實施例，所述晶片包括具有第二絕緣層的第三晶片，並且所述第一虛設結構通過熔融結合所述第一絕緣層與所述第二絕緣層而結合到所述第三晶片，且所述第一晶片及所述第二晶片通過混合結合而結合到所述第三晶片，並且所述混合結合包括金屬到金屬的直接結合及介電質到介電質的結合。根據本揭露的一些實施例，所述第一虛設結構在俯視圖中具有矩形形狀或環形形狀。根據本揭露的一些實施例，更包括將第二虛設結構結合到所述晶片區中的所述晶片，其中所述第一虛設結構鄰近所述晶片的第一切割道，而所述第二虛設結構鄰近所述晶片的第二切割道，並且所述第一切割道與所述第二切割道是沿著不同的方向。
根據本揭露的一些實施例，一種封裝結構包括：底部晶片；第一晶片，結合到所述底部晶片的第一側；第二晶片，結合到所述底部晶片的所述第一側；包封體，側向包封所述第一晶片及所述第二晶片；以及第一虛設晶片，結合到所述底部晶片的所述第一側，其中所述第一虛設晶片的側壁與所述底部晶片的第一側壁共面。
根據本揭露的一些實施例，所述第一虛設結構在俯視圖中具有矩形形狀或環形形狀。根據本揭露的一些實施例，所述第一虛設結構覆蓋在所述底部晶片的多個轉角上方。根據本揭露的一些實施例，所述包封體位於所述第一虛設結構內並被所述第一虛設結構包圍。根據本揭露的一些實施例，所述封裝結構，更包括：第二虛設結構，結合到所述底部晶片的所述第一側，其中所述第一虛設結構與所述第二虛設結構沿著不同的方向，並且所述第二虛設結構的側壁與所述底部晶片的第二側壁共面。根據本揭露的一些實施例，所述包封體鄰接所述第一虛設結構及所述第二虛設結構。根據本揭露的一些實施例，所述封裝結構，更包括：穿孔，延伸穿過所述底部晶片，所述第一晶片及所述第二晶片電耦合到所述穿孔；重佈線結構，位於所述底部晶片的第二側上，所述第二側與所述第一側相對；以及多個電性連接件，位於所述重佈線結構上，所述多個電性連接件通過所述重佈線結構電耦合到所述穿孔。
9、11:切割道 102:載體基底 104:IC晶片 104a:IC晶片的前側表面 104b:IC晶片的後側表面 105:基底 105b:基底的後側表面 108:介電層 109:穿孔（TV） 111:介電層 113:互連件 1131 、1132 、1133 、1134 、1135 、1136 、1137 、1138 、1139 、113i :晶片區 114:互連結構 115:接觸墊 116:導電柱/穿孔/集成扇出型穿孔（TIV） 117:介電層 119:絕緣層 120:結合結構 121:通孔 123:結合墊 124:釋放層 125:虛設墊/虛設結合墊 127:包封體 128:粘合劑 129:載體 131:重佈線結構 133:介電層 135:金屬化圖案 137:介電層 138:絕緣層 139:導電墊（UBM） 141:電性連接件/晶片連接件 142:包封體 143:導電頂蓋 144:前側重佈線結構 145:絕緣層 146:介電層 147:載體 148:金屬化圖案 149:框架 150:介電層 152:金屬化圖案 154:介電層 156:金屬化圖案 158:介電層 160:凸塊下金屬（UBM） 162:導電性連接件 166:InFO封裝 168:導電性連接件 170:底部填充材料 204:裝置晶片 205:基底 214:互連結構 215:接觸墊 217:介電層 219:絕緣層 220:結合結構 221:通孔 223:結合墊 225:虛設墊 304:裝置晶片 305:基底 314:互連結構 315:接觸墊 317:介電層 319:絕緣層 320:結合結構 321:通孔 323:結合墊 325:虛設墊 404:虛設結構/虛設晶片 404’、4041 、4042 、4043 、4044 、40421 、40422 、40423 、40424 、40431 、40432 、40441 、40442 :虛設結構 404a:虛設結構的前側表面 404b、404c:虛設結構的後側表面 405:塊狀材料 419:絕緣層 500:頂部封裝 502:基底 503、504:結合墊 506:穿孔 508:堆疊晶片/堆疊記憶體晶片 510:引線結合 512:模製材料 1000:晶圓級晶片結構/晶片 1004:3DIC結構 C:轉角 CL:導線 D1:第一方向 D2:第二方向 H1、H2、H3、H4、H41、H423、H441、H442:長度 H7、H42:寬度 I-I’:線 L1:長度 P1、P2:虛設結構的部分 S10、S20、S30:步驟 SW1:IC晶片的側壁 SW4、SW42、SW4221、SW4222、SW4231、SW4232、SW4241、SW4242、SW431、SW432、SW441、SW442:虛設結構的側壁 SWe:包封體的側壁 T1、T2、T3:厚度 V:導通孔 W1:IC晶片的長度 W2:裝置晶片的長度 W3:裝置晶片的長度 W4:虛設結構的長度 W7:包封體的寬度 W41:虛設結構的長度 W42:虛設結構的寬度 W422、W431、W432:虛設結構的長度
結合附圖閱讀以下詳細說明，會最好地理解本發明的各個方面。應注意，根據本行業中的標準慣例，各種特徵並非按比例繪製。事實上，為論述清晰起見，可任意增大或減小各種特徵的尺寸。 圖1A到圖1H是示出根據本揭露一些實施例的一種形成三維積體電路（three-dimensional integrated circuit，3DIC）結構的方法的示意性剖視圖。 圖2A到圖6A示出根據一些實施例的圖1B所示晶圓級晶片結構的俯視圖。 圖2B到圖6B示出根據一些實施例的從圖2A到圖6A所示晶圓級晶片結構單體化的個別3DIC結構的俯視圖。 圖3C、圖4C、圖4D、圖4E、圖4F、圖5C及圖6C示出根據一些其他實施例的個別3DIC結構的俯視圖。 圖7A到圖7E示出根據一些實施例的形成封裝的剖視圖。 圖8示出根據一些實施例的用於形成3DIC結構的製程流程。
S10、S20、S30:步驟

Claims (1)

  1. 一種封裝結構的製造方法，包括： 通過混合結合將第一晶片及第二晶片結合到晶片的第一晶片區中的所述晶片； 將第一虛設結構結合到所述第一晶片區中的所述晶片及所述晶片的第一切割道；以及 沿所述第一切割道使所述晶片及所述第一虛設結構單體化，以形成堆疊積體電路（IC）結構。
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