TW202038396A - 積體電路封裝體及其製造方法 - Google Patents

積體電路封裝體及其製造方法 Download PDF

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TW202038396A
TW202038396A TW108136769A TW108136769A TW202038396A TW 202038396 A TW202038396 A TW 202038396A TW 108136769 A TW108136769 A TW 108136769A TW 108136769 A TW108136769 A TW 108136769A TW 202038396 A TW202038396 A TW 202038396A
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dielectric layer
width
metallization pattern
under
integrated circuit
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TW108136769A
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TWI719670B (zh
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劉重希
李建勳
吳俊毅
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台灣積體電路製造股份有限公司
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Priority claimed from US16/408,620 external-priority patent/US11217538B2/en
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Abstract

在一實施例中，元件包含：積體電路晶粒；密封體，至少部分地密封積體電路晶粒；導通孔，延伸穿過密封體；重佈線結構，位於密封體上，重佈線結構包含：金屬化圖案，電耦合至導通孔及積體電路晶粒；介電層，位於金屬化圖案上，介電層具有介於10微米至30微米的第一厚度；以及第一凸塊下金屬（UBM），具有延伸穿過介電層的第一通孔部分及在介電層上的第一凸塊部分，第一凸塊下金屬實體地耦合及電耦合至金屬化圖案，第一通孔部分具有第一寬度，第一厚度與第一寬度的比率為1.33至1.66。

Description

積體電路封裝體及方法
半導體行業已歸因於多種電子組件（例如，電晶體、二極體、電阻器、電容器等）的積體密度的持續改良而經歷快速發展。一般地，積體密度的改良來自最小特徵大小的逐漸減小，其允許將更多的組件積體至給定區域中。隨著對於縮小的電子元件的需求增長，對於更小且更創造性的半導體晶粒的封裝技術的需要已出現。此類封裝系統的實例為疊層封裝（Package-on-Package；PoP）技術。在PoP元件中，頂部半導體封裝堆疊於底部半導體封裝的頂部上，以提供高水準的積體及組件密度。PoP技術通常使得能夠產生具有增強的功能性及在印刷電路板（printed circuit board；PCB）上有小佔據面積的半導體元件。
以下揭露內容提供用以實施本發明的不同特徵的許多不同實施例或實例。以下描述組件及配置的具體實例以簡化本發明。當然，這些組件及配置僅為實例且不意欲為限制性的。舉例而言，在以下描述中，第一特徵在第二特徵上方或上的形成可包含第一特徵及第二特徵直接接觸地形成的實施例，且亦可包含額外特徵可在第一特徵與第二特徵之間形成使得第一特徵與第二特徵可不直接接觸的實施例。另外，本發明可在各種實例中重複圖式元件符號及/或字母。此重複是出於簡化及清楚之目的，且自身並不規定所論述之各種實施例及/或組態之間的關係。
此外，可在本文中使用空間相對術語，諸如「在...下方」、「在...之下」、「下部」、「在...上方」、「上部」以及類似術語，以描述如在圖式中所說明的一個元件或特徵與另一（一些）元件或特徵的關係。除圖式中所描繪的定向以外，空間相對術語意欲涵蓋元件在使用或操作中的不同定向。設備可以其他方式定向（旋轉90度或處於其他定向），且本文中所使用的空間相對描述詞可同樣相應地進行解釋。
根據一些實施例，凸塊下金屬（under-bump metallurgies；UBM）經形成用於重佈線結構，且外部連接件（external connectors）經形成以實體耦合及電耦合UBM。UBM具有延伸穿過重佈線結構的最頂部介電層的通孔部分，及其上形成有外部連接件的凸塊部分。通孔部分具有小的寬度及大的高度對寬度比率（larger height-to-width ratio）。此外，最頂部介電層具有大的厚度。形成具有大的高度對寬度比率的UBM允許重佈線結構的UBM及最頂部介電層緩衝機械性應力，進而提高重佈線結構在測試或操作期間的可靠性。
圖1說明根據一些實施例的積體電路晶粒50的橫截面圖。積體電路晶粒50將在後續處理中經封裝以形成積體電路封裝體。積體電路晶粒50可為邏輯晶粒（例如，中央處理單元（central processing unit；CPU）、圖形處理單元（graphics processing unit；GPU）、系統晶片（system-on-a-chip；SoC）、應用程式處理器（application processor；AP）、微控制器等）、記憶體晶粒（例如，動態隨機存取記憶體（dynamic random access memory；DRAM）晶粒、靜態隨機存取記憶體（static random access memory；SRAM）晶粒等）、功率管理晶粒（例如，功率管理積體電路（power management integrated circuit；PMIC）晶粒）、射頻（radio frequency；RF）晶粒、感測器晶粒、微機電系統（micro-electro-mechanical-system；MEMS）晶粒、訊號處理晶粒（例如，數位訊號處理（digital signal processing；DSP）晶粒）、前端晶粒（例如，類比前端（analog front-end；AFE）晶粒）、類似者或其組合。
積體電路晶粒50可形成於晶圓中，所述晶圓可包含在後續步驟中經單體化以形成多個積體電路晶粒的不同元件區。積體電路晶粒50可根據適用之製造製程而經處理以形成積體電路。舉例而言，積體電路晶粒50包含諸如摻雜矽或未摻雜矽的半導體基底52，或絕緣層上半導體（semiconductor-on-insulator；SOI）基底的主動層。半導體基底52可包含其他半導體材料，諸如：鍺；化合物半導體，包含碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦及/或銻化銦；合金半導體，包含SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP及/或GaInAsP；或其組合。亦可使用其他基底，諸如多層基底（multi-layer substrate）或梯度基底（gradient substrate）。半導體基底52具有有時稱作前側的主動表面（例如，圖1中面向上的表面）及有時稱作背側的非主動表面（例如，圖1中面向下的表面）。
元件54可形成於半導體基底52的前表面處。元件54可為主動元件（例如，電晶體、二極體等）、電容器、電阻器等。層間介電質（inter-layer dielectric；ILD）56位於半導體基底52的前表面上方。層間介電質56包圍元件54且可覆蓋所述元件54。層間介電質56可包含由諸如以下的材料形成的一或多個介電層：磷矽酸鹽玻璃（Phospho-Silicate Glass；PSG）、硼矽酸鹽玻璃（Boro-Silicate Glass；BSG）、硼摻雜磷矽酸鹽玻璃（Boron-Doped Phospho-Silicate Glass；BPSG）、未摻雜矽酸鹽玻璃（undoped Silicate Glass；USG）或類似物。
導電插塞58延伸穿過層間介電質56以電耦合及實體耦合元件54。舉例而言，當元件54為電晶體時，導電插塞58可耦合電晶體的閘極及源極/汲極區。導電插塞58可由鎢、鈷、鎳、銅、銀、金、鋁、類似者或其組合形成。內連線結構60位於層間介電質56及導電插塞58上方。內連線結構60與元件54互連以形成積體電路。內連線結構60可由例如層間介電質56上之多個介電層中的多個金屬化圖案形成。金屬化圖案包含形成於一或多個介電層中的多個金屬線及多個通孔。內連線結構60的金屬化圖案藉由導電插塞58電耦合至元件54。
積體電路晶粒50更包含多個接墊62，諸如鋁接墊，對所述接墊62進行外部連接。接墊62位於積體電路晶粒50的主動側上，諸如位於內連線結構60中及/或所述內連線結構60上。一或多個鈍化膜64位於積體電路晶粒50上，諸如位於內連線結構60及接墊62的部分上。多個開口穿過鈍化膜64延伸至接墊62。諸如導電柱（例如，由諸如銅的金屬形成）的多個晶粒連接件66延伸穿過鈍化膜64中的開口，且實體耦合及電耦合至接墊62的相應者。晶粒連接件66可由例如鍍覆或類似者形成。晶粒連接件66電耦合積體電路晶粒50的各別積體電路。
視情況，多個焊料區（例如，多個焊球或多個焊料凸塊）可安置於接墊62上。焊球可用於對積體電路晶粒50執行晶片探針（chip probe；CP）測試。可對積體電路晶粒50執行CP測試以確定積體電路晶粒50是否為良裸晶粒（known good die；KGD）。因此，僅經歷後續處理之作為KGD的積體電路晶粒50被封裝，且未通過CP測試的晶粒則不被封裝。在測試後，可在後續處理步驟中移除焊料區。
介電層68可（或可不）位於積體電路晶粒50的主動側上，諸如位於鈍化膜64及晶粒連接件66上。介電層68橫向地密封晶粒連接件66，且介電層68與積體電路晶粒50橫向地相連。首先，介電層68可掩埋晶粒連接件66，使得介電層68的最頂部表面位於晶粒連接件66的最頂部表面上方。在一些實施例中，其中焊料區安置於晶粒連接件66上，介電層68亦可掩埋焊料區。或者，可在形成介電層68之前移除焊料區。
介電層68可為聚合物，諸如聚苯并噁唑（polybenzoxazole；PBO）、聚醯亞胺、苯并環丁烯（benzocyclobutene；BCB）或類似者；氮化物，諸如氮化矽或類似者；氧化物，諸如氧化矽、PSG、BSG、BPSG或類似者；類似者，或其組合。介電層68可例如藉由旋塗、層壓、化學氣相沈積（chemical vapor deposition；CVD）或類似者形成。在一些實施例中，在積體電路晶粒50的形成期間，晶粒連接件66經由介電層68而暴露出來。在一些實施例中，晶粒連接件66保持埋入，且在封裝積體電路晶粒50的後續製程期間中被暴露出來。晶粒連接件66的暴露可移除任何可存在於晶粒連接件66上的焊料區。
在一些實施例中，積體電路晶粒50為包含多個半導體基底52的堆疊元件。舉例而言，積體電路晶粒50可為包含多個記憶體晶粒的記憶體元件，諸如混合記憶體（hybrid memory cube；HMC）模組、高頻寬記憶體（high bandwidth memory；HBM）模組或類似者。在此類實施例中，積體電路晶粒50包含由基底穿孔（through-substrate vias；TSV）互連的多個半導體基底52。半導體基底52中的每一者可（或可不）具有內連線結構60。
圖2至圖20說明根據一些實施例的在用於形成第一封裝組件100之製程期間的中間步驟的橫截面圖。示出第一封裝區100A及第二封裝區100B，且積體電路晶粒50中的一或多者經封裝以在封裝區100A及封裝區100B中的每一者中形成積體電路封裝體。積體電路封裝體亦可稱作整合扇出型（integrated fan-out；InFO）封裝體。
在圖2中，提供載體基底102，且釋放層104形成於載體基底102上。載體基底102可為玻璃載體基底、陶瓷載體基底或類似者。載體基底102可為晶圓，使得多個封裝可同時形成於載體基底102上。釋放層104可由聚合物類材料形成，可將所述聚合物類材料連同載體基底102一起自將在後續步驟中形成的上覆結構移除。在一些實施例中，釋放層104為在加熱時損失其黏著性質之環氧類熱釋放材料，諸如光-熱轉換（light-to-heat-conversion；LTHC）釋放塗層。在其他實施例中，釋放層104可為在暴露於UV光時損失其黏著性質之紫外光（ultra-violet；UV）黏膠。釋放層104可以液體形式施配且經固化，可為層壓至載體基底102上的層壓膜，或可為類似者。可使釋放層104之頂部表面水平化，且所述頂部表面可具有高度平面性。
在圖3中，背側重佈線結構106可形成於釋放層104上。在所展示實施例中，背側重佈線結構106包含介電層108、金屬化圖案110（有時稱為多個重佈線層或多個重佈線）以及介電層112。背側重佈線結構106為視情況選用的。在一些實施例中，不含金屬化圖案的介電層代替背側重佈線結構106形成於釋放層104上。
介電層108可形成於釋放層104上。介電層108的底部表面可與釋放層104的頂部表面接觸。在一些實施例中，介電層108由諸如以下的聚合物形成：聚苯并噁唑（PBO）、聚醯亞胺、苯并環丁烯（BCB）或類似者。在其他實施例中，介電層108由以下形成：氮化物，諸如氮化矽；氧化物，諸如氧化矽、磷矽酸鹽玻璃（PSG）、硼矽酸鹽玻璃（BSG）、硼摻雜磷矽酸鹽玻璃（BPSG）或類似者；或類似者。介電層108可藉由諸如以下的任何可接受的沈積製程形成：旋塗、CVD、層壓、類似者或其組合。
金屬化圖案110形成於介電層108上。作為形成金屬化圖案110的一實例，晶種層形成於介電層108上方。在一些實施例中，晶種層為金屬層，其可為單一層或包括由不同材料形成之多個子層的複合層。在一些實施例中，晶種層包括鈦層及在鈦層上方的銅層。可使用例如物理氣相沈積（physical vapor deposition；PVD）或類似者形成晶種層。隨後在晶種層上形成光阻並使所述光阻圖案化。光阻可藉由旋塗或類似製程而形成，且可暴露於光以用於圖案化。光阻的圖案對應於金屬化圖案110。透過圖案化，形成穿過光阻的多個開口以暴露晶種層。導電材料形成於光阻的開口中及晶種層的經暴露部分上。導電材料可藉由諸如以下的鍍覆形成：電鍍（electro plating）或無電電鍍（electroless plating）或類似者。導電材料可包括金屬，如銅、鈦、鎢、鋁或類似者。隨後，移除光阻以及晶種層上未形成導電材料的部分。可藉由可接受的灰化或剝離製程，諸如使用氧電漿或類似者來移除光阻。一旦移除光阻，則諸如藉由使用可接受的蝕刻製程，諸如藉由濕式蝕刻或乾式蝕刻來移除晶種層的經暴露部分。晶種層及導電材料的其餘部分形成金屬化圖案110。
介電層112可形成於金屬化圖案110及介電層108上。在一些實施例中，介電層112由聚合物形成，所述聚合物可為可使用微影罩幕圖案化的感光性材料，諸如PBO、聚醯亞胺、BCB或類似者。在其他實施例中，介電層112由以下形成：氮化物，諸如氮化矽；氧化物，諸如氧化矽、PSG、BSG、BPSG；或類似者。介電層112可藉由旋塗、層壓、CVD、類似者或其組合形成。介電層112隨後經圖案化以形成多個開口114從而暴露金屬化圖案110的多個部分。圖案化可藉由可接受的製程形成，諸如當介電層112為感光性材料時藉由將介電層112暴露於光，或藉由使用例如非等向性蝕刻的蝕刻方式。若介電層112為感光性材料，則介電層112可在曝光之後顯影。
應瞭解，背側重佈線結構106可包含任何數目的介電層及金屬化圖案。若較多介電層及金屬化圖案待形成，則可重複上文所論述之步驟及製程。金屬化圖案可包含多個導線及多個導通孔。可在形成金屬化圖案期間藉由在下伏介電層的開口中形成金屬化圖案的晶種層及導電材料來形成導通孔。導通孔可因此互連且電耦合各種導線。
在圖4中，多個穿孔116可分別形成於開口114中，且遠離背側重佈線結構106的最頂部介電層（例如，介電層112）延伸。穿孔116為視情況選用的，且可省略。舉例而言，在省略背側重佈線結構106的實施例中可（或可不）省略穿孔116。作為形成穿孔116的一實例，晶種層形成於背側重佈線結構106上方，例如介電層112及由開口114暴露的金屬化圖案110的部分上。在一些實施例中，晶種層為金屬層，其可為單一層或包括由不同材料形成之多個子層的複合層。在一實施例中，晶種層包括鈦層及在鈦層上方的銅層。可使用例如PVD或類似者來形成晶種層。在晶種層上形成光阻並使所述光阻圖案化。光阻可藉由旋塗或類似製程而形成，且可暴露於光以用於圖案化。光阻的圖案對應於導通孔。所述圖案化形成貫穿光阻的多個開口以暴露晶種層。導電材料形成於光阻的開口中及晶種層的經暴露部分上。導電材料可藉由諸如以下的鍍覆形成：電鍍或無電電鍍或類似者。導電材料可包括金屬，如銅、鈦、鎢、鋁或類似者。將光阻及晶種層上未形成導電材料的部分移除。可藉由可接受的灰化或剝離製程，諸如使用氧電漿或類似者來移除光阻。一旦移除光阻，則諸如藉由使用可接受的蝕刻製程，諸如藉由濕式蝕刻或乾式蝕刻來移除晶種層的經暴露部分。晶種層及導電材料的其餘部分形成穿孔116。
在圖5中，積體電路晶粒50藉由黏著劑118黏著至介電層112。將所需類型及數量的積體電路晶粒50黏著至封裝區100A及封裝區100B中的每一者中。在所示之實施例中，包含第一積體電路晶粒50A及第二積體電路晶粒50B的多個積體電路晶粒50以鄰接於彼此的方式被貼黏。第一積體電路晶粒50A可為邏輯元件，諸如中央處理單元（CPU）、圖形處理單元（GPU）、系統晶片（SoC）、微控制器或類似者。第二積體電路晶粒50B可為記憶體元件，諸如動態隨機存取記憶體（DRAM）晶粒、靜態隨機存取記憶體（SRAM）晶粒、混合記憶體立方（HMC）模組、高頻寬記憶體（HBM）模組或類似者。在一些實施例中，積體電路晶粒50A及積體電路晶粒50B可為相同類型的晶粒，諸如SoC晶粒。第一積體電路晶粒50A及第二積體電路晶粒50B可形成於相同技術節點的製程中，或可形成於不同技術節點的製程中。舉例而言，第一積體電路晶粒50A可屬於比第二積體電路晶粒50B更後期（先進）的製程節點。積體電路晶粒50A及積體電路晶粒50B可具有不同大小（例如，不同高度及/或表面區域），或可具有相同大小（例如，相同高度及/或表面區域）。特定言之，當積體電路晶粒50A及積體電路晶粒50B包含具有大佔據面積的元件，諸如SoC時，可用於封裝區100A及封裝區100B中之穿孔116的空間可有限。當封裝區100A及封裝區100B中可用於穿孔116的空間有限時，使用背側重佈線結構106能夠實現改良之內連線配置。
黏著劑118位於積體電路晶粒50A及積體電路晶粒50B的背側上，且將積體電路晶粒50A及積體電路晶粒50B黏著至背側重佈線結構106，諸如黏著至介電層112。黏著劑118可為任何適合的黏著劑、環氧樹脂、晶粒貼合膜（die attach film；DAF）或類似者。黏著劑118可經塗覆至積體電路晶粒50A及積體電路晶粒50B的背側，或可經塗覆於載體基底102的表面上。舉例而言，在單體化以使積體電路晶粒50A及積體電路晶粒50B分離之前，黏著劑118可經塗覆至積體電路晶粒50A及積體電路晶粒50B的背側。
在圖6中，密封體120形成於各種組件上且圍繞各種組件。在形成之後，密封體120密封穿孔116、積體電路晶粒50A及積體電路晶粒50B。密封體120可為模製化合物、環氧樹脂或類似者。密封體120可藉由壓縮模製（compression molding）、轉移模製（transfer molding）或類似者施加，且可形成於載體基底102上方，使得穿孔116及/或積體電路晶粒50A及積體電路晶粒50B被其掩埋或覆蓋。若存在，則密封體120進一步形成於積體電路晶粒50A與積體電路晶粒50B之間的間隔區中。密封體120可以透過液體或半液體形式而施加且然後經固化。
在圖7中，對密封體120執行平面化製程以暴露穿孔116及晶粒連接件66。平面化製程亦可移除穿孔116、介電層68及/或晶粒連接件66的材料直至暴露晶粒連接件66及穿孔116為止。在平面化製程後，穿孔116、晶粒連接件66、介電層68以及密封體120的頂部表面為共面的。平面化製程可為例如化學機械研磨（chemical-mechanical polish；CMP）、研磨製程或類似者。在一些實施例中，例如若穿孔116及晶粒連接件66已暴露，則可省略平面化。
在圖8至圖11中，前側重佈線結構122（見圖11）形成於密封體120、穿孔116、積體電路晶粒50A及積體電路晶粒50B上方。前側重佈線結構122包含多個介電層，例如介電層124、介電層128、介電層132以及介電層136；以及多個金屬化圖案，例如金屬化圖案126、金屬化圖案130以及金屬化圖案134。金屬化圖案亦可稱作重佈線層或重佈線。前側重佈線結構122經示出為具有三個金屬化圖案層的實例。更多或更少介電層及金屬化圖案可形成於前側重佈線結構122中。若更少介電層及金屬化圖案待形成，則可省略下文論述的步驟及製程。若更多介電層及金屬化圖案待形成，則可重複下文所論述的步驟及製程。
在圖8中，介電層124沈積於密封體120、穿孔116以及晶粒連接件66上。在一些實施例中，介電層124由諸如PBO、聚醯亞胺、BCB或類似者的感光性材料形成，可使用微影罩幕使所述介電層124圖案化。介電層124可藉由旋塗、層壓、CVD、類似者或其組合形成。介電層124隨後被圖案化。透過圖案化，形成多個開口從而暴露穿孔116及晶粒連接件66的多個部分。可藉由可接受的製程圖案化，諸如當介電層124為感光性材料時藉由將介電層124暴露於光，或藉由使用例如非等向性蝕刻來蝕刻。若介電層124為感光性材料，則介電層124可在曝光之後顯影。
隨後形成金屬化圖案126。金屬化圖案126包含在介電層124的主表面上及沿所述介電層124的主表面延伸的多個線路部分（亦稱為導線）。金屬化圖案126更包含延伸穿過介電層124以實體耦合及電耦合穿孔116、積體電路晶粒50A及積體電路晶粒50B的多個通孔部分（亦稱為導通孔）。作為形成金屬化圖案126的一實例，晶種層形成於介電層124上方及延伸穿過介電層124的開口中。在一些實施例中，晶種層為金屬層，其可為單一層或包括由不同材料形成之多個子層的複合層。在一些實施例中，晶種層包括鈦層及在鈦層上方的銅層。可使用例如PVD或類似者來形成晶種層。隨後在晶種層上形成光阻並使所述光阻圖案化。光阻可藉由旋塗或類似製程而形成，且可暴露於光以用於圖案化。光阻的圖案對應於金屬化圖案126。透過圖案化，形成穿過光阻的多個開口以暴露晶種層。導電材料隨後形成於光阻的開口中及晶種層的經暴露部分上。導電材料可藉由諸如以下的鍍覆形成：電鍍或無電電鍍或類似者。導電材料可包括金屬，如銅、鈦、鎢、鋁或類似者。導電材料與晶種層的下伏部分的組合形成金屬化圖案126。光阻及晶種層上不形成導電材料的部分經移除。可藉由可接受的灰化或剝離製程，諸如使用氧電漿或類似者來移除光阻。一旦移除光阻，則諸如藉由使用可接受的蝕刻製程，諸如藉由濕式蝕刻或乾式蝕刻來移除晶種層的經暴露部分。
在圖9中，介電層128沈積於金屬化圖案126及介電層124上。介電層128可以類似於介電層124的方式形成，且可由與介電層124類似的材料形成。
隨後形成金屬化圖案130。金屬化圖案130包含在介電層128的主表面上及沿所述介電層的主表面延伸的多個線路部分。金屬化圖案130更包含延伸穿過介電層128以實體耦合及電耦合金屬化圖案126的多個通孔部分。金屬化圖案130可以與金屬化圖案126類似的方式及類似的材料形成。在一些實施例中，金屬化圖案130具有與金屬化圖案126不同的大小。舉例而言，金屬化圖案130的導線及/或通孔可比金屬化圖案126的導線及/或通孔更寬或更厚。此外，金屬化圖案130可以透過比金屬化圖案126更大的間距形成。
在圖10中，介電層132沈積於金屬化圖案130及介電層128上。介電層132可以類似於介電層124的方式形成，且可由與介電層124類似的材料形成。
隨後形成金屬化圖案134。金屬化圖案134包含在介電層132的主表面上及沿所述介電層的主表面延伸的多個線路部分。金屬化圖案134更包含延伸穿過介電層132以實體耦合及電耦合金屬化圖案130的多個通孔部分。金屬化圖案134可以與金屬化圖案126類似的方式及類似的材料形成。金屬化圖案134為前側重佈線結構122的最頂部金屬化圖案。如此，前側重佈線結構122的所有中間金屬化圖案（例如，金屬化圖案126及金屬化圖案130）安置於金屬化圖案134與積體電路晶粒50A及積體電路晶粒50B之間。在一些實施例中，金屬化圖案134具有與金屬化圖案126及金屬化圖案130不同的大小。舉例而言，金屬化圖案134的導線及/或通孔可比金屬化圖案126及金屬化圖案130的導線及/或通孔更寬或更厚。此外，金屬化圖案134可以透過比金屬化圖案130更大的間距形成。
在圖11中，介電層136沈積於金屬化圖案134及介電層132上。所述介電層136可以與介電層124類似的方式形成，且可由與介電層124類似的材料形成。介電層136為前側重佈線結構122的最頂部介電層。如此，前側重佈線結構122的所有金屬化圖案（例如，金屬化圖案126、金屬化圖案130以及金屬化圖案134）安置於介電層136與積體電路晶粒50A及積體電路晶粒50B之間。此外，前側重佈線結構122的所有中間介電層（例如，介電層124、介電層128、介電層132）安置於介電層136與積體電路晶粒50A及積體電路晶粒50B之間。
在圖12中，多個凸塊下金屬138經形成以與前側重佈線結構122進行外部連接。凸塊下金屬138具有在介電層136的主表面上及沿所述介電層的主表面延伸的凸塊部分，且具有延伸穿過介電層136以實體耦合及電耦合金屬化圖案134的通孔部分。因而，凸塊下金屬138電耦合至穿孔116、積體電路晶粒50A及積體電路晶粒50B。凸塊下金屬138可形成於若干製程中的一者或若干製程之組合中。
圖13A至圖13C說明根據一些實施例的形成凸塊下金屬138的方法。單個凸塊下金屬138的形成說明於第一封裝組件100的區域的詳細視圖中。應瞭解，為了清楚起見，省略或放大一些細節。此外，多個凸塊下金屬138可同時形成。
在圖13A中，介電層136經圖案化以形成開口140從而暴露金屬化圖案134的部分。圖案化可藉由可接受的製程進行，諸如當介電層136為感光性材料時藉由將介電層136暴露於光，或藉由使用例如非等向性蝕刻來蝕刻。若介電層136感光性材料，則介電層136可在曝光之後顯影。開口140具有小平均寬度W1 。在一些實施例中，寬度W1 介於約20微米至約25微米範圍內，諸如約25微米。開口140的小寬度W1 減小金屬化圖案134與凸塊下金屬138接觸的量。換言之，凸塊下金屬138接觸金屬化圖案134的較小著陸襯墊（smaller landing pad）。可用於訊號佈線的金屬化圖案134的量可因此增大。
介電層136具有大的厚度，且因此開口140具有大的深度D1 。深度D1 大於前側重佈線結構122的中間介電層的厚度。在一些實施例中，深度D1 為至少約7微米，諸如介於約10微米至約30微米範圍內，諸如約15微米。當前側重佈線結構122貼合到另一基底（下文進一步論述）時，介電層136的大的厚度可幫助減小施加在金屬化圖案126、金屬化圖案130以及金屬化圖案134上的機械應力。特定言之，因為介電層136為前側重佈線結構122的最頂部介電層，因此大的厚度允許介電層136緩衝可以其他方式施加在前側重佈線結構122的中間介電層上的機械應力。可因此避免前側重佈線結構122中的破裂及剝離。在一實驗中，約15微米的深度D1 ，介電層136與金屬化圖案134之間的機械應力會減小約23%，其中在後處理及應力測試期間不進一步產生破裂。
在圖13B中，晶種層142形成於介電層136上方及開口140中。在一些實施例中，晶種層142為金屬層，所述金屬層可為單一層或包括由不同材料形成之多個子層的複合層。在一些實施例中，晶種層142包括鈦層及在鈦層上方的銅層。可使用例如PVD或類似者來形成晶種層142。隨後在晶種層142上形成光阻144且使所述光阻144圖案化。光阻144可藉由旋塗或類似者形成。在一些實施例中，光阻144經形成以具有介於約10微米至約100微米範圍內（諸如約72微米）的厚度T2 。光阻144可隨後暴露於光以進行圖案化。光阻144的圖案對應於凸塊下金屬138。透過圖案化，形成穿過光阻144的開口146以暴露晶種層142。在上述形成後，開口140及開口146具有合併深度D2 。在一些實施例中，合併深度D2 介於約5微米至約90微米範圍內，諸如約35微米。
在圖13C中，導電材料148形成於光阻144的開口146中及晶種層142的經暴露部分上。導電材料148可藉由諸如以下的鍍覆形成：電鍍或無電電鍍或類似者。導電材料148可包括金屬，如銅、鈦、鎢、鋁或類似者。隨後，移除光阻144以及晶種層142上未形成導電材料148的部分。可藉由可接受的灰化或剝離製程，諸如使用氧電漿或類似者來移除光阻144。一旦移除光阻144，則諸如藉由使用可接受的蝕刻製程，諸如藉由濕式蝕刻或乾式蝕刻來移除晶種層142的經暴露部分。晶種層142及導電材料148的其餘部分形成凸塊下金屬138。在凸塊下金屬138以不同方式而形成的實施例中，更多的光阻144及圖案化步驟可被利用。
在上述形成後，凸塊下金屬138的通孔部分138A具有厚度T1 ，厚度T1 等於開口140之深度D1 。厚度T1 與寬度W1 的比率可稱作凸塊下金屬138的通孔部分138A的縱橫比。在一些實施例中，開口140的縱橫比介於約1.33至約1.66範圍內。在一實驗中，縱橫比介於約1.33至約1.66範圍內，施加在金屬化圖案134上的機械應力會減小約14%。此外，在一些實施例中，金屬化圖案134具有介於約0.8微米至約4微米範圍內的厚度T3 。在一些實施例中，厚度T1 與厚度T3 的比率為至少6。
此外，在上述形成後，凸塊下金屬138的凸塊部分138B具有大於厚度T1 的厚度T2 。在一些實施例中，厚度T2 介於約10微米至約40微米範圍內，諸如約30微米。此類厚度T2 亦可幫助減小施加在金屬化圖案134上的機械應力。在一實驗中，約30微米的厚度T2 將施加在金屬化圖案134上的機械應力減小約10%。厚度T2 與厚度T1 的比率為大的。在一些實施例中，厚度T2 與厚度T1 的比率為至少1.5，諸如介於約1.5至約2.33範圍內。
此外，在上述形成後，凸塊下金屬138的通孔部分138A具有與開口140相同的寬度W1 。凸塊下金屬138的凸塊部分138B具有小的平均寬度W2 。在一些實施例中，寬度W2 為至少50微米，諸如介於約70微米至約105微米範圍內。在一實驗中，約82微米的寬度W2 將施加在金屬化圖案134上的機械應力減小約10%。寬度W2 大於寬度W1 。小的平均寬度W2 允許彼此鄰接之凸塊下金屬138之間的距離增大。因隨後所形成的導電連接件而在凸塊下金屬138之間的焊料橋連（solder bridging）的風險可因此減小。寬度W2 與寬度W1 的比率為大的。在一些實施例中，寬度W2 與寬度W1 的比率為至少2.5，諸如介於約2.5至約3.6範圍內。此外，在上述形成後，凸塊下金屬138具有合併厚度TC ，其為厚度T1 及厚度T2 的總和。在一些實施例中，合併厚度TC 介於約20微米至約70微米範圍內。合併厚度TC 與寬度W1 的比率為大的。在一些實施例中，合併厚度TC 與寬度W1 的比率為至少0.2，諸如介於約0.2至約3.3範圍內。在一實驗中，約15微米的寬度W1 與約50微米的合併厚度TC 的組合將施加在金屬化圖案134上的機械應力減小約15%。
如上所指出，凸塊下金屬138的各種數值及比率允許前側重佈線結構122的機械可靠性增強。在一實驗中，開口140的縱橫比的組合介於約1.33至約1.66範圍內，厚度T1 與厚度T3 的比率介於約3.5至約10範圍內，且厚度T2 與厚度T1 的比率介於約1.5至約2.33範圍內，從而允許凸塊下金屬138經歷超過2000次熱應力測試而無組件故障。
圖14說明根據一些其他實施例的凸塊下金屬138。第一封裝組件100的第一區10A及第二區10B的詳細視圖中示出多個凸塊下金屬138。應瞭解，為了清楚起見，省略或放大一些細節。在此實施例中，凸塊下金屬138的凸塊部分138B在第一區10A及第二區10B兩者中具有相同寬度W2 及厚度T2 。此外，凸塊下金屬138的通孔部分138A在第一區10A及第二區10B兩者中具有相同厚度T1 。然而，凸塊下金屬138的通孔部分138A在第一區10A及第二區10B中具有不同寬度。舉例而言，凸塊下金屬138的通孔部分138A在第一區10A中具有第一寬度W1A ，且凸塊下金屬138的通孔部分138A在第二區10B中具有第二寬度W1B 。寬度W1A 及寬度W1B 相差較大的量。在一些實施例中，寬度W1A 與寬度W1B 之間的差值為至少5微米，諸如介於約25微米至約45微米範圍內。較窄寬度的通孔部分形成於較高機械應力下的區域中。舉例而言，當在第一區10A的機械應力是更高於第二區10B的機械應力狀態下時，寬度W1A 小於寬度W1B 。
圖15說明根據一些其他實施例的凸塊下金屬138。單個凸塊下金屬138示於第一封裝組件100的區域的詳細視圖中。應瞭解，為了圖解清楚起見，省略或放大一些細節。此外，多個凸塊下金屬138可同時形成。在此實施例中，凸塊下金屬138具有多個通孔部分138A，所述多個通孔部分138A各自具有相同寬度W1 。給定凸塊下金屬138的所述多個通孔部分138A中的每一者接觸金屬化圖案134中的相同著陸襯墊。凸塊下金屬138可具有任何數量的通孔部分138A，諸如介於2至4範圍內的數量。額外的通孔部分138A可幫助緩衝可能以其他方式施加在前側重佈線結構122的中間金屬化圖案上的機械應力。前側重佈線結構122中的破裂及剝離可因此避免。
圖16說明根據一些其他實施例的凸塊下金屬138。單個凸塊下金屬138示於第一封裝組件100的區域的詳細視圖中。應瞭解，為了圖解清楚起見，省略或放大一些細節。此外，多個凸塊下金屬138可同時形成。在此實施例中，凸塊下金屬138具有多個通孔部分138A，所述多個通孔部分138A各自具有不同寬度。舉例而言，凸塊下金屬138可具有帶有第一寬度W1C 的第一通孔部分及帶有第二寬度W1D 的第二通孔部分。寬度W1C 及寬度W1D 可不同。在一些實施例中，寬度W1C 與寬度W1D 之間的差值為至少5微米，諸如介於約25微米至約45微米範圍內。
圖17A至圖17O為根據圖15及圖16的實施例的凸塊下金屬138的俯視圖。凸塊下金屬138的通孔部分138A及凸塊部分138B在俯視圖中可具有若干可能的形狀。此外，凸塊下金屬138的通孔部分138A及凸塊部分138B在俯視圖中可具有相同形狀，或在俯視圖中可具有不同形狀。通孔部分138A可具有圓形形狀（見圖17A至圖17E）、四邊形/正方形形狀（見圖17F至圖17J）及/或八邊形形狀（見圖17K至圖17O）。單個凸塊下金屬138可包含不同形狀的多個通孔部分138A。同樣地，凸塊部分138B可具有圓形形狀（見圖17A、圖17F以及圖17K）、橢圓形形狀（見圖17B、圖17G以及圖17L）、八邊形形狀（見圖17C、圖17H以及圖17M）、六角形狀（見圖17D、圖17I以及圖17N）及/或四邊形/正方形形狀（見圖17E、圖17J以及圖17O）。此外，具有不同形狀的凸塊部分138B之凸塊下金屬138可組合在相同封裝上。
在圖18中，多個導電連接件150分別形成於凸塊下金屬138上。導電連接件150可為球柵陣列封裝（ball grid array；BGA）連接件、焊球、金屬柱、受控塌陷晶片連接（controlled collapse chip connection；C4）凸塊、微型凸塊（microp bump）、化學鍍鎳鈀浸金技術（electroless nickel-electroless palladium-immersion gold technique；ENEPIG）形成的凸塊或類似者。導電連接件150可包含導電材料，諸如焊料、銅、鋁、金、鎳、銀、鈀、錫、類似者或其組合。在一些實施例中，導電連接件150藉由首先經由蒸發、電鍍、印刷、焊料轉移、植球或類似者形成焊料層而形成。在焊料層已形成於結構上後，可執行回流以便將材料塑形成所需之凸塊形狀。在另一實施例中，導電連接件150包括藉由濺鍍、印刷、電鍍、無電電鍍、CVD或類似者形成的金屬柱（諸如銅柱）。金屬柱可不具有焊料且具有實質上垂直之側壁。在一些實施例中，金屬頂蓋層形成於金屬柱之頂部。金屬頂蓋層可包含鎳、錫、錫鉛、金、銀、鈀、銦、鎳鈀金、鎳金、類似者或其組合，且可由鍍覆製程形成。
在圖19中，執行載體基底剝離，以自背側重佈線結構106（例如，介電層108）分離（或「剝離」）載體基底102。根據一些實施例，剝離方法包含對釋放層104發射光，諸如雷射光或UV光，使得釋放層104在光的熱量下分解，而移除載體基底102。接著翻轉上述結構且將其置放於載帶（tape）上。
在圖20中，多個導電連接件152經形成為延伸穿過介電層108以接觸金屬化圖案110。多個開口經形成為穿過介電層108以暴露金屬化圖案110的多個部分。開口可使用例如雷射鑽孔、蝕刻或類似者形成。導電連接件152形成於開口中。在一些實施例中，導電連接件152包括焊劑且形成於焊劑浸漬製程中。在一些實施例中，導電連接件152包括諸如焊料膏（solder paste）、銀膏或類似者的導電膏，且在印刷製程中被施配（dispense）。在一些實施例中，導電連接件152以類似於導電連接件150之方式形成，且可由與導電連接件150類似之材料形成。
圖21及圖22說明根據一些實施例的元件堆疊的形成及實施方案。元件堆疊由形成於第一封裝組件100中的積體電路封裝體所形成。元件堆疊亦可稱作疊層封裝（PoP）結構。因為PoP結構包含整合扇出型（InFO）封裝體，因此其亦可稱作InFO-PoP結構。
在圖21中，多個第二封裝組件200耦合至第一封裝組件100。所述多個第二封裝組件200中的一者耦合於封裝區100A及封裝區100B中的一者，以在第一封裝組件100的每一區域中形成積體電路元件堆疊。
第二封裝組件200包含基底202及耦合至基底202的一或多個堆疊晶粒210（包括堆疊晶粒210A及堆疊晶粒210B）。雖然示出了一組堆疊晶粒210（包括堆疊晶粒210A及堆疊晶粒210B），但在其他實施例中，多個堆疊晶粒210（各自具有一或多個堆疊晶粒）可並排設置從而耦合至基底202的相同表面。基底202可由諸如矽、鍺、金剛石或類似者的半導體材料製成。在一些實施例中，亦可使用化合物材料，諸如矽鍺、碳化矽、砷化鎵、砷化銦、磷化銦、碳化矽鍺、磷砷化鎵、磷化鎵銦、這些的組合以及類似者。另外，基底202可為絕緣層上有矽（SOI）基底。通常，SOI基底包含半導體材料層，諸如磊晶矽、鍺、矽鍺、SOI、絕緣層上有矽鍺（silicon germanium on insulator；SGOI）或其組合。在一個替代實施例中，基底202基於諸如玻璃纖維強化樹脂芯的絕緣芯（insulating core）。一種實例的芯材料為玻璃纖維樹脂，諸如FR4。芯材料的替代方案包含雙馬來醯亞胺三嗪（bismaleimide-triazine；BT）樹脂，或替代地，其他印刷電路板（printed circuit board；PCB）材料或膜。諸如味素累積膜（Ajinomoto build-up film；ABF）的累積膜或其他層壓物亦可用於基底202。
基底202可包含主動元件及被動元件（未示出）。對第二封裝組件200的設計的結構性及功能性要求，可使用諸如電晶體、電容器、電阻器、這些的組合以及類似者的多種元件來產生。元件可使用任何適合之方法形成。
基底202亦可包含多個金屬化層（未示出）以及多個導通孔208。金屬化層可形成於主動元件以及被動元件上方，且經設計以連接各種元件以形成功能性電路（functional circuitry）。金屬化層可由介電質（例如，低k介電材料）與導電材料（例如，銅）的多個交替層以及內連導電材料層的多個通孔所構成，且其可經由任何適合的製程（諸如，沈積、鑲嵌、雙鑲嵌或類似者）而形成。在一些實施例中，基底202實質上不含主動元件及被動元件。
基底202可具有在基底202的第一側上的多個接合墊204以耦合至堆疊晶粒210，及在基底202的第二側上的多個接合墊206以耦合至導電連接件152，基底202的第二側與第一側相對。在一些實施例中，接合墊204及接合墊206藉由在基底202的第一側及第二側上的介電層（未示出）中形成多個凹部來形成。凹部可經形成以允許接合墊204及接合墊206嵌入至介電層中。在其他實施例中，省略凹部，這是因為接合墊204及接合墊206可形成於介電層上。在一些實施例中，接合墊204及接合墊206包含由銅、鈦、鎳、金、鈀、類似者或其組合製成之薄晶種層。接合墊204及接合墊206之導電材料可沈積於薄晶種層上方。導電材料可藉由電化學鍍覆製程、無電電鍍製程、CVD、原子層沈積（atomic layer deposition；ALD）、PVD、類似者或其組合形成。在一實施例中，接合墊204及接合墊206之導電材料為銅、鎢、鋁、銀、金、類似者或其組合。
在一實施例中，接合墊204及接合墊206為包含三個導電材料層（諸如，鈦層、銅層以及鎳層）之凸塊下金屬。其他的材料及膜層之配置，諸如鉻/鉻-銅合金/銅/金的配置、鈦/鈦鎢/銅的配置或銅/鎳/金的配置亦可被利用以形成接合墊204及接合墊206。任何可用於接合墊204及接合墊206的適合之材料或材料層也完全地被包含於當前應用的範疇內。在一些實施例中，多個導通孔208延伸穿過基底202且將接合墊204中之至少一者耦合至接合墊206中之至少一者。
在所說明實施例中，儘管堆疊晶粒210藉由打線接合（wire bond）212耦合至基底202，但可使用其他連接件，諸如，導電凸塊。在一實施例中，堆疊晶粒210為堆疊記憶體晶粒。舉例而言，堆疊晶粒210可為諸如低功率（low-power；LP）雙資料速率（double data rate；DDR）記憶體模組之記憶體晶粒，諸如LPDDR1、LPDDR2、LPDDR3、LPDDR4或類似記憶體模組。
堆疊晶粒210及打線接合212可由模製材料214密封。模製材料214可例如使用壓縮模製來模製在堆疊晶粒210及打線接合212上。在一些實施例中，模製材料214為模製化合物、聚合物、環氧樹脂、氧化矽填充物材料、類似者或其組合。可執行固化製程以固化模製材料214；固化製程可為熱固化、UV固化、類似者，或其組合。
在一些實施例中，堆疊晶粒210及打線接合212掩埋於模製材料214中，且在固化模製材料214之後，執行諸如研磨的平面化步驟以移除模製材料214之過量部分且為第二封裝組件200提供實質上平面之表面。
在形成第二封裝組件200後，第二封裝組件200借助於導電連接件152、接合墊206以及背側重佈線結構106來機械接合及電接合至第一封裝組件100。在一些實施例中，堆疊晶粒210可經由打線接合212、接合墊204及接合墊206、導通孔208、導電連接件152、背側重佈線結構106、穿孔116以及前側重佈線結構122來耦合至積體電路晶粒50A及積體電路晶粒50B。
在一些實施例中，阻焊劑（solder resist）形成於基底202與堆疊晶粒210相對的側面上。導電連接件152可安置於阻焊劑中的多個開口中以電耦合及機械地耦合至基底202中的導電特徵（例如，接合墊206）。阻焊劑可用於保護基底202的多個區域免受外部損壞。
在一些實施例中，導電連接件152可在其回流之前先形成有環氧樹脂助焊劑（epoxy flux），其中所述環氧樹脂助焊劑中的至少一些環氧樹脂部分在第二封裝組件200貼合至第一封裝組件100之後被保留。
在一些實施例中，底部填充物形成於第一封裝組件100與第二封裝組件200之間，從而包圍導電連接件152。底部填充物可減小應力且保護由導電連接件152的回流產生的接頭（joint）。底部填充物可在貼合第二封裝組件200後藉由毛細流動製程（capillary flow process）形成，或可在貼合第二封裝組件200之前藉由適合的沈積方法形成。在形成環氧樹脂助焊劑之實施例中，環氧樹脂助焊劑可充當底部填充物。
在圖22中，藉由沿例如第一封裝區100A與第二封裝區100B之間的切割道區（scribe line region）進行鋸割，來執行單體化製程。透過鋸割（sawing），使第一封裝區100A與第二封裝區100B單體化。所產生之單體化元件堆疊來自第一封裝區100A或第二封裝區100B中之一者。在一些實施例中，在第二封裝組件200耦合至第一封裝組件100後執行單體化製程。在其他實施例中，在第二封裝組件200耦合至第一封裝組件100之前執行單體化製程，諸如在剝離載體基底102及形成導電連接件152之後。
每一個經單體化第一封裝組件100是隨後使用導電連接件150安裝至封裝基底300。封裝基底300包含基底芯（substrate core）302及基底芯302上方的多個接合墊304。基底芯302可由諸如矽、鍺、金剛石或類似者的半導體材料製成。或者，亦可使用化合物材料，諸如矽鍺、碳化矽、砷化鎵、砷化銦、磷化銦、碳化矽鍺、磷砷化鎵、磷化鎵銦、這些的組合以及類似者。另外，基底芯302可為SOI基底。通常，SOI基底包含半導體材料層，諸如磊晶矽、鍺、矽鍺、SOI、SGOI或其組合。在一個替代實施例中，基底芯302基於諸如玻璃纖維強化樹脂芯的絕緣芯。一個實例的芯材料為玻璃纖維樹脂，諸如FR4。芯材料的替代方案包含雙馬來醯亞胺三嗪（BT）樹脂，或者，其他PCB材料或膜層。諸如ABF或其他層壓物的累積膜也可用作為基底芯302。
基底芯302可包含主動元件及被動元件（未示出）。如於本領域具有通常知識者了解，對元件堆疊的設計的結構性及功能性要求，也可使用諸如電晶體、電容器、電阻器、這些的組合以及類似者的多種元件來產生。元件可使用任何合適的方法來形成。
基底芯302亦可包含多個金屬化層及多個通孔（未示出），其中接合墊304實體耦合及/或電耦合至金屬化層及通孔。金屬化層可形成於主動元件及被動元件上方，且經設計以連接各種元件以形成功能性電路。金屬化層可由介電質（例如，低k介電材料）與導電材料（例如，銅）的交替層以及內連導電材料層的通孔所構成，且可經由任何適合的製程（諸如，沈積、鑲嵌、雙鑲嵌或類似者）而形成。在一些實施例中，基底芯302實質上不含主動元件及被動元件。
在一些實施例中，回流導電連接件150以將第一封裝組件100貼合至接合墊304。導電連接件150將封裝基底300（包含在基底芯302中的金屬化層）電耦合及/或實體耦合至第一封裝組件100。在一些實施例中，阻焊劑306形成於基底芯302上。導電連接件150可安置於阻焊劑306中的多個開口中以電耦合及機械耦合至接合墊304。阻焊劑306可用於保護基底芯302的多個區域免受外部損壞。
導電連接件150可在其回流之前先形成有環氧樹脂助焊劑，其中所述環氧樹脂助焊劑中的至少一些環氧樹脂部分在第一封裝組件100貼合至封裝基底300之後被保留。此保留的環氧樹脂部分可充當底部填充物，以減小因對導電連接件150進行回流而產生之應力並保護因對導電連接件150進行回流而產生的接頭。在一些實施例中，底部填充物308可形成於第一封裝組件100與封裝基底300之間且包圍導電連接件150。底部填充物308可在貼合第一封裝組件100後藉由毛細流動製程形成，或可在貼合第一封裝組件100之前藉由適合的沈積方法形成。
在一些實施例中，亦可將被動元件（例如，表面安裝元件（surface mount devices；SMD），未示出）貼合至第一封裝組件100（例如，貼合至凸塊下金屬138）或貼合至封裝基底300（例如，貼合至接合墊304）。舉例而言，被動元件可接合至第一封裝組件100或封裝基底300與導電連接件150相同的表面。被動元件可在將第一封裝組件100安裝在封裝基底300上之前貼合至封裝組件100，或可在將第一封裝組件100安裝在封裝基底300上之前或之後貼合至封裝基底300。
應瞭解，第一封裝組件100可實施於其他元件堆疊中。舉例而言，示出一PoP結構，但其第一封裝組件100亦可實施於倒裝晶片球柵陣列（FCBGA）封裝中。在此類實施例中，第一封裝組件100安裝至諸如封裝基底300之基底，但省略第二封裝組件200。替代地，封蓋（lid）或散熱器（heat spreader）可貼合至第一封裝組件100。當省略第二封裝組件200時，背側重佈線結構106及穿孔116亦可省略。
亦可包含其他特性及製程。舉例而言，可包含測試結構以幫助對3D封裝或3DIC元件的驗證測試。測試結構可包含例如形成於重佈線層中或基底上的測試墊，其允許測試3D封裝或3DIC、使用探針及/或探測卡以及類似者。可對中間結構及最終結構執行驗證測試。另外，本文中所揭露的結構及方法可結合併入有對良裸晶粒的中間驗證的測試方法而使用，以提高良率且降低成本。
圖23說明根據一些其他實施例的元件堆疊。在此實施例中，省略背側重佈線結構106、穿孔116以及第二封裝組件200。此外，第一封裝組件100包含一個第一積體電路晶粒50A（例如，邏輯元件）及多個第二積體電路晶粒50B（例如，記憶體元件）。在這個實施例中，第二積體電路晶粒50B為包含多個半導體基底52及內連線結構60的堆疊元件，諸如記憶體立方體。
上述實施例可實現多個優點。第一封裝組件100及封裝基底300可具有不匹配的熱膨脹係數（coefficients of thermal expansion；CTE）。此差異值可為大的。舉例而言，在一些實施例中，第一封裝組件100可具有10ppm至30ppm範圍內的CTE，且封裝基底300可具有3ppm至17ppm範圍內的CTE。大的CTE差異值在測試或操作期間中會產生施加在前側重佈線結構122上的機械應力。介電層136的增大厚度允許介電層136緩衝機械應力。前側重佈線結構122中的破裂及剝離可因此避免，且凸塊下金屬138的平均寬度可減小。藉由減小凸塊下金屬138的平均寬度，金屬化圖案134與凸塊下金屬138接觸的量可減小。金屬化圖案134可用於訊號佈線的量可因此增大。減小凸塊下金屬138的寬度亦減小在凸塊下金屬138之間透過導電連接件150而焊料橋連的風險。
在一實施例中，一種元件包含：積體電路晶粒；密封體，至少部分地密封積體電路晶粒；導通孔，延伸穿過密封體；重佈線結構，位於密封體上，重佈線結構包含：金屬化圖案，電耦合至導通孔及積體電路晶粒；介電層，位於金屬化圖案上，介電層具有10微米至30微米的第一厚度；以及第一凸塊下金屬，具有延伸穿過介電層的第一通孔部分及在介電層上的第一凸塊部分，第一凸塊下金屬實體耦合及電耦合至金屬化圖案，第一通孔部分具有第一寬度，第一厚度與第一寬度的比率為1.33至1.66。
在上述元件之一些實施例中，第一凸塊部分具有第二寬度，第二寬度與第一寬度之比率為至少2.5。在上述元件之一些實施例中，第一寬度為20微米至25微米。在上述元件之一些實施例中，第二寬度為70微米至105微米。在上述元件之一些實施例中，第一凸塊部分具有第二厚度，第二厚度與第一厚度之比率為至少1.5。在上述元件之一些實施例中，第二厚度為10微米至40微米。在上述元件之一些實施例中，金屬化圖案具有第三厚度，第一厚度與第三厚度之比率為至少6。在上述元件之一些實施例中，第三厚度為0.8微米至4微米。在上述元件之一些實施例中，重佈線結構更包含：第二凸塊下金屬，具有延伸穿過介電層的第二通孔部分及在介電層上的第二凸塊部分，第二凸塊下金屬實體耦合及電耦合至金屬化圖案，第二通孔部分具有第二寬度，第二寬度比第一寬度大至少5微米。在上述元件之一些實施例中，第一凸塊下金屬更具有延伸穿過介電層的第二通孔部分，所述介電層的一部分介於第一通孔部分與第二通孔部分之間，且第一凸塊下金屬的第一通孔部分及第二通孔部分接觸金屬化圖案中的相同著陸襯墊。在上述元件之一些實施例中，第二通孔部分具有與第一通孔部分相同的寬度。在上述元件之一些實施例中，第二通孔部分具有第二寬度，第二寬度比第一寬度大至少5微米。在上述元件之一些實施例中，第一凸塊下金屬的第一凸塊部分、第一通孔部分以及第二通孔部分在俯視圖中具有相同形狀。在上述元件之一些實施例中，第一凸塊下金屬的第一凸塊部分在俯視圖中具有第一形狀，且第一凸塊下金屬的第一通孔部分及第二通孔部分在俯視圖中具有第二形狀，第一形狀不同於第二形狀。
在一實施例中，一種方法包含：形成自載體基底延伸的導電通孔；鄰接於導電通孔置放積體電路晶粒；用密封體密封積體電路晶粒及導電通孔；在密封體上沈積第一介電層；圖案化多個第一開口於第一介電層中，從而暴露出積體電路晶粒及導電通孔；在多個第一開口中及沿第一介電層形成金屬化圖案，金屬化圖案電耦合導通孔及積體電路晶粒；在金屬化圖案上沈積第二介電層，第二介電層具有10微米至30微米的第一厚度；圖案化第二開口於第二介電層中，從而暴露出金屬化圖案，第二開口具有第一寬度，第一厚度與第一寬度之比率為1.33至1.66；以及在第二開口中及沿第二介電層形成第一凸塊下金屬，第一凸塊下金屬實體耦合及電耦合至金屬化圖案。
在一些實施例中，所述方法更包含：圖案化第三開口於第二介電層中，從而暴露出金屬化圖案，且形成第一凸塊下金屬更包含在第三開口中形成第一凸塊下金屬。在一些實施例中，所述方法更包含：圖案化第三開口於第二介電層，從而暴露出金屬化圖案，第三開口具有第二寬度，第二寬度小於第一寬度；以及在第三開口中及沿第二介電層形成第二凸塊下金屬，第二凸塊下金屬實體耦合及電耦合至金屬化圖案。
在一實施例中，一種方法包含：形成自載體基底延伸的導通孔；鄰接於導通孔置放積體電路晶粒；用密封體密封積體電路晶粒及導通孔；形成金屬化圖案從而電耦合導通孔及積體電路晶粒；在金屬化圖案上沈積介電層；圖案化多個第一開口於介電層中，從而暴露出金屬化圖案的著陸襯墊，多個第一開口中的每一者具有不同寬度；以及在介電層上方形成罩幕，罩幕具有暴露多個第一開口中的每一者的第二開口；以及在多個第一開口及第二開口中鍍覆凸塊下金屬，多個第一開口中的凸塊下金屬的多個部分在俯視圖中各自具有第一形狀，第二開口中的凸塊下金屬的一個部分在俯視圖中具有第二形狀，第二形狀不同於第一形狀。
在上述方法之一些實施例中，介電層具有10微米至30微米的第一厚度。在上述方法之一些實施例中，第一厚度與多個第一開口中的每一者的寬度的比率為1.33至1.66。
前文概述若干實施例的特徵以使得本領域的技術人員可更佳地理解本發明的態樣。本領域的技術人員應理解，其可易於使用本發明作為設計或修改用於實現本文中所引入的實施例的相同目的及/或達成相同優點的其他製程及結構的基礎。本領域的技術人員亦應認識到，這些等效構造並不脫離本發明的精神及範疇，且本領域的技術人員可在不脫離本發明的精神及範疇之情況下在本文中作出各種改變、替代及更改。
10A:第一區 10B:第二區 50:積體電路晶粒 52:半導體基底 54:元件 56:層間介電質 58:導電插塞 60:內連線結構 62:接墊 64:鈍化膜 66:晶粒連接件 68、108、112、124、128、132、136:介電層 100:第一封裝組件 100A:第一封裝區 100B:第二封裝區 102:載體基底 104:釋放層 106:背側重佈線結構 110、126、130、134:金屬化圖案 114、140、146:開口 116:穿孔 118:黏著劑 120:密封體 122:前側重佈線結構 138:凸塊下金屬 138A:通孔部分 138B:凸塊部分 142:晶種層 144:光阻 148:導電材料 150、152:導電連接件 200:第二封裝組件 202:基底 204、206、304:接合墊 208:導通孔 210、210A、210B:堆疊晶粒 212:打線接合 214:模製材料 300:封裝基底 302:基底芯 306:阻焊劑 D1:深度 D2:合併深度 T1、T2、T3:厚度 TC:合併厚度 W1、W2:平均寬度 W1A、W1C:第一寬度 W1B、W1D:第二寬度
當結合附圖閱讀時，自以下詳細描述最佳地理解本發明之態樣。應注意，根據業界中的標準慣例，各種特徵未按比例繪製。實際上，可出於論述清楚起見，任意地增加或減小各種特徵之尺寸。 圖1示出根據一些實施例的積體電路晶粒的橫截面圖。 圖2至圖20根據一些實施例示出在用於形成封裝組件之製程期間的中間步驟的橫截面圖。 圖21及圖22示出根據一些實施例的元件堆疊的形成及實施方案。 圖23示出根據一些其他實施例的元件堆疊。
60:內連線結構
62:接墊
64:鈍化膜
66:晶粒連接件
68、124、128、132、136:介電層
126、130、134:金屬化圖案
122:前側重佈線結構
138:凸塊下金屬
138A:通孔部分
138B:凸塊部分
142:晶種層
148:導電材料
T1、T2、T3:厚度
TC:合併厚度
W1、W2:平均寬度

Claims (20)

  1. 一種元件，包括： 積體電路晶粒； 密封體，至少部分地密封所述積體電路晶粒； 導通孔，延伸穿過所述密封體；以及 重佈線結構，位於所述密封體上，所述重佈線結構包括： 金屬化圖案，電耦合至所述導通孔及所述積體電路晶粒； 介電層，位於所述金屬化圖案上，所述介電層具有10微米至30微米的第一厚度；以及 第一凸塊下金屬，具有延伸穿過所述介電層的第一通孔部分及在所述介電層上的第一凸塊部分，所述第一凸塊下金屬實體耦合及電耦合至所述金屬化圖案，所述第一通孔部分具有第一寬度，所述第一厚度與所述第一寬度的比率為1.33至1.66。
  2. 如申請專利範圍第1項所述的元件，其中所述第一凸塊部分具有第二寬度，所述第二寬度與所述第一寬度的比率為至少2.5。
  3. 如申請專利範圍第2項所述的元件，其中所述第一寬度為20微米至25微米。
  4. 如申請專利範圍第2項所述的元件，其中所述第二寬度為70微米至105微米。
  5. 如申請專利範圍第1項所述的元件，其中所述第一凸塊部分具有第二厚度，所述第二厚度與所述第一厚度的比率為至少1.5。
  6. 如申請專利範圍第5項所述的元件，其中所述第二厚度為10微米至40微米。
  7. 如申請專利範圍第5項所述的元件，其中所述金屬化圖案具有第三厚度，所述第一厚度與所述第三厚度的比率為至少6。
  8. 如申請專利範圍第7項所述的元件，其中所述第三厚度為0.8微米至4微米。
  9. 如申請專利範圍第1項所述的元件，其中所述重佈線結構更包括： 第二凸塊下金屬，具有延伸穿過所述介電層的第二通孔部分及在所述介電層上的第二凸塊部分，所述第二凸塊下金屬實體上耦合及電耦合至所述金屬化圖案，所述第二通孔部分具有第二寬度，所述第二寬度比所述第一寬度大至少5微米。
  10. 如申請專利範圍第1項所述的元件，其中所述第一凸塊下金屬更具有延伸穿過所述介電層的第二通孔部分，所述介電層的一部分介於所述第一通孔部分與所述第二通孔部分之間，且所述第一凸塊下金屬的所述第一通孔部分及所述第二通孔部分接觸所述金屬化圖案的同一個著陸襯墊。
  11. 如申請專利範圍第10項所述的元件，其中所述第二通孔部分具有與所述第一通孔部分相同的寬度。
  12. 如申請專利範圍第10項所述的元件，其中所述第二通孔部分具有第二寬度，所述第二寬度比所述第一寬度大至少5微米。
  13. 如申請專利範圍第10項所述的元件，其中所述第一凸塊下金屬的所述第一凸塊部分、所述第一通孔部分以及所述第二通孔部分在俯視圖中具有相同形狀。
  14. 如申請專利範圍第10項所述的元件，其中所述第一凸塊下金屬的所述第一凸塊部分在俯視圖中具有第一形狀，且所述第一凸塊下金屬的所述第一通孔部分及所述第二通孔部分在所述俯視圖中具有第二形狀，所述第一形狀不同於所述第二形狀。
  15. 一種方法，包括： 形成自載體基底延伸的導通孔； 鄰接所述導通孔置放積體電路晶粒； 用密封體密封所述積體電路晶粒及所述導通孔； 在所述密封體上沈積第一介電層； 圖案化多個第一開口於所述第一介電層中，所述多個第一開口暴露所述積體電路晶粒及所述導通孔； 在所述多個第一開口中及沿所述第一介電層形成金屬化圖案，所述金屬化圖案電耦合所述導通孔與所述積體電路晶粒； 在所述金屬化圖案上沈積第二介電層，所述第二介電層具有10微米至30微米的第一厚度； 圖案化第二開口於所述第二介電層中，所述第二開口暴露所述金屬化圖案，所述第二開口具有第一寬度，所述第一厚度與所述第一寬度的比率為1.33至1.66；以及 在所述第二開口中及沿所述第二介電層形成第一凸塊下金屬，所述第一凸塊下金屬實體耦合及電耦合至所述金屬化圖案。
  16. 如申請專利範圍第15項所述的方法，更包括： 圖案化第三開口於所述第二介電層中，所述第三開口暴露所述金屬化圖案，其中形成所述第一凸塊下金屬更包括在所述第三開口中形成所述第一凸塊下金屬。
  17. 如申請專利範圍第15項所述的方法，更包括： 圖案化第三開口於所述第二介電層中，所述第三開口暴露所述金屬化圖案，所述第三開口具有第二寬度，所述第二寬度小於所述第一寬度；以及 在所述第三開口中及沿所述第二介電層形成第二凸塊下金屬，所述第二凸塊下金屬實體耦合及電耦合至所述金屬化圖案。
  18. 一種方法，包括： 形成自載體基底延伸的導通孔； 鄰接所述導通孔置放積體電路晶粒； 用密封體密封所述積體電路晶粒及所述導通孔； 形成電耦合所述導通孔及所述積體電路晶粒的金屬化圖案； 在所述金屬化圖案上沈積介電層； 圖案化多個第一開口於所述介電層中，所述多個第一開口暴露所述金屬化圖案的著陸襯墊，所述多個第一開口中的每一者具有不同寬度； 在所述介電層上方形成罩幕，所述罩幕具有暴露出所述多個第一開口中的每一者的第二開口；以及 在所述多個第一開口及所述第二開口中鍍覆凸塊下金屬，所述多個第一開口中的所述凸塊下金屬的多個部分在俯視圖中各自具有第一形狀，所述第二開口中的所述凸塊下金屬的一個部分在所述俯視圖中具有第二形狀，所述第二形狀不同於所述第一形狀。
  19. 如申請專利範圍第18項所述的方法，其中所述介電層具有10微米至30微米的第一厚度。
  20. 如申請專利範圍第19項所述的方法，其中所述第一厚度與所述多個第一開口中的每一者的所述寬度的比率為1.33至1.66。
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