TWI777437B - 半導體封裝體及其製造方法 - Google Patents

半導體封裝體及其製造方法 Download PDF

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TWI777437B
TWI777437B TW110107930A TW110107930A TWI777437B TW I777437 B TWI777437 B TW I777437B TW 110107930 A TW110107930 A TW 110107930A TW 110107930 A TW110107930 A TW 110107930A TW I777437 B TWI777437 B TW I777437B
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Taiwan
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substrate
package
connectors
die
packages
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TW110107930A
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TW202141709A (zh
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張進傳
盧思維
余振華
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台灣積體電路製造股份有限公司
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Priority claimed from US17/097,579 external-priority patent/US11948930B2/en
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Abstract

提供一種方法，方法包含在基底中形成一組穿孔，且所述一組穿孔部分地穿過基底的厚度。多個第一連接件在基底的第一側上形成在所述一組穿孔上方。基底的第一側附接至載體。自基底的第二側薄化基底以暴露出所述一組穿孔。多個第二連接件在基底的第二側上形成在所述一組穿孔上方。元件晶粒接合至第二連接件。基底經單一化為多個封裝體。

Description

半導體封裝體及其製造方法
本發明實施例是有關於一種半導體封裝體及其製造方法。
半導體行業因於進行中的多種電子組件(例如電晶體、二極體、電阻器、電容器等)的整合密度的改良而經歷快速發展。主要地，整合密度的改良源自於最小特徵尺寸的反覆減小，其允許更多組件整合至給定區域中。隨著對於縮小的電子元件的需求增長，對於更小且更具創造性的半導體晶粒封裝技術的需要已出現。此類封裝系統的實例為疊層封裝(Package-on-Package；PoP)技術。在PoP元件中，頂部半導體封裝體堆疊於底部半導體封裝體的頂部上，以提供高整合度及高組件密度。PoP技術大體上使得能夠生產具有增強的功能性及在印刷電路板(printed circuit board；PCB)上的具有小佔據面積的半導體元件。
本發明實施例提供一種半導體封裝體的製造方法，所述 製造方法包括：在基底中形成一組穿孔，所述一組穿孔部分地穿過所述基底的厚度；在所述基底的第一側上在所述一組穿孔上方形成多個第一連接件；將所述基底的所述第一側附接至載體；薄化所述基底以暴露出所述一組穿孔；在所述基底的第二側上在所述一組穿孔上方形成多個第二連接件，所述第二側與所述第一側相對；將元件晶粒接合至所述多個第二連接件；以及將所述基底單一化為多個封裝體。
本發明實施例提供一種半導體封裝體的製造方法，所述製造方法包括：測試第一基底的第一組連接件，所述第一組連接件電耦接至第一組通孔結構；將所述第一基底的所述第一組連接件安裝至載體；薄化所述第一基底以暴露所述第一組通孔結構；將元件晶粒電耦接至所述第一組通孔結構；以及將所述第一基底單一化為多個封裝體。
本發明實施例提供一種半導體封裝體，其包括第一材料層、第一組連接件、第二組連接件、第一半導體元件以及包封體。所述第一材料層包括第一組穿孔，所述第一組穿孔具有自上而下愈來愈寬的寬度。所述第一組連接件安置在所述第一材料層的第一側上方。所述第二組連接件安置在所述第一材料層的第二側之下。所述第一半導體元件耦接至所述第一組連接件。所述包封體側向包圍所述第一半導體元件。
120:晶圓
122:元件晶粒
124、152:半導體基底
125、216、704:穿孔
126:積體電路元件
128、138、160:內連線結構
128a、156:層間介電質
128b:接觸插塞
128c:金屬線
128d:通孔
130:表面介電層
131:頂部金屬層
132、304、306、504:接合墊
134、172:焊料區
136、168、208、212、224、228、232、236:介電層
140、238:凸塊下金屬化物
141、141':探針卡
144、170、250、252:導電連接件
148、202:載體基底
150:積體電路晶粒
154:元件
158:導電插塞
162:襯墊
164:鈍化膜
166:晶粒連接件
174、520、720、790:底部填充膠
175、220:包封體
180:連接件
182:晶粒附接膜
185:框架
190:晶粒鋸切製程
195、195'、195":封裝體
200、200A、200B:封裝組件
204:釋放層
206:背側重佈線結構
210、226、230、234:金屬化圖案
218:黏著劑
222:前側重佈線結構
255:載帶
300:第二封裝組件
302、700:基底
308、760:導通孔
310、310A、310B:堆疊晶粒
312:導線
314:模製材料
400:積體電路元件堆疊
400A:第一封裝區
400B:第二封裝區
500:封裝基底
502、755:基底芯
506:阻焊劑
510、780A、780B:重佈線結構
600:3D封裝體
600':覆晶封裝體
600":基底上晶圓上晶片封裝體
706、712:接觸墊
710:第二重佈線結構
714:焊料凸塊
750:中介體
770、775:導電特徵
800、900:製程流程
802、804、806、808、810、812、814、816、818、820、822、824、902、904、906、908、910、912、914、916、918:製程
A-A:切線
P1:間距
W1:橫向尺寸
當結合隨附圖式閱讀時根據以下詳細描述最佳地理解本揭露的態樣。應注意，根據業界中的標準慣例，各種特徵未按比 例繪製。事實上，出於論述清楚起見，可任意地增加或減小各種特徵之尺寸。
圖1至圖11、圖12A、圖12B、圖13A、圖13B、圖14A以及圖14B示出根據一些實施例的小晶片(chiplet)晶粒堆疊的形成中的中間階段的橫截面圖。
圖15至圖18示出根據一些實施例的整合式扇出型封裝體(integrated fan-out(InFO)package)的形成中的中間階段的橫截面圖。
圖19示出根據一些實施例的覆晶封裝體(flip chip package)。
圖20示出根據一些實施例的基底上晶圓上晶片封裝體(chip-on-wafer-on-substrate(CoWoS)package)。
圖21示出根據一些實施例的用於形成小晶片晶粒堆疊的製程流程。
圖22示出根據一些實施例的用於形成包含小晶片晶粒堆疊的整合式扇出型封裝體的製程流程。
以下揭露內容提供用以實施本揭露的不同特徵的許多不同實施例或實例。下文描述組件及配置的具體實例以簡化本揭露。當然，此等組件及配置僅為實例且不意欲為限制性的。舉例而言，在以下描述中，第一特徵在第二特徵上方或第二特徵上的形成可包含第一特徵及第二特徵直接接觸地形成的實施例，且亦可包含額外特徵可在第一特徵與第二特徵之間形成以使得第一特徵及第二特徵可不直接接觸的實施例。另外，本揭露可在各種實 例中重複附圖標號及/或字母。此重複是出於簡單及清楚的目的，且本身並不指示所論述的各種實施例及/或組態之間的關係。
另外，為易於描述，本文中可使用諸如「底層」、「在...下方」、「下部」、「上覆」、「上部」以及類似術語的空間相對術語來描述如諸圖中所說明的一個元件或特徵與另一元件或特徵的關係。除圖式中所描繪的定向以外，空間相對術語意欲涵蓋元件在使用或操作中的不同定向。裝置可以其他方式定向(旋轉90度或處於其他定向)，且本文中所使用的空間相對描述詞可同樣相應地進行解釋。
根據一些實施例，提供一種晶粒堆疊及形成晶粒堆疊的製程。隨著技術發展，至少部分地藉由使類似組件配合於較小空間中來減小元件晶粒的尺寸。多個元件晶粒可組合為一種封裝格式，因此具有不同功能態樣(例如處理器、記憶體、感測器、天線等)的封裝體一起實體上緊密結合為單個封裝體。一個此類封裝格式可被稱為小晶片。如本文中所使用，小晶片可理解為特定類型的晶粒堆疊，即為將各種元件晶粒的特定功能結合在一起的各種元件晶粒的封裝體。接著，所得小晶片的使用方式可與元件晶粒的使用方式大致相同。即使由本文中所描述的實施例實現的所得結構稱為小晶片，但應理解，實施例可適用於任何晶粒堆疊。
由於先進技術節點中元件晶粒的小型化，使用此類元件晶粒(或來自不同技術節點的元件晶粒的混合)形成小晶片需要加強對製造公差(manufacturing tolerance)的控制。本揭露的實施例利用前側平坦化技術來實現一組穿孔的小於3微米(micrometer)的總厚度變化。鑒於元件晶粒可安裝至中介體 (interposer)的前側，並接著薄化中介體的反向側以暴露一組矽穿孔，實施例替代地翻轉中介體，薄化中介體以暴露矽穿孔，且接著將元件晶粒安裝至中介體的背面(現為前面)。藉由此方法，可實現小於3微米的總厚度變化。本文中所論述的實施例用於提供使得能夠製備或使用本揭露的主題的實例，且本領域中具有通常知識者將易於理解在屬於不同實施例的所設想範疇內的情況下可進行的修改。貫穿各圖及說明性實施例，相同附圖標號用以指明相同元件。儘管方法實施例可論述為以特定次序執行，但其他方法實施例可以任何邏輯次序執行。
圖1至圖11、圖12A、圖12B、圖13A、圖13B、圖14A以及圖14B示出根據本揭露的一些實施例的小晶片晶粒堆疊的形成中的中間階段的橫截面圖。對應製程示意性地反映於如圖21中所繪示的製程流程800中。
圖1示出晶圓120的橫截面圖。晶圓120可於其中包含多個元件晶粒122，其中示出一連串三個元件晶粒122作為實例。多個元件晶粒122可具有相同的設計。根據本揭露的一些實施例，晶圓120為中介體式晶圓(interposer wafer)，且元件晶粒122中的每一者為中介體。元件晶粒(或中介體式元件晶粒)122可包含視情況選用的主動元件及/或被動元件，其示出為積體電路元件126。為簡單起見，在其他圖中省略積體電路元件126的視圖。
根據一些實施例，元件晶粒122為邏輯晶粒，其可為專用積體電路(Application Specific Integrated Circuit；ASIC)晶粒、現場可程式化閘陣列(Field Programmable Gate Array；FPGA)晶粒或類似物。舉例而言，元件晶粒122可為中央處理單元(Central Processing Unit；CPU)晶粒、圖形處理單元(Graphic Processing Unit；GPU)晶粒或類似物。
根據本揭露的一些實施例，元件晶粒122包含半導體基底124。半導體基底124可由結晶矽、結晶鍺、矽鍺或III-V族化合物半導體形成，所述III-V族化合物半導體諸如GaN、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP、GaInAsP或類似物。半導體基底124亦可為塊狀半導體基底(bulk semiconductor substrate)或絕緣層上有半導體(Semiconductor-On-Insulator；SOI)基底。多個淺溝渠隔離(Shallow Trench Isolation；STI)區(圖中未繪示)可形成於半導體基底124中，以隔離半導體基底124中的多個主動區。
多個穿孔(有時稱為矽穿孔或半導體穿孔)125形成為延伸至半導體基底124中，其中穿孔125用於使元件晶粒122的相對兩側上的多個特徵電性互連。穿孔125電連接至上覆接合墊132。
根據本揭露的一些實施例，積體電路元件126可包含互補金屬氧化物半導體(Complementary Metal-Oxide Semiconductor；CMOS)電晶體、電阻器、電容器、二極體以及類似物。所述多個積體電路元件126中的一些可形成在半導體基底124的頂部表面處。本文中並未示出積體電路元件126的細節。
內連線結構128形成在半導體基底124上方。根據一些實施例，內連線結構128包含處於半導體基底124上方且填充多個積體電路元件126中的電晶體(圖中未繪示)的閘極堆疊之間的空間的層間介電質(Inter-Layer Dielectric；ILD)128a。根據一 些實施例，層間介電質128a由磷矽酸鹽玻璃(Phospho Silicate Glass；PSG)、硼矽酸鹽玻璃(Boro Silicate Glass；BSG)、硼摻雜磷矽酸鹽玻璃(Boron-Doped Phospho Silicate Glass；BPSG)、氟摻雜矽酸鹽玻璃(Fluorine-Doped Silicate Glass；FSG)、氧化矽或類似物形成。根據本揭露的一些實施例，使用沈積方法形成層間介電質，所述沈積方法諸如電漿增強型化學氣相沈積(Plasma-Enhanced Chemical Vapor Deposition；PECVD)、低壓化學氣相沈積(Low Pressure Chemical Vapor Deposition；LPCVD)、旋塗式塗佈、可流動化學氣相沈積(Flowable Chemical Vapor Deposition；FCVD)或類似方法。
多個接觸插塞(contact plug)128b形成在層間介電質128a中，且用於將積體電路元件126及穿孔125電連接至上覆的多個金屬線及多個通孔。根據本揭露的一些實施例，接觸插塞128b由選自鎢、鋁、銅、鈦、鉭、氮化鈦、氮化鉭、其合金及/或其多層的導電材料形成。接觸插塞128b的形成可包含在層間介電質128a中形成多個接觸開口，將導電材料填充至接觸開口中，以及執行平坦化製程(諸如化學機械拋光(Chemical Mechanical Polish；CMP)製程或機械研磨製程)，以使接觸插塞128b的頂部表面與層間介電質128a的頂部表面齊平。
內連線結構128可更包含層間介電質128a及接觸插塞128b上方的多個介電層。多個金屬線128c及多個通孔128d形成在所述多個介電層(亦稱為金屬間介電質(Inter-Metal Dielectric；IMD))中。處於同一層級處的多個金屬線在下文中統稱為金屬層。根據本揭露的一些實施例，內連線結構128包含多個金屬層， 每一金屬層包含處於同一層級的多個金屬線128c。相鄰金屬層中的金屬線128c經由通孔128d互連。金屬線128c及通孔128d可由銅或銅合金形成，且其亦可由其他金屬形成。根據本揭露的一些實施例，金屬間介電質由低k介電材料形成。舉例而言，低k介電材料的介電常數(k值)可小於約3.0。介電層可包括含碳低k介電材料、氫倍半氧矽烷(Hydrogen SilsesQuioxane；HSQ)、甲基倍半氧矽烷(MethylSilsesQuioxane；MSQ)或類似物。根據本揭露的一些實施例，介電層的形成包含沈積含致孔劑的介電材料，且接著執行固化製程以向外驅動致孔劑，且因此剩餘的介電層為多孔的。
頂部金屬層131形成在內連線結構128上方。根據一些實施例，使用與金屬線128c的形成中所使用的材料及製程類似的材料及製程來形成頂部金屬層131。表面介電層130形成在內連線結構128及頂部金屬層131上方。根據一些實施例，表面介電層130由聚合物形成，所述聚合物可包含聚苯并噁唑(PBO)、聚醯亞胺、苯并環丁烯(BCB)或類似物。
多個接合墊132形成在元件晶粒122的頂部表面上以及頂部金屬層131上。相應製程被示出為如圖21中所繪示的製程流程800中的製程802。根據一些實施例，接合墊132電連接且訊號連接至積體電路元件126(若使用)，且電連接且訊號連接至穿孔125。根據一些實施例，接合墊132具有橫向尺寸W1及間距P1的微凸塊。橫向尺寸W1可處於16微米與30微米之間，且間距P1可處於19微米與36微米之間，但涵蓋其他尺寸且可使用其他尺寸。
多個焊料區134可形成於接合墊132的頂部上。相應製程亦被示出為如圖21中所繪示的製程流程800中的製程802。接合墊132及焊料區134的形成可包含沈積金屬晶種層，形成且圖案化鍍覆罩幕(例如：光阻)，以及在經圖案化鍍覆罩幕中的多個開口中鍍覆接合墊132及焊料區134。金屬晶種層可包含銅層，或鈦層及在鈦層上方的銅層。經鍍覆的接合墊132可包含銅、鎳、鈀或其複合層。接著移除經圖案化鍍覆罩幕，接著執行蝕刻製程以移除先前由鍍覆罩幕覆蓋的金屬晶種層的部分。接著執行回焊製程以回焊焊料區134。
進一步參考圖1，例如藉由使探針卡(probe card)141的多個引腳與焊料區134接觸來探測(probe)元件晶粒122。相應製程被示出為如圖21中所繪示的製程流程800中的製程804。探針卡141連接至探測元件(圖中未繪示)，所述探測元件電連接至組態成判別元件晶粒122的連接及功能性的工具(圖中未繪示)。經由元件晶粒122的探測，可判別元件晶粒122中的哪些為有缺陷的晶粒，且元件晶粒122中的哪些為運作正常的(良好)晶粒。焊料區134比下覆的接合墊132更軟，因此探針卡141中的引腳可更佳地電連接至接合墊132。在一些實施例中，可省略焊料區134。
參考圖2，根據一些實施例，在探測製程之後，經由蝕刻移除焊料區134。相應製程被示出為如圖21中所繪示的製程流程800中的製程806。根據其他實施例，此時焊料區134未經蝕刻，且保留在最終封裝體中或可在製程中的稍後階段移除。在後續圖式中，並未示出焊料區134。然而，應瞭解，在此等圖式中，焊料 區134可仍然存在(或可不存在)。
介電層136沈積於接合墊132上方且填充接合墊132之間的空間。相應製程被示出為如圖21中所繪示的製程流程800中的製程806。可使用任何適當材料及沈積技術沈積介電層136。在一些實施例中，介電層136為聚合物層。可藉由在晶圓120上方沈積包括溶解於溶劑中的溶質(例如聚合物)的溶液來形成介電層136，其中聚合物包括聚醯亞胺(PI)、聚苯并噁唑(PBO)、聚丙烯酸酯(polyacrylate)、類似物或其組合，且溶劑包括N-甲基-2-吡咯啶酮(NMP)、γ-丁內酯(GBL)、乳酸乙酯(EL)、四氫呋喃(THF)、二甲基甲醯胺(DMF)、類似物或其組合。諸如旋塗的適合沈積方法可用於沈積介電層136。
在一些實施例中，在介電層136沈積於晶圓120上方以及多個晶粒連接件(接合墊132)上方之後，遠離晶圓120的介電層136(例如此處理階段的溶液)的上部表面為平坦的。接著，執行固化製程以固化介電層136。固化製程可在約170℃與約350℃之間的溫度下執行約1小時與約4小時之間的持續時間。在固化之後，收縮可導致介電層136變為不平坦(例如不均勻、非平面、非齊平、彎曲或波狀)表面。舉例而言，由於介電層136的處於接合墊132上方(例如正上方)的第一部分的厚度小於介電層136的處於兩個接合墊132之間(例如表面介電層130正上方或側向鄰近於接合墊132)的第二部分的厚度，故在固化之後介電層136的第一部分比介電層136的第二部分收縮更小。因此，在固化製程之後，介電層136的上部表面可為波狀的，在對應於具有接合墊132的底層圖案的凹形表面與凸形表面之間交替。
在圖3中，使用例如研磨或化學機械拋光(CMP)製程來平坦化介電層136的上部表面，藉此使介電層136的上部表面變得平坦。相應製程被示出為如圖21中所繪示的製程流程800中的製程808。
在半導體製造中，總厚度變化(total thickness variation；TTV)可用以表徵(characterize)膜層或元件的厚度的變化。在所示出的實施例中，由於假定晶圓120的半導體基底124的底部表面相對平坦，晶圓120(包含視情況選用的內連線結構128及接合墊132)的總厚度變化最終藉由介電層136的上部表面的不均勻性判定。在所示出的實施例中，介電層136的總厚度變化可計算作為安置在介電層136之中間(mid-way)的平面的偏差，所述中間的平面位在介電層136的上部表面的最高點與介電層136的上部表面的最低點之間。換言之，在一些實施例中，介電層136的上部表面的最高點與最低點之間的距離等於晶圓120的總厚度變化的值的兩倍。
在介電層136的平坦化製程之後，晶圓120的總厚度變化小於3微米，例如0微米與3微米之間的非零值。
在圖4中，晶圓120翻轉且安裝至載體基底148。相應製程被示出為如圖21中所繪示的製程流程800中的製程810。晶圓120的背側因此變為晶圓120的前側。載體基底148可為玻璃載體基底、陶瓷載體基底或類似載體基底。載體基底148可為晶圓，使得多個封裝體可同時形成在載體基底148上。
晶圓120與載體基底148之間可使用釋放層(圖中未繪示)。釋放層可由聚合物類材料形成，所述聚合物類材料可在後續 步驟中與載體基底148一起移除。在一些實施例中，介電層136可用作釋放層。在一些實施例中，釋放層為在加熱時損失其黏著特性的環氧樹脂類熱釋放材料，諸如光-熱轉換(light-to-heat-conversion；LTHC)釋放塗層。在其他實施例中，釋放層可為在暴露於UV光時損失其黏著特性的紫外線(ultra-violet；UV)膠。釋放層可為液體形式施配且被固化，可為疊層於載體基底148上的疊層膜(laminate film)，或可為類似物。可使釋放層的頂部表面平整化，且所述頂部表面可具有高度平面性。
接著，在圖5中，對晶圓120的前側執行薄化製程。相應製程被示出為如圖21中所繪示的製程流程800中的製程812。可利用研磨製程來執行薄化製程，所述研磨製程移除晶圓120的半導體基底124的部分以暴露穿孔125。藉由先執行穿孔125的突起(protrusion)，晶圓120的總厚度變化(TTV)減小。由於晶圓120的表面上的沈積速率及蝕刻速率不同，故在半導體基底124上方添加的每一結構將導致晶圓120的總厚度變化自零變大。可利用平坦化製程來使上部表面變平，然而，諸如整個晶圓120上的表面愈寬，由平坦化引起的高度變化愈大。
在先進技術節點中，薄化之後的穿孔125縮短，小於15微米，諸如介於約3微米與約10微米之間。透過在製程的早期(在任何晶粒安裝在晶圓120上之前)執行穿孔125的突起，因由於避免了將藉由元件晶粒的安裝引入的厚度變化，故總厚度變化減小。由於薄化製程另外可導致縮短的穿孔125中的故障，故具有減小的總厚度變化為有利的。
由於晶圓120的翻轉，穿孔125可由上至下為自較窄第一寬度至較寬第二寬度的錐形。
在圖6中，在薄化製程之後，視情況選用的內連線結構138可形成在穿孔125上方。相應製程被示出為如圖21中所繪示的製程流程800中的製程814。可使用與內連線結構128的形成類似的製程及材料形成內連線結構138。多個凸塊下金屬化物(under bump metallization；UBM)140被形成以用作為前側內連線結構138的外部連接。凸塊下金屬化物140具有在內連線結構138的最上部介電層的主表面上且沿著其延伸的凸塊部分，且具有延伸穿過內連線結構138的最上部介電層以實體耦接且電耦接內連線結構138的金屬層的通孔部分。因此，凸塊下金屬化物140電耦接至穿孔125。凸塊下金屬化物140可由與內連線結構138的金屬線的材料相同的材料且使用與內連線結構138的金屬線的製程類似的製程形成。
多個導電連接件144可接著形成在凸塊下金屬化物140上。相應製程亦被示出為如圖21中所繪示的製程流程800中的製程814。導電連接件144可為球柵陣列(ball grid array；BGA)連接件、焊料球、金屬柱、受控塌陷晶片連接(controlled collapse chip connection；C4)凸塊、微凸塊、化學鍍鎳鈀浸金技術(electroless nickel-electroless palladium-immersion gold；ENEPIG)形成的凸塊，或類似物。導電連接件144可包含導電材料，諸如焊料、銅、鋁、金、鎳、銀、鈀、錫、類似導電材料或其組合。在一些實施例中，導電連接件144藉由經由蒸鍍、電鍍、列印、焊料轉移、植球或類似者初始地形成焊料層來形成。一旦焊料層已形成於結 構上，便可執行回焊以便將材料塑形成所要凸塊形狀。在另一實施例中，導電連接件144包括藉由濺鍍、列印、電鍍、化學電鍍(electroless plating)、CVD或類似者形成的金屬柱(諸如銅柱)。金屬柱可不含焊料且具有實質上豎直(substantially vertical)的側壁。在一些實施例中，金屬頂蓋層(metal cap layer)形成在金屬柱的頂部上。金屬頂蓋層可包含鎳、錫、錫鉛、金、銀、鈀、銦、鎳鈀金、鎳金、類似物或其組合，且可由鍍覆製程形成。
在後續製程中，一或多個元件晶粒可附接至導電連接件144。
圖7示出根據一些實施例的晶圓中的積體電路晶粒150的橫截面圖。多個積體電路晶粒150將在後續處理中被封裝以形成積體電路封裝體或小晶片。積體電路晶粒150可為：邏輯晶粒(例如中央處理單元(CPU)、圖形處理單元(GPU)、系統晶片(system-on-a-chip；SoC)、應用程式處理器(application processor；AP)、微控制器等)；記憶體晶粒(例如動態隨機存取記憶體(dynamic random access memory；DRAM)晶粒、靜態隨機存取記憶體(static random access memory；SRAM)晶粒等)；功率管理晶粒(例如功率管理積體電路(power management integrated circuit；PMIC)晶粒)；射頻(radio frequency；RF)晶粒；感測器晶粒；微機電系統(micro-electro-mechanical-system；MEMS)晶粒；訊號處理晶粒(例如數位訊號處理(digital signal processing；DSP)晶粒)；前端晶粒(例如類比前端(analog front-end；AFE)晶粒)；類似物；或其組合。可使用與用於形成元件晶粒122相同的技術節點或不同的技術節點中的技術來形成 積體電路晶粒150。
積體電路晶粒150可形成於晶圓中，所述晶圓可包含在後續步驟中經單一化以形成多個積體電路晶粒的多個不同元件區域。積體電路晶粒150可根據可適用的製造製程來處理以形成積體電路。舉例而言，積體電路晶粒150包含半導體基底152(諸如經摻雜或未經摻雜的矽)，或是絕緣層上有半導體(SOI)基底的主動層。半導體基底152可包含其他半導體材料，諸如：鍺；化合物半導體，包含碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦及/或銻化銦；合金半導體，包含SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP及/或GaInAsP；或其組合。亦可使用其他基底，諸如多層基底(multi-layered substrate)或梯度基底(gradient substrate)。半導體基底152具有有時稱為前側的主動表面(例如，圖7中朝向上方的表面)及有時稱為背側的非主動表面(例如，圖7中朝向下方的表面)。
多個元件(由電晶體表示)154可形成在半導體基底152的前表面處。元件154可為主動元件(例如電晶體、二極體等)、電容器、電阻器等。層間介電質(ILD)156處於半導體基底152的前表面上方。層間介電質156包圍且可覆蓋元件154。層間介電質156可包含由諸如以下材料形成的一或多個介電層：磷矽酸鹽玻璃(PSG)、硼矽酸鹽玻璃(BSG)、硼摻雜磷矽酸鹽玻璃(BPSG)、未摻雜矽酸鹽玻璃(undoped Silicate Glass；USG)或類似物。
多個導電插塞158延伸穿過層間介電質156以電耦接且實體耦接元件154。舉例而言，當元件154為電晶體時，導電插塞158可耦接電晶體的閘極及源極/汲極區。導電插塞158可由鎢、 鈷、鎳、銅、銀、金、鋁、類似物或其組合形成。內連線結構160處於層間介電質156及導電插塞158上方。內連線結構160使元件154互連以形成積體電路。內連線結構160可藉由例如層間介電質156上的多個介電層中的多個金屬化圖案形成。金屬化圖案包含形成在一或多個低k介電層中的多個金屬線及多個通孔，所述金屬線及通孔在與上文關於內連線結構128所論述的製程類似的製程中以及使用與上文關於內連線結構128所論述的材料類似的材料形成。內連線結構160的金屬化圖案藉由導電插塞158電耦接至元件154。
積體電路晶粒150更包含多個襯墊(pad)162，諸如鋁襯墊，其進行外部連接。襯墊162處於積體電路晶粒150的主動側上，諸如處於內連線結構160中及/或其上。一或多個鈍化膜164處於積體電路晶粒150上，諸如處於內連線結構160及襯墊162的多個部分上。多個開口穿過鈍化膜164延伸至襯墊162。多個晶粒連接件166延伸穿過鈍化膜164中的開口且實體耦接且電耦接至襯墊162中的相應一者。其中，晶粒連接件166是例如由金屬(諸如銅)形成的導電柱。晶粒連接件166可藉由例如鍍覆或類似者形成。晶粒連接件166電耦接積體電路晶粒150的相應的積體電路。
多個導電連接件170形成在積體電路晶粒150的表面處。導電連接件170的形成製程及材料可與導電連接件144(圖6)的形成製程及材料類似。舉例而言，使用探針卡141'探測積體電路晶粒150，因此找到有缺陷的積體電路晶粒150，且判別已知良好晶粒(known-good-die；KGD)。對積體電路晶粒150中的每一 者執行探測。相應製程被示出為如圖21中所繪示的製程流程800中的製程816。
介電層168可能(或可能不)處於積體電路晶粒150的主動側上，諸如處於鈍化膜164及晶粒連接件166上。介電層168側向地(laterally)包封晶粒連接件166，且介電層168與積體電路晶粒150側向共端(laterally coterminous)。最初，介電層168可掩埋晶粒連接件166，使得介電層168的最頂部表面在晶粒連接件166的最頂部表面之上。在多個焊料區安置在晶粒連接件166上的一些實施例中，介電層168亦可掩埋焊料區。替代地，可在形成介電層168之前移除焊料區。
介電層168可為：聚合物，諸如PBO、聚醯亞胺、BCB或類似物；氮化物，諸如氮化矽或類似物；氧化物，諸如氧化矽、PSG、BSG、BPSG或類似物；類似物；或其組合。介電層168可例如藉由旋塗、疊層、化學氣相沈積(chemical vapor deposition；CVD)或類似者形成。在一些實施例中，在積體電路晶粒150的形成期間，晶粒連接件166經由介電層168暴露。在一些實施例中，晶粒連接件166保持掩埋且在用於封裝積體電路晶粒150的後續製程期間暴露。暴露晶粒連接件166可移除可能存在於晶粒連接件166上的任何焊料區。
在積體電路晶粒150的膜層、元件以及連接件的形成之後，可使用分割刀片(dicing blade)、雷射切割工具(laser cutting tool)或類似物來使積體電路晶粒150彼此單一化，藉此形成多個個別積體電路晶粒150。已知良好晶粒可分離且在後續製程中使用，而可能丟棄未通過測試的晶粒。
在一些實施例中，積體電路晶粒150為包含多個半導體基底152的堆疊元件。舉例而言，積體電路晶粒150可為記憶體元件，諸如混合記憶體立方體(hybrid memory cube；HMC)模組、高頻寬記憶體(high bandwidth memory；HBM)模組，或包含多個記憶體晶粒的類似物。在此類實施例中，積體電路晶粒150包含由多個基底穿孔(through-substrate via；TSV)互連的多個半導體基底152。半導體基底152中的每一者可能(或可能不)具有內連線結構160。
在圖8中，作為已知良好晶粒的積體電路晶粒150接合至晶圓120中的已知良好晶粒。相應製程被示出為如圖21中所繪示的製程流程800中的製程818。積體電路晶粒150為呈晶粒形式的離散晶粒，而元件晶粒122為呈晶圓形式的未鋸切晶圓120的部分。在一些實施例中，接合製程包含將焊劑(flux)施加至導電連接件144上，將積體電路晶粒150置放至元件晶粒122上，以及執行回焊製程，因此導電連接件144及導電連接件170熔融以形成多個焊料區172。在回焊製程之後，底部填充膠174可任選施配至積體電路晶粒150與相應的底層元件晶粒122之間的間隙中，且接著被固化。
在圖9中，可沈積包封體175以側向包封積體電路晶粒150，且可覆蓋積體電路晶粒150中的每一者的上部表面。相應製程被示出為如圖21中所繪示的製程流程800中的製程820。包封體175填充相鄰積體電路晶粒150之間的間隙。包封體175可為或可包括模製化合物、模製底部填充膠、環氧樹脂及/或樹脂，且可使用任何適合的製程沈積。在包封之後，包封體175的頂部表 面高於積體電路晶粒150的頂部表面。包封體175可包含一個層或多個層。
在圖10中，在包封製程之後，執行平坦化製程以減小包封體175的厚度且使包封體175的頂部表面水平化。相應製程亦被示出為如圖21中所繪示的製程流程800中的製程820。積體電路晶粒150的半導體基底152(圖7)的厚度亦可薄化。在平坦化製程之後，積體電路晶粒150的上部表面可與包封體175的上部表面齊平。由於穿孔125的厚度已減小，故包封體175的上部表面的平面性的誤差容差大於穿孔125仍需要薄化的情況下的誤差容差。舉例而言，包封體175的總厚度變化可大於300奈米。
在圖11中，具有嵌入式積體電路晶粒150的晶圓120翻轉且經由晶粒附接膜(die attach film；DAF)182(其為黏著膜)附接至框架185。舉例而言，藉由將光束(例如雷射光束)投射在釋放膜上來移除載體基底148，且光穿過透明載體基底148。相應製程被示出為如圖21中所繪示的製程流程800中的製程822。釋放膜因此分解，且晶圓120自載體基底148釋放。如圖11中所示出，在一些實施例中，多個開口可形成於介電層136中，藉此暴露接合墊132。之後，多個連接件180可形成於開口中。可使用與上文關於導電連接件144(圖6)所論述的材料及製程類似的材料及製程形成連接件180。在其他實施例中，可能不形成連接件180。
接著經由晶粒鋸切製程190執行單一化製程，因此經組合的元件晶粒122及積體電路晶粒150分離成多個封裝體195。相應製程被示出為如圖21中所繪示的製程流程800中的製程824。封裝體195可具有使用不同技術節點形成的多個不同部分。舉例 而言，可使用N5、N7等技術節點技術形成元件晶粒122，且可使用N3技術節點技術形成積體電路晶粒150。封裝體195亦可具有使用相同技術節點形成的多個不同部分。在清潔製程中移除晶粒附接膜182，從而自框架185移除封裝體195。所得結構繪示於圖12A及圖12B中。
在圖12A及圖12B中，示出根據一些實施例的封裝體195。圖12A為封裝體195的沿著圖12B的切線A-A的橫截面圖。圖12B為封裝體195的俯視圖。如圖12A及圖12B中所提及，封裝體195可包含用以形成小晶片的一個積體電路晶粒150。
在圖13A及圖13B中，示出根據其他實施例的封裝體195'。圖13A為封裝體195'的沿著圖13B的切線A-A的橫截面圖。圖13B為圖13A的封裝體195'的俯視圖。如圖13A及圖13B中所示出，封裝體195'與圖12A及圖12B的封裝體195類似，但可包含用以形成小晶片的兩個積體電路晶粒150。兩個積體電路晶粒150可具有相同功能或不同功能，且元件晶粒122可用以將一個積體電路晶粒150中的多個觸點連接至另一積體電路晶粒150。
在圖14A及圖14B中，示出根據其他實施例的封裝體195"。圖14A為封裝體195"的沿著圖14B的切線A-A的橫截面圖。圖14B為圖14A的封裝體195"的俯視圖。如圖14A及圖14B中所示出，封裝體195"與圖12A及圖12B的封裝體195類似，但可包含用以形成小晶片的其他倍數(在所示出的實施例中，四個)的積體電路晶粒150。各種積體電路晶粒150可具有相同功能或不同功能，或其組合。元件晶粒122可用以將一個積體電路晶粒150中的多個觸點連接至另一積體電路晶粒150。
圖15至圖18示出使用封裝體195、封裝體195'或封裝體195"作為整合式扇出型(InFO)封裝體的小晶片元件晶粒的InFO封裝體的形成的中間階段。為簡單起見，此等封裝體的任何變體將簡單地稱為封裝體195。對應製程示意性地反映於如圖22中所繪示的製程流程900中。
在圖15中，提供載體基底202，且釋放層204形成於載體基底202上。相應製程被示出為如圖22中所繪示的製程流程900中的製程902。載體基底202可為玻璃載體基底、陶瓷載體基底或類似載體基底。載體基底202可為晶圓，使得多個封裝體可同時形成在載體基底202上。
釋放層204可由聚合物類材料形成，所述聚合物類材料可與載體基底202一起自將在後續步驟中形成的上覆結構移除。在一些實施例中，釋放層204為在加熱時損失其黏著特性的環氧樹脂類熱釋放材料，諸如光-熱轉換(LTHC)釋放塗層。在其他實施例中，釋放層204可為在暴露於UV光下時損失其黏著特性的紫外線(UV)膠。釋放層204可以為液體形式施配且被固化，可以為疊層在載體基底202上的疊層膜，或可以為類似物。釋放層204的頂部表面可經平整化，且可具有高度平面性。
在圖15中，背側重佈線結構206可形成於釋放層204上。相應製程亦被示出為如圖22中所繪示的製程流程900中的製程902。在所繪示的實施例中，背側重佈線結構206包含介電層208、金屬化圖案210(有時稱為重佈線層或重佈線)以及介電層212。視情況選用背側重佈線結構206。在一些實施例中，不含金屬化圖案的介電層代替背側重佈線結構206形成於釋放層204上。
介電層208可形成於釋放層204上。介電層208的底部表面可與釋放層204的頂部表面接觸。在一些實施例中，介電層208由諸如聚苯并噁唑(PBO)、聚醯亞胺、苯并環丁烯(BCB)或類似物的聚合物形成。在其他實施例中，介電層208由以下形成：氮化物，諸如氮化矽；氧化物，諸如氧化矽、磷矽酸鹽玻璃(PSG)、硼矽酸鹽玻璃(BSG)、硼摻雜磷矽酸鹽玻璃(BPSG)或類似物；或類似物。介電層208可藉由諸如以下的任何可接受沈積製程形成：旋塗、CVD、疊層、類似製程或其組合。
金屬化圖案210可形成於介電層208上。作為形成金屬化圖案210的實例，晶種層形成在介電層208上方。在一些實施例中，晶種層為金屬層，其可為單層或包括由不同材料形成的多個子層的複合層。在一些實施例中，晶種層包括鈦層及在鈦層上方的銅層。可使用例如物理氣相沈積(physical vapor deposition；PVD)或類似者形成晶種層。光阻(圖中未繪示)接著形成於晶種層上且在所述晶種層上圖案化。光阻可藉由旋塗或類似者形成，且可暴露於光以用於圖案化。光阻的圖案對應於金屬化圖案210。圖案化形成穿過光阻的多個開口以暴露晶種層。導電材料在光阻的開口中以及晶種層的暴露部分上形成。導電材料可藉由諸如電鍍或化學電鍍的鍍覆或類似者形成。導電材料可包括金屬，比如銅、鈦、鎢、鋁或類似物。接著，移除光阻以及晶種層上未形成導電材料的部分。可藉由可接受灰化或剝離製程(諸如使用氧電漿或類似物)移除光阻。一旦移除光阻，便諸如藉由使用可接受蝕刻製程(諸如藉由濕式蝕刻或乾式蝕刻)來移除晶種層的被暴露出來的多個部分。晶種層及導電材料的其餘部分形成金屬 化圖案210。
介電層212可形成於金屬化圖案210及介電層208上。在一些實施例中，介電層212由可使用微影罩幕圖案化的聚合物形成，所述聚合物可為感光性材料，諸如PBO、聚醯亞胺、BCB或類似物。在其他實施例中，介電層212由以下形成：氮化物，諸如氮化矽；氧化物，諸如氧化矽、PSG、BSG、BPSG；或類似物。介電層212可藉由旋塗、疊層、CVD、類似者或其組合形成。介電層212接著經圖案化以形成暴露部分的金屬化圖案210的多個開口。圖案化可藉由可接受製程形成，諸如藉由在介電層212為感光性材料時將介電層212暴露於光或藉由使用例如非等向性蝕刻來進行蝕刻。若介電層212為感光性材料，則介電層212可在曝光之後顯影。
在一些實施例中，背側重佈線結構206可包含任何數目的介電層及金屬化圖案。若預定形成更多介電層及金屬化圖案，則可重複上文所論述的步驟及製程。金屬化圖案可包含一或多個導電元件。導電元件可在金屬化圖案的形成期間藉由在底層介電層的表面上方以及底層介電層的多個開口中形成晶種層及金屬化圖案的導電材料來形成，藉此互連且電耦接各種導電線。
多個穿孔216形成於背側重佈線結構206中的多個開口中，且延伸遠離背側重佈線結構206的最頂部介電層(例如介電層212)。作為形成穿孔216的實例，晶種層(圖中未繪示)形成在背側重佈線結構206上方，例如，形成於介電層212及藉由多個開口而暴露出來的金屬化圖案210的部分上。在一些實施例中，晶種層為金屬層，其可為單層或包括由不同材料形成的多個子層 的複合層。在特定實施例中，晶種層包括鈦層及在鈦層上方的銅層。可使用例如PVD或類似者形成晶種層。光阻形成於晶種層上且在所述晶種層上圖案化。光阻可藉由旋塗或類似者形成，且可暴露於光以用於圖案化。光阻的圖案對應於導電通孔。圖案化形成穿過光阻的多個開口以暴露出晶種層。導電材料在光阻的開口中以及晶種層的暴露部分上形成。導電材料可藉由諸如電鍍或化學電鍍的鍍覆或類似者形成。導電材料可包括金屬，比如銅、鈦、鎢、鋁或類似物。移除光阻以及晶種層上未形成導電材料的部分。可藉由可接受灰化或剝離製程，諸如使用氧電漿或類似物移除光阻。一旦移除光阻，便諸如藉由使用可接受蝕刻製程(諸如藉由濕式蝕刻或乾式蝕刻)來移除晶種層的暴露部分。晶種層及導電材料的其餘部分形成穿孔216。
多個封裝體(亦稱小晶片封裝體)195藉由黏著劑218黏著至介電層212。相應製程被示出為如圖22中所繪示的製程流程900中的製程904。黏著劑218處於封裝體195的背側上且將封裝體195黏著至背側重佈線結構206，例如黏著至介電層212。黏著劑218可為任何適合的黏著劑、環氧樹脂、晶粒附接膜(DAF)或類似物。黏著劑218可施加至封裝體195的背側，在不利用背側重佈線結構206的情況下可施加至載體基底202的表面，或可施加至背側重佈線結構206(若適用)的上部表面。舉例而言，在對晶圓120進行單一化以分離多個封裝體195(參看圖11)之前，黏著劑218可施加至封裝體195的背側。儘管針對每一封裝組件200(例如在對應於封裝組件200A的封裝區中)示出多個封裝體195中的一者，但應理解，可以任何組合來使用多個封裝體195、 封裝體195'或封裝體195"(參看例如圖18)。
接著，包封體220形成在各種組件上且圍繞各種組件。相應製程被示出為如圖22中所繪示的製程流程900中的製程906。在形成之後，包封體220包封穿孔216及封裝體195。包封體220可為模製化合物、環氧樹脂或類似物。包封體220可藉由壓縮模製、轉移模製或類似者施加，且可形成在載體基底202上方以使得穿孔216及/或封裝體195經掩埋或覆蓋。包封體220進一步形成在封裝體195之間的多個間隙區中。包封體220可以為液體形式或半液體形式施加且隨後被固化。包封體220側向包圍封裝體195，且其側向範圍(又稱橫向範圍(lateral extent)大於封裝體195中的各種特徵的側向範圍。
接著對包封體220執行平坦化製程，以暴露穿孔216及接合墊132(參看例如圖12A)。相應製程亦被示出為如圖22中所繪示的製程流程900中的製程906。平坦化製程亦可移除穿孔216、介電層136及/或接合墊132的材料直至接合墊132及穿孔216暴露為止。穿孔216、接合墊132、介電層136以及包封體220的頂部表面在平坦化製程之後在製程變化內實質上共面。平坦化製程可為例如化學機械拋光(CMP)、研磨製程或類似製程。在一些實施例中，例如在穿孔216及/或接合墊132已暴露的情況下，可省略平坦化。
接著，前側重佈線結構222形成在包封體220、穿孔216以及封裝體195上方。相應製程被示出為如圖22中所繪示的製程流程900中的製程908。前側重佈線結構222包含介電層224、介電層228、介電層232以及介電層236，以及金屬化圖案226、金 屬化圖案230以及金屬化圖案234。金屬化圖案亦可稱為重佈線層或重佈線。前側重佈線結構222繪示為具有三個金屬化圖案層的實例。更多或更少的介電層及金屬化圖案可形成於前側重佈線結構222中。可使用與上文關於背側重佈線結構206所論述的製程及材料類似的製程及材料來形成前側重佈線結構222。若預定形成更少介電層及金屬化圖案，則可省略或重複上文所論述的步驟及製程。
形成多個凸塊下金屬化物238以用於外部連接至前側重佈線結構222。相應製程被示出為如圖22中所繪示的製程流程900中的製程910。凸塊下金屬化物238具有處於介電層236的主表面上且沿著所述主表面延伸的凸塊部分，且具有延伸穿過介電層236以實體耦接且電耦接金屬化圖案234的通孔部分。因此，凸塊下金屬化物238電耦接至穿孔216及封裝體195。凸塊下金屬化物238可由與金屬化圖案226相同的材料形成。在一些實施例中，凸塊下金屬化物238具有與金屬化圖案226、金屬化圖案230以及金屬化圖案234不同的尺寸。
多個導電連接件250形成在凸塊下金屬化物238上。相應製程亦被示出為如圖22中所繪示的製程流程900中的製程910。導電連接件250可為球柵陣列(BGA)連接件、焊料球、金屬柱、受控塌陷晶片連接(C4)凸塊、微凸塊、化學鍍鎳鈀浸金技術(ENEPIG)形成的凸塊，或類似物。導電連接件250可包含導電材料，諸如焊料、銅、鋁、金、鎳、銀、鈀、錫、類似導電材料或其組合。在一些實施例中，導電連接件250藉由經由蒸鍍、電鍍、列印、焊料轉移、植球或類似者初始地形成焊料層來形成。 一旦焊料層已形成於結構上，便可執行回焊以便將材料塑形成所要凸塊形狀。在另一實施例中，導電連接件250包括藉由濺鍍、列印、電鍍、化學電鍍、CVD或類似者形成的金屬柱(諸如銅柱)。金屬柱可不含焊料且具有實質上豎直的側壁。在一些實施例中，金屬頂蓋層形成在金屬柱的頂部上。金屬頂蓋層可包含鎳、錫、錫鉛、金、銀、鈀、銦、鎳鈀金、鎳金、類似物或其組合，且可由鍍覆製程形成。
可在後續製程中單一化完成的整合式扇出型封裝組件200(諸如封裝組件200A及封裝組件200B)。所得的封裝組件200為整合式扇出型封裝體。在一些實施例中，額外封裝組件可在單一化之前或之後附接至封裝組件200。
在圖16中，執行載體基底剝離以自背側重佈線結構206(例如介電層208)分離(或「剝離」)載體基底202(圖15)。相應製程被示出為如圖22中所繪示的製程流程900中的製程912。根據一些實施例，剝離包含將諸如雷射光或UV光的光投射於釋放層204上，以使得釋放層204在光熱下分解且載體基底202可移除。上述結構接著經翻轉且置放於載帶255上。
為將第二封裝組件300附接至封裝組件200，首先，多個導電連接件252形成為延伸穿過介電層208以接觸金屬化圖案210，或在不具有背側重佈線結構206的實施例中，導電連接件252可接觸通孔216。第二封裝組件300耦接至封裝組件200。相應製程被示出為如圖22中所繪示的製程流程900中的製程914。第二封裝組件300中的一者於第一封裝區400A及第二封裝區400B中的每一者中經耦接，以在封裝組件200的每一區中形成積體電路 元件堆疊400。積體電路元件堆疊400為整合式扇出型疊層封裝結構(integrated InFO Package-on-Package(PoP)structure)。
第二封裝組件300包含例如基底302及耦接至基底302的一或多個堆疊晶粒310(例如堆疊晶粒310A及堆疊晶粒310B)。儘管示出一組堆疊晶粒310(例如堆疊晶粒310A及堆疊晶粒310B)，但在其他實施例中，多個堆疊晶粒310(各自具有一或多個堆疊晶粒)可並列安置為耦接至基底302的同一表面。基底302可由半導體材料製成，所述半導體材料諸如矽、鍺、金剛石或類似物。在一些實施例中，亦可使用化合物材料，諸如矽鍺、碳化矽、砷化鎵、砷化銦、磷化銦、碳化矽鍺、磷砷化鎵、磷化鎵銦、其組合以及類似物。另外，基底302可為絕緣層上有矽(silicon-on-insulator；SOI)基底。一般而言，SOI基底包含諸如磊晶矽、鍺、矽鍺、SOI、絕緣層上有矽鍺(silicon germanium on insulator；SGOI)或其組合的半導體材料的膜層。在一個替代實施例中，基底302是基於諸如玻璃纖維加固樹脂芯(fiberglass reinforced resin core)的絕緣芯(insulating core)。芯材料的一個實例為玻璃纖維樹脂，諸如FR4。芯材料的替代例包含雙順丁烯二醯亞胺三嗪(bismaleimide-triazine；BT)樹脂，或替代地，其他印刷電路板(PCB)材料或膜層。諸如味之素累積膜(Ajinomoto build-up film；ABF)的累積膜或其他疊層物可用於基底302。
基底302可包含主動元件及被動元件(圖中未繪示)。諸如電晶體、電容器、電阻器、其組合以及類似物的多種元件可用於產生第二封裝組件300的設計的結構性及功能要求。可使用任何適合方法形成所述元件。基底302亦可包含多個金屬化層(圖 中未繪示)及多個導通孔308。在一些實施例中，基底302實質上不含主動元件及被動元件。
基底302可具有用以耦接至堆疊晶粒310的處於基底302的第一側上的多個接合墊304，以及用以耦接至導電連接件252的處於基底302的第二側上的多個接合墊306，所述第二側與基底302的所述第一側相對。在所示出的實施例中，堆疊晶粒310藉由多個導線(wire bonds)312耦接至基底302，但可使用其他連接件，諸如導電凸塊。在一實施例中，堆疊晶粒310為堆疊記憶體晶粒。舉例而言，堆疊晶粒310可為諸如低功率(low-power；LP)雙倍資料速率(double data rate；DDR)記憶體模組的記憶體晶粒，諸如LPDDR1、LPDDR2、LPDDR3、LPDDR4或類似記憶體模組。
堆疊晶粒310及導線312可由模製材料314包封。模製材料314可例如使用壓縮模製來模製於堆疊晶粒310及導線312上。在一些實施例中，模製材料314為模製化合物、聚合物、環氧樹脂、氧化矽填充物材料、類似材料或其組合。可執行固化製程以固化模製材料314；固化製程可為熱固化、UV固化、類似固化或其組合。
在第二封裝組件300形成之後，第二封裝組件300藉助於導電連接件252、接合墊306以及背側重佈線結構206的金屬化圖案機械接合且電接合至封裝組件200。在一些實施例中，堆疊晶粒310可經由導線312、接合墊304及接合墊306、導通孔308、導電連接件252、背側重佈線結構206、穿孔216以及前側重佈線結構222來耦接至封裝體195。
在一些實施例中，底部填充膠(圖中未繪示)形成在封 裝組件200與第二封裝組件300之間，從而包圍導電連接件252。底部填充膠可減小應力且保護由導電連接件252的回焊產生的多個接合部。底部填充膠可在第二封裝組件300附接之後藉由毛細流動製程(capillary flow process)來形成，或可在第二封裝組件300附接之前藉由適合的沈積方法來形成。
藉由沿著例如第一封裝區400A與第二封裝區400B之間的切割道區鋸切來執行單一化製程。相應製程被示出為如圖22中所繪示的製程流程900中的製程916。所述鋸切將第一封裝區400A自第二封裝區400B單一化。所得的單一化積體電路元件堆疊400來自第一封裝區400A或第二封裝區400B中的一者。在一些實施例中，在第二封裝組件300耦接至封裝組件200之後執行單一化製程。在其他實施例中，在第二封裝組件300耦接至封裝組件200之前，諸如在剝離載體基底202且形成導電連接件252之後，執行單一化製程。
在圖17中，可接著使用導電連接件250將每一積體電路元件堆疊400安裝至封裝基底500，以形成3D封裝體600。相應製程亦被示出為如圖22中所繪示的製程流程900中的製程918。封裝基底500包含基底芯(substrate core)502及基底芯502上方的多個接合墊504。基底芯502可由半導體材料製成，所述半導體材料諸如矽、鍺、金剛石或類似物。替代地，亦可使用化合物材料，諸如矽鍺、碳化矽、砷化鎵、砷化銦、磷化銦、碳化矽鍺、磷砷化鎵、磷化鎵銦、其組合以及類似物。另外，基底芯502可為SOI基底。一般而言，SOI基底包含諸如磊晶矽、鍺、矽鍺、SOI、SGOI或其組合的半導體材料的膜層。基底芯502可為有機 基底。在一個替代實施例中，基底芯502是基於諸如玻璃纖維加固樹脂芯的絕緣芯。一個實例芯材料為玻璃纖維樹脂，諸如FR4。芯材料的替代例包含雙順丁烯二醯亞胺三嗪(BT)樹脂，或替代地，其他PCB材料或膜層。諸如ABF的累積膜或其他疊層物可用於基底芯502。
基底芯502可包含主動元件及被動元件(圖中未繪示)。諸如電晶體、電容器、電阻器、其組合以及類似物的多種元件可用於產生元件堆疊的設計的結構性及功能要求。可使用任何適合方法形成所述元件。基底芯502亦可包含重佈線結構510，其包含多個金屬化層及多個通孔，其中接合墊504實體耦接且/或電耦接至金屬化層及通孔。
在一些實施例中，回焊導電連接件250以將封裝組件200附接至接合墊504。導電連接件250將具有在基底芯502中包含金屬化層的封裝基底500電耦接且/或實體耦接至封裝組件200。在一些實施例中，阻焊劑506形成在基底芯502上。導電連接件250可安置於阻焊劑506中的多個開口中以電耦接且機械耦接至接合墊504。阻焊劑506可用以保護基底芯502的多個區域免受外部損害。
導電連接件250可在其被回焊之前在其上方形成有環氧樹脂焊劑(圖中未繪示)，其中所述環氧樹脂焊劑的環氧樹脂部分中的至少一些環氧樹脂部分在封裝組件200附接至封裝基底500之後被保留。此保留的環氧樹脂部分可充當底部填充膠以減小應力且保護由回焊導電連接件250產生的多個接合部。在一些實施例中，視情況選用的底部填充膠520可形成在封裝組件200與封 裝基底500之間且包圍導電連接件250。底部填充膠520可在附接封裝組件200之後藉由毛細流動製程形成，或可在附接封裝組件200之前藉由適合的沈積方法形成。
圖18示出使用整合式扇出型封裝組件200的3D封裝體600，其具有嵌入於其中的多個封裝體195。圖18的用於形成3D封裝體600的製程與上文關於圖15至圖17所描述的製程類似，並不重複所述製程。
圖19示出接合至基底700以形成覆晶封裝體600'的封裝體195。儘管封裝體195、封裝體195'或封裝體195"中的一者示出為接合至基底700，但應理解，可以任何組合來使用多個封裝體195、封裝體195'或封裝體195"。為簡單起見，封裝體195、封裝體195'或封裝體195"稱為封裝體195。封裝體195可藉由焊料或藉由接合墊132的直接金屬對金屬接合(direct metal-to-metal bonding)或藉由任何其他適合的製程與基底700接合。與底部填充膠520類似的視情況選用的底部填充膠720可形成為包圍接合墊132的多個接合部。
基底700可為任何適合的基底，且可與封裝基底500類似，其中相同附圖標號指明相同結構。重佈線結構510可包含用於接收(recieve)封裝體195的多個接觸墊706。基底700亦可包含安置在基底芯502的與重佈線結構510相對的側上的第二重佈線結構710。可使用與用於形成重佈線結構510的製程及材料類似的製程及材料形成第二重佈線結構710。基底芯502包含多個穿孔704，其將重佈線結構510電耦接至第二重佈線結構710。可藉由利用蝕刻或雷射鑽孔或另一適合製程在基底芯502中形成多個開 口且接著利用導電材料填充開口來形成穿孔704。障壁層材料亦可在沈積導電材料之前用於開口中以包圍開口中的導電材料。
基底700亦可包含耦接至第二重佈線結構710的多個接觸墊712。接觸墊712中的每一者亦可包含安置在其上的多個焊料球或焊料凸塊714，以在基底700的底部上形成球柵陣列。球柵陣列可用於覆晶接合。可藉由將焊料材料沈積在接觸墊712上以及回焊焊料材料來形成焊料凸塊714。
圖20示出接合至中介體750的封裝體195，所述中介體750接著接合至基底700，以形成基底上晶圓上晶片(chip on wafer on substrate；CoWoS)封裝體600"。儘管封裝體195、封裝體195'或封裝體195"中的一者示出為接合至中介體750，但應理解，可以任何組合來使用多個封裝體195、封裝體195'或封裝體195"。為簡單起見，封裝體195、封裝體195'或封裝體195"稱為封裝體195。封裝體195可藉由焊料或藉由接合墊132的直接金屬對金屬接合或藉由任何其他適合的製程與中介體750接合。與底部填充膠520類似的視情況選用的底部填充膠720可形成為包圍接合墊132的接合部。
中介體750包含基底芯755。基底芯755可為有機基底、陶瓷基底、矽基底或類似基底。基底芯755可由玻璃纖維、樹脂、填充物、其他材料及/或其組合形成。在一些實施例中，基底芯755包含嵌入於內部的一或多個被動組件(圖中未繪示)。在另一實施例中，基底芯755可包括其他材料或組件。
多個導通孔760延伸穿過基底芯755。在一些實施例中，導通孔760包括導電材料，諸如銅、銅合金或其他導體，且可包 含障壁層、內襯(liner)、晶種層及/或填充材料。導通孔760提供自基底芯755的一側至基底芯755的另一側的豎直(即垂直)電連接。舉例而言，導通孔760中的一些在基底芯755的一側處的多個導電特徵770與基底芯755的相對側處的多個導電特徵775之間電耦接。可使用例如鑽孔製程、微影技術、雷射製程或其他方法形成用於導通孔760的多個孔洞，且接著利用導電材料填充用於形成導通孔760的孔洞。
導電特徵775可為例如導電墊或凸塊下金屬。導電特徵770可為例如球柵陣列或其他適合的導電結構。中介體750亦可包含基底芯755的相對側上的重佈線結構780A及重佈線結構780B。重佈線結構780A及重佈線結構780B藉由導通孔760電耦接。重佈線結構780A及重佈線結構780B各自包含與上文關於圖15的背側重佈線結構206所論述的介電層及金屬化圖案類似的多個介電層及多個金屬化圖案。每一各別金屬化圖案具有在相應的介電層的主表面上且沿著所述主表面延伸的線部分，且具有延伸穿過相應的介電層的通孔部分。
所示出中介體750為中介體式晶圓的部分，其包含與所示出中介體750類似的多個部位(site)，以用於附接在晶粒鋸切製程中經單一化的封裝體195。在一些實施例中，封裝體195可接合至中介體式晶圓，所述中介體式晶圓接著單一化為封裝體195與中介體750的組合，所述中介體750接著接合至基底700。在其他實施例中，中介體式晶圓可首先單一化為中介體750，封裝體195接著接合至所述中介體750，其接著接合至基底700。在又其他實施例中，中介體750接合至基底700，且接著封裝體195接合 至中介體750。
在一些實施例中，基底700可包含與上文關於圖19所論述的特徵類似的特徵，其中相同附圖標號指明相同結構。其他實施例可省略穿孔704、第二重佈線結構710、接觸墊712或焊料凸塊714中的一者或多者，且可具有與上文關於圖18的封裝基底500所論述的特徵類似的特徵。與底部填充膠520類似的視情況選用的底部填充膠790可形成為包圍導電特徵770的多個接合部。
在上文所示出的實施例中，根據本揭露的一些實施例論述一些製程及特徵以形成三維(three-dimensional；3D)封裝體。亦可包含其他特徵及製程。舉例而言，可包含測試結構以輔助3D封裝體或3DIC元件的校驗測試。測試結構可包含例如形成於重佈線層中或基底上的測試墊，其允許3D封裝體或3DIC元件的測試、探針及/或探針卡的使用以及類似者。可對中間結構以及最末結構執行校驗測試。另外，本文中所揭露的結構及方法可結合包括對已知良好晶粒進行中間校驗的測試方法來使用，以提高良率且降低成本。
本揭露的實施例具有一些有利特徵。藉由在附接積體電路元件晶粒之前薄化基底穿孔，總厚度變化被減小。總厚度變化的減小導致更佳的良率，且因此，降低製造成本。小晶片元件封裝體可使用先進技術節點來形成且以與較不先進技術負載中的積體元件晶粒類似的方式使用。舉例而言，小晶片元件封裝體可用於InFO製程中，以在包含經由接合而堆疊的兩個或多於兩個晶粒的晶粒堆疊上形成內連線結構。因此，InFO內連線結構可取代習知封裝基底。小晶片元件封裝體亦可用以形成覆晶封裝體或基底 上晶圓上晶片封裝體。
一個實施例包括一種方法，所述方法包括在基底中形成一組穿孔，所述一組穿孔部分地穿過基底的厚度。所述方法亦包括在所述基底的第一側上在所述一組穿孔上方形成多個第一連接件。所述基底的所述第一側附接至載體，且所述基底經薄化以暴露所述一組穿孔。所述方法亦包括在所述基底的第二側上在所述一組穿孔上方形成多個第二連接件，所述第二側與所述第一側相對。所述方法亦包括將元件晶粒接合至所述多個第二連接件。將所述基底單一化為多個封裝體。在一實施例中，所述方法更包括在所述多個第一連接件上方形成介電層，其中將所述基底的所述第一側附接至所述載體包括將所述介電層附接至所述載體。在一實施例中，所述方法更包括在所述一組穿孔上方形成第一內連線，所述第一內連線夾置於所述一組穿孔與所述多個第二連接件之間。在一實施例中，所述方法更包括將多個封裝體中的第一封裝體安裝至另一載體；在所述第一封裝體上方形成重佈線結構；在所述重佈線結構上方形成多個第三連接件；以及將所述第一封裝體及所述重佈線結構單一化為整合式扇出型封裝體。在一實施例中，在將所述基底單一化為多個封裝體之後，所述多個封裝體中的每一者包括多個元件晶粒。在一實施例中，所述方法更包括：將所述多個封裝體中的第一封裝體安裝至另一基底，以形成覆晶封裝體。在一實施例中，所述方法更包括將所述多個封裝體中的第一封裝體安裝至中介體式晶圓；將所述中介體式晶圓接合至另一基底；以及將所述中介體式晶圓、所述另一基底以及所述第一封裝體單一化為基底上晶圓上晶片封裝體。
另一實施例包括一種方法，所述方法包括測試第一基底的第一組連接件，所述第一組連接件電耦接至第一組通孔結構。所述方法亦包括將所述第一基底的所述第一組連接件安裝至載體，以及薄化所述第一基底以暴露所述第一組通孔結構。所述方法亦包括將元件晶粒電耦接至所述第一組通孔結構。將所述第一基底單一化為多個封裝體。在一實施例中，所述第一組通孔結構逐漸變窄，愈接近於所述元件晶粒愈窄且愈遠離所述元件晶粒愈寬。在一實施例中，測試所述第一組連接件包括探測安置在所述第一組連接件上的多個焊料蓋，且所述方法更包括：自所述第一組連接件移除所述多個焊料蓋；以及在所述第一組連接件上方沈積介電材料，其中將所述第一組連接件安裝至所述載體包括將所述介電材料接合至所述載體。在一實施例中，所述方法更包括：將多個封裝體附接至另一載體；在所述多個封裝體上方形成第一重佈線層；在所述第一重佈線層上方形成多個第一連接件；以及單一化所述第一重佈線層、所述多個第一連接件以及所述多個封裝體，形成整合式扇出型封裝體。在一實施例中，整合式扇出型封裝體包括所述多個封裝體中的至少兩者。在一實施例中，所述方法更包括在基底的與球柵陣列相對的側上將所述多個封裝體中的第一封裝體附接至所述基底，以形成覆晶封裝體。在一實施例中，所述方法更包括：將所述多個封裝體中的第一封裝體附接至中介體式基底晶圓；將所述中介體式基底晶圓單一化為多個封裝組件；以及將所述多個封裝組件中的第一封裝組件附接至基底，以形成所述基底上晶圓上晶片封裝體。
另一實施例包括一種結構，所述結構包括第一材料層， 所述第一材料層包括第一組穿孔，所述第一組穿孔具有自上而下愈來愈寬的寬度。所述結構亦包括安置在所述第一材料層的第一側上方的第一組連接件。所述結構亦包括安置在所述第一材料層的第二側之下的第二組連接件。第一半導體元件耦接至所述第一組連接件。包封體側向包圍所述第一半導體元件。在一實施例中，所述結構更包括耦接至所述第一組連接件的一或多個額外半導體元件。在一實施例中，所述結構更包括：第一重佈線結構，耦接至所述第二組連接件，所述第一重佈線結構的側向範圍大於所述第一材料層的側向範圍；第二包封體，側向包圍所述第一材料層；以及第三組連接件，安置在所述第一重佈線結構的底面上。在一實施例中，所述結構更包括：第二重佈線結構，安置在所述第一半導體元件上方；第二組穿孔，所述第二組穿孔將所述第一重佈線結構耦接至所述第二重佈線結構；第二半導體元件，安置在所述第二重佈線結構上方且電耦接至所述第二重佈線結構；以及元件基底，實體耦接且電耦接至所述第三組連接件。在一實施例中，所述結構更包括：元件基底，耦接至所述第二組連接件，所述元件基底包括具有球柵陣列的覆晶封裝體。在一實施例中，所述結構更包括：中介體式基底，所述中介體式基底在所述中介體式基底的第一側處耦接至所述第二組連接件；以及元件基底，所述元件基底耦接至所述中介體式基底的第二側，所述中介體式基底的所述第二側與所述中介體式基底的所述第一側相對。
前文概述若干實施例的特徵，使得本領域的技術人員可更佳地理解本揭露的態樣。本領域的技術人員應理解，其可易於使用本揭露作為設計或修改用於實現本文中所引入的實施例的相 同目的及/或達成相同優點的其他方法及結構的基礎。本領域的技術人員亦應認識到，此類等效構造並不脫離本揭露的精神及範疇，且本領域的技術人員可在不脫離本揭露的精神及範疇的情況下在本文中作出各種改變、替代以及更改。
800:製程流程
802、804、806、808、810、812、814、816、818、820、822、824:製程

Claims (9)

  1. 一種半導體封裝體的製造方法，包括：在基底中形成一組穿孔，所述一組穿孔部分地穿過所述基底的厚度；在所述基底的第一側上在所述一組穿孔上方形成多個第一連接件；在所述多個第一連接件上方形成介電層；透過所述介電層附接至載體，將所述基底的所述第一側附接至所述載體；薄化所述基底以暴露出所述一組穿孔；在所述基底的第二側上在所述一組穿孔上方形成多個第二連接件，所述第二側與所述第一側相對；將元件晶粒接合至所述多個第二連接件，其中所述薄化是在將所述基底的所述第一側附接至所述載體之後且是在將所述元件晶粒接合至所述多個第二連接件之前；以及將所述基底單一化為多個封裝體。
  2. 如請求項1所述的製造方法，更包括：在所述一組穿孔上方形成第一內連線，所述第一內連線夾置於所述一組穿孔與所述多個第二連接件之間。
  3. 如請求項1所述的製造方法，更包括：將所述多個封裝體中的第一封裝體安裝至另一載體；在所述第一封裝體上方形成重佈線結構；在所述重佈線結構上方形成多個第三連接件；以及將所述第一封裝體及重佈線結構單一化為整合式扇出型封裝 體。
  4. 如請求項1所述的製造方法，更包括：將多個元件晶粒接合至所述多個第二連接件，其中在將所述基底單一化為多個封裝體之後，所述多個封裝體中的每一者包括多個元件晶粒。
  5. 如請求項1所述的製造方法，更包括：將所述多個封裝體中的第一封裝體安裝至另一基底，以形成覆晶封裝體。
  6. 如請求項1所述的製造方法，更包括：將所述多個封裝體中的第一封裝體安裝至中介體式晶圓；將所述中介體式晶圓接合至另一基底；以及將所述中介體式晶圓、所述另一基底以及所述第一封裝體單一化為基底上晶圓上晶片封裝體。
  7. 一種半導體封裝體的製造方法，包括：測試第一基底的第一組連接件，所述第一組連接件電耦接至第一組通孔結構；在所述多個第一組連接件上方形成介電層；透過所述介電層附接至載體，將所述第一基底的所述第一組連接件安裝至所述載體；薄化所述第一基底以暴露所述第一組通孔結構；將元件晶粒電耦接至所述第一組通孔結構，其中所述薄化是在將所述第一基底的所述第一組連接件安裝至所述載體之後且是在將所述元件晶粒電耦接至所述第一組通孔結構之前；以及將所述第一基底單一化為多個封裝體。
  8. 如請求項7所述的製造方法，其中測試所述第一組連接件包括探測安置在所述第一組連接件上的多個焊料蓋，所述方法更包括：自所述第一組連接件移除所述多個焊料蓋。
  9. 如請求項7所述的製造方法，更包括：將所述多個封裝體附接至另一載體；在所述多個封裝體上方形成第一重佈線層；在所述第一重佈線層上方形成多個第一連接件；以及單一化所述第一重佈線層、所述多個第一連接件以及所述多個封裝體，形成整合式扇出型封裝體。
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