CN113223970B - 半导体结构及其制造方法 - Google Patents

半导体结构及其制造方法 Download PDF

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Publication number
CN113223970B
CN113223970B CN202110434987.8A CN202110434987A CN113223970B CN 113223970 B CN113223970 B CN 113223970B CN 202110434987 A CN202110434987 A CN 202110434987A CN 113223970 B CN113223970 B CN 113223970B
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substrate
package
vias
packages
over
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CN113223970A (zh
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张进传
卢思维
余振华
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

方法包括：在衬底中形成通孔组，该组通孔部分地穿透衬底的厚度。第一连接件形成在衬底第一侧上的该通孔组上方。衬底的第一侧附接到载体。衬底从第二侧被减薄以暴露该通孔组。第二连接件形成在衬底第二侧上的通孔组上方。器件管芯接合到第二连接件。衬底被分割成多个封装件。本申请的实施例还涉及半导体结构及其制造方法。

Description

半导体结构及其制造方法
技术领域
本申请的实施例涉及半导体结构及其制造方法。
背景技术
由于各种电子组件(例如，晶体管、二极管、电阻器、电容器等)的集成密度的不断提高，半导体工业经历了快速的增长。在大多数情况下，迭代减小最小部件尺寸可提高集成密度，使得可以将更多组件集成到给定区域中。随着对缩小电子器件的需求的增长，对更小且更具创造性的半导体管芯封装技术的需求也随之出现。这种封装系统的示例是堆叠封装(PoP)技术。在PoP器件中，顶部半导体封装件堆叠在底部半导体封装件的顶部，以提供高集成水平的和组件密度。PoP技术通常能够在印刷电路板(PCB)上产生功能增强且占位面积小的半导体器件。
发明内容
本申请的一些实施例提供了一种制造半导体结构的方法，包括：在衬底中形成通孔组，所述通孔组部分地穿透所述衬底的厚度；在所述衬底的第一侧上方的所述通孔组上方形成第一连接件；将所述衬底的所述第一侧附接到载体上；减薄所述衬底以暴露所述通孔组；在所述衬底的第二侧上方的所述通孔组上方形成第二连接件，所述第二侧与所述第一侧相对；将器件管芯接合到所述第二连接件；以及将所述衬底分割成多个封装件。
本申请的另一些实施例提供了一种制造半导体结构的方法，包括：测试第一衬底的第一组连接件，所述第一组连接件电耦合到第一组通孔结构；将所述第一衬底的所述第一组连接件安装到载体上；减薄所述第一衬底以暴露所述第一组通孔结构；将器件管芯电耦合到所述第一组通孔结构；以及将所述第一衬底分割成多个封装件。
本申请的又一些实施例提供了一种半导体结构，包括：第一材料层，所述第一材料层包括第一组通孔，所述第一组通孔具有从顶部到底部扩展得更宽的宽度；第一组连接件，设置在所述第一材料层的第一侧上方；第二组连接件，设置在所述第一材料层的第二侧下方；第一半导体器件，耦合到所述第一组连接件；以及密封剂，横向围绕所述第一半导体器件。
附图说明
当结合附图阅读以下详细描述时，将更好地理解本发明的各个方面。应该注意，根据工业中的标准做法，各种部件未按比例绘制。实际上，为论述清楚，各部件的尺寸可任意放大或缩小。
图1至图11、图12A、图12B、图13A、图13B、图14A和图14B示出了根据一些实施例的小芯片管芯堆叠件形成工艺中的中间阶段的截面图。
图15至图18示出了根据一些实施例的集成扇出封装件形成工艺中的中间阶段的截面图。
图19示出了根据一些实施例的倒装芯片封装件。
图20示出了根据一些实施例的衬底上晶圆上芯片(CoWoS)封装件。
图21示出了根据一些实施例的用于形成小芯片管芯堆叠件的工艺流程。
图22示出了根据一些实施例的用于形成包括小芯片管芯堆叠件的集成扇出封装件的工艺流程。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同部件的多个不同实施例或示例。以下描述了组件和布置的具体示例以简化本发明。当然，这些仅仅是示例，而不旨在限制本发明。例如，在以下描述中，在第二部件上方或者上形成第一部件可以是第一部件和第二部件直接触而形成，并且也可以是包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接触。此外，本发明可在各个示例中重复参考标号和/或字符。这种重复是为了简化和清楚的目的，并且其本身不指示所讨论的各个实施例和/或结构之间的关系。
而且，为了便于描述，在此可以使用诸如“位于…之下”、“在…下方”、“下部”、“位于…之上”、“上部”等空间相对术语，以描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。空间相对术语旨在包含除了附图所示的方向之外的使用或操作中的器件的不同方向。装置可以以其他方式定向(旋转90度或在其他方位上)，而本文使用的空间相对描述符可以同样地作出相应的解释。
根据一些实施例，提供了管芯堆叠件和形成管芯堆叠件的工艺。随着技术的发展，通过将相似的组件装配到更小的空间中，至少部分地减小了器件管芯的尺寸。器件管芯可以组合成封装格式，使得封装件的不同功能方面(例如，处理器、存储器、传感器、天线等)在物理上紧密接合在单个封装件中。这样的封装格式可以被称为小芯片。如本文所使用的，小芯片可以被理解为特定类型的管芯堆叠件，是将各种器件管芯的特定功能集合在一起的各种器件管芯的封装件。然后可以通过与使用器件管芯几乎相同的方式来使用所得的小芯片。即使由这里描述的实施例带来的最终结构被称为小芯片，应当理解，实施例可以适用于任何管芯堆叠件。
由于先进技术节点中器件管芯的尺寸缩小，使用这种器件管芯(或来自不同技术节点的器件管芯的混合)形成小芯片需要对制造公差进行越来越多的控制。本发明的实施例利用正面平坦化技术来实现总厚度差异小于3μm的通孔组。尽管器件管芯可以被安装到中介层的正面，然后中介层的反面被减薄以暴露硅通孔组，但是实施例将中介层翻转，减薄中介层以暴露硅通孔，然后将器件管芯安装到中介层的背面(现在是正面)。通过该工艺，可以实现小于3μm的总厚度差异。本文所讨论的实施例是为了提供能够实现或使用本发明的主题的示例，并且本领域普通技术人员将容易理解在不同实施例的预期范围内可以进行的修改。在各个视图和说明性实施例中，相同的参考标号用于表示相同的组件。虽然在讨论中，方法实施例可以按特定顺序执行，但是其他方法实施例可以按任何逻辑顺序执行。
图1至图11、图12A、图12B、图13A、图13B、图14A和图14B示出了根据本发明的一些实施例的小芯片管芯堆叠件形成工艺中的中间阶段的截面图。相应的工艺示意性地反映在如图21所示的工艺流程800中。
图1示出了晶圆120的截面图。晶圆120中可以包括多个器件管芯122，其中作为示例示出了三个器件管芯122的系列。多个器件管芯122可以具有相同的设计。根据本发明的一些实施例，晶圆120是中介层晶圆，并且每个器件管芯122是中介层。中介层器件管芯122可以包括可选的有源和/或无源器件，其被示为集成电路器件126。为简单起见，在其他图中省略了集成电路器件126的视图。
根据一些实施例，器件管芯122是逻辑管芯，其可以是专用集成电路(ASIC)管芯、现场可编程门阵列(FPGA)管芯等。例如，器件管芯122可以是中央处理单元(CPU)管芯、图形处理单元(GPU)管芯等。
根据本发明的一些实施例，器件管芯122包括半导体衬底124。半导体衬底124可以由晶体硅、晶体锗、硅锗或诸如GaN、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP、GaInAsP等III-V族化合物半导体形成。半导体衬底124还可以是体半导体衬底或绝缘体上半导体(SOI)衬底。可以在半导体衬底124上形成浅槽隔离(STI)区(未示出)，以隔离半导体衬底124上的有源区域。
通孔(有时称为硅通孔或半导体通孔)125被形成为延伸到半导体衬底24中，其中，通孔125用于与器件管芯122的相对侧上的部件进行电互耦合。通孔125电连接到上方的接合焊盘132。
根据本发明的一些实施例，集成电路器件126可以包括互补金属氧化物半导体(CMOS)晶体管、电阻器、电容器、二极管等。一些集成电路器件126可以形成在半导体衬底124的顶面处。本文未示出集成电路器件126的细节。
互连结构128形成在半导体衬底124上方。根据一些实施例，互连结构128包括半导体衬底124上方的层间电介质(ILD)128a，并且填充集成电路器件126中的晶体管(未示出)的栅极堆叠件之间的空间。根据一些实施例，ILD 128a由磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、掺硼磷硅酸盐玻璃(BPSG)、掺氟硅酸盐玻璃(FSG)、氧化硅等形成。根据本发明的一些实施例，使用沉积方法形成层间介电层，例如等离子体增强化学气相沉积(PECVD)、低压化学气相沉积(LPCVD)、旋涂、可流动化学气相沉积(FCVD)等。
接触插塞128b形成在ILD中，并且用于将集成电路器件126和通孔125电连接到上方的金属线和通孔。根据本发明的一些实施例，接触插塞由选自钨、铝、铜、钛、钽、氮化钛、氮化钽及其合金和/或其多层的导电材料形成。接触插塞的形成可以包括在ILD中形成接触开口，将导电材料填充到接触开口中，并且执行平坦化工艺(例如化学机械抛光(CMP)工艺或机械研磨工艺)以使接触插塞的顶面与ILD的顶面齐平。
互连结构128还可以包括在ILD和接触插塞上方的多个介电层。金属线128c和通孔128d形成在介电层(也称为金属间电介质(IMD))中。在下文中将在同一水平面上的金属线统称为金属层。根据本发明的一些实施例，互连结构128包括多个金属层，每个金属层包括处于相同水平面上的多个金属线128c。相邻金属层中的金属线128c通过通孔128d进行互连。金属线128c和通孔128d可以由铜或铜合金形成，并且也可以由其他金属形成。根据本发明的一些实施例，IMD由低k介电材料形成。例如，低k介电材料的介电常数(k值)可以小于约3.0。介电层可以包括含碳的低k介电材料、氢硅倍半氧烷(HSQ)、甲基硅倍半氧烷(MSQ)等。根据本发明的一些实施例，介电层的形成包括沉积含成孔剂的介电材料，然后执行固化工艺以驱除成孔剂，因此保留的介电层是多孔的。
顶部金属层131形成在互连结构128上方。根据一些实施例，使用与形成金属线128c中所使用的材料和工艺相似的材料和工艺来形成顶部金属层131。表面介电层130形成在互连结构128和顶部金属层131上方。根据一些实施例，表面介电层130由聚合物形成，该聚合物可以包括聚苯并噁唑(PBO)、聚酰亚胺、苯并环丁烯(BCB)等。
接合焊盘132形成在器件管芯122的顶面上和顶部金属层131上。在图21所示的工艺流程800中，相应工艺被示出为工艺802。根据一些实施例，接合焊盘132电连接并且信号连接到集成电路器件126(如果使用)和通孔125。根据一些实施例，接合焊盘132是具有横向尺寸W1和间距P1的微凸块。W1可能在16μm至30μm之间，而P1可能在19μm至36μm之间，但是也可以考虑和使用其他尺寸。
焊料区域134可以形成在接合焊盘132的顶部。在如图21所示的工艺流程800中，相应的工艺也被示为工艺802。接合焊盘132和焊料区域134的形成可以包括沉积金属晶种层，形成和图案化诸如光刻胶的镀掩模，以及在图案化的镀掩模的开口中镀接合焊盘132和焊料区域134。金属晶种层可以包括铜层或钛层以及在钛层上方的铜层。电镀接合焊盘132可包括铜、镍、钯或其复合层。然后去除图案化的镀掩模，接着进行蚀刻工艺以去除先前被镀掩模覆盖的金属晶种层的部分。然后执行回流工艺以回流料区域134。
进一步参考图1，例如，通过将探针卡141的引脚与焊料区域134接触来探测器件管芯122。在图21所示的工艺流程800中，相应工艺被示出为工艺804。探针卡141连接到探测器件(未示出)，该探测器件电连接到被配置为确定器件管芯122的连接和功能的工具(未示出)。通过探测器件管芯122，可以确定器件管芯122中的哪些是有缺陷的管芯，以及器件管芯122中的哪些是起作用的(好的)管芯。焊料区域134比下面的接合焊盘132软，使得探针卡141中的引脚可以更好地电连接到接合焊盘132。在一些实施例中，可以省略焊料区域134。
参考图2，根据一些实施例，在探测工艺之后，通过蚀刻去除焊料区域134。在图21所示的工艺流程800中，相应工艺被示出为工艺806。根据其他实施例，此时不蚀刻焊料区域134，并且焊料区域134留在最终封装件中，或者可以在工艺的稍后阶段去除。在随后的附图中，未示出焊料区域134。然而，应当理解，在这些图中，焊料区域134可能仍然存在(或者可能不存在)。
介电层136沉积在接合焊盘132上方并且填充接合焊盘132之间的空间。如图21所示，在工艺流程800中，相应的工艺被示为工艺806。可以使用任何适当的材料和沉积技术来沉积介电层136。在一些实施例中，介电层136是聚合物层。介电层136可以通过在晶圆120上方沉积包含溶解在溶剂中的溶质(例如，聚合物)的溶液来形成，其中，聚合物包括聚酰亚胺(PI)、聚苯并噁唑(PBO)、聚丙烯酸酯等，或其组合，并且溶剂包括N-甲基-2-吡咯烷酮(NMP)、γ-丁内酯(GBL)、乳酸乙酯(EL)、四氢呋喃(THF)、二甲基甲酰胺(DMF)等，或其组合。可以使用诸如旋涂的合适沉积方法来沉积介电层136。
在一些实施例中，在将介电层136沉积在晶圆120上方和管芯连接件接合焊盘132上方之后，介电层136的远离晶圆120的上表面(例如，在该处理阶段的溶液)是平坦的。。接下来，执行固化工艺以固化介电层136。固化工艺可在约170℃至约350℃的温度下进行，持续约1小时至约4小时。固化后，收缩会导致介电层136变成非平坦(例如，不平坦、非平面、非水平、弯曲或波浪形)表面。例如，由于接合焊盘132上方(例如，正上方)的介电层136的第一部分的厚度小于两个接合焊盘132之间的介电层136的第二部分的厚度(例如，在表面介电层130正上方，或者横向邻近接合焊盘132)，因此固化后介电层136的第一部分的收缩小于介电层136的第二部分的收缩。结果，在固化工艺之后，介电层136的上表面可以是波浪形的，在对应于接合焊盘132的下层图案的凹面和凸面之间交替。
在图3中，使用例如研磨或化学机械抛光(CMP)工艺来平坦化介电层136的上表面，从而使介电层136的上表面变得平坦。如图21所示，相应的工艺在工艺流程800中被示为工艺808。
在半导体制造中，总厚度差异(TTV)可用于表征层或器件厚度的差异。在图示的实施例中，晶圆120(包括可选的互连结构128和接合焊盘132)的TTV最终由介电层136的上表面的不平坦度决定，因为晶圆120的半导体衬底124的底面被假定为相对平坦。在图示的实施例中，介电层136的TTV可以被计算为介电层136的上表面相对于设置在介电层136的最高点和介电层136的上表面的最低点之间的中间的平面的偏差。换句话说，在一些实施例中，介电层136的上表面的最高点和最低点之间的距离等于晶圆120的TTV值的两倍。
在介电层136的平坦化工艺之后，晶圆120的TTV小于3μm，例如，在0μm与3μm之间的非零值。
在图4中，将晶圆120翻转并安装到载体衬底148上方。如图21所示，相应的工艺在工艺流程800中被示为工艺810。因此，晶圆120的背面成为晶圆120的正面。载体衬底148可以是玻璃载体衬底、陶瓷载体衬底等。载体衬底148可以是晶圆，从而可以在载体衬底148上同时形成多个封装件。
可以在晶圆120和载体衬底148之间使用释放层(未示出)。释放层可以由基于聚合物的材料形成，其可以在后续步骤中与载体衬底148一起被去除。在一些实施例中，介电层136可以用作释放层。在一些实施例中，释放层是环氧基热释放材料，其在加热时失去其粘合性，例如光热转换(LTHC)释放涂层。在其他实施例中，隔离层可以是紫外(UV)胶，当暴露于紫外线下时会失去其粘合特性。释放层可以以液体的形式分配并固化，可以是层压在载体衬底148上的层压膜，或者可以是类似物。释放层的顶面可以是水平的，并且可以具有高平坦度。
接下来，在图5中，对晶圆120的正面执行减薄工艺。如图21所示，相应的工艺在工艺流程800中被示为工艺812。可以利用研磨工艺来执行减薄工艺，该研磨工艺去除晶圆120的半导体衬底124的部分以暴露通孔125。通过首先执行通孔125突出，减小晶圆120的总厚度差异(TTV)。由于在晶圆120的整个表面上的沉积速率和蚀刻速率不同，因此在半导体衬底124上方添加的每个结构将导致晶圆120的TTV离零更远。可以利用平坦化工艺来平坦化上表面，但是该表面越宽，例如横跨整个晶圆120，则由平坦化导致的高度差异越大。
在先进技术节点中，变薄后的通孔125被缩短，小于15μm，例如在约3μm至约10μm之间。通过在工艺早期(在将任何管芯安装在晶圆120上之前)执行通孔125的突出，由于避免了由于安装器件管芯而引起的厚度差异，因此TTV减小了。TTV减小是有利的，因为否则减薄工艺可能会导致缩短的通孔125中出现故障。
由于晶圆120的翻转，通孔125可以从顶部到底部从较窄的第一宽度逐渐变化到较宽的第二宽度。
在图6中，在减薄工艺之后，可以在通孔125上方形成可选的互连结构138。在图21所示的工艺流程800中，相应工艺被示出为工艺814。可以使用类似于形成互连结构128的工艺和材料来形成互连结构138。形成凸块下金属化层(UBM)140，用于外部连接到正面互连结构138。UBM 140具有在互连结构138的最上面的介电层的主表面上并沿其延伸的凸块部分，并且具有延伸穿过互连结构138的最上面的介电层的通孔部分，以与互连结构138的金属层进行物理耦合和电耦合。结果，UBM 140电耦合到通孔125。UBM 140可以由与互连结构138的金属线相同的材料并使用类似的工艺形成。
接下来，可以在UBM 140上形成导电连接件144。在如图21所示的工艺流程800中，相应的工艺也被示为工艺814。导电连接件144可以是球栅阵列(BGA)连接件、焊球、金属柱、可控塌陷芯片连接(C4)凸块、微凸块、化学镀镍-化学镀镍钯浸金(ENEPIG)形成的凸块等。导电连接件144可包括导电材料，诸如焊料、铜、铝、金、镍、银、钯、锡等，或其组合在一些实施例中，通过蒸发、电镀、印刷、焊料转移、焊球放置首先形成焊料层来形成导电连接件144。一旦在结构上形成焊料层之后，就可执行回流以便将材料成形为期望的凸块形状。在另一实施例中，导电连接件144包括通过溅射、印刷、电镀、化学镀、CVD等形成的金属柱(诸如铜柱)。金属柱可以是无焊料的并且具有基本垂直的侧壁。在一些实施例中，在金属柱的顶部上形成金属保护层。金属保护层可包括镍、锡、锡铅、金、银、钯、铟、镍-钯-金、镍-金等，或其组合，并且可通过镀工艺形成。
在后续工艺中，可以将一个或多个器件管芯附接到导电连接件144。
图7示出了根据一些实施例的晶圆中的集成电路管芯150的截面图。集成电路管芯150将在后续工艺中被封装以形成集成电路封装件或小芯片。集成电路管芯150可以是逻辑管芯(例如，中央处理单元(CPU)、图形处理单元(GPU)、片上系统(SoC)、应用处理器(AP)、微控制器等)、存储器管芯(例如，动态随机存取存储器(DRAM)单元、静态随机存取存储器(SRAM)单元等)、电源管理管芯(例如，电源管理集成电路(PMIC)单元)、射频(RF))管芯、传感器管芯、微机电系统(MEMS)管芯、信号处理管芯(例如，数字信号处理(DSP)管芯)、前端管芯(例如，模拟前端(AFE))、模具等，或其组合。可以使用与用于形成器件管芯122的技术节点相同或不同的技术节点中的技术来形成集成电路管芯150。
集成电路管芯150可以形成在晶圆中，该晶圆可以包括不同的器件区域，这些器件区域在后续步骤中被分割以形成多个集成电路管芯。集成电路管芯150可以根据适用的制造工艺进行处理以形成集成电路。例如，集成电路管芯150包括半导体衬底152(例如，掺杂或未掺杂的硅)或绝缘体上半导体(SOI)的有源层衬底。半导体衬底152可包括其他半导体材料，例如锗；化合物半导体，包括碳化硅、砷化镓、磷化镓、磷化铟、砷化铟和/或锑化铟；合金半导体，包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP；或其组合。也可使用其他衬底，诸如多层或梯度衬底。半导体衬底152具有有源表面(例如，在图7中面向上的表面)，有时被称为正面；以及非有源表面(例如，在图7中面向下的表面)，有时被称为背面。
器件(由晶体管表示)154可以形成在半导体衬底152的前表面。器件154可以是有源器件(例如，晶体管、二极管等)、电容、电阻等。层间电介质(ILD)156在半导体衬底152的前表面上方。ILD 156包围并可以覆盖器件154。ILD 156可以包括由诸如磷硅玻璃(PSG)、硼硅玻璃(BSG)、硼掺杂磷硅玻璃(BPSG)、未掺杂硅酸盐玻璃(USG)等材料形成的一个或多个介电层。
导电插塞158延伸穿过ILD 156，从而与器件154进行电耦合和物理耦合。例如，当器件154是晶体管时，导电插塞158可耦合晶体管的栅极和源极/漏极区。导电插塞158可以由钨、钴、镍、铜、银、金、铝等或其组合形成。互连结构160在ILD 156和导电插头158上方。互连结构160将器件154互连以形成集成电路。互连结构160可以由例如ILD 156上的介电层中的金属化图案形成。金属化图案包括在一个或多个低k介电层中形成的金属线和通孔，该金属线和通孔在工艺中形成，并且使用类似于以上关于互连结构128讨论的材料。互连结构160的金属化图案通过导电插头158电耦合到器件154。
集成电路管芯150还包括焊盘162，例如铝焊盘，通过焊盘162进行外部连接。焊盘162在集成电路管芯150的有源侧，例如在互连结构160中和/或其上。一个或多个钝化膜164在集成电路管芯150上，例如在互连结构160和焊盘162的部分上。开口穿过钝化膜164延伸至焊盘162。诸如导电柱(例如，由诸如铜等金属形成)的管芯连接件166延伸穿过钝化膜164中的开口，并且物理耦合和电耦合至相应焊盘162。管芯连接件166可以通过例如镀等形成。管芯连接件166电耦合集成电路管芯150的相应集成电路。
导电连接件170形成在集成电路管芯150的表面处。导电连接件170的形成工艺和材料可以类似于导电连接件144的形成工艺和材料(图6)。例如，使用探针卡141’探测集成电路管芯150，以便发现有缺陷的集成电路管芯150，并确定已知良好管芯(KGD)。在每个集成电路管芯150上执行探测。在图21所示的工艺流程800中，相应工艺被示出为工艺816。
介电层168可以(或者可以不)在集成电路管芯150的有源侧，例如在钝化膜164和管芯连接件166上。介电层168横向地密封管芯连接件166，并且介电层168与集成电路芯片150横向地相接。最初，介电层168可以掩埋管芯连接件166，使得介电层168的最上表面在管芯连接件166的最上表面之上。在焊料区布置在管芯连接件166上的一些实施例中，介电层168也可以掩埋焊料区。可选地，可以在形成介电层168之前去除焊料区。
介电层168可以是诸如PBO、聚酰亚胺、BCB等聚合物，诸如氮化硅等氮化物，诸如氧化硅、PSG、BSG、BPSG等氧化物，其类似物或其组合。介电层168可以通过旋涂、层压、化学气相沉积(CVD)等方法形成。在一些实施例中，管芯连接件166在集成电路管芯150的形成期间通过介电层168暴露。在一些实施例中，管芯连接件166保持掩埋并在用于密封集成电路管芯150的后续工艺中暴露。暴露管芯连接件166可以去除管芯连接件166上可能存在的任何焊料区。
在形成集成电路管芯150的层、器件和连接件之后，可以使用切割刀片、激光切割工具等将集成电路管芯150彼此分割开，从而形成多个单独的集成电路管芯150。KGD可被分离并用于后续工艺，而未通过测试的管芯可以丢弃。
在一些实施例中，集成电路管芯150是包括多个半导体衬底152的堆叠器件。例如，集成电路管芯150可以是包括多个存储器管芯的存储器件，例如混合存储器立方体(HMC)模块、高带宽存储器(HBM)模块等。在这样的实施例中，集成电路管芯150包括通过衬底通孔(TSV)互连的多个半导体衬底152。每个半导体衬底152可以(或者可以不)具有互连结构160。
在图8中，作为KGD的集成电路管芯150被接合到晶圆120中的KGD。在图21所示的工艺流程800中，相应工艺被示出为工艺818。集成电路管芯150是管芯形式的分立管芯，而器件管芯122是晶圆形式的未切割的晶圆120的一部分。在一些实施例中，接合工艺包括将助焊剂施加到导电连接件144上，将集成电路管芯150放置到器件管芯122上，并且执行回流工艺，使得导电连接件144和170熔化以形成焊料区域172。在回流工艺之后，底部填料174可以可选地分配到集成电路管芯150和相应的下面的器件管芯122之间的间隙中，然后进行固化。
在图9中，可以沉积密封剂175以横向密封集成电路管芯150，并且可以覆盖每个集成电路管芯150的上表面。在图21所示的工艺流程800中，相应工艺被示出为工艺820。密封剂175填充相邻集成电路150之间的间隙。密封剂175可以是或可以包括模制化合物、模制底部填料、环氧树脂和/或树脂，并且可以使用任何合适的工艺来沉积。在密封之后，密封剂175的顶面高于集成电路管芯150的顶面。密封剂175可以包括一层或多层。
在图10中，在密封工艺之后，执行平坦化工艺以减小密封剂175的厚度，并使其顶面平坦。在如图21所示的工艺流程800中，相应的工艺也被示为工艺820。集成电路管芯150的半导体衬底152(图7)的厚度也可以变薄。在平坦化工艺之后，集成电路管芯150的上表面可以与密封剂175的上表面齐平。因为TSV 125的厚度已经减小，所以与通孔125仍然需要减薄的情况相比，密封剂175的上表面的平坦度的误差容限更大。例如，密封剂的TTV可以大于300nm。
在图11中，具有嵌入式集成电路管芯150的晶圆120被翻转并通过管芯附接膜(DAF)182附接到框架185，该DAF 182是粘合膜。例如，通过将光束(例如激光束)投射到释放膜上来去除载体衬底148，并且光穿过透明的载体衬底148。在图21所示的工艺流程800中，相应工艺被示出为工艺822。释放膜因此被分解，并且晶圆120从载体衬底148被释放。如图11所示，在一些实施例中，可以在介电层136中形成开口，从而暴露接合焊盘132。此后，可以在开口中形成连接件180。可以使用与以上关于导电连接件144(图6)讨论的材料和工艺相似的材料和工艺来形成连接件180。在其他实施例中，可以不形成连接件180。
然后通过管芯切割工艺190执行分割工艺，使得组合的器件管芯122和集成电路管芯150被分离成封装件195。在如图21所示的工艺流程800中，相应的工艺被示为工艺824。封装件195可以具有使用不同技术节点形成的不同部分。例如，可以使用N5、N7等技术节点技术来形成器件管芯122，并且可以使用N3技术节点技术来形成集成电路管芯150。封装件195也可以具有使用相同技术节点形成的不同部分。在清洁工艺中去除DAF 182，从而从框架185上去除封装件195。最终的结构如图12A和图12B所示。
在图12A和图12B中，根据一些实施例示出了封装件195。图12A是沿着图12B的A-A线的封装件195的截面图。图12B是封装件195的俯视图。如图12A和图12B所示，封装件195可以包括一个集成电路管芯150以形成小芯片。
在图13A和图13B中，根据其他实施例示出了封装件195’。图13A是沿着图13B的A-A线的封装件195’的截面图。图13B是图13A的封装件195’的俯视图。如图13A和图13B所示，封装件195’类似于图12A和图12B的封装件195，但是可以包括两个集成电路管芯150以形成小芯片。两个集成电路管芯150可以具有相同的功能或不同的功能，并且器件管芯122可以用于将一个集成电路管芯150中的接触件连接到另一个集成电路管芯150。
在图14A和图14B中，根据其他实施例示出了封装件195”。图14A是沿着图14B的A-A线的封装件195”的截面图。图14B是图14A的封装件195”的俯视图。如图14A和图14B所示，封装件195”类似于图12A和图12B的封装件195，但是可以包括其他数量的集成电路管芯150(在所示实施例中为四个)以形成小芯片。各种集成电路管芯150可以具有相同的功能或不同的功能或其组合。器件管芯122可以用于将一个集成电路管芯150中的接触件连接到另一个集成电路管芯150。
图15至图18示出了使用封装件195、封装件195’或封装件195”作为集成扇出(InFO)封装件的小芯片器件管芯来形成InFO封装件的中间阶段。为简单起见，这些封装件的任何变型都将简称为封装件195。相应的工艺示意性地反映在如图22所示的工艺流程900中。
在图15中，提供载体衬底202，并且在载体衬底202上形成释放层204。在图22所示的工艺流程900中，相应工艺被示出为工艺902。载体衬底202可以是玻璃载体衬底、陶瓷载体衬底等。载体衬底202可以是晶圆，使得可在载体衬底202上同时形成多个封装件。
释放层204可由基于聚合物的材料形成，其可与载体衬底202一起从将在后续步骤中形成的上方结构中去除。在一些实施例中，释放层204是基于环氧树脂的热释放材料(例如光-热转换(LTHC)释放涂层)，其在加热时失去其粘合性。在其他实施例中，释放层204可以是紫外(UV)胶，其在暴露于UV光时失去其粘合性。释放层204可以液体形式分配并固化，可以是层压到载体衬底202上的层压膜，或者可以是类似物。释放层204的顶面可以是水平的并且可具有高平面度。
在图15中，背面再分布结构206可以形成在释放层204上。在如图22所示的工艺流程900中，相应的工艺也被示为工艺902。在所示实施例中，背面再分布结构206包括介电层208、金属化图案210(有时称为再分布层或再分布线)和介电层212。背面再分布结构206是可选的。在一些实施例中，没有金属化图案的介电层形成在介电层204上，以代替背面再分布结构206。
介电层208可以形成在释放层204上。介电层208的底面可以与释放层204的顶面接触。在一些实施例中，介电层208由聚合物形成，例如聚苯并噁唑(PBO)、聚酰亚胺、苯并环丁烯(BCB)等。在其他实施例中，介电层208由下列物质形成：诸如氮化硅的氮化物；诸如氧化硅、磷硅酸盐玻璃、硼硅酸盐玻璃(BSG)、掺硼磷硅酸盐玻璃(BPSG)的氧化物等；或者类似物。介电层208可通过任何可行的沉积工艺形成，例如旋涂、CVD、层压等，或其组合。
金属化图案210可以形成在介电层208上。作为形成金属化图案210的实例，在介电层208上方形成晶种层。在一些实施例中，晶种层是金属层，其可以是单层或包括由不同材料形成的多个子层的复合层。在一些实施例中，晶种层包括钛层和在钛层上方的铜层。可以使用例如物理气相沉积(PVD)等形成晶种层。然后在晶种层上形成光刻胶(未示出)并将光刻胶图案化。光刻胶可以通过旋涂等形成，并且可以曝光以用于图案化。光刻胶的图案对应于金属化图案210。图案化形成穿过光刻胶的开口以暴露晶种层。在光刻胶的开口中和晶种层的暴露部分上形成导电材料。可以通过诸如电镀或化学镀等的镀来形成导电材料。导电材料可以包括金属，例如铜、钛、钨、铝等。然后，去除光刻胶和晶种层上未形成导电材料的部分。可以通过可行的灰化或剥离工艺，例如使用氧等离子体等，来去除光刻胶。一旦例如通过使用诸如湿法或干法蚀刻的可行的蚀刻工艺去除了光刻胶，就去除了晶种层的暴露部分。晶种层的剩余部分和导电材料形成金属化图案210。
介电层212可以形成在金属化图案210和介电层208上。在一些实施例中，介电层212由聚合物形成，该聚合物可以是光敏材料，例如PBO、聚酰亚胺、BCB等，其可以使用光刻掩模来图案化。在其他实施例中，介电层212由诸如氮化硅的氮化物，诸如氧化硅、BSG、PSG氧化物或者类似物来形成。介电层212可以通过旋涂、层压、CVD等或其组合来形成。介电层212然后被图案化以形成暴露金属化图案210的部分的开口。图案化可以通过可行的工艺形成，例如当介电层212是光敏材料时，通过将介电层212曝光，或者通过使用例如各向异性蚀刻进行蚀刻。如果介电层212是光敏材料，则介电层212可以在曝光后显影。
在一些实施例中，背面再分布结构206可以包括任意数量的介电层和金属化图案。如果要形成更多的介电层和金属化图案，可以重复上述步骤和工艺。金属化图案可以包括一个或多个导电组件。可以通过在金属化图案形成期间通过在下面的介电层的表面上方和下面的介电层的开口中形成晶种层和金属化图案的导电材料来形成导电组件，从而互连和电耦合各种导电线。
通孔216形成在再分布结构206中的开口中，并从背面再分布结构206的最顶层介电层(例如，介电层212)延伸出去。作为形成通孔216的实例，晶种层(未示出)形成在背面再分布结构206上方，例如，在介电层212和由开口214暴露的金属化图案210的部分上。在一些实施例中，晶种层是金属层，其可以是单层或包括由不同材料形成的多个子层的复合层。在特定实施例中，晶种层包括钛层和钛层上方的铜层。可使用例如PVD等形成晶种层。在晶种层上形成光刻胶并对其进行图案化。光刻胶可以通过旋涂等形成，并且可以曝光以用于图案化。光刻胶的图案对应于导电通孔。图案化形成穿过光刻胶的开口以暴露晶种层。在光刻胶的开口中和晶种层的暴露部分上形成导电材料。可以通过诸如电镀或化学镀等的镀来形成导电材料。导电材料可以包括金属，例如铜、钛、钨、铝等。去除光刻胶和晶种层上未形成导电材料的部分。可以通过可行的灰化或剥离工艺，例如使用氧等离子体等，来去除光刻胶。一旦例如通过使用诸如湿法或干法蚀刻的可行的蚀刻工艺去除了光刻胶，就去除了晶种层的暴露部分。晶种层的剩余部分和导电材料形成通孔216。
小芯片封装件195通过粘合剂218粘附到介电层212。在图22所示的工艺流程900中，相应工艺被示出为工艺904。粘合剂218位于封装件195的背面，并将封装件195粘附到背面再分布结构206，例如粘附到介电层212。粘合剂218可以是任何合适的粘合剂、环氧树脂、管芯附接膜(DAF)等。粘合剂218可以施加到封装件195的背面，如果没有使用背面再分布结构206，则可以施加到载体衬底202的表面上，或者如果适用，可以施加到背面再分布结构206的上表面。例如，在分割晶圆120以分离封装件195之前，可以将粘合剂218施加到封装件195的背面(见图11)。尽管针对每个封装组件200(例如，在对应于封装组件200A的封装区域中)示出了封装件195的其中一个，但是应当理解，多个封装件195、封装件195’或封装件195”可以以任何组合使用(例如，参见图18)。
接下来，在各个组件上和周围形成密封剂220。在图22所示的工艺流程900中，相应工艺被示出为工艺906。形成后，密封剂220密封通孔216和封装件195。密封剂220可以是模塑料、环氧树脂等。密封剂220可以通过压缩模制、传递模制等施加，并且可以形成在载体衬底202上方，使得通孔216和/或封装件195被掩埋或覆盖。密封剂220进一步形成在封装件195之间的间隙区域中。密封剂220可以以液体或半液体形式施加，然后固化。密封剂220横向围绕封装件195，并且其横向范围比封装件195的各种部件的横向范围更大。
然后在密封剂220上执行平坦化工艺，以暴露通孔216和接合焊盘132(例如，参见图12A)。在如图22所示的工艺流程900中，相应的工艺也被示为工艺906。平坦化工艺还可以去除通孔216、介电层136和/或接合焊盘132的材料，直到暴露接合焊盘132和通孔216。在工艺差异内的平坦化工艺之后，通孔216、接合焊盘132、介电层136和密封剂220的顶面基本共面。平坦化工艺可以是例如化学机械抛光(CMP)、研磨工艺等。在一些实施例中，例如，如果通孔216和/或焊盘132已经暴露，则可以省略平坦化。
接下来，在密封剂220、通孔216和封装件195上方形成正面再分布结构222。在图22所示的工艺流程900中，相应工艺被示出为工艺908。正面再分布结构222包括介电层224、228、232和236，以及金属化图案226、230和234。金属化图案也可被称为再分布层或重布线。作为具有三层金属化图案的实例，示出了正面再分布结构222。可以在正面再分布结构222中形成更多或更少的介电层和金属化图案。可以使用与以上关于再分布结构206所讨论的那些工艺和材料相似的工艺和材料来形成正面再分布结构222。如果要形成更少的介电层和金属化图案，可以省略或重复上述步骤和工艺。
形成UBM 238以外部连接到正面再分布结构222。在图22所示的工艺流程900中，相应工艺被示出为工艺910。UBM 238具有在介电层236的主表面上并沿着介电层236的主表面延伸的凸块部分，并且具有延伸穿过介电层236以物理耦合和电耦合金属化图案234的通孔部分。结果，UBM 238电耦合到通孔216和封装件195。UBM 238可以由与金属化图案226相同的材料形成。在一些实施例中，UBM 238具有与金属化图案226、230和234不同的尺寸。
导电连接件250形成在UBM 238上。在如图22所示的工艺流程900中，相应的工艺也被示为工艺910。导电连接件250可以是球栅阵列(BGA)连接件、焊球、金属柱、可控塌陷芯片连接(C4)凸块、微凸块、化学镀镍-化学镀镍钯浸金(ENEPIG)形成的凸块等。导电连接件250可包括导电材料，诸如焊料、铜、铝、金、镍、银、钯、锡等，或其组合在一些实施例中，通过蒸发、电镀、印刷、焊料转移、焊球放置首先形成焊料层来形成导电连接件250。一旦在结构上形成焊料层之后，就可执行回流以便将材料成形为期望的凸块形状。在另一实施例中，导电连接件250包括通过溅射、印刷、电镀、化学镀、CVD等形成的金属柱(诸如铜柱)。金属柱可以是无焊料的并且具有基本垂直的侧壁。在一些实施例中，在金属柱的顶部上形成金属保护层。金属保护层可包括镍、锡、锡铅、金、银、钯、铟、镍-钯-金、镍-金等，或其组合，并且可通过镀工艺形成。
可以在后续工艺中将完成的集成扇出封装组件200(例如封装组件200A和封装组件200B)分割。产生的封装组件200是集成扇出封装件。在一些实施例中，额外的封装组件可以在分割之前或之后附接到封装组件200。
在图16中，执行载体衬底去接合，以将载体衬底202(图15)从背面再分布结构206(例如，介电层208)分离(或“去接合”)。在图22所示的工艺流程900中，相应工艺被示出为工艺912。根据一些实施例，去接合包括在释放层204上投射诸如激光或UV光等光，使得释放层204在光的热量下分解并且可以去除载体衬底202。然后将结构翻转并放置在胶带255上方。
为了将第二封装组件300附接到封装组件200，首先，形成延伸穿过介电层208以接触金属化图案210的导电连接件252，或者在没有再分布结构206的实施例中，导电连接件可以接触通孔216。第二封装组件300耦合到封装组件200。在图22所示的工艺流程900中，相应工艺被示出为工艺914。第二封装组件300中的一个在第一封装区域400A和第二封装区域400B中的每个中耦合，以在封装组件200的每个区域中形成集成电路器件堆叠件400。集成电路器件堆叠件400是集成扇出堆叠式封装结构。
第二封装组件300包括例如衬底302和耦合到衬底302的一个或多个堆叠管芯310(例如，310A和310B)。尽管示出一组堆叠的管芯310(310A和310B)，但在其他实施例中，可将多个堆叠的管芯310(各自具有一个或多个堆叠的管芯)并排布置并且耦合到衬底302的相同表面。衬底302可由诸如硅、锗、金刚石等半导体材料制成。在一些实施例中，也可使用复合材料，诸如硅锗、碳化硅、砷化镓、砷化铟、磷化铟、碳化硅锗、磷砷化镓、磷化镓铟和其组合。另外，衬底302可以是绝缘体上硅(SOI)衬底。通常，SOI衬底包括半导体材料层，诸如外延硅、锗、硅锗、SOI、绝缘体上硅锗(SGOI)或其组合。在一个可选的实施例中，衬底302基于绝缘芯，例如玻璃纤维增强树脂芯。一种示例性芯材料是玻璃纤维树脂，例如FR4。芯材料的替代材料包括双马来酰亚胺三嗪(BT)树脂或可选的其他印刷电路板(PCB)材料或薄膜。诸如味之素(Ajinomoto)堆积膜(ABF)等堆积膜或其他堆叠可用于衬底302。
衬底302可包括有源器件和无源器件(未示出)。可以使用诸如晶体管、电容器、电阻器、其组合的多种器件来满足第二封装组件300的设计的结构和功能要求。可以使用任何合适的方法来形成器件。衬底302还可以包括金属化层(未示出)和导电通孔308。在一些实施例中，衬底302基本上不含有源器件和无源器件。
衬底302可在衬底302的第一侧上具有接合焊盘304以耦合到堆叠的管芯310，并且在衬底302的第二侧上具有接合焊盘306以耦合到导电连接件252，第二侧与衬底302的第一侧相对。在所示的实施例中，堆叠的管芯310通过导线接合312耦合到衬底302，但可使用其他连接，诸如导电凸块。在实施例中，堆叠的管芯310是堆叠的存储器管芯。例如，堆叠的管芯310可以是诸如低功率(LP)双倍数据速率(DDR)存储器模块等存储器管芯，例如LPDDR1、LPDDR2、LPDDR3、LPDDR4等存储器模块。
可以通过模制材料314来密封堆叠管芯310和引线接合312。例如，可以使用压缩模制将模制材料314模制在堆叠的管芯310和引线接合312上。在一些实施例中，模制材料314是模制化合物、聚合物、环氧树脂、氧化硅填充材料等，或其组合。可执行固化工艺来固化模制材料314；固化工艺可以是热固化、紫外固化等，或其组合。
在形成第二封装组件300之后，第二封装组件300通过导电连接件252、接合焊盘306和背面再分布结构206的金属化图案机械地和电气地接合到封装组件200。在一些实施例中，堆叠管芯310可以通过引线接合312、接合焊盘304和306、导电通孔308、导电连接件252、背面再分布结构206、通孔216和正面再分布结构222耦合到封装件195。
在一些实施例中，底部填料(未示出)形成在封装组件200和第二封装组件300之间，并围绕导电连接件252。底部填料可减少应力并保护产生于导电连接件252的回流的接头。底部填料可以在第二封装组件300被附接之后通过毛细流动工艺形成，或者可以在第二封装组件300被附接之前通过合适的沉积方法形成。
通过沿着例如第一封装区域400A和第二封装区域400B之间的划线区域进行切割来执行分割工艺。在图22所示的工艺流程900中，相应工艺被示出为工艺916。切割将第一封装区域400A与第二封装区域400B进行分割。所得的分割集成电路器件堆叠件400来自第一封装区域400A或第二封装区域400B中的一个。在一些实施例中，在第二封装组件300耦合到封装组件200之后，执行分割工艺。在其他实施例中，在第二封装组件300耦合到封装组件200之前，例如在载体衬底202被去接合并且形成导电连接件252之后，执行分割工艺。
在图17中，然后可以使用导电连接件250将每个集成电路器件堆叠件400安装到封装衬底500上，以形成3D封装件600。在如图22所示的工艺流程900中，相应的工艺也被示为工艺918。封装衬底500包括衬底核心502和衬底核心502上方的焊盘504。衬底核心502可由诸如硅、锗、金刚石等半导体材料制成。可选地，也可使用复合材料，诸如硅锗、碳化硅、砷化镓、砷化铟、磷化铟、碳化硅锗、磷化砷化镓、磷化镓铟和其组合。另外，衬底核心502可以是SOI衬底。通常，SOI衬底包括半导体材料层，诸如外延硅、锗、硅锗、SOI、SGOI或其组合。衬底核心502可以是有机衬底。在一个可选的实施例中，衬底核心502基于绝缘芯，例如玻璃纤维增强树脂芯。一种示例性芯材料是玻璃纤维树脂，例如FR4。芯材料的替代材料包括双马来酰亚胺三嗪BT树脂或可选地其他PCB材料或薄膜。诸如ABF或其他层压材料的堆积膜可用于衬底核心502。
衬底核心502可包括有源器件和无源器件(未示出)。诸如晶体管、电容器、电阻器、其组合等广泛多种器件可用于产生器件堆叠的设计的结构和功能要求。可以使用任何合适的方法来形成器件。衬底核心502还可以包括包含金属化层和通孔的再分布结构510，其中，接合焊盘504物理耦合和/或电耦合到金属化层和通孔。
在一些实施例中，导电连接件250被回流以将封装组件200附接到接合焊盘504。导电连接件250将封装衬底500(包括衬底核心502中的金属化层)电耦合和/或物理耦合到封装组件200。在一些实施例中，阻焊剂506形成在衬底核心502上。导电连接件250可以设置在阻焊剂506的开口中，以电耦合和机械耦合到接合焊盘504。阻焊剂506可用于保护衬底核心502的区域免受外部损坏。
导电连接件250在回流之前可以具有形成在其上的环氧助焊剂(未示出)，在封装组件200附接到封装衬底500之后，环氧助焊剂的至少一些环氧部分保留在导电连接件250上。此保留的环氧树脂部分可用作底部填料，以减小应力并保护产生于使导电连接件250回流的接头。在一些实施例中，可选的底部填料520可以形成在封装组件200和封装衬底500之间，并且围绕导电连接件250。底部填料520可以在附接封装组件200之后通过毛细流动工艺形成，或者可以在附接封装组件200之前通过合适的沉积方法形成。
图18示出了使用集成扇出封装组件200的3D封装件600，其中嵌入了多个封装件195。用于形成图18的3D封装件600的工艺类似于以上关于图15至图17描述的工艺，这些工艺不再赘述。
图19示出了封装件195接合到衬底700以形成倒装芯片封装件600’。尽管封装件195、封装件195’或封装件195”中的一个被图示为接合到衬底700，但是应当理解，多个封装件195、封装件195’或封装件195”可以以任何组合使用。为了简单起见，将封装件195、封装件195’或封装件195”称为封装件195。封装件195可以通过焊料或者通过接合焊盘132与衬底700的直接金属对金属接合，或者通过任何其他合适的工艺来接合。可以形成类似于底部填料520的可选底部填料720，以围绕接合焊盘132的接头。
衬底700可以是任何合适的衬底，并且可以类似于封装衬底500，其中，相同的参考标号表示相同的结构。再分布结构510可以包括用于接收封装件195的接触焊盘706。衬底700还可以包括第二再分布结构710，该第二再分布结构710设置在衬底核心502的与再分布结构510相反的一侧。第二再分布结构710可以使用与用于形成再分布结构510的工艺和材料类似的工艺和材料来形成。衬底核心502包括将再分布结构510电耦合到第二再分布结构710的通孔704。可以通过蚀刻或激光钻孔或其他合适的工艺在衬底核心502中形成开口，然后用导电材料填充开口来形成通孔704。在沉积导电材料以包围开口中的导电材料之前，也可以在开口中使用势垒层材料。
衬底700还可以包括耦合到第二再分布结构710的接触焊盘712。每个接触焊盘712还可以包括设置在其上的焊球或焊料凸块714，以在衬底700的底部形成球栅阵列。球栅阵列可以用于倒装芯片接合。可以通过在焊盘上沉积焊料材料并且使焊料材料回流来形成焊料凸块714。
图20示出了接合到中介层750的封装件195，中介层750然后接合到衬底700，以形成衬底上晶圆上芯片(CoWoS)封装件600”。尽管封装件195、封装件195’或封装件195”中的一个被示出为接合到中介层750，但是应当理解，多个封装件195、封装件195’或封装件195”可以以任何组合使用。为了简单起见，将封装件195、封装件195’或封装件195”称为封装件195。封装件195可以通过焊料或者通过接合焊盘132与中介层750的直接金属对金属接合，或者通过任何其他合适的工艺来接合。可以形成类似于底部填料520的可选底部填料720，以围绕接合焊盘132的接头。
中介层750包括衬底核心755。衬底核心755可以是有机衬底、陶瓷衬底、硅衬底等。衬底核心755可以由玻璃纤维、树脂、填料、其他材料和/或其组合形成。在一些实施例中，衬底核心755包括嵌入其中的一个或多个无源组件(未示出)。在另一个实施例中，衬底核心755可以包括其他材料或组件。
导电通孔760延伸穿过衬底核心755。在一些实施例中，导电通孔760包括导电材料，例如铜、铜合金或其他导体，并且可以包括势垒层、衬垫、晶种层和/或填充材料。导电通孔760提供从衬底核心755的一侧到衬底核心755的另一侧的垂直电连接。例如，一些导电通孔760电耦合在衬底核心755一侧的导电部件770和衬底核心755相对侧的导电部件775之间。作为示例，可以使用钻孔工艺、光刻技术、激光工艺或其他方法来形成导电通孔760的孔，然后用导电材料填充导电通孔760的孔。
导电部件775可以是例如导电焊盘或凸块下金属化层。导电部件770可以是例如球栅阵列或其他合适的导电结构。中介层750还可以包括在衬底核心755的相对侧上的再分布结构780A和780B。再分布结构780A和780B通过导电通孔760电耦合。再分布结构780A和780B各自包括类似于以上关于图15的再分布结构206所讨论的介电层和金属化图案。每个相应的金属化图案具有在相应的介电层的主表面上并沿着其延伸的线部分，并且具有延伸穿过相应的介电层的通孔部分。
图示的中介层750是中介层晶圆的一部分，该中介层晶圆包括类似于图示的中介层750的多个位置，用于附接在管芯切割工艺中被分割的封装件195。在一些实施例中，封装件195可以被接合到中介层晶圆，然后中介层晶圆被分割成封装件195和中介层750的组合，然后封装件195和中介层750被接合到衬底700。在其他实施例中，中介层晶圆可以首先被分割成中介层750，接下来封装件195被接合到中介层750，然后中介层750被接合到衬底700。在其他实施例中，中介层750被接合到衬底700，然后封装件195被接合到中介层750。
在一些实施例中，衬底700可以包括类似于上面关于图19所讨论的部件，其中，相同的参考标号表示相同的结构。其他实施例可以省略通孔704、第二再分布结构710、接触焊盘712或焊料凸块714中的一个或多个，并且可以具有类似于以上关于图18的封装衬底500所讨论的部件。可以形成类似于底部填料520的可选底部填料790，以围绕导电部件770的接头。
在上述实施例中，根据本发明的一些实施例讨论了一些工艺和部件，以形成三维(3D)封装件。也可以包括其他部件和工艺。例如，可以包括测试结构以辅助3D封装件或3DIC器件的验证测试。测试结构可以包括诸如形成在再分布层中或衬底上的测试焊盘，其允许测试3D封装件或3DIC，使用探针和/或探针卡等。验证测试可以在中间结构以及最终结构上执行。另外，本文公开的结构和方法可以与结合了已知良好管芯的中间验证的测试方法结合使用，以增加良率并降低成本。
本发明的实施例具有一些有利的特征。通过在附接集成电路器件管芯之前减薄TSV，减小了总厚度差异。总厚度差异的减少导致更好的良率，因此降低了制造成本。小芯片器件封装件可以使用先进技术节点来形成，并且以类似于集成器件管芯的方式在不太先进的技术负载中使用。例如，小芯片器件封装可以在InFO工艺中使用，以在包括通过接合堆叠的两个或更多个管芯的管芯堆叠件上形成互连结构。因此，InFO互连结构可以代替传统的封装衬底。小芯片器件封装件也可用于形成倒装芯片封装件或衬底上晶圆上芯片(CoWoS)封装件。
一个实施例是一种方法，包括在衬底中形成通孔组，该组通孔部分地穿透衬底的厚度。该方法还包括在衬底的第一侧上方的该组通孔上方形成第一连接件。衬底的第一侧附接到载体，并且衬底被减薄以暴露该组通孔。该方法还包括在衬底的第二侧上方的该组通孔上方形成第二连接件，第二侧与第一侧相对。该方法还包括将器件管芯接合到第二连接件。衬底被分割成多个封装件。在实施例中，该方法还包括在第一连接件上方形成介电层，其中，将衬底的第一侧附接到载体包括将介电层附接到载体。在实施例中，该方法还包括在该组通孔上方形成第一互连件，该第一互连件插在该组通孔和第二连接件之间。在实施例中，该方法还包括将多个封装件中的第一封装件安装到载体上；在第一封装件上方形成再分布结构；在再分布结构上方形成第三连接件；以及将第一封装和再分布结构分割成集成扇出封装件。在实施例中，在将衬底分割成多个封装件之后，多个封装件中的每个包括多个器件管芯。在实施例中，该方法还包括：将多个封装件中的第一封装件安装到衬底上以形成倒装芯片封装件。在实施例中，该方法还包括将多个封装件中的第一封装件安装到中介层晶圆上；将中介层晶圆接合到衬底上；以及将中介层晶圆、衬底和第一封装件分割为衬底上晶圆上芯片(CoWoS)封装件。
另一实施例是一种方法，包括测试第一衬底的第一组连接件，第一组连接件电耦合到第一组通孔结构。该方法还包括将第一衬底的第一组连接件安装到载体上，并且减薄第一衬底以暴露第一组通孔结构。该方法还包括将器件管芯电耦合到第一组通孔结构。第一衬底被分割成多个封装件。在实施例中，第一组通孔结构是渐变的，即越靠近器件管芯越窄，越远离器件管芯越宽。在实施例中，测试第一组连接件包括探测设置在第一组连接件上的焊帽，并且该方法还包括从第一组连接件去除焊帽，并且在第一组连接件上方沉积介电材料，其中，将第一组连接件安装到载体包括将介电材料接合到载体。在实施例中，该方法还包括：将多个封装件附接到载体上；在多个封装件上方形成第一再分布层；在第一再分布层上方形成第一连接件；以及分割第一再分布层、第一连接件和多个封装件，从而形成集成扇出封装件。在实施例中，集成扇出封装件包括多个封装件中的至少两个。在实施例中，该方法还包括将多个封装件中的第一封装件在与球栅阵列相对的衬底的相对侧上附接到衬底，以形成倒装芯片封装件。在实施例中，该方法还包括：将多个封装件中的第一封装件附接到中介层衬底晶圆；将中介层衬底晶圆分割成多个封装组件；以及将多个封装组件中的第一封装组件附接到衬底上，以形成衬底上晶圆上芯片(CoWoS)封装件。
另一实施例是一种结构，该结构包括第一材料层，第一材料层包括第一组通孔，第一组通孔具有从顶部到底部扩展更宽的宽度。该结构还包括设置在第一材料层的第一侧上方的第一组连接件。该结构还包括设置在第一材料层的第二侧下方的第二组连接件。第一半导体器件耦合到第一组连接件。横向围绕第一半导体器件的密封剂。在实施例中，该结构还包括耦合到第一组连接件的一个或多个附加半导体器件。在实施例中，该结构还包括：耦合到第二组连接件的第一再分布结构，该第一再分布结构的横向范围大于第一材料层的横向范围；横向围绕第一材料层的第二密封剂；以及设置在第一再分布结构下侧的第三组连接件。在实施例中，该结构还包括：第二再分布结构，设置在第一半导体器件上方；第二组通孔，第二组通孔将第一再分布结构耦合到第二再分布结构；第二半导体器件，设置在第二再分布结构上方，并电耦合到第二再分布结构；以及物理耦合和电耦合到第三组连接件的器件衬底。在实施例中，该结构还包括：耦合到第二组连接件的器件衬底，该器件衬底包括球栅阵列，该球栅阵列包括倒装芯片封装件。在实施例中，该结构还包括：中介层衬底，该中介层衬底在中介层衬底的第一侧耦合到第二组连接件；以及器件衬底，该器件衬底耦合到中介层衬底的第二侧，中介层衬底的第二侧与中介层衬底的第一侧相对。
上文概述了若干实施例的特征，使得本领域技术人员可以更好地理解本发明的各个方面。本领域技术人员应该理解，他们可以容易地使用本发明作为基础来设计或修改用于实施与本文所介绍的实施例相同目的和/或实现相同优势的其他工艺和结构。本领域技术人员还应认识到，这种等效结构并不背离本发明的精神和范围，并且其可以进行各种更改、替换和变更而不背离本发明的精神和范围。

Claims (20)

1.一种制造半导体结构的方法，包括：
在衬底中形成通孔组，所述通孔组部分地穿透所述衬底的厚度；
在所述衬底的第一侧上方的所述通孔组上方形成第一连接件；
将所述衬底的所述第一侧附接到载体上；
减薄所述衬底以暴露所述通孔组；
在所述衬底的第二侧上方的所述通孔组上方形成第二连接件，所述第二侧与所述第一侧相对；
将器件管芯接合到所述第二连接件；
将所述衬底分割成多个封装件；
将所述多个封装件中的第一封装件安装到另一载体上；
在所述第一封装件上方形成再分布结构；
在所述再分布结构上方形成第三连接件；以及
将所述第一封装件和再分布结构分割成集成扇出封装件。
2.根据权利要求1所述的方法，还包括：
在所述第一连接件上方形成介电层，其中，将所述衬底的所述第一侧附接到所述载体包括将所述介电层附接到所述载体。
3.根据权利要求1所述的方法，还包括：
在所述通孔组上方形成第一互连件，所述第一互连件插入在所述通孔组和所述第二连接件之间。
4.根据权利要求1所述的方法，其中，利用研磨工艺来执行所述减薄。
5.根据权利要求1所述的方法，还包括：
将多个器件管芯接合到所述第二连接件，其中，在将所述衬底分割成多个封装件之后，所述多个封装件中的每个包括多个器件管芯。
6.根据权利要求1所述的方法，其中，所述第二连接件包括通过溅射、印刷、电镀、化学镀、化学气相沉积形成的金属柱。
7.一种制造半导体结构的方法，包括：
在衬底中形成通孔组，所述通孔组部分地穿透所述衬底的厚度；
在所述衬底的第一侧上方的所述通孔组上方形成第一连接件；
将所述衬底的所述第一侧附接到载体上；
减薄所述衬底以暴露所述通孔组；
在所述衬底的第二侧上方的所述通孔组上方形成第二连接件，所述第二侧与所述第一侧相对；
将器件管芯接合到所述第二连接件；
将所述衬底分割成多个封装件；
将所述多个封装件中的第一封装件安装到中介层晶圆上；
将所述中介层晶圆接合到衬底上；以及
将所述中介层晶圆、所述衬底和所述第一封装件分割成衬底上晶圆上芯片封装件。
8.一种制造半导体结构的方法，包括：
测试第一衬底的第一组连接件，所述第一组连接件电耦合到第一组通孔结构，测试所述第一组连接件包括探测设置在所述第一组连接件上的焊帽；
从所述第一组连接件去除所述焊帽；以及
在所述第一组连接件上方沉积介电材料，
将所述第一衬底的所述第一组连接件安装到载体上，其中，将所述第一组连接件安装到所述载体包括将所述介电材料接合到所述载体；
减薄所述第一衬底以暴露所述第一组通孔结构；
将器件管芯电耦合到所述第一组通孔结构；以及
将所述第一衬底分割成多个封装件。
9.根据权利要求8所述的方法，其中，所述第一组通孔结构是渐变的，即越靠近所述器件管芯越窄，并且越远离所述器件管芯越宽。
10.根据权利要求8所述的方法，其中，所述介电材料是聚合物层。
11.根据权利要求8所述的方法，还包括：
将所述多个封装件附接到另一载体上；
在所述多个封装件上方形成第一再分布层；
在所述第一再分布层上方形成第一连接件；以及
分割所述第一再分布层、所述第一连接件和所述多个封装件，从而形成集成扇出封装件。
12.根据权利要求11所述的方法，其中，所述集成扇出封装件包括所述多个封装件中的至少两个。
13.根据权利要求8所述的方法，还包括：
将所述多个封装件中的第一封装件在衬底的与球栅阵列相对的侧上附接到衬底，以形成倒装芯片封装件。
14.根据权利要求8所述的方法，还包括：
将所述多个封装件中的第一封装件附接到中介层衬底晶圆；
将所述中介层衬底晶圆分割成多个封装组件；以及
将所述多个封装组件中的第一封装组件附接到衬底上，以形成衬底上晶圆上芯片封装件。
15.一种半导体结构，包括：
第一材料层，所述第一材料层包括第一组通孔，所述第一组通孔具有从顶部到底部扩展得更宽的宽度；
第一组连接件，设置在所述第一材料层的第一侧上方；
第二组连接件，设置在所述第一材料层的第二侧下方；
第一半导体器件，耦合到所述第一组连接件；
密封剂，横向围绕所述第一半导体器件；
第一再分布结构，耦合到所述第二组连接件，所述第一再分布结构的横向范围大于所述第一材料层的横向范围；
第二密封剂，横向围绕所述第一材料层；以及
第三组连接件，设置在所述第一再分布结构的下侧上。
16.根据权利要求15所述的半导体结构，还包括：
耦合到所述第一组连接件的一个或多个附加半导体器件。
17.根据权利要求15所述的半导体结构，其中，所述第一组通孔为硅通孔。
18.根据权利要求15所述的半导体结构，还包括：
第二再分布结构，设置在所述第一半导体器件上方；
第二组通孔，所述第二组通孔将所述第一再分布结构耦合到所述第二再分布结构；
第二半导体器件，设置在所述第二再分布结构上方，并电耦合到所述第二再分布结构；以及
器件衬底，物理耦合和电耦合到所述第三组连接件。
19.根据权利要求15所述的半导体结构，其中，所述第二密封剂为模塑料。
20.一种半导体结构，包括：
第一材料层，所述第一材料层包括第一组通孔，所述第一组通孔具有从顶部到底部扩展得更宽的宽度；
第一组连接件，设置在所述第一材料层的第一侧上方；
第二组连接件，设置在所述第一材料层的第二侧下方；
第一半导体器件，耦合到所述第一组连接件；
密封剂，横向围绕所述第一半导体器件；
中介层衬底，所述中介层衬底在所述中介层衬底的第一侧耦合到所述第二组连接件；以及
器件衬底，所述器件衬底耦合到所述中介层衬底的第二侧，所述中介层衬底的所述第二侧与所述中介层衬底的所述第一侧相对。
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