CN105895616A - 金属氧化物层状结构及其形成方法 - Google Patents
金属氧化物层状结构及其形成方法 Download PDFInfo
- Publication number
- CN105895616A CN105895616A CN201510768173.2A CN201510768173A CN105895616A CN 105895616 A CN105895616 A CN 105895616A CN 201510768173 A CN201510768173 A CN 201510768173A CN 105895616 A CN105895616 A CN 105895616A
- Authority
- CN
- China
- Prior art keywords
- metal
- layer
- dielectric layer
- metallization pattern
- oxide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 229910044991 metal oxide Inorganic materials 0.000 title claims abstract description 144
- 150000004706 metal oxides Chemical class 0.000 title claims abstract description 143
- 238000000034 method Methods 0.000 title claims abstract description 67
- 238000001465 metallisation Methods 0.000 claims abstract description 137
- 239000000463 material Substances 0.000 claims abstract description 44
- 238000005538 encapsulation Methods 0.000 claims abstract description 31
- 239000003795 chemical substances by application Substances 0.000 claims abstract description 30
- 125000004429 atom Chemical group 0.000 claims abstract description 14
- 125000004430 oxygen atom Chemical group O* 0.000 claims abstract description 10
- 239000010410 layer Substances 0.000 claims description 366
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 45
- 239000001301 oxygen Substances 0.000 claims description 45
- 229910052760 oxygen Inorganic materials 0.000 claims description 45
- 230000008569 process Effects 0.000 claims description 23
- 239000012790 adhesive layer Substances 0.000 claims description 12
- 239000002131 composite material Substances 0.000 claims description 11
- 239000004568 cement Substances 0.000 claims description 4
- 150000004767 nitrides Chemical class 0.000 claims description 3
- 229910052751 metal Inorganic materials 0.000 description 91
- 239000002184 metal Substances 0.000 description 91
- 239000013078 crystal Substances 0.000 description 69
- 229920002120 photoresistant polymer Polymers 0.000 description 61
- 238000004806 packaging method and process Methods 0.000 description 38
- 239000000758 substrate Substances 0.000 description 34
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 24
- 239000010949 copper Substances 0.000 description 23
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 22
- 229910052802 copper Inorganic materials 0.000 description 22
- 239000010936 titanium Substances 0.000 description 22
- 229910052719 titanium Inorganic materials 0.000 description 22
- 238000000059 patterning Methods 0.000 description 19
- 230000015572 biosynthetic process Effects 0.000 description 17
- 229920000642 polymer Polymers 0.000 description 16
- 238000007747 plating Methods 0.000 description 15
- 239000004065 semiconductor Substances 0.000 description 15
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 12
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 12
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 12
- 238000004528 spin coating Methods 0.000 description 12
- 230000008859 change Effects 0.000 description 11
- 239000010931 gold Substances 0.000 description 11
- 229910052737 gold Inorganic materials 0.000 description 11
- 229920002577 polybenzoxazole Polymers 0.000 description 11
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 10
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 10
- 238000003475 lamination Methods 0.000 description 10
- 150000002739 metals Chemical class 0.000 description 10
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 10
- 229910001868 water Inorganic materials 0.000 description 10
- 239000004642 Polyimide Substances 0.000 description 9
- 229910052782 aluminium Inorganic materials 0.000 description 9
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 9
- 229920001721 polyimide Polymers 0.000 description 9
- QPLDLSVMHZLSFG-UHFFFAOYSA-N Copper oxide Chemical compound [Cu]=O QPLDLSVMHZLSFG-UHFFFAOYSA-N 0.000 description 8
- 150000001875 compounds Chemical class 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 8
- 238000005240 physical vapour deposition Methods 0.000 description 8
- 229910000679 solder Inorganic materials 0.000 description 8
- 238000004544 sputter deposition Methods 0.000 description 8
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 8
- 229910052721 tungsten Inorganic materials 0.000 description 8
- 239000010937 tungsten Substances 0.000 description 8
- 238000004380 ashing Methods 0.000 description 7
- 238000009713 electroplating Methods 0.000 description 7
- 239000002356 single layer Substances 0.000 description 7
- 239000000126 substance Substances 0.000 description 7
- 238000001039 wet etching Methods 0.000 description 7
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 description 6
- 229910052786 argon Inorganic materials 0.000 description 6
- 229910017052 cobalt Inorganic materials 0.000 description 6
- 239000010941 cobalt Substances 0.000 description 6
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 6
- 229910052739 hydrogen Inorganic materials 0.000 description 6
- 239000001257 hydrogen Substances 0.000 description 6
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 6
- 229910052759 nickel Inorganic materials 0.000 description 6
- 239000011230 binding agent Substances 0.000 description 5
- BERDEBHAJNAUOM-UHFFFAOYSA-N copper(I) oxide Inorganic materials [Cu]O[Cu] BERDEBHAJNAUOM-UHFFFAOYSA-N 0.000 description 5
- LBJNMUFDOHXDFG-UHFFFAOYSA-N copper;hydrate Chemical compound O.[Cu].[Cu] LBJNMUFDOHXDFG-UHFFFAOYSA-N 0.000 description 5
- 239000003292 glue Substances 0.000 description 5
- 238000004140 cleaning Methods 0.000 description 4
- 239000003989 dielectric material Substances 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 238000010422 painting Methods 0.000 description 4
- 238000003860 storage Methods 0.000 description 4
- UHOVQNZJYSORNB-UHFFFAOYSA-N Benzene Chemical compound C1=CC=CC=C1 UHOVQNZJYSORNB-UHFFFAOYSA-N 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 3
- 238000010276 construction Methods 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 150000002927 oxygen compounds Chemical class 0.000 description 3
- 238000001259 photo etching Methods 0.000 description 3
- 239000002516 radical scavenger Substances 0.000 description 3
- 238000004088 simulation Methods 0.000 description 3
- 239000004593 Epoxy Substances 0.000 description 2
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 239000011469 building brick Substances 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 229910000431 copper oxide Inorganic materials 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 150000002118 epoxides Chemical class 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000000992 sputter etching Methods 0.000 description 2
- -1 36E metal-oxide Chemical class 0.000 description 1
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 239000005751 Copper oxide Substances 0.000 description 1
- PMPVIKIVABFJJI-UHFFFAOYSA-N Cyclobutane Chemical compound C1CCC1 PMPVIKIVABFJJI-UHFFFAOYSA-N 0.000 description 1
- 229910005540 GaP Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 1
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 239000002390 adhesive tape Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000000712 assembly Effects 0.000 description 1
- 238000000429 assembly Methods 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 229940125844 compound 46 Drugs 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 150000002343 gold Chemical class 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000003801 milling Methods 0.000 description 1
- 229910003465 moissanite Inorganic materials 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 239000000206 moulding compound Substances 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000010992 reflux Methods 0.000 description 1
- 230000011218 segmentation Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000007711 solidification Methods 0.000 description 1
- 230000008023 solidification Effects 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76832—Multiple layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
- H01L21/76888—By rendering at least a portion of the conductor non conductive, e.g. oxidation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3135—Double encapsulation or coating and encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3185—Partial encapsulation or coating the coating covering also the sidewalls of the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05005—Structure
- H01L2224/05008—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05541—Structure
- H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05569—Disposition the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/0651—Wire or wire-like electrical connections from device to substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06568—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices decreasing in size, e.g. pyramidical stack
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
- H01L2225/1035—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1041—Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1047—Details of electrical connections between containers
- H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
- H01L23/49894—Materials of the insulating layers or coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00012—Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Chemical & Material Sciences (AREA)
- Ceramic Engineering (AREA)
- Geometry (AREA)
Abstract
本发明描述了一些示例性结构和方法。结构包括至少由包封剂横向包封的集成电路管芯以及位于集成电路管芯和包封剂上的再分布结构。再分布结构电连接至集成电路管芯。再分布结构包括位于至少包封剂上的第一介电层、位于第一介电层上的金属化图案、位于金属化图案上的金属氧化物层状结构、以及位于第一介电层和金属化图案上的第二介电层。金属氧化物层状结构包括具有基本上1:1的金属原子与氧原子的比率的金属氧化物层,并且金属氧化物层状结构的厚度为至少第二介电层是光敏材料。金属氧化物层状结构设置在金属化图案和第二介电层之间。本发明的实施例还涉及金属氧化物层状结构及其形成方法。
Description
本申请要求2015年2月13日提交的标题为“Metal Oxide Layered Structure andMethods of Forming the Same”的美国临时申请第62/116,170号的优先权和权益,其全部内容结合于此作为参考。
技术领域
本发明的实施例涉及集成电路器件,更具体地,涉及金属氧化物层状结构及其形成方法。
背景技术
半导体器件用于各种电子应用中,作为实例,诸如个人计算机、手机、数码相机和其他电子设备。通常通过在半导体衬底上方依次沉积绝缘或介电层、导电层和半导体材料层以及使用光刻图案化各个材料层以在材料层上形成电路组件和元件来制造半导体器件。通常在单个半导体晶圆上制造数十或数百个集成电路。通过沿着划线锯切集成电路来分割单独的管芯。例如,然后以多芯片模块、或以其他类型的封装单独地封装单独的管芯。
半导体工业通过不断地减小最小部件尺寸不断地改进各种电子组件(例如,晶体管、二极管、电阻器、电容器等)的集成密度,这允许更多的组件集成到给定区域内。在一些应用中,诸如集成电路管芯的这些较小的电子组件也可能需要比之前的封装件利用更小区域的较小的封装件。
发明内容
本发明的实施例提供了一种结构,包括:集成电路管芯,至少由包封剂横向包封;再分布结构,位于所述集成电路管芯和所述包封剂上,所述再分布结构电连接至所述集成电路管芯,所述再分布结构包括:第一介电层,至少位于所述包封剂上,金属化图案,位于所述第一介电层上,金属氧化物层状结构,位于所述金属化图案上,所述金属氧化物层状结构包括具有基本上1:1的金属原子与氧原子的比率的金属氧化物层,所述金属氧化物层状结构的厚度为至少以及第二介电层,位于所述第一介电层和所述金属化图案上,所述第二介电层是光敏材料,所述金属氧化物层状结构设置在所述金属化图案和所述第二介电层之间。
本发明的另一实施例提供了一种结构,包括:集成电路管芯;包封剂,至少横向包封所述集成电路管芯;第一介电层,位于所述包封剂和所述集成电路管芯的有源侧上;金属化图案,位于所述第一介电层上,所述金属化图案电连接至所述集成电路管芯的有源侧;粘合层,位于所述金属化图案上,所述粘合层包括具有基本上1:1的金属原子与氧原子的比率的金属氧化物层,所述粘合层的厚度为至少以及第二介电层,位于所述第一介电层和所述粘合层上,所述第二介电层是光敏材料。
本发明的又一实施例提供了一种方法,包括:以包封剂包封集成电路管芯;在所述包封剂和所述集成电路管芯上方形成介电层;在所述介电层上方形成金属化图案;以含氧等离子体处理所述金属化图案,所述处理在所述金属化图案上方形成具有基本上1:1的金属原子与氧原子的比率的金属氧化物层,所述金属氧化物层的厚度为至少以及在所述金属氧化物层上方形成光敏材料。
附图说明
当结合附图进行阅读时,从以下详细描述可最佳理解本发明的各方面。应该注意,根据工业中的标准实践,各个部件未按比例绘制。实际上,为了清楚的讨论,各个部件的尺寸可以任意地增大或减小。
图1至图3是根据一些实施例的在处理期间的中间步骤的一般方面的截面图。
图4A和图4B是根据一些实施例的第一示例金属氧化物层状结构和形成金属氧化物层状结构的方法。
图5A和图5B是根据一些实施例的第二示例金属氧化物层状结构和形成金属氧化物层状结构的方法。
图6A和图6B是根据一些实施例的第三示例金属氧化物层状结构和形成金属氧化物层状结构的方法。
图7A和图7B是根据一些实施例的第四示例金属氧化物层状结构和形成金属氧化物层状结构的方法。
图8A和图8B是根据一些实施例的第五示例金属氧化物层状结构和形成金属氧化物层状结构的方法。
图9至图23是根据一些实施例的在用于形成封装件上芯片(CoP)和/或叠层封装件(PoP)结构的工艺期间的中间步骤的截面图。
图24是根据一些实施例的CoP结构。
图25是根据一些实施例的第一PoP结构。
图26是根据一些实施例的第二PoP结构。
图27是根据一些实施例的第三PoP结构。
具体实施方式
以下公开内容提供了许多用于实现所提供主题的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然,这些仅仅是实例,而不旨在限制本发明。例如,在以下描述中,在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例,并且也可以包括在第一部件和第二部件之间可以形成额外的部件,从而使得第一部件和第二部件可以不直接接触的实施例。此外,本发明可在各个实例中重复参考标号和/或字符。该重复是为了简单和清楚的目的,并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且,为便于描述,在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等的空间相对术语,以描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。类似地,诸如“前侧”和“后侧”的术语在本文中可以用于更容易地识别各种组件,并且可以识别那些组件例如位于另一组件的相对侧上。除了图中所示的方位外,空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上),而本文使用的空间相对描述符可以同样地作相应的解释。
可以在具体上下文中讨论本文中讨论的实施例,即,扇出或扇入晶圆级封装件,诸如封装件上芯片(CoP)和/或叠层封装件(PoP)结构中使用的。其他实施例预期其他应用,诸如本领域普通技术人员在阅读本发明之后将显而易见的不同封装件类型或不同配置。应该注意,本文中讨论的实施例可以不必示出可以在结构中存在的每个组件或部件。例如,诸如当一个组件的讨论可能足以表达实施例的各方面时,可以从图中省略多倍的组件。此外,本文中讨论的方法实施例可能讨论为以特定顺序实施;然而,可以以任何逻辑顺序实施其他方法实施例。
图1至图3是根据一些实施例的在处理期间的中间步骤的一般方面的截面图。图1示出了第一介电层30、位于第一介电层30上的金属化图案32以及位于金属化图案32上的原生氧化物34。在一些实施例中,第一介电层30由聚合物形成,其可以是诸如聚苯并恶唑(PBO)、聚酰亚胺、苯并环丁烯(BCB)等的光敏材料。可以通过诸如旋涂、层压等或它们的组合的任何可接受的沉积工艺在任何支撑衬底上形成第一介电层30,在随后的图的背景下描述第一介电层30的一些实例。
作为实例,为了形成金属化图案32,在第一介电层30上形成晶种层(未示出)。在一些实施例中,晶种层是金属层,其可以是单层或包括由不同材料形成的多个子层的复合层。在一些实施例中,晶种层包括钛层和位于钛层上方的铜层。例如,可以使用物理汽相沉积(PVD)、溅射等形成晶种层。然后在晶种层上形成光刻胶并且图案化光刻胶。光刻胶可以通过旋涂等形成并且可以暴露于光以用于图案化。光刻胶的图案对应于金属化图案32。图案化形成穿过光刻胶的开口以暴露晶种层。金属形成在光刻胶的开口中和晶种层的暴露部分上。可以通过诸如电镀或化学镀等的镀形成金属。该金属可以是铜、镍、钴、钛、钨、铝等。然后,去除光刻胶和其上未形成金属的晶种层的部分。可以通过可接受的灰化或剥离工艺去除光刻胶,诸如使用氧等离子体等。一旦去除光刻胶,诸如通过使用可接受的蚀刻工艺,诸如通过湿蚀刻或干蚀刻,去除晶种层的暴露部分。晶种层的剩余部分和金属形成金属化图案32。
可以通过在周围环境下金属化图案32的金属与氧气的反应来形成原生氧化物34。例如,可以通过当在蚀刻之后清洗金属时金属和水、过氧化氢等之间的反应形成原生氧化物34。此外,可以通过当金属暴露于空气时金属和空气中的氧之间的反应来形成原生氧化物34。可以通过许多方式形成原生氧化物34。
在图2中,在金属化图案32上形成金属氧化物层状结构36。在一些实施例中,金属氧化物层状结构36可以包括原生氧化物34,或者在其他实施例中,可以去除原生氧化物34。关于图4A至图4B、图5A至图5B、图6A至图6B、图7A至图7B以及图8A至图8B示出和讨论了各个金属氧化物层状结构36的实例和进一步的细节。金属氧化物层状结构36包括基本上由比率为基本上1:1(仅为了方便,此后这个比率表示为“Mx:O=1:1”)的金属的原子(诸如金属化图案32的金属的原子)和氧的原子组成的金属氧化物的层。基本上1:1的比率可以包括0.8:1至1.2:1的比率,诸如0.9:1至1.1:1。例如,在一些实施例中,其中金属化图案32是铜,金属氧化物层状结构36包括氧化铜(CuO)的层,并且该层中的铜原子与氧原子的比率为基本上1:1。本领域普通技术人员将容易理解,例如,由于处理,诸如氮和/或碳的其他附带原子可以包括在基本上由比率为基本上1:1的金属的原子和氧的原子组成的金属氧化物的层。
在图3中,在金属氧化物层状结构36和第一介电层30上形成第二介电层38。在一些实施例中,第二介电层38由聚合物形成,聚合物可以是诸如聚苯并恶唑(PBO)、聚酰亚胺、苯并环丁烯(BCB)等的光敏材料。如本文中使用的,光敏材料包括在显影之前是光敏的显影的材料。可以通过诸如旋涂、层压等或它们的组合的任何可接受的沉积工艺形成第二介电层38。
图4A和图4B是根据一些实施例的第一示例金属氧化物层状结构36A和形成金属氧化物层状结构36A的方法。图4A示出了关于图1讨论的金属化图案32,其在图4B的步骤200中形成。如在图1中进一步讨论的,可以在金属化图案32上形成原生氧化物34。在图4B的步骤202中,去除原生氧化物34。该去除可以通过诸如氮气(N2)等离子体工艺的可接受的清洗工艺。在图4B的步骤204中,在金属化图案32上直接形成具有Mx:O=1:1的金属氧化物层40。可以通过以诸如包括氧气(O2)、臭氧(O3)、水(H2O)等或它们的组合的等离子体的含氧等离子体处理金属化图案32来形成金属氧化物层40。含氧等离子体可以包括额外的等离子体物质,诸如氮气(N2)、氢气(H2)、氩气(Ar)等或它们的组合。作为实例,金属化图案32可以是铜,并且金属氧化物层40可以是氧化铜(CuO)。如示出的,金属氧化物层状结构36A由具有Mx:O=1:1的金属氧化物层40组成。在图4B的步骤206中,如关于图3讨论的,在金属氧化物层状结构36A上形成第二介电层38。
图5A和图5B是根据一些实施例的第二示例金属氧化物层状结构36B和形成金属氧化物层状结构36B的方法。图5A示出了关于图1讨论的金属化图案32,其在图5B的步骤210中形成。如在图1中进一步讨论的,可以在金属化图案32上形成原生氧化物34。在图5B的步骤212中,去除原生氧化物34。该去除可以通过诸如氮气(N2)等离子体工艺的可接受的清洗工艺。在图5B的步骤214中,在金属化图案32上直接形成具有Mx:O=1:1的金属氧化物层42。可以通过以诸如包括氧气(O2)、臭氧(O3)、水(H2O)等或它们的组合的等离子体的含氧等离子体处理金属化图案32来形成金属氧化物层42。含氧等离子体可以包括额外的等离子体物质,诸如氮气(N2)、氢气(H2)、氩气(Ar)等或它们的组合。在图5B的步骤216中,在金属氧化物层42上形成原生氧化物44。可以通过将金属化图案32和金属氧化物层42暴露于含氧的周围环境中来形成原生氧化物44,诸如在使用水的清洗工艺期间或通过将结构暴露于空气。作为实例,金属化图案32可以是铜;金属氧化物层42可以是氧化铜(CuO);并且原生氧化物44可以是氧化亚铜(Cu2O)。如示出的,金属氧化物层状结构36B由具有Mx:O=1:1的金属氧化物层42和原生氧化物44组成。在图5B的步骤218中,如关于图3讨论的,在金属氧化物层状结构36B上形成第二介电层38。
图6A和图6B是根据一些实施例的第三示例金属氧化物层状结构36C和形成金属氧化物层状结构36C的方法。图6A示出了关于图1讨论的金属化图案32,其在图6B的步骤220中形成。如在图1中进一步讨论的和在图6B的步骤222中,在金属化图案32上直接形成原生氧化物46。在图6B的步骤224中,在原生氧化物46上直接形成具有Mx:O=1:1的金属氧化物层48。可以通过以诸如包括氧气(O2)、臭氧(O3)、水(H2O)等或它们的组合的等离子体的含氧等离子体处理原生氧化物46和金属化图案32来形成金属氧化物层48。含氧等离子体可以包括额外的等离子体物质,诸如氮气(N2)、氢气(H2)、氩气(Ar)等或它们的组合。作为实例,金属化图案32可以是铜;原生氧化物46可以是氧化亚铜(Cu2O);并且金属氧化物层48可以是氧化铜(CuO)。如示出的,金属氧化物层状结构36C由原生氧化物46和具有Mx:O=1:1的金属氧化物层48组成。在图6B的步骤226中,如关于图3讨论的,在金属氧化物层状结构36C上形成第二介电层38。
图7A和图7B是根据一些实施例的第四示例金属氧化物层状结构36D和形成金属氧化物层状结构36D的方法。图7A示出了关于图1讨论的金属化图案32,其在图7B的步骤230中形成。如在图1中进一步讨论的,可以在金属化图案32上形成原生氧化物34。在图7B的步骤232中,去除原生氧化物34。该去除可以通过诸如氮气(N2)等离子体工艺的可接受的清洗工艺。在图7B的步骤234中,在金属化图案32上直接形成具有Mx:O=1:1的金属氧化物层50。可以通过以诸如包括氧气(O2)、臭氧(O3)、水(H2O)等或它们的组合的等离子体的含氧等离子体处理金属化图案32来形成金属氧化物层50。含氧等离子体可以包括额外的等离子体物质,诸如氮气(N2)、氢气(H2)、氩气(Ar)等或它们的组合。在图7B的步骤236中,在金属氧化物层50上形成原生氧化物52。可以通过将金属化图案32和金属氧化物层50暴露于含氧的周围环境中来形成原生氧化物52,诸如在使用水的清洗工艺期间或通过将结构暴露于空气。在图7B的步骤238中,在原生氧化物52上直接形成具有Mx:O=1:1的金属氧化物层54。可以通过以诸如包括氧气(O2)、臭氧(O3)、水(H2O)等或它们的组合的等离子体的含氧等离子体处理原生氧化物52、金属氧化物层50和金属化图案32来形成金属氧化物层54。含氧等离子体可以包括额外的等离子体物质,诸如氮气(N2)、氢气(H2)、氩气(Ar)等或它们的组合。作为实例,金属化图案32可以是铜;金属氧化物层50可以是氧化铜(CuO);原生氧化物52可以是氧化亚铜(Cu2O);并且金属氧化物层54可以是氧化铜(CuO)。如示出的,金属氧化物层状结构36D由具有Mx:O=1:1的金属氧化物层50、原生氧化物52和具有Mx:O=1:1的金属氧化物层54组成。在图7B的步骤240中,如关于图3讨论的,在金属氧化物层状结构36D上形成第二介电层38。
图8A和图8B是根据一些实施例的第五示例金属氧化物层状结构36E和形成金属氧化物层状结构36E的方法。图8A示出了关于图1讨论的金属化图案32,其在图8B的步骤250中形成。如在图1中进一步讨论的并且在图8B的步骤252中,在金属化图案32上直接形成原生氧化物56。在图8B的步骤254中,在原生氧化物56上直接形成具有Mx:O=1:1的金属氧化物层58。可以通过以诸如包括氧气(O2)、臭氧(O3)、水(H2O)等或它们的组合的等离子体的含氧等离子体处理原生氧化物56和金属化图案32来形成金属氧化物层58。含氧等离子体可以包括额外的等离子体物质,诸如氮气(N2)、氢气(H2)、氩气(Ar)等或它们的组合。在图8B的步骤256中,在金属氧化物层58上形成原生氧化物60。可以通过将金属化图案32和金属氧化物层58暴露于含氧的周围环境中来形成原生氧化物60,诸如在使用水的清洗工艺期间或通过将结构暴露于空气。作为实例,金属化图案32可以是铜;原生氧化物56可以是氧化亚铜(Cu2O);金属氧化物层58可以是氧化铜(CuO);并且原生氧化物60可以是氧化亚铜(Cu2O)。如示出的,金属氧化物层状结构36E由原生氧化物56、具有Mx:O=1:1的金属氧化物层58和原生氧化物60组成。在图8B的步骤258中,如关于图3讨论的,在金属氧化物层状结构36E上形成第二介电层38。
诸如金属氧化物层状结构36A、36B、36C、36D和36E的金属氧化物层状结构36可以促进下面的金属化层和上面的介电层之间的粘合,如上所讨论的,介电层可以是光敏材料。因此,金属氧化物层状结构36可以称为粘合结构。在一些实施例中,金属氧化物层状结构36的厚度大于或等于约诸如在从约至约的范围内,更具体地,在从约至约的范围内。例如,金属氧化物层状结构36的具有Mx:O=1:1的金属氧化物层(诸如金属氧化物层状结构36A的金属氧化物层40)的厚度大于或等于约诸如在从约至约的范围内,更具体地,在从约至约的范围内。已经发现,金属氧化物层状结构36的大于或等于约的厚度增加粘合。
应该注意,虽然已经使用铜、氧化铜和氧化亚铜提供了具体实例,但是可以使用其他金属和氧化物。本领域普通技术人员将容易理解当使用诸如镍、钴、钛、钨、铝等的不同金属时可以使用的各种氧化物。
图9至图23是根据一些实施例的在用于形成封装件上芯片(CoP)和/或叠层封装件(PoP)结构的工艺期间的中间步骤的截面图。图9示出了载体衬底100和形成在载体衬底100上的释放层102。载体衬底100可以是玻璃载体衬底、陶瓷载体衬底等。载体衬底100可以是晶圆,从而使得可以在载体衬底100上同时形成多个封装件。释放层102可以由聚合物基材料形成,其与载体衬底100从将在随后的步骤中形成的上面的结构一起被去除。在一些实施例中,释放层102是环氧基热释放材料(诸如光热转换(LTHC)释放涂层),当被加热时,环氧基热释放材料失去其粘合性。在其他实施例中,释放层102可以是紫外(UV)胶,当暴露于UV光时,UV胶失去其粘合性。释放层102可以作为液体分配并且固化,释放层102可以是层压在载体衬底100上的层压膜等。可以使释放层102的顶面齐平,并且释放层102可以具有高度的共面性。
在图9至图11中,形成后侧再分布结构114。后侧再分布结构包括介电层104和110以及金属化图案106。如图9所示,在释放层102上形成介电层104。介电层104的底面可以与释放层102的顶面接触。在一些实施例中,介电层104由聚合物形成,聚合物可以是诸如PBO、聚酰亚胺、BCB等的光敏材料。可以通过诸如旋涂、层压等或它们的组合的任何可接受的沉积工艺形成介电层104。
在图10中,在介电层104上形成金属化图案106。作为实例,为了形成金属化图案106,在介电层104上方形成晶种层(未示出)。在一些实施例中,晶种层是金属层,其可以是单层或包括由不同材料形成的多个子层的复合层。在一些实施例中,晶种层包括钛层和位于钛层上方的铜层。例如,可以使用PVD、溅射等形成晶种层。然后在晶种层上形成光刻胶并且图案化光刻胶。光刻胶可以通过旋涂等形成并且可以暴露于光以用于图案化。光刻胶的图案对应于金属化图案106。图案化形成穿过光刻胶的开口以暴露晶种层。金属形成在光刻胶的开口中和晶种层的暴露部分上。可以通过诸如电镀或化学镀等的镀形成金属。该金属可以是铜、镍、钴、钛、钨、铝等。然后,去除光刻胶和其上未形成金属的晶种层的部分。可以通过可接受的灰化或剥离工艺去除光刻胶,诸如使用氧等离子体等。一旦去除光刻胶,诸如通过使用可接受的蚀刻工艺,诸如通过湿蚀刻或干蚀刻,去除晶种层的暴露部分。晶种层的剩余部分和金属形成金属化图案106。
然后在金属化图案106的暴露表面上形成金属氧化物层状结构108。金属氧化物层状结构108可以具有图4A、图5A、图6A、图7A和图8A等中示出的任何结构,并且可以通过图4B、图5B、图6B、图7B和图8B等中概述的任何方法形成。
在图11中,在金属化图案106和介电层104上形成介电层110。在一些实施例中,介电层110由聚合物形成,聚合物可以是诸如PBO、聚酰亚胺、BCB等的光敏材料。可以通过旋涂、层压等或它们的组合形成介电层110。然后图案化介电层110以形成开口,从而暴露金属化图案106上的金属氧化物层状结构108的部分112。当介电层110是光敏材料时,图案化可以通过使用光刻掩模将介电层110暴露于光以及随后显影介电层110。可以使用诸如蚀刻的其他图案化技术。
如示出的,后侧再分布结构114包括两个介电层104和110以及一个金属化图案106。在其他实施例中,后侧再分布结构114可以包括任何数量的介电层、金属化图案和通孔。可以通过重复用于形成金属化图案106和介电层110的工艺而在后侧再分布结构114中形成一个或多个额外的金属化图案和介电层。可以在通过在下面的介电层的开口中形成晶种层和金属化图案的金属的金属化图案的形成期间形成通孔。因此,通孔可以互连和电连接各个金属化图案。
在图12中,形成通孔116。作为实例,为了形成通孔116,去除金属氧化物层状结构108的暴露部分112以暴露金属化图案106的部分,以及然后在介电层110和金属化图案106的暴露部分上形成晶种层(未示出)。可以通过溅射蚀刻等去除金属氧化物层状结构108的暴露部分112。在一些实施例中,晶种层是金属层,其可以是单层或包括由不同材料形成的多个子层的复合层。在一些实施例中,晶种层包括钛层和位于钛层上方的铜层。例如,可以使用PVD、溅射等形成晶种层。可以在与形成晶种层的相同的处理室中去除金属氧化物层状结构108的暴露部分112。然后在晶种层上形成光刻胶并且图案化光刻胶。光刻胶可以通过旋涂等形成并且可以暴露于光以用于图案化。光刻胶的图案对应于通孔116。图案化形成穿过光刻胶的开口以暴露晶种层。金属形成在光刻胶的开口中和晶种层的暴露部分上。可以通过诸如电镀或化学镀等的镀形成金属。该金属可以是铜、钛、钨、铝等。然后,去除光刻胶和其上未形成金属的晶种层的部分。可以通过可接受的灰化或剥离工艺去除光刻胶,诸如使用氧等离子体等。一旦去除光刻胶,诸如通过使用可接受的蚀刻工艺,诸如通过湿蚀刻或干蚀刻,去除晶种层的暴露部分。晶种层的剩余部分和金属形成通孔116。由于从金属化图案106去除金属氧化物层状结构108的暴露部分112,在通孔116和金属化图案106之间形成直接金属-金属界面118。
进一步在图12中,集成电路管芯119通过粘合剂120粘合至介电层110。如示出的,一个集成电路管芯119粘合在封装结构中,并且在其他实施例中,多个集成电路管芯可以粘合在封装结构中。在粘合至介电层110之前,可以根据适用的制造工艺处理集成电路管芯119以在集成电路管芯119中形成集成电路。例如,集成电路管芯119包括半导体衬底122。半导体衬底122可以是块状半导体衬底122、绝缘体上半导体(SOI)衬底、多层或梯度衬底等。半导体衬底122的半导体材料可以是掺杂或未掺杂的,并且可以包括元素半导体,诸如硅或锗;化合物或合金半导体,包括SiGe、SiC、GaAs、GaP、InP、InAs、InSb、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP、GaInAsP等;或它们的组合。诸如晶体管、二极管、电容器、电阻器等的器件可以形成在半导体衬底122中和/或上并且可以通过互连结构124互连以形成集成电路,互连结构124由例如半导体衬底122上的一个或多个介电层中的金属化图案形成。
集成电路管芯119还包括诸如铝焊盘的焊盘126,形成至焊盘126的外部连接。焊盘126位于可以称为集成电路管芯119的有源侧的一侧上。钝化膜128位于集成电路管芯119和焊盘126的部分上。开口穿过钝化膜128至焊盘126。诸如导电柱(例如,包括诸如铜的金属)的管芯连接件130位于穿过钝化膜128的开口中并且机械和电连接至相应的焊盘126。例如,可以通过镀等形成管芯连接件130。管芯连接件130电连接集成电路管芯119的集成电路。
介电材料132位于集成电路管芯119的有源侧上,诸如位于钝化膜128和管芯连接件130上。介电材料132横向包封管芯连接件130,并且介电材料132与集成电路管芯119横向共末端。介电材料132可以是诸如PBO、聚酰亚胺、BCB等的聚合物;诸如氮化硅等的氮化物;诸如氧化硅、PSG、BSG、BPSG等的氧化物;或它们的组合,并且可以例如通过旋涂、层压、CVD等形成。
粘合剂120位于集成电路管芯119的后侧上并且将集成电路管芯119粘合至后侧再分布结构114,诸如示出的介电层110。粘合剂120可以是任何合适的粘合剂、环氧化物等。粘合剂可以施加至集成电路管芯119的后侧,诸如施加至相应的半导体晶圆的后侧。诸如通过锯切或切割,可以分割集成电路管芯119,并且使用例如拾放工具通过粘合剂120将集成电路管芯119粘合至介电层110。
在图13中,在各个组件上形成包封剂134。包封剂134可以是模塑料、环氧化物等,并且可以通过压缩模制、传递模制等施加。在固化之后,包封剂134可以经受研磨工艺以暴露通孔116和管芯连接件130。在研磨工艺之后,通孔116、管芯连接件130和包封剂134的顶面可以共面。在一些实施例中,例如,如果通孔116和管芯连接件130已经暴露,则可以省略研磨。
在图14至图20中,形成前侧再分布结构166。如将在图20中示出的,前侧再分布结构166包括介电层136、142、152和162以及金属化图案138、146和156。
在图14中,在包封剂134、通孔116和管芯连接件130上形成介电层136。在一些实施例中,介电层136由聚合物形成,聚合物可以是诸如PBO、聚酰亚胺、BCB等的光敏材料。可以通过旋涂、层压等或它们的组合形成介电层136。然后图案化介电层136以形成开口,从而暴露通孔116和管芯连接件130的部分。当介电层136是光敏材料时,图案化可以通过使用光刻掩模将介电层136暴露于光以及随后显影介电层136。可以使用诸如蚀刻的其他图案化技术。
在图15中,在介电层136上形成具有通孔的金属化图案138。作为实例,为了形成金属化图案138,在介电层136上方和在穿过介电层136的开口中形成晶种层(未示出)。在一些实施例中,晶种层是金属层,其可以是单层或包括由不同材料形成的多个子层的复合层。在一些实施例中,晶种层包括钛层和位于钛层上方的铜层。例如,可以使用PVD等形成晶种层。然后在晶种层上形成光刻胶并且图案化光刻胶。光刻胶可以通过旋涂等形成并且可以暴露于光以用于图案化。光刻胶的图案对应于金属化图案138。图案化形成穿过光刻胶的开口以暴露晶种层。金属形成在光刻胶的开口中和晶种层的暴露部分上。可以通过诸如电镀或化学镀等的镀形成金属。该金属可以包括金属,如铜、镍、钴、钛、钨、铝等。然后,去除光刻胶和其上未形成金属的晶种层的部分。可以通过可接受的灰化或剥离工艺去除光刻胶,诸如使用氧等离子体等。一旦去除光刻胶,诸如通过使用可接受的蚀刻工艺,诸如通过湿蚀刻或干蚀刻,去除晶种层的暴露部分。晶种层的剩余部分和金属形成金属化图案138和通孔。通孔形成在穿过介电层136至例如通孔116和/或管芯连接件130的开口中。
然后在金属化图案138的暴露表面上形成金属氧化物层状结构140。金属氧化物层状结构140可以具有图4A、图5A、图6A、图7A和图8A等中示出的任何结构,并且可以通过图4B、图5B、图6B、图7B和图8B等中概述的任何方法形成。
在图16中,在金属化图案138和介电层136上形成介电层142。在一些实施例中,介电层142由聚合物形成,聚合物可以是诸如PBO、聚酰亚胺、BCB等的光敏材料。可以通过旋涂、层压等或它们的组合形成介电层142。然后图案化介电层142以形成开口,从而暴露金属化图案138上的金属氧化物层状结构140的部分144。当介电层142是光敏材料时,图案化可以通过使用光刻掩模将介电层142暴露于光以及随后显影介电层142。可以使用诸如蚀刻的其他图案化技术。
在图17中,在介电层142上形成具有通孔的金属化图案146。作为实例,为了形成金属化图案146,去除金属氧化物层状结构140的暴露部分144以暴露金属化图案138的部分,以及然后在介电层142和金属化图案138的暴露部分上形成晶种层(未示出)。可以通过溅射蚀刻等去除金属氧化物层状结构140的暴露部分144。在一些实施例中,晶种层是金属层,其可以是单层或包括由不同材料形成的多个子层的复合层。在一些实施例中,晶种层包括钛层和位于钛层上方的铜层。例如,可以使用PVD、溅射等形成晶种层。然后可以在与形成晶种层的相同的处理室中去除金属氧化物层状结构140的暴露部分144。然后在晶种层上形成光刻胶并且图案化光刻胶。光刻胶可以通过旋涂等形成并且可以暴露于光以用于图案化。光刻胶的图案对应于金属化图案146。图案化形成穿过光刻胶的开口以暴露晶种层。金属形成在光刻胶的开口中和晶种层的暴露部分上。可以通过诸如电镀或化学镀等的镀形成金属。该金属可以是铜、镍、钴、钛、钨、铝等。然后,去除光刻胶和其上未形成金属的晶种层的部分。可以通过可接受的灰化或剥离工艺去除光刻胶,诸如使用氧等离子体等。一旦去除光刻胶,诸如通过使用可接受的蚀刻工艺,诸如通过湿蚀刻或干蚀刻,去除晶种层的暴露部分。晶种层的剩余部分和金属形成金属化图案146和通孔。通孔形成在穿过介电层142至例如金属化图案138的部分的开口中。由于从金属化图案138去除金属氧化物层状结构140的部分144,在金属化图案146的通孔和金属化图案138之间形成直接金属-金属界面148。
然后在金属化图案146的暴露表面上形成金属氧化物层状结构150。金属氧化物层状结构150可以具有图4A、图5A、图6A、图7A和图8A等中示出的任何结构,并且可以通过图4B、图5B、图6B、图7B和图8B等中概述的任何方法形成。
在图18中,在金属化图案146和介电层142上形成介电层152。在一些实施例中,介电层152由聚合物形成,聚合物可以是诸如PBO、聚酰亚胺、BCB等的光敏材料。可以通过旋涂、层压等或它们的组合形成介电层152。然后图案化介电层152以形成开口,从而暴露金属化图案146上的金属氧化物层状结构150的部分154。当介电层152是光敏材料时,图案化可以通过使用光刻掩模将介电层152暴露于光以及随后显影介电层152。可以使用诸如蚀刻的其他图案化技术。
在图19中,在介电层152上形成具有通孔的金属化图案156。作为实例,为了形成金属化图案156,去除金属氧化物层状结构150的暴露部分154以暴露金属化图案146的部分,以及然后在介电层152和金属化图案146的暴露部分上形成晶种层(未示出)。可以通过溅射蚀刻等去除金属氧化物层状结构150的暴露部分154。在一些实施例中,晶种层是金属层,其可以是单层或包括由不同材料形成的多个子层的复合层。在一些实施例中,晶种层包括钛层和位于钛层上方的铜层。例如,可以使用PVD、溅射等形成晶种层。可以在与形成晶种层的相同的处理室中去除金属氧化物层状结构150的暴露部分154。然后在晶种层上形成光刻胶并且图案化光刻胶。光刻胶可以通过旋涂等形成并且可以暴露于光以用于图案化。光刻胶的图案对应于金属化图案156。图案化形成穿过光刻胶的开口以暴露晶种层。金属形成在光刻胶的开口中和晶种层的暴露部分上。可以通过诸如电镀或化学镀等的镀形成金属。该金属可以是铜、镍、钴、钛、钨、铝等。然后,去除光刻胶和其上未形成金属的晶种层的部分。可以通过可接受的灰化或剥离工艺去除光刻胶,诸如使用氧等离子体等。一旦去除光刻胶,诸如通过使用可接受的蚀刻工艺,诸如通过湿蚀刻或干蚀刻,去除晶种层的暴露部分。晶种层的剩余部分和金属形成金属化图案156和通孔。通孔形成在穿过介电层152至例如金属化图案146的部分的开口中。由于从金属化图案146去除金属氧化物层状结构150的部分154,在金属化图案156的通孔和金属化图案146之间形成直接金属-金属界面158。
然后在金属化图案156的暴露表面上形成金属氧化物层状结构160。金属氧化物层状结构160可以具有图4A、图5A、图6A、图7A和图8A等中示出的任何结构,并且可以通过图4B、图5B、图6B、图7B和图8B等中概述的任何方法形成。
在图20中,在金属化图案156和介电层152上形成介电层162。在一些实施例中,介电层162由聚合物形成,聚合物可以是诸如PBO、聚酰亚胺、BCB等的光敏材料。可以通过旋涂、层压等或它们的组合形成介电层162。然后图案化介电层162以形成开口,从而暴露金属化图案156上的金属氧化物层状结构160的部分164。当介电层162是光敏材料时,图案化可以通过使用光刻掩模将介电层162暴露于光以及随后显影介电层162。可以使用诸如蚀刻的其他图案化技术。
前侧再分布结构166示出为实例。可以在前侧再分布结构166中形成更多或更少的介电层和金属化图案。如果形成更少的介电层和金属化图案,则可以省略以上讨论的步骤和工艺。如果形成更多的介电层和金属化图案,则可以重复以上讨论的步骤和工艺。本领域普通技术人员将容易理解可以省略或重复哪些步骤和工艺。
在图21中,在前侧再分布结构166的外侧上形成可以称为凸块下金属化(UBM)的焊盘168。在示出的实施例中,通过穿过介电层162至金属化图案156的开口形成焊盘168。作为实例,为了形成焊盘168,去除金属氧化物层状结构160的暴露部分164以暴露金属化图案156的部分,以及然后在介电层162和金属化图案156的暴露部分上形成晶种层(未示出)。可以通过溅射蚀刻等去除金属氧化物层状结构160的暴露部分164。在一些实施例中,晶种层是金属层,其可以是单层或包括由不同材料形成的多个子层的复合层。在一些实施例中,晶种层包括钛层和位于钛层上方的铜层。例如,可以使用PVD、溅射等形成晶种层。可以在与形成晶种层的相同的处理室中去除金属氧化物层状结构160的暴露部分164。然后在晶种层上形成光刻胶并且图案化光刻胶。光刻胶可以通过旋涂等形成并且可以暴露于光以用于图案化。光刻胶的图案对应于焊盘168。图案化形成穿过光刻胶的开口以暴露晶种层。金属形成在光刻胶的开口中和晶种层的暴露部分上。可以通过诸如电镀或化学镀等的镀形成金属。该金属可以是铜、钛、钨、铝等。然后,去除光刻胶和其上未形成金属的晶种层的部分。可以通过可接受的灰化或剥离工艺去除光刻胶,诸如使用氧等离子体等。一旦去除光刻胶,诸如通过使用可接受的蚀刻工艺,诸如通过湿蚀刻或干蚀刻,去除晶种层的暴露部分。晶种层的剩余部分和金属形成焊盘168。焊盘168形成在穿过介电层162至例如金属化图案156的部分的开口中。由于从金属化图案156去除金属氧化物层状结构160的部分164,在焊盘168和金属化图案156之间形成直接金属-金属界面170。
在图22中,在焊盘168上形成外部电连接件172,诸如焊球,如球栅阵列(BGA)球。外部电连接件172可以包括诸如焊料的可低温重回流材料,其可以是无铅的或含铅的。可以通过使用适当的球落工艺形成外部电连接件172。在一些实施例中,可以省略焊盘168,并且外部电连接件172可以通过穿过介电层162的开口直接形成在金属化图案156上。
在图23中,实施载体衬底脱粘以使载体衬底100从后侧再分布结构114(例如,介电层104)分离(脱粘)。根据一些实施例,脱粘包括将诸如激光或UV光的光投射到释放层102上,从而使得释放层102在光的热量下分解,并且可以去除载体衬底100。然后将结构翻转并且放置在胶带174上。形成穿过介电层104的开口以暴露金属化图案106的部分。例如,可以使用激光钻孔、蚀刻等形成开口。
虽然未具体示出,本领域普通技术人员将容易理解,也在载体衬底100(可以是晶圆)的其他区域中同时形成图9至图23中形成的结构。因此,诸如通过锯切实施分割工艺以将单个封装件180从已经与封装件180同时形成的其他封装件分割。
如图24至图27中示出的,封装件180可以合并入各种封装件上芯片(CoP)和叠层封装件(PoP)结构。图24至图27是示例结构,并且封装件180可以合并入任何封装结构。在图24至图27中,封装件180附接至衬底182。外部电连接件172电连接和机械连接至衬底182上的焊盘184。例如,衬底182可以是印刷电路板(PCB)等。
在图24中,集成电路管芯300(或芯片)通过外部电连接件302附接至封装件180的后侧再分布结构114。集成电路管芯300可以是诸如逻辑管芯、模拟管芯、存储管芯等的任何集成电路管芯。集成电路管芯300通过外部电连接件302电连接和机械连接至后侧再分布结构114,外部电连接件302通过穿过介电层104的开口附接至金属化图案106。外部电连接件302可以包括诸如焊料的可低温重回流材料,诸如无铅焊料,并且在额外的实施例中,外部电连接件302可以包括金属柱。在一些实施例中,外部电连接件302是可控塌陷芯片连接(C4)凸块、微凸块等。在一些实施例中,可以回流外部电连接件302以将集成电路管芯300附接至封装件180。也可以在集成电路管芯300和封装件180的后侧再分布结构114之间以及外部电连接件302周围分配底部填充材料304。
在图25中,封装组件310通过外部电连接件312附接至封装件180的后侧再分布结构114。该实例中的封装组件310包括附接至中介板的集成电路管芯倒装芯片。集成电路管芯可以是诸如逻辑管芯、模拟管芯、存储管芯等的任何集成电路管芯。封装组件310通过外部电连接件312电连接和机械连接至后侧再分布结构114,外部电连接件312通过穿过介电层104的开口附接至金属化图案106。外部电连接件312可以包括诸如焊料的可低温重回流材料,诸如无铅焊料,并且在额外的实施例中,外部电连接件312可以包括金属柱。在一些实施例中,外部电连接件312是C4凸块、微凸块等。在一些实施例中,可以回流外部电连接件312以将封装组件310附接至封装件180。
在图26中,封装件320通过外部电连接件322附接至封装件180的后侧再分布结构114。封装件320包括衬底、位于衬底上的两个堆叠的集成电路管芯、将集成电路管芯电连接至衬底的引线接合以及包封堆叠的集成电路管芯和引线接合的包封剂。在实例中,封装件320的集成电路管芯是诸如动态随机存取存储器(DRAM)管芯的存储管芯。封装件320通过外部电连接件322电连接和机械连接至后侧再分布结构114,外部电连接件322通过穿过介电层104的开口附接至金属化图案106。在一些实施例中,外部电连接件322可以包括诸如焊料的可低温重回流材料,诸如无铅焊料,并且在额外的实施例中,外部电连接件322可以包括金属柱。在一些实施例中,外部电连接件322是C4凸块、微凸块等。在一些实施例中,可以回流外部电连接件322以将封装件320附接至金属化图案106。例如,封装件320的集成电路管芯通过封装件320中的引线接合和衬底、外部电连接件322、后侧再分布结构114、通孔116和前侧再分布结构166电连接和机械连接至集成电路管芯119。
在图27中,封装件330通过外部电连接件332附接至封装件180的后侧再分布结构114。封装件330可以类似于封装件180并且可以通过类似的工艺形成。例如,与封装件180相比,封装件330省略了后侧再分布结构和通孔。在实例中,封装件330的集成电路管芯可以是逻辑管芯、模拟管芯、诸如动态随机存取存储器(DRAM)管芯的存储管芯等。封装件330通过外部电连接件332电连接和机械连接至后侧再分布结构114,外部电连接件332通过穿过介电层104的开口附接至金属化图案106。在一些实施例中,外部电连接件332可以包括诸如焊料的可低温重回流材料,诸如无铅焊料,并且在额外的实施例中,外部电连接件332可以包括金属柱。在一些实施例中,外部电连接件332是C4凸块、微凸块等。在一些实施例中,可以回流外部电连接件332以将封装件330附接至金属化图案106。例如,封装件330的集成电路管芯通过封装件330的前侧再分布结构、外部电连接件332、后侧再分布结构114、通孔116和前侧再分布结构166电连接和机械连接至集成电路管芯119。
实施例可以实现一些优势。例如,通过在金属化图案上以及在金属化图案和介电层(诸如光敏介电材料)之间提供金属氧化物层状结构,可以改进粘合。该改进的粘合可以降低金属化图案和介电层之间的分层的风险。
一个实施例是一种结构,该结构包括至少由包封剂横向包封的集成电路管芯以及位于集成电路管芯和包封剂上的再分布结构。再分布结构电连接至集成电路管芯。再分布结构包括位于至少包封剂上的第一介电层、位于第一介电层上的金属化图案、位于金属化图案上的金属氧化物层状结构、以及位于第一介电层和金属化图案上的第二介电层。金属氧化物层状结构包括具有基本上1:1的金属原子与氧原子的比率的金属氧化物层,并且金属氧化物层状结构的厚度为至少第二介电层是光敏材料。金属氧化物层状结构设置在金属化图案和第二介电层之间。
在上述结构中,其中,所述金属氧化物层状结构基本上由所述金属氧化物层组成,所述金属氧化物层直接邻接所述金属化图案。
在上述结构中,其中,所述金属氧化物层状结构还包括原生氧化物层,所述原生氧化物层直接邻接所述金属化图案,所述金属氧化物层直接邻接所述原生氧化物层。
在上述结构中,其中,所述金属氧化物层状结构还包括原生氧化物层,所述金属氧化物层直接邻接所述金属化图案,所述原生氧化物层直接邻接所述金属氧化物层。
在上述结构中,其中,所述厚度不大于
在上述结构中,其中,所述厚度不大于
在上述结构中,其中,所述金属氧化物层的厚度在从至的范围内。
在上述结构中,其中,所述金属氧化物层的厚度在从至的范围内。
一个实施例是一种结构,该结构包括集成电路管芯、至少横向包封集成电路管芯的包封剂、位于包封剂和集成电路管芯的有源侧上的第一介电层、位于第一介电层上的金属化图案、位于金属化图案上的粘合层、以及位于第一介电层和粘合层上的第二介电层。金属化图案电连接至集成电路管芯的有源侧。粘合层包括具有基本上1:1的金属原子与氧原子的比率的金属氧化物层,并且粘合层的厚度为至少第二介电层是光敏材料。
在上述结构中,其中,所述金属氧化物层直接邻接所述金属化图案。
在上述结构中,其中,所述粘合层还包括原生氧化物层,所述原生氧化物层直接邻接所述金属化图案,所述金属氧化物层直接邻接所述原生氧化物层。
在上述结构中,其中,所述厚度不大于
在上述结构中,其中,所述厚度不大于
在上述结构中,其中,所述金属氧化物层的厚度在从至的范围内。
在上述结构中,其中,所述金属氧化物层的厚度在从至的范围内。
另一实施例是一种方法。该方法包括以包封剂包封集成电路管芯;在包封剂和集成电路管芯上方形成介电层;在介电层上方形成金属化图案;以含氧等离子体处理金属化图案,该处理在金属化图案上方形成具有基本上1:1的金属原子与氧原子的比率的金属氧化物层,金属氧化物层的厚度为至少以及在金属氧化物层上方形成光敏材料。
在上述方法中,还包括:在处理所述金属化图案之前,从所述金属化图案去除原生氧化物。
在上述方法中,其中,处理所述金属化图案在原生氧化物上形成所述金属氧化物层,所述原生氧化物设置在所述金属化图案和所述金属氧化物层之间。
在上述方法中,其中,所述厚度不大于
在上述方法中,其中,所述厚度不大于
上面概述了若干实施例的特征,使得本领域技术人员可以更好地理解本发明的方面。本领域技术人员应该理解,他们可以容易地使用本发明作为基础来设计或修改用于实施与本文所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到,这种等同构造并不背离本发明的精神和范围,并且在不背离本发明的精神和范围的情况下,本文中他们可以做出多种变化、替换以及改变。
Claims (10)
1.一种结构,包括:
集成电路管芯,至少由包封剂横向包封;
再分布结构,位于所述集成电路管芯和所述包封剂上,所述再分布结构电连接至所述集成电路管芯,所述再分布结构包括:
第一介电层,至少位于所述包封剂上,
金属化图案,位于所述第一介电层上,
金属氧化物层状结构,位于所述金属化图案上,所述金属氧化物层状结构包括具有基本上1:1的金属原子与氧原子的比率的金属氧化物层,所述金属氧化物层状结构的厚度为至少以及
第二介电层,位于所述第一介电层和所述金属化图案上,所述第二介电层是光敏材料,所述金属氧化物层状结构设置在所述金属化图案和所述第二介电层之间。
2.根据权利要求1所述的结构,其中,所述金属氧化物层状结构基本上由所述金属氧化物层组成,所述金属氧化物层直接邻接所述金属化图案。
3.根据权利要求1所述的结构,其中,所述金属氧化物层状结构还包括原生氧化物层,所述原生氧化物层直接邻接所述金属化图案,所述金属氧化物层直接邻接所述原生氧化物层。
4.根据权利要求1所述的结构,其中,所述金属氧化物层状结构还包括原生氧化物层,所述金属氧化物层直接邻接所述金属化图案,所述原生氧化物层直接邻接所述金属氧化物层。
5.根据权利要求1所述的结构,其中,所述厚度不大于
6.根据权利要求1所述的结构,其中,所述厚度不大于
7.根据权利要求1所述的结构,其中,所述金属氧化物层的厚度在从至的范围内。
8.根据权利要求1所述的结构,其中,所述金属氧化物层的厚度在从至的范围内。
9.一种结构,包括:
集成电路管芯;
包封剂,至少横向包封所述集成电路管芯;
第一介电层,位于所述包封剂和所述集成电路管芯的有源侧上;
金属化图案,位于所述第一介电层上,所述金属化图案电连接至所述集成电路管芯的有源侧;
粘合层,位于所述金属化图案上,所述粘合层包括具有基本上1:1的金属原子与氧原子的比率的金属氧化物层,所述粘合层的厚度为至少以及
第二介电层,位于所述第一介电层和所述粘合层上,所述第二介电层是光敏材料。
10.一种方法,包括:
以包封剂包封集成电路管芯;
在所述包封剂和所述集成电路管芯上方形成介电层;
在所述介电层上方形成金属化图案;
以含氧等离子体处理所述金属化图案,所述处理在所述金属化图案上方形成具有基本上1:1的金属原子与氧原子的比率的金属氧化物层,所述金属氧化物层的厚度为至少以及
在所述金属氧化物层上方形成光敏材料。
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201562116170P | 2015-02-13 | 2015-02-13 | |
US62/116,170 | 2015-02-13 | ||
US14/697,380 | 2015-04-27 | ||
US14/697,380 US10153175B2 (en) | 2015-02-13 | 2015-04-27 | Metal oxide layered structure and methods of forming the same |
Publications (2)
Publication Number | Publication Date |
---|---|
CN105895616A true CN105895616A (zh) | 2016-08-24 |
CN105895616B CN105895616B (zh) | 2019-03-08 |
Family
ID=56551915
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201510768173.2A Active CN105895616B (zh) | 2015-02-13 | 2015-11-11 | 金属氧化物层状结构及其形成方法 |
Country Status (5)
Country | Link |
---|---|
US (5) | US10153175B2 (zh) |
KR (1) | KR101761008B1 (zh) |
CN (1) | CN105895616B (zh) |
DE (1) | DE102015109751B4 (zh) |
TW (1) | TWI612594B (zh) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN113223970A (zh) * | 2020-04-29 | 2021-08-06 | 台湾积体电路制造股份有限公司 | 半导体结构及其制造方法 |
US11948930B2 (en) | 2020-04-29 | 2024-04-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor package and method of manufacturing the same |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10153175B2 (en) * | 2015-02-13 | 2018-12-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Metal oxide layered structure and methods of forming the same |
US9832865B2 (en) * | 2016-04-26 | 2017-11-28 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Methods and devices for providing increased routing flexibility in multi-layer printed circuit boards |
US10014260B2 (en) | 2016-11-10 | 2018-07-03 | Taiwan Semiconductor Manufacturing Co., Ltd. | Package structure and method for forming the same |
US10269587B2 (en) | 2017-06-30 | 2019-04-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit packages and methods of forming same |
CN107507816A (zh) * | 2017-08-08 | 2017-12-22 | 中国电子科技集团公司第五十八研究所 | 扇出型晶圆级多层布线封装结构 |
US11101209B2 (en) * | 2017-09-29 | 2021-08-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Redistribution structures in semiconductor packages and methods of forming same |
DE102018106038A1 (de) | 2017-11-15 | 2019-05-16 | Taiwan Semiconductor Manufacturing Co., Ltd. | Integrierte schaltkreis-packages und verfahren zu deren herstellung |
US11410918B2 (en) * | 2017-11-15 | 2022-08-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of making an integrated circuit package including an integrated circuit die soldered to a bond pad of a carrier |
KR102486561B1 (ko) | 2017-12-06 | 2023-01-10 | 삼성전자주식회사 | 재배선의 형성 방법 및 이를 이용하는 반도체 소자의 제조 방법 |
KR102395199B1 (ko) | 2018-02-22 | 2022-05-06 | 삼성전자주식회사 | 반도체 패키지 |
CN110429089B (zh) * | 2019-08-15 | 2023-02-03 | 京东方科技集团股份有限公司 | 驱动背板及其制作方法、显示装置 |
US11791332B2 (en) * | 2021-02-26 | 2023-10-17 | Taiwan Semiconductor Manufacturing Co., Ltd. | Stacked semiconductor device and method |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20090261466A1 (en) * | 2006-11-10 | 2009-10-22 | Stats Chippac, Ltd. | Semiconductor Device and Method of Forming Vertical Interconnect Structure Using Stud Bumps |
CN101570854A (zh) * | 2008-04-28 | 2009-11-04 | 财团法人工业技术研究院 | 图案化金属氧化物层的制作方法 |
US20100308449A1 (en) * | 2009-06-03 | 2010-12-09 | Hung-Jen Yang | Semiconductor packages and manufacturing method thereof |
US20130171774A1 (en) * | 2010-03-22 | 2013-07-04 | Chia-Ching Chen | Stackable semiconductor package and manufacturing method thereof |
US20140264853A1 (en) * | 2013-03-12 | 2014-09-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Adhesion between Post-Passivation Interconnect Structure and Polymer |
Family Cites Families (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4998157A (en) * | 1988-08-06 | 1991-03-05 | Seiko Epson Corporation | Ohmic contact to silicon substrate |
US5565378A (en) * | 1992-02-17 | 1996-10-15 | Mitsubishi Denki Kabushiki Kaisha | Process of passivating a semiconductor device bonding pad by immersion in O2 or O3 solution |
US5753975A (en) * | 1994-09-01 | 1998-05-19 | Kabushiki Kaisha Toshiba | Semiconductor device with improved adhesion between titanium-based metal wiring layer and insulation film |
US5989999A (en) * | 1994-11-14 | 1999-11-23 | Applied Materials, Inc. | Construction of a tantalum nitride film on a semiconductor wafer |
US6155198A (en) * | 1994-11-14 | 2000-12-05 | Applied Materials, Inc. | Apparatus for constructing an oxidized film on a semiconductor wafer |
US6707152B1 (en) | 1999-04-16 | 2004-03-16 | Micron Technology, Inc. | Semiconductor device, electrical conductor system, and method of making |
JP2002321970A (ja) | 2001-04-25 | 2002-11-08 | Murata Mfg Co Ltd | セラミック焼結体の製造方法および積層型セラミック電子部品の製造方法 |
KR20060000106A (ko) | 2004-06-28 | 2006-01-06 | 삼성전자주식회사 | 최외곽 수지층의 접착성을 향상시킨 인쇄 회로 기판과 그제조방법, 그 인쇄 회로 기판을 포함하는 반도체 패키지및 그 제조방법 |
US8592992B2 (en) | 2011-12-14 | 2013-11-26 | Stats Chippac, Ltd. | Semiconductor device and method of forming vertical interconnect structure with conductive micro via array for 3-D Fo-WLCSP |
JP5229026B2 (ja) | 2009-03-16 | 2013-07-03 | セイコーエプソン株式会社 | 発光素子、発光装置、表示装置および電子機器 |
US7939421B2 (en) | 2009-07-08 | 2011-05-10 | Nanya Technology Corp. | Method for fabricating integrated circuit structures |
JP5355504B2 (ja) | 2009-07-30 | 2013-11-27 | 株式会社東芝 | 半導体装置の製造方法および半導体装置 |
US9355975B2 (en) | 2010-05-11 | 2016-05-31 | Xintec Inc. | Chip package and method for forming the same |
US9818734B2 (en) * | 2012-09-14 | 2017-11-14 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming build-up interconnect structures over a temporary substrate |
US9087832B2 (en) | 2013-03-08 | 2015-07-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Warpage reduction and adhesion improvement of semiconductor die package |
TWI523171B (zh) | 2013-07-24 | 2016-02-21 | 精材科技股份有限公司 | 晶片封裝體及其製造方法 |
US9159556B2 (en) * | 2013-09-09 | 2015-10-13 | GlobalFoundries, Inc. | Alleviation of the corrosion pitting of chip pads |
US10153175B2 (en) * | 2015-02-13 | 2018-12-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Metal oxide layered structure and methods of forming the same |
-
2015
- 2015-04-27 US US14/697,380 patent/US10153175B2/en active Active
- 2015-06-18 DE DE102015109751.6A patent/DE102015109751B4/de active Active
- 2015-08-21 KR KR1020150118040A patent/KR101761008B1/ko active IP Right Grant
- 2015-11-11 CN CN201510768173.2A patent/CN105895616B/zh active Active
- 2015-11-24 TW TW104138927A patent/TWI612594B/zh active
-
2018
- 2018-07-31 US US16/051,273 patent/US10658195B2/en active Active
-
2020
- 2020-05-18 US US16/876,938 patent/US11443957B2/en active Active
-
2022
- 2022-07-20 US US17/869,150 patent/US11854826B2/en active Active
-
2023
- 2023-11-29 US US18/523,457 patent/US20240096642A1/en active Pending
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20090261466A1 (en) * | 2006-11-10 | 2009-10-22 | Stats Chippac, Ltd. | Semiconductor Device and Method of Forming Vertical Interconnect Structure Using Stud Bumps |
CN101570854A (zh) * | 2008-04-28 | 2009-11-04 | 财团法人工业技术研究院 | 图案化金属氧化物层的制作方法 |
US20100308449A1 (en) * | 2009-06-03 | 2010-12-09 | Hung-Jen Yang | Semiconductor packages and manufacturing method thereof |
US20130171774A1 (en) * | 2010-03-22 | 2013-07-04 | Chia-Ching Chen | Stackable semiconductor package and manufacturing method thereof |
US20140264853A1 (en) * | 2013-03-12 | 2014-09-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Adhesion between Post-Passivation Interconnect Structure and Polymer |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN113223970A (zh) * | 2020-04-29 | 2021-08-06 | 台湾积体电路制造股份有限公司 | 半导体结构及其制造方法 |
US11948930B2 (en) | 2020-04-29 | 2024-04-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor package and method of manufacturing the same |
CN113223970B (zh) * | 2020-04-29 | 2024-04-05 | 台湾积体电路制造股份有限公司 | 半导体结构及其制造方法 |
Also Published As
Publication number | Publication date |
---|---|
US20240096642A1 (en) | 2024-03-21 |
US10153175B2 (en) | 2018-12-11 |
US20180337062A1 (en) | 2018-11-22 |
US10658195B2 (en) | 2020-05-19 |
US11443957B2 (en) | 2022-09-13 |
US11854826B2 (en) | 2023-12-26 |
US20200279750A1 (en) | 2020-09-03 |
KR101761008B1 (ko) | 2017-07-24 |
US20160240480A1 (en) | 2016-08-18 |
DE102015109751B4 (de) | 2022-07-28 |
US20220359223A1 (en) | 2022-11-10 |
TWI612594B (zh) | 2018-01-21 |
TW201703162A (zh) | 2017-01-16 |
DE102015109751A1 (de) | 2016-08-18 |
KR20160100196A (ko) | 2016-08-23 |
CN105895616B (zh) | 2019-03-08 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN105895616B (zh) | 金属氧化物层状结构及其形成方法 | |
CN107068669B (zh) | 半导体装置封装以及半导体封装及其制造方法 | |
KR102103531B1 (ko) | 패키지 구조와 그 형성 방법 | |
US10515930B2 (en) | Three-layer package-on-package structure and method forming same | |
US9082636B2 (en) | Packaging methods and structures for semiconductor devices | |
TWI630664B (zh) | 封裝結構及其形成方法 | |
US11282761B2 (en) | Semiconductor packages and methods of manufacturing the same | |
US9034730B2 (en) | Recessed semiconductor substrates and associated techniques | |
US9991190B2 (en) | Packaging with interposer frame | |
KR102591618B1 (ko) | 반도체 패키지 및 반도체 패키지의 제조 방법 | |
US20160056087A1 (en) | Package-on-package structure with organic interposer | |
CN107818974A (zh) | 具有伪连接件的半导体封装件及其形成方法 | |
US20160343694A1 (en) | Semiconductor package assembly and method for forming the same | |
CN105374693A (zh) | 半导体封装件及其形成方法 | |
CN105789062A (zh) | 封装件结构及其形成方法 | |
KR101605600B1 (ko) | 반도체 디바이스의 제조 방법 및 이에 따른 반도체 디바이스 | |
CN103681367A (zh) | 封装方法和封装器件 | |
US9870975B1 (en) | Chip package with thermal dissipation structure and method for forming the same | |
KR20150091932A (ko) | 반도체 디바이스의 제조 방법 및 이에 따른 반도체 디바이스 | |
CN105428329A (zh) | 具有ubm的封装件和形成方法 | |
US20140127857A1 (en) | Carrier Wafers, Methods of Manufacture Thereof, and Packaging Methods | |
TW201630121A (zh) | 封裝結構及其形成方法 | |
US10559495B2 (en) | Methods for processing semiconductor dice and fabricating assemblies incorporating same | |
KR102491905B1 (ko) | 패키지 및 그 제조 방법 | |
KR102457349B1 (ko) | 반도체 패키지들 및 이의 제조 방법들 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |