CN107507816A - 扇出型晶圆级多层布线封装结构 - Google Patents

扇出型晶圆级多层布线封装结构 Download PDF

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CN107507816A
CN107507816A CN201710668576.9A CN201710668576A CN107507816A CN 107507816 A CN107507816 A CN 107507816A CN 201710668576 A CN201710668576 A CN 201710668576A CN 107507816 A CN107507816 A CN 107507816A
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pinboard
multilayer wiring
semiconductor chip
interconnection
perpendicular interconnection
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吉勇
张荣臻
毛冲冲
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CETC 58 Research Institute
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CETC 58 Research Institute
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Priority to CN201710668576.9A priority Critical patent/CN107507816A/zh
Publication of CN107507816A publication Critical patent/CN107507816A/zh
Priority to US16/044,496 priority patent/US10580755B2/en
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Abstract

本发明实施例涉及集成电路的封装领域。一种扇出型晶圆级多层布线封装结构，包括一个扇出型晶圆级半导体芯片封装体，以及封装体底部的焊球阵列，所述的扇出型晶圆级半导体芯片封装体的半导体芯片背面与多层布线转接板背面由粘接材料键合在一起形成特征组件，垂直互连转接板与特征组件通过粘接材料集成为一个封装体，在所得封装体的上下表面分别制作再布线层、装配焊球。通过再布线层的导电金属层连接半导体芯片、多层布线转接板与垂直互连转接板中的导电材料及焊球，实现半导体芯片与多层布线转接板之间的信号互连以及半导体芯片信号引出端的转移。

Description

扇出型晶圆级多层布线封装结构
技术领域
本发明涉及集成电路的封装技术领域，特别是涉及扇出型晶圆级封装领域。
背景技术
扇出型晶圆级封装技术作为实现电子系统元器件小型化和低成本应用的解决途径，目前正在发展成为集成灵活性高的主要先进封装工艺。该技术无需LTCC基板，可以减重约40%以上；且晶圆级集成可实现微米级尺度的制造精度，提高生产效率，满足现代电子装备系统小型化、低成本、高集成度的迫切需求。扇出型晶圆级封装的关键工艺技术在于焊料凸点制作工艺和重布线技术（RDL）。
其中，RDL技术用于实现半导体芯片间信号互连及其信号引出端（I/O）的转移。由于电子系统的功能越来越强，其布线和安装密度也越来越高。然而RDL技术受布线层数的限制，使得扇出型晶圆级封装难以满足互连关系较复杂的设计。
为了满足当前微电子系统复杂性较高的布线设计要求，亟需发展一种扇出型晶圆级多层布线封装结构。
发明内容
本发明提供一种扇出型晶圆级多层布线封装结构以及制备该封装结构的方法，用以解决现有技术中存在的扇出型晶圆级封装难以满足互连关系较复杂的要求。
本发明实施例提供一种扇出型晶圆级多层布线封装结构，所述封装结构，包括多个半导体芯片、多层布线转接板、垂直互连转接板、粘接材料和再布线层；半导体芯片背面与多层布线转接板背面由粘接材料键合在一起，且与垂直互连转接板同一水平面放置并通过粘接材料封装为一个整体，在所得结构表面设有再布线层；再布线层的导电金属层连接半导体芯片、多层布线转接板、垂直互连转接板中的导电材料及焊球，实现半导体芯片与多层布线转接板之间的信号互连以及半导体芯片信号引出端的转移。
可选的，所述封装结构通过多层布线转接板实现布线层数的增加；所述多层布线转接板根据系统的电互连设计要求采用CMOS工艺制作而成。
可选的，多层布线转接板、半导体芯片、垂直互连转接板同一水平面放置后集成，通过再布线导电金属实现半导体芯片或多层布线转接板与垂直互连转接板中导电材料及焊球之间的电互连。
可选的，所述垂直互连转接板是根据半导体芯片间的电互连设计要求，截取相应尺寸的预制的通孔节距固定的垂直互连转接板圆片所得。
本发明实施例还提供了一种扇出型晶圆级封装结构的制备方法，其特征在于：采用晶圆级CMOS工艺，根据半导体芯片间的信号互连设计要求制作多层布线转接板；采用预制的通孔节距固定的垂直互连转接板圆片，根据半导体芯片间的信号互连设计要求以及系统信号引出端数量的具体要求，通过划片截取得到相应尺寸的垂直互连转接板5；半导体芯片1背面及多层布线转接板2背面通过键合工艺由粘接材料7键合；将键合后的半导体芯片1和多层布线转接板2，与垂直互连转接板5先临时贴装到一个载片9上，半导体芯片1正面背向载片9 ，垂直互连转接板5置于半导体芯片1和多层布线转接板2的侧边；对载片9上的半导体芯片1、多层布线转接板2和垂直互连转接板5进行封装，然后将载片9取下；在上述所得结构表面制作再布线层RDL3，通过上表面RDL将半导体芯片1的信号引出端I/O连接至垂直互连转接板，再通过垂直互连转接板中的导电材料及下表面的RDL连接至多层布线转接板2，或直接通过垂直互连转接板中的导电材料连接至底部焊球。
根据半导体芯片间的信号互连设计要求，制作多层布线转接板，增加扇出型晶圆级封装的布线层数，弥补晶圆级封装受RDL布线层数限制的弊端，可满足当前微电子系统高密度、高复杂性布线的发展需求，用于复杂性较高的微系统封装。采用侧边垂直互连转接板的方法实现半导体芯片引出端（I/O）与多层布线转接板之间的信号互连，简化了互连方式。采用预制的通孔节距固定的垂直互连转接板圆片，根据半导体芯片间的信号互连设计要求，截取得到相应的垂直互连转接板，简化和固定了工艺过程，提高了封装效率。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简要介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域的普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1是本发明扇出型晶圆级多层布线封装结构的多层布线转接板圆片；
图2是本发明扇出型晶圆级多层布线封装结构的预制的通孔节距固定的垂直互连转接板圆片；
图3是本发明扇出型晶圆级多层布线封装结构键合后的半导体芯片和多层布线转接板、垂直互连转接板集成的结构示意图；
图4是本发明扇出型晶圆级多层布线封装结构示意图。
其中，1-半导体芯片，2-多层布线转接板，3-再布线层，4-粘接材料，5-垂直互连转接板，6-多层布线转接板布线层，7-粘接材料，8-焊球，9-载片。
具体实施方式
为了使本发明的目的、技术方案和优点更加清楚，下面将结合附图对本发明作进一步地详细描述，显然，所描述的实施例仅仅是本发明一部份实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其它实施例，都属于本发明保护的范围。
下面结合附图对本发明作进一步说明。
如图3所示，本发明一种扇出型晶圆级多层布线封装结构，包含半导体芯片1、多层布线转接板2、垂直互连转接板5、粘接材料4和再布线层3，半导体芯片1背面及多层布线转接板2背面由粘接材料键合在一起后，与垂直互连转接板同一水平面放置，通过粘接材料封装为一个整体。在所得结构表面设有再布线层3，通过上表面RDL将半导体芯片1的信号引出端I/O连接至垂直互连转接板，再通过垂直互连转接板中的导电材料及下表面的RDL连接至多层布线转接板2，或直接通过垂直互连转接板中的导电材料连接至底部焊球。
其中，所述封装结构通过多层布线转接板实现布线层数的增加；所述多层布线转接板根据系统的电互连设计要求采用CMOS工艺制作而成。
其中，多层布线转接板、半导体芯片、垂直互连转接板同一水平面放置后集成，通过再布线导电金属实现半导体芯片或多层布线转接板与垂直互连转接板中导电材料及焊球之间的电互连。
其中，粘接材料4为填充材料但不限于填充材料。
其中，所述垂直互连转接板是根据半导体芯片间的电互连设计要求，截取相应尺寸的预制的通孔节距固定的垂直互连转接板圆片所得。
该扇出型晶圆级封装结构的制备方法，包括以下步骤：
（1）采用晶圆级CMOS工艺，根据半导体芯片间的信号互连设计要求制作多层布线转接板；
（2）采用一种高效的工艺设计，即采用如图2所示的预制的（通用工艺制备）通孔节距固定的垂直互连转接板圆片，根据半导体芯片间的信号互连设计要求以系统信号引出端数量的具体要求，通过划片截取得到相应尺寸的垂直互连转接板5；
（3）半导体芯片1背面及多层布线转接板2背面（硅片侧）通过键合工艺由粘接材料7键合；粘接材料7为贴片材料但不限于贴片材料；
（4）将键合后的半导体芯片1和多层布线转接板2，与垂直互连转接板5先临时贴装到一个载片9上，半导体芯片1正面背向载片9 ，垂直互连转接板5置于半导体芯片1和多层布线转接板2的侧边（采用侧边垂直互连转接板方法）；
（5）对载片9上的器件（半导体芯片1和多层布线转接板2、垂直互连转接板5）进行封装，然后将载片9取下；
（6）通过光刻但不限于光刻的方式在上述所得结构表面制作再布线层（RDL）3，通过上表面RDL将半导体芯片1的信号引出端I/O连接至垂直互连转接板，再通过垂直互连转接板中的导电材料及下表面的RDL连接至多层布线转接板2，或直接通过垂直互连转接板中的导电材料连接至底部焊球。所得多层布线的扇出型晶圆级封装结构如图4所示。通过多层布线转接板2增加了扇出型晶圆级封装的布线层数，实现布线复杂性较高的微电子系统的封装集成。
尽管已描述了本发明的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本发明范围的所有变更和修改。
显然，本领域的技术人员可以对本发明进行各种改动和变型而不脱离本发明的精神和范围。这样，倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包含这些改动和变型在内。

Claims (5)

1.一种扇出型晶圆级多层布线封装结构，其特征在于：所述封装结构，包括多个半导体芯片、多层布线转接板、垂直互连转接板、粘接材料和再布线层；
半导体芯片背面与多层布线转接板背面由粘接材料键合在一起，且与垂直互连转接板同一水平面放置并通过粘接材料封装为一个整体，在所得结构表面设有再布线层；
再布线层的导电金属层连接半导体芯片、多层布线转接板、垂直互连转接板中的导电材料及焊球，实现半导体芯片与多层布线转接板之间的信号互连以及半导体芯片信号引出端的转移。
2.根据权利要求1所述的扇出型晶圆级多层布线封装结构，其特征在于：所述封装结构通过多层布线转接板实现布线层数的增加；所述多层布线转接板根据系统的电互连设计要求采用CMOS工艺制作而成。
3.根据权利要求1所述的扇出型晶圆级多层布线封装结构，其特征在于：多层布线转接板、半导体芯片、垂直互连转接板同一水平面放置后集成，通过再布线导电金属实现半导体芯片或多层布线转接板与垂直互连转接板中导电材料及焊球之间的电互连。
4.根据权利要求1所述的扇出型晶圆级多层布线封装结构，其特征在于：所述垂直互连转接板是根据半导体芯片间的电互连设计要求，截取相应尺寸的预制的通孔节距固定的垂直互连转接板圆片所得。
5.一种扇出型晶圆级封装结构的制备方法，其特征在于：
采用晶圆级CMOS工艺，根据半导体芯片间的信号互连设计要求制作多层布线转接板；
采用预制的通孔节距固定的垂直互连转接板圆片，根据半导体芯片间的信号互连设计要求以及系统信号引出端数量的具体要求，通过划片截取得到相应尺寸的垂直互连转接板5；
半导体芯片1背面及多层布线转接板2背面通过键合工艺由粘接材料7键合；
将键合后的半导体芯片1和多层布线转接板2，与垂直互连转接板5先临时贴装到一个载片9上，半导体芯片1正面背向载片9 ，垂直互连转接板5置于半导体芯片1和多层布线转接板2的侧边；
对载片9上的半导体芯片1、多层布线转接板2和垂直互连转接板5进行封装，然后将载片9取下；
在上述所得结构表面制作再布线层RDL3，通过上表面RDL将半导体芯片1的信号引出端I/O连接至垂直互连转接板，再通过垂直互连转接板中的导电材料及下表面的RDL连接至多层布线转接板2，或直接通过垂直互连转接板中的导电材料连接至底部焊球。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111834232A (zh) * 2020-06-12 2020-10-27 珠海越亚半导体股份有限公司 一种无特征层结构的转接载板及其制造方法
CN113023660A (zh) * 2021-03-26 2021-06-25 华南农业大学 单板双侧布线式微机械结构及其制备方法

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110729257A (zh) * 2019-03-11 2020-01-24 Pep创新私人有限公司 芯片封装方法及芯片结构
DE102020109555A1 (de) 2020-04-06 2021-10-07 Infineon Technologies Ag Eingehäuste halbleitervorrichtung und verfahren zur herstellung einer eingehäusten halbleitervorrichtung

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090008762A1 (en) * 2007-07-02 2009-01-08 Nepes Corporation Ultra slim semiconductor package and method of fabricating the same
US8907498B2 (en) * 2009-03-25 2014-12-09 Stats Chippac, Ltd. Semiconductor device and method of forming a shielding layer between stacked semiconductor die
CN105957842A (zh) * 2016-06-08 2016-09-21 中国电子科技集团公司第五十八研究所 一种高效可重构三维封装结构
CN106601623A (zh) * 2015-10-19 2017-04-26 台湾积体电路制造股份有限公司 半导体器件及其制造方法
CN106653709A (zh) * 2016-12-30 2017-05-10 三星半导体(中国)研究开发有限公司 封装件及其制造方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3326485A1 (en) * 2012-08-20 2018-05-30 Forever Mount, LLC A brazed joint for attachment of gemstones to a metallic mount
KR101411813B1 (ko) * 2012-11-09 2014-06-27 앰코 테크놀로지 코리아 주식회사 반도체 디바이스 및 그 제조 방법
US9799592B2 (en) * 2013-11-19 2017-10-24 Amkor Technology, Inc. Semicondutor device with through-silicon via-less deep wells
US9899248B2 (en) * 2014-12-03 2018-02-20 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming semiconductor packages having through package vias
US10325853B2 (en) * 2014-12-03 2019-06-18 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming semiconductor packages having through package vias
US10153175B2 (en) * 2015-02-13 2018-12-11 Taiwan Semiconductor Manufacturing Company, Ltd. Metal oxide layered structure and methods of forming the same
US9818684B2 (en) * 2016-03-10 2017-11-14 Amkor Technology, Inc. Electronic device with a plurality of redistribution structures having different respective sizes
US9559081B1 (en) * 2015-08-21 2017-01-31 Apple Inc. Independent 3D stacking
US9761571B2 (en) * 2015-09-17 2017-09-12 Deca Technologies Inc. Thermally enhanced fully molded fan-out module
US10032722B2 (en) * 2016-05-31 2018-07-24 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package structure having am antenna pattern and manufacturing method thereof
US9793230B1 (en) * 2016-07-08 2017-10-17 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structure and method of forming
US10332841B2 (en) * 2016-07-20 2019-06-25 Taiwan Semiconductor Manufacturing Company, Ltd. System on integrated chips and methods of forming the same

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090008762A1 (en) * 2007-07-02 2009-01-08 Nepes Corporation Ultra slim semiconductor package and method of fabricating the same
US8907498B2 (en) * 2009-03-25 2014-12-09 Stats Chippac, Ltd. Semiconductor device and method of forming a shielding layer between stacked semiconductor die
CN106601623A (zh) * 2015-10-19 2017-04-26 台湾积体电路制造股份有限公司 半导体器件及其制造方法
CN105957842A (zh) * 2016-06-08 2016-09-21 中国电子科技集团公司第五十八研究所 一种高效可重构三维封装结构
CN106653709A (zh) * 2016-12-30 2017-05-10 三星半导体(中国)研究开发有限公司 封装件及其制造方法

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111834232A (zh) * 2020-06-12 2020-10-27 珠海越亚半导体股份有限公司 一种无特征层结构的转接载板及其制造方法
CN111834232B (zh) * 2020-06-12 2021-04-09 珠海越亚半导体股份有限公司 一种无特征层结构的转接载板及其制造方法
CN113023660A (zh) * 2021-03-26 2021-06-25 华南农业大学 单板双侧布线式微机械结构及其制备方法
CN113023660B (zh) * 2021-03-26 2023-06-23 华南农业大学 单板双侧布线式微机械结构及其制备方法

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Application publication date: 20171222