CN103383923A - 用于应用处理器和存储器集成的薄3d扇出嵌入式晶片级封装(ewlb) - Google Patents

用于应用处理器和存储器集成的薄3d扇出嵌入式晶片级封装(ewlb) Download PDF

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CN103383923A
CN103383923A CN2013101566318A CN201310156631A CN103383923A CN 103383923 A CN103383923 A CN 103383923A CN 2013101566318 A CN2013101566318 A CN 2013101566318A CN 201310156631 A CN201310156631 A CN 201310156631A CN 103383923 A CN103383923 A CN 103383923A
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semiconductor element
conductive layer
semiconductor
film
layer
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CN103383923B (zh
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R·D·彭德斯
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Stats Chippac Pte Ltd
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Stats Chippac Pte Ltd
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Abstract

本发明涉及一种用于应用处理器和存储器集成的薄3D扇出嵌入式晶片级封装(EWLB)。本发明涉及一种具有多个第一半导体管芯的半导体器件，该第一半导体管芯具有沉积在第一半导体管芯的第一表面上和第一半导体管芯周围的密封剂。在密封剂上和第一半导体管芯的与第一表面相对的第二表面上形成绝缘层。该绝缘层包括在第一半导体管芯上的开口。在第一半导体管芯上在开口内形成第一导电层。在第一导电层上形成第二导电层以形成垂直导电通孔。第二半导体管芯被置于第一半导体管芯上且被电连接到第一导电层。将凸点形成在第一半导体管芯的占位面积外的第二导电层上。第二半导体管芯被置于有效表面或第一半导体管芯的后表面上。

Description

用于应用处理器和存储器集成的薄3D扇出嵌入式晶片级封装(EWLB)
优先权要求 
本申请要求2012年3月8日提交的编号为61/608,402的美国临时申请的优先权，在此通过引用将该申请并入本文。 
技术领域
本发明通常涉及半导体器件，并且更具体地涉及形成包括具有精细间距互连的薄膜互连结构的扇出(fan-out)嵌入式晶片级球栅阵列(Fo-eWLB)的半导体器件和方法。 
背景技术
在现代电子产品中通常可找到半导体器件。半导体器件在电子元件的数量和密度上是变化的。分立半导体器件通常包括一类电子元件，例如，发光二极管(LED)、小信号晶体管、电阻器、电容器、电感器和功率金属氧化物半导体场效应晶体管(MOSFET)。集成半导体器件典型地包含几百到几百万个电子元件。集成半导体器件的例子包括微控制器、微处理器、电荷耦合器件(CCD)、太阳能电池和数字微镜器件(DMD)。 
半导体器件执行广泛的功能，诸如信号处理、高速计算、发送和接收电磁信号、控制电子器件、将太阳光转换为电、和产生用于电视显示的视觉投射。半导体器件在娱乐、通信、功率转换、网络、计算机和消费产品的领域中被找到。半导体器件也在军事应用、航空、汽车、工业控制器和办公设备中被找到。 
半导体器件利用了半导体材料的电性质。半导体材料的原子结构允许通过施加电场或基极电流或通过掺杂工艺来操纵其电导率。掺杂向半导体材料中引入杂质来操纵和控制半导体器件的电导率。 
半导体器件包含有源和无源电结构。有源结构，包括双极和场效应晶体管，控制电流的流动。通过改变掺杂水平和电场或基极电流的施加，晶体管提升或 限制电流的流动。无源结构，包括电阻器、电容器和电感器，建立执行各种电学功能所必需的电压和电流间的关系。无源和有源结构被电连接以形成电路，其使半导体器件能够执行高速计算和其他有用的功能。 
半导体器件通常使用两个复杂的制造工艺来制造，即，前端制造和后端制造，均潜在地涉及几百个步骤。前端制造涉及在半导体晶片上形成多个管芯。每个半导体管芯通常是相同的且包含通过电连接有源和无源元件所形成的电路。后端制造涉及从完成的晶片分割各个半导体管芯并且封装管芯以提供结构支撑和环境隔离。如此处使用的术语“半导体管芯”涉及该词语的单数和复数形式两者，且因此可涉及单个半导体器件和多个半导体器件两者。 
半导体制造的一个目的是生产更小的半导体器件。更小的器件通常地消耗更低的功率，具有更高的性能，且能被更有效率地生产。另外，更小的半导体器件具有更小的占位面积(footprint)，其对于更小的终端产品是期望的。更小的半导体管芯尺寸可通过前端工艺中的改进所实现，导致具有更小、更高密度的有源和无源元件的半导体管芯。后端工艺可通过电互连和封装材料中的改进而导致具有更小占位面积的半导体器件封装。 
半导体制造的另一目的是生产更高性能的半导体器件。器件性能上的增加可以通过形成能够操作在更高速度下的电接口来实现。更高的操作速度可以通过缩短在半导体器件封装内的信号路径长度来实现。实现更高集成和更小、更高速度半导体器件的目标的一个方法是专注于包括封装体叠层(PoP)的三维(3D)封装技术。在半导体结构和外部器件中，器件间的电互连可以利用导电穿透硅通孔(TSV)或穿通孔(THV)来实现。 
THV衬底的垂直Z-方向互连消耗空间，增加封装的总体高度，且强加更高的制造成本。THV衬底的厚度限制了信号路径长度和总体封装厚度能被减少的程度。在THV衬底中的信号路径长度限制了半导体器件的速度和电性能。常规的THV衬底是250微米(μm)到350μm厚。THV衬底的厚度导致翘曲和降低的热性能。此外，在THV衬底中，常通过激光钻孔来形成通孔，这限制了在THV衬底中可以实现的通孔间距。常规的THV衬底具有100μm间距或更大的通孔间距。在THV衬底内最小可实现的通孔间距不足以安装高密度的半导体器件且限制了在3D半导体结构中半导体器件集成的灵活性。 
发明内容
存在对于具有降低的封装高度和更精细间距互连的薄互连结构的需求。因此，在一实施例中，本发明是一种制造半导体器件的方法，包括以下步骤：提供多个第一半导体管芯，在第一半导体管芯的第一表面上和第一半导体管芯周围沉积密封剂，在密封剂上和第一半导体管芯相对第一表面的第二表面上形成绝缘层，在绝缘层上形成第一导电层，以及在第一半导体管芯上布置第二半导体管芯且将其电连接到第一导电层。 
在另一实施例中，本发明是一种制造半导体器件的方法，包括以下步骤：提供多个第一半导体管芯，在第一半导体管芯上沉积密封剂，在第一半导体管芯上形成包括开口的绝缘层，在第一半导体管芯上形成第一导电层，以及在第一半导体管芯上布置第二半导体管芯且将其电连接到第一导电层。 
在另一实施例中，本发明是一种制造半导体器件的方法，包括以下步骤：提供第一半导体管芯，在第一半导体管芯上形成第一绝缘层，在第一半导体管芯上形成第一导电层，以及在第一半导体管芯上布置第二半导体管芯。 
在另一实施例中，本发明是一种半导体器件，其包括多个第一半导体管芯和在第一半导体管芯上形成的包括开口的第一绝缘层。在第一半导体管芯上形成的第一导电层。在第一半导体管芯上布置的第二半导体管芯。 
附图说明
图1图示出具有安装到其表面的不同类型封装的印刷电路板(PCB)； 
图2a-2c图示出安装到所述PCB的代表性半导体封装的进一步的细节； 
图3a-3c图示出具有通过锯道(saw street)分离的多个半导体管芯的半导体晶片； 
图4a-4n图示出形成包括具有精细间距互连的薄膜互连结构和安装到薄膜互连结构的相对侧的半导体管芯的Fo-eWLB的工艺； 
图5a-5n图示出形成包括具有精细间距互连的薄膜互连结构和安装在TSV半导体管芯上的半导体管芯的Fo-eWLB的工艺；以及 
图6a-6g图示出形成Fo-eWLB的工艺的替代实施例。 
具体实施方式
在以下描述中参考附图来在一个或多个实施例中描述本发明，其中同样的数字表示相同或相似的元件。尽管将本发明按照用于实现本发明的目的的最好的模式进行描述，但本领域普通技术人员将认识到，本发明意图覆盖可以包括在由随后的公开及附图所支持的所附权利要求及其等价方式所限定的本发明的精神和范围之内的替代、修改和等价方式。 
半导体器件通常使用两个复杂的制造工艺来制造：前端制造和后端制造，前端制造涉及在半导体晶片的表面上形成多个管芯。晶片上每个管芯包含有源和无源电子元件，其被电连接以形成功能电子电路。有源电子元件，诸如晶体管和二极管，具有控制电流流动的能力。无源电子元件，诸如电容器、电感器、电阻器和变压器，在执行电子电路功能所必需的电压和电流间建立关系。 
无源和有源元件在半导体晶片表面上通过一系列工艺步骤，包括掺杂、沉积、光刻、蚀刻和平坦化而被形成。通过诸如离子注入或热扩散的技术，掺杂向半导体材料中引入杂质。在有源器件中，掺杂工艺修改半导体材料的电导率，将半导体材料转换成绝缘体、导体或响应于电场或基极电流来动态改变半导体材料电导率。晶体管包含被布置为使晶体管在施加电场或基极电流时能够提升或限制电流流动所必需的变化类型和程度的掺杂的区域。 
由具有不同电性质的材料的层来形成有源和无源元件。可以通过部分地由被沉积材料的类型所确定的各种沉积技术来形成这些层。例如，薄膜沉积涉及化学气相沉积(CVD)、物理气相沉积(PVD)、电解电镀和无电镀工艺。通常将每一层图案化以形成有源元件、无源元件或元件间的电连接的部分。 
这些层可使用光刻来图案化，其涉及在要被图案化的层上沉积光敏材料，例如，光致抗蚀剂。使用光来将图案从光掩模转移到光致抗蚀剂。在一实施例中，将光致抗蚀剂图案的受到光影响的部分使用溶剂来去除，暴露要被图案化的底层的部分。在另一实施例中，光致抗蚀剂图案的部分不受到光影响，将负性光致抗蚀剂使用溶剂来去除，暴露要被图案化的底层的部分。去除光致抗蚀剂的其余部分，留下图案化的层。替代地，将一些类型的材料通过直接向区域或空隙中沉积材料来图案化，该区域或空隙由使用诸如无电镀或电解电镀的技术的先前的沉积/蚀刻工艺所形成。 
图案化是基本的操作，通过其来去除半导体晶片表面上的顶层的部分。使用光刻、光掩模、掩模、氧化物或金属去除、照相和模板印制、以及显微光刻 法来去除半导体晶片的部分。光刻包括在中间掩模(reticle)或光掩模中形成图案和将图案转移到半导体晶片的表面层中。在两步工艺中光刻在半导体晶片的表面上形成有源和无源元件的水平尺寸。首先，在中间掩模或光掩模上的图案被转移到光致抗蚀剂层中。光致抗蚀剂是光敏材料，当其暴露于光时，经历结构和性质上的改变。改变光致抗蚀剂的结构和性质的工艺作为负性作用光致抗蚀剂或正性作用光致抗蚀剂而发生。其次，光致抗蚀剂层被转移到晶片表面中。该转移发生在蚀刻去除半导体晶片顶层未被光致抗蚀剂所覆盖的部分时。光致抗蚀剂的化学性质是这样的，使得光致抗蚀剂在半导体晶片顶层未被光致抗蚀剂所覆盖的部分被去除的同时保持基本上完整且抵抗由化学蚀刻溶液进行去除。根据使用的特定抗蚀剂和期望的结果，可以修改成形、曝光和去除光致抗蚀剂的工艺，以及去除半导体晶片的一部分的工艺。 
在负性作用光致抗蚀剂中，光致抗蚀剂被暴露于光并且在称为聚合作用的工艺中从可溶状况改变为不可溶状况。在聚合作用中，未聚合材料被暴露于光或能量源并且聚合物形成抗蚀刻的交联材料。在大多数负性抗蚀剂中，聚合物是聚异戊二烯。用化学溶剂或显影剂去除可溶部分(即未暴露于光的部分)在与中间掩模上的不透明图案相对应的抗蚀剂层中留下孔。图案存在于不透明区域中的掩模被称为亮场(clear-field)掩模。 
在正性作用光致抗蚀剂中，光致抗蚀剂被暴露于光并且在称为光溶液化的工艺中从相对不可溶状况改变为更加可溶状况。在光溶液化中，相对不可溶抗蚀剂被暴露于适当的光能量且被转化为更可溶状态。抗蚀剂的光溶液化部分可由显影工艺中的溶剂所去除。基本的正性光致抗蚀剂聚合物是酚醛树脂聚合物，也称为苯酚-甲醛酚醛清漆树脂。利用化学溶剂或显影剂去除可溶部分(即暴露于光的部分)在与中间掩模上的透明图案相对应的抗蚀剂层中留下孔。图案存在于透明区域中的掩模被称为暗场(dark-field)掩模。 
在去除半导体晶片未被光致抗蚀剂所覆盖的顶部部分后，去除光致抗蚀剂的其余部分，留下图案化的层。替代地，一些类型的材料通过直接向区域或空隙中沉积材料来被图案化，该区域或空隙通过使用诸如无电镀和电解电镀的技术的先前沉积/蚀刻工艺所形成。 
在现有的图案上沉积材料的薄膜可以放大底层图案并建立不均匀的平面。产生更小和更密集包装的有源和无源元件需要均匀的平面。平坦化可被用来从 晶片表面去除材料和产生均匀的平面。平坦化涉及用抛光垫来抛光晶片表面。研磨材料和腐蚀性化学品在抛光期间被添加到晶片表面。研磨和化学品的腐蚀作用的组合机械作用去除任何不规则的外形，导致均匀的平面。 
后端制造涉及将完成的晶片切割或分割成各个半导体管芯且然后封装半导体管芯以用于结构支撑和环境隔离。为了分割半导体管芯，将镜片刻痕并沿着称为锯道或划线的晶片的非功能区使晶片断裂。使用激光切割工具或锯条来分割晶片。在分割后，将各个半导体管芯安装到包括用于与其他系统元件互连的引脚或接触焊盘的封装衬底。半导体管芯上形成的接触焊盘然后被连接到封装中的接触焊盘。电连接可以利用焊料凸点、纽扣凸点、导电胶或丝焊来制成。将密封剂或其他模制材料沉积在封装上以提供物理支撑和电隔离。完成的封装然后被插入到电学系统且使半导体器件的功能性对于其他系统元件是可用的。 
图1图示出具有芯片载体衬底或印刷电路板(PCB)52的电子器件50，其中在其表面安装有多个半导体封装。取决于应用，电子器件50可以具有一类半导体封装，或多类半导体封装。在图1中出于说明的目的示出了半导体封装的不同类型。 
电子器件50可以是使用半导体封装来执行一个或多个电学功能的独立系统。替代地，电子器件50可以是更大系统的子元件。例如，电子器件50可以是蜂窝电话、个人数字助理(PDA)、数字视频相机(DVC)或其他电子通信设备的一部分。替代地，电子器件50可以是图形卡、网络接口卡或可以插入计算机的其他信号处理卡。半导体封装可以包括微处理器、存储器、专用集成电路(ASIC)、逻辑电路、模拟电路、RF电路、分立器件或其他半导体管芯或电子元件。为了使产品被市场所接受，小型化和轻量化是必要的。半导体器件间的距离必须被减小以实现更高的密度。 
在图1中，PCB52提供一种通用衬底以用于安装在PCB上的半导体封装的结构支撑和电互连。使用蒸发、电解电镀、无电镀、丝网印刷或其他合适的金属沉积工艺，来在PCB52的表面上或层内形成导电信号迹线54。信号迹线54在每个半导体封装、安装的元件和其他外部系统元件间提供电通信。迹线54也对每个半导体封装提供电源和接地连接。 
在一些实施例中，半导体器件具有两个封装级。第一级封装是用于将半导体管芯机械和电学地附着到中间载体的技术。第二级封装涉及将中间载体机械 和电学地附着到PCB。在其他实施例中，半导体器件可能仅具有第一级封装，其中将管芯直接机械和电学地安装到PCB。 
出于说明的目的，在PCB52上示出了第一级封装的若干种类型，包括接合线封装56和倒装芯片58。另外，第二级封装的若干种类型，包括球栅阵列(BGA)60、凸点芯片载体(BCC)62、双列直插封装(DIP)64、连接盘网格阵列(LGA)66、多芯片模块(MCM)68、方形扁平无引线封装(QFN)70和方形扁平封装72，被示出安装在PCB52上。取决于系统要求，以第一级和第二级封装样式的任何组合所配置的半导体封装的任何组合，以及其他电子元件，可以连接到PCB52。在一些实施例中，电子器件50包括单附着半导体封装，而其他实施例需要多互连封装。通过在单衬底上组合一个或多个半导体封装，制造商可将预制元件结合到电子器件和系统中。因为半导体封装包括复杂的功能，可以使用更廉价的元件和流水线制造工艺来制造电子器件。所得到的器件不太可能出故障并且是更廉价制造的，导致对于消费者而言更低的成本。 
图2a-2c图示出示例性的半导体封装。图2a图示出安装在PCB52上的DIP64的进一步的细节。半导体管芯74包括作用区，其包含模拟或数字电路，该模拟或数字电路被实现为在管芯内形成且根据管芯的电学设计来电互连的有源器件、无源器件、导电层和电介质层。例如，电路可以包括在半导体管芯74的作用区内形成的一个或多个晶体管、二极管、电感器、电容器、电阻器和其他电路元件。接触焊盘76是一层或多层导电材料，诸如铝(Al)、铜(Cu)、锡(Sn)、镍(Ni)、金(Au)或银(Ag)，且被电连接到半导体管芯74内形成的电路元件。在组装DIP64期间，使用金-硅共熔层或诸如热环氧树脂或环氧树脂的粘合材料来将半导体管芯74安装到中间载体78。封装体包括绝缘封装材料，诸如聚合物或陶瓷。导体引线80和结合线82提供半导体管芯74和PCB52间的电互连。将密封剂84沉积在封装上以用于通过阻止湿气和微粒进入封装并污染半导体管芯74或接合线82来进行环境保护。 
图2b图示出安装在PCB52上的BCC62的进一步细节。使用底部填充或环氧树脂粘合材料92来将半导体管芯88安装在载体90上。接合线94在接触焊盘96和98间提供第一级封装互连。将模制化合物或密封剂100沉积在半导体管芯88和接合线94上以对器件提供物理支撑和电隔离。使用合适的金属沉积工艺，诸如电解电镀或无电镀以阻止氧化，来在PCB52的表面上形成接触焊 盘102。将接触焊盘102电连接到PCB52中的一个或多个导电信号迹线54。在BCC62的接触焊盘98和PCB52的接触焊盘102间形成凸点104。 
在图2c中，将半导体管芯58用倒装芯片样式的第一级封装面朝下安装到中间载体106。半导体管芯58的作用区108包含被实现为根据管芯的电学设计所形成的有源器件、无源器件、导电层和电介质层的模拟或数字电路。例如，电路可以包括在作用区108内的一个或多个晶体管、二极管、电感器、电容器、电阻器和其他电路元件。将半导体管芯58通过凸点110电学和机械地连接到载体106。 
将BGA60利用BGA样式第二级封装使用凸点112电学和机械地连接到PCB52。将半导体管芯58通过凸点110、信号线114和凸点112电学地连接到PCB52中的导电信号迹线54。将模制化合物或密封剂116沉积在半导体管芯58和载体106上以对器件提供物理支撑和电隔离。为了减小信号传播距离、更小的电容和提高总体电路性能，倒装芯片半导体器件提供了从半导体管芯58上的有源器件到PCB52上的导电迹线的短的导电通路。在另一实施例中，可以使用倒装芯片样式的第一级封装而没有中间载体106来将半导体管芯58直接机械和电学地连接到PCB52。 
图3a示出用于结构支撑的具有诸如硅、锗、砷化镓、磷化铟或碳化硅的基体衬底材料122的半导体晶片120。多个半导体管芯或元件124在通过如上描述的非作用的、管芯间的晶片区或锯道126所隔离的晶片120上形成。锯道126提供切割区域以将半导体晶片120分割成各个半导体管芯124。 
图3b示出半导体晶片120的一部分的横截面视图。每个半导体管芯124具有后表面128和有效表面130，其包括被实现为在管芯内形成的且根据管芯的电学设计和功能所电连接的有源器件、无源器件、导电层和电介质层的模拟或数字电路。例如，电路可以包括在有效表面130内形成的一个或多个晶体管、二极管和其他电路元件以实现模拟和数字电路，诸如数字信号处理器(DSP)、ASIC、存储器或其他信号处理电路。半导体管芯124可以包括分立器件。分立器件可以是有源器件，诸如晶体管和二极管，或无源器件，诸如用于RF信号处理的电容器、电阻器和电感器。半导体管芯124也可以包括封装的半导体管芯。在一个实施例中，半导体管芯124是倒装芯片型器件。 
使用PVD、CVD、电解电镀、无电镀工艺或其他合适的金属沉积工艺，来 在有效表面130上形成导电层132。导电层132可以是Al、Cu、Sn、Ni、Au、Ag或其他合适的导电材料的一层或多层。导电层132操作为接触焊盘，该接触焊盘被电连接到有效表面130上的电路。如图3b中所示，将导电层132形成为接触焊盘，其被并排布置在距离半导体管芯124边缘的第一距离。替代地，将导电层132形成为接触焊盘，其以多行被分支，使得接触焊盘的第一行被布置在距离管芯边缘的第一距离，且与第一行交替的接触焊盘的第二行被布置在距离管芯边缘的第二距离。 
在图3c中，使用锯条或激光切割工具134通过锯道126将半导体晶片120分割成各个半导体管芯124。 
图4a-4m图示出形成Fo-eWLB的工艺，包括具有精细间距互连的薄膜互连结构和安装到薄膜互连结构的相对侧的半导体管芯。图4a示出衬底或载体150的一部分，包含临时和消耗的基体材料，诸如硅、锗、砷化镓、磷化铟、碳化硅、树脂、氧化铍、玻璃或其他适合的低成本坚固的材料，以用于结构支撑。在载体150上形成交界层或双面带152作为临时粘性接合膜、蚀刻阻挡层或释放层。 
图4b中，将来自图3c的半导体管芯124安装到交界层152和载体150上，例如使用与朝向载体取向的有效表面130进行的取放操作。 
在图4c中，使用焊膏印刷、压缩模制、转移模制、液态密封模制、真空层压、膜辅助模制或其他合适的敷料器，将密封剂或模制化合物154沉积在交界层152和载体150上以及在半导体管芯124上和周围。在半导体管芯124的后表面128上形成密封剂154，且可以将其在随后的背部研磨步骤中减薄。也可如此沉积密封剂154，使得密封剂与后表面128共面且不覆盖后表面。密封剂154可以是聚合物复合材料，诸如带填料的环氧树脂、带填料的环氧丙烯酸盐或带适当填料的聚合物。密封剂154是非导电的，提供物理支撑，并在环境上保护半导体器件免受外部元素和污染物。 
图4d示出了被密封剂154覆盖的复合衬底或重构的晶片156。在图4d中，使密封剂154的表面158经受利用研磨机160进行的可选的研磨操作以平坦化表面和减小密封剂的厚度。化学蚀刻也可以被用来去除和平坦化密封剂154。图4e示出去除密封剂154的一部分以露出半导体管芯124的后表面128。 
图4e中，通过化学蚀刻、机械剥落、化学机械平坦化(CMP)、机械研磨、 热烘、UV光、激光扫描或湿剥离来从复合衬底156去除载体150和交界层152，以促进在半导体管芯周围的半导体管芯124的有效表面130和密封剂154上形成互连结构。 
在图4f中，在半导体管芯124和密封剂154上形成绝缘或钝化层170。绝缘层170包含一层或多层有或没有填料的低温可固化聚合物电介质抗蚀剂(例如，在低于260摄氏度固化)、二氧化硅(SiO2)、氮化硅(Si3N4)、氮氧化硅(SiON)、氧化钽(Ta2O5)、氧化铝(Al2O3)或具有相似的绝缘和结构性质的其他材料。使用PVD、CVD、印刷、旋涂、喷涂、烧结、热氧化或其他适合的工艺来沉积绝缘层170。绝缘层170具有低于10μm的厚度且典型地薄如4μm。通过曝光或显影工艺、激光直接烧蚀(LDA)、蚀刻或其他适合的工艺来去除部分绝缘层170，以在导电层132上形成开口。开口露出半导体管芯124的导电层132以用于随后的电互连。 
在图4g中，将导电层172图案化并且沉积在绝缘层170上、沉积在半导体管芯124上，并且置于绝缘层170中的开口内，作为包括种子层的一层或多层，以填充开口并接触导电层132。一层或多层导电层172包括Al、Cu、Sn、Ni、Au、Ag、钛(Ti)/Cu、钛钨(TiW)/Cu、Ti/镍钒(NiV)/Cu、TiW/NiV/Cu或其他适合的导电材料。导电层172的沉积使用PVD、CVD、电解电镀、无电镀或其他适合的工艺。导电层172具有低于15μm的厚度且典型地薄如3μm。导电层172操作为RDL以将电连接扇出并从半导体管芯124延伸到半导体管芯124外部的点。 
在图4h中，在绝缘层170和导电层172上形成绝缘或钝化层174。绝缘层174包含一层或多层有或没有填料的低温可固化聚合物电介质抗蚀剂(例如，在低于260摄氏度固化)、SiO2、Si3N4、SiON、Ta2O5、Al2O3或具有相似的绝缘和结构性质的其他材料。使用PVD、CVD、印刷、旋涂、喷涂、烧结、热氧化或其他适合的工艺来沉积绝缘层174。绝缘层174具有低于10μm的厚度且典型地薄如4μm。通过曝光或显影工艺、LDA、蚀刻或其他适合的工艺来去除部分绝缘层174，以在绝缘层中形成开口，其露出部分导电层172以用于随后的电互连。 
图4i中，将导电层176图案化并且沉积在绝缘层174上，沉积在导电层172上，并且置于绝缘层174中的开口内，作为包括种子层的一层或多层，以填充 开口并接触和电连接到导电层172。一层或多层导电层176包括Al、Cu、Sn、Ni、Au、Ag、Ti/Cu、TiW/Cu、Ti/NiV/Cu、TiW/NiV/Cu或其他适合的导电材料。导电层176的沉积使用了PVD、CVD、电解电镀、无电镀或其他适合的工艺。导电层176具有低于15μm的厚度且典型地薄如3μm。在一个实施例中，导电层176的沉积包括利用种子层和光刻的选择性镀敷。导电层176操作为RDL以将电连接扇出和从半导体管芯124延伸到半导体管芯124外部的点。 
绝缘层170和174以及导电层172和176一起形成薄膜178。薄膜178构成互连结构。在替代实施例中，薄膜178可以包括少到一个导电层，诸如导电层172。在另一替代实施例中，薄膜178包括两个或更多个RDL层，诸如导电层172和176和类似于导电层172和176的附加导电层。薄膜178可以包括如对于为特定半导体器件所需要的互连密度和电学布线而言所必要的那样多的绝缘和导电层。 
薄膜178包括半导体管芯124置于其上的表面180和与表面180相对的表面182。薄膜178具有低于50μm的厚度，其薄于典型地具有250到350μm厚度的传统THV衬底。由均利用低于10μm的厚度形成的绝缘和导电材料层形成薄膜178。绝缘和导电材料薄层允许紧邻薄层内的相邻的水平和垂直互连来形成水平和垂直互连(例如，具有低于50μm的间距)。利用紧邻相邻的互连所形成的水平和垂直互连，在互连结构内实现更高密度的互连。因为薄膜178包括更高密度的互连，薄膜178在将半导体器件集成到3D半导体结构方面提供更大的灵活性。高密度互连结构适应具有变化的凸点间距的半导体管芯，例如，来自多个制造源的半导体管芯。 
导电层172和176形成水平和垂直互连或穿过薄膜178的垂直导电通孔184。将水平和垂直互连如对于到半导体管芯或元件的连接或通过薄膜178路由电信号而言所必要的那样靠近在一起而形成。例如，导电层172和176可以包括导电迹线。紧邻第二导电迹线形成第一导电迹线(例如，导电迹线之间的间距小于50μm)。导电迹线之间的精细间距允许在薄膜178内形成用于更多的导电迹线的空间，同时与传统THV衬底相比，每个薄膜层的薄度减小了互连结构的厚度。 
导电层172和176也形成垂直导电通孔184，其中紧邻第二垂直导电通孔形成第一垂直导电通孔(例如，垂直导电通孔间的间距小于50μm)。导电层172 包括垂直导电通孔184的第一部分，以及导电层176包括垂直导电通孔184的第二部分。垂直导电通孔184可从薄膜178的表面180延伸到表面182或者可部分地穿过薄膜178形成垂直导电通孔184。垂直导电通孔184间的间距P小于50μm。在薄膜178中垂直导电通孔184间的间距P比传统穿通孔(THV)衬底中导电通孔间的间距(其典型地是100μm或更大)更精细。 
在薄膜178中精细间距水平和垂直互连提供更高的互连密度和输入/输出(I/O)端数。薄膜178提供一种互连间距，其允许在倒装芯片取向上将高密度的半导体管芯安装到薄膜178的表面180和182的任一或两者。可以将半导体管芯在面对面的取向上安装在薄膜178上。薄膜178在扇出设计中延伸超出半导体管芯124的占位面积以进一步增加I/O端数。薄膜178的薄度允许更小和更薄的总体半导体器件封装，其减小了翘曲和增加了器件速度。此外，高密度互连适应每个3D半导体结构的更多电信号并提高了互连结构与更多种多样的半导体器件和元件类型的兼容性。 
图4j中，在绝缘层174和导电层176上形成可选的绝缘或钝化层186。绝缘层186包含一层或多层有或没有填料的低温可固化聚合物电介质抗蚀剂(例如，在低于260摄氏度固化)、SiO2、Si3N4、SiON、Ta2O5、Al2O3或具有相似的绝缘和结构性质的其他材料。使用PVD、CVD、印刷、旋涂、喷涂、烧结、热氧化或其他适合的工艺来沉积绝缘层186。通过曝光或显影工艺、LDA、蚀刻或其他适合的工艺来去除部分绝缘层186，以在绝缘层中形成开口，其露出部分导电层176以用于随后的电互连。 
图4j还示出了在绝缘层186中的开口内沉积在导电层176上的导电凸点材料。在导电层176上形成凸点188。替代地，如果薄膜178包括一个RDL层，诸如导电层172，则在所述单个RDL层上形成凸点188。可以在导电层172或176或附加导电层上形成凸点188。在半导体管芯124的占位面积外侧的薄膜178区域上形成凸点188。也可以在半导体管芯124的占位面积正下方或与其重叠的薄膜178区域中形成凸点188。 
使用蒸发、电解电镀、无电镀、球滴(ball drop)或丝网印刷工艺来形成凸点188。凸点材料可以是Al、Sn、Ni、Au、Ag、铅(Pb)、Bi、Cu、焊料、及其组合，具有可选的助熔剂溶液。例如，凸点材料可以是共熔的Sn/Pb、高铅焊料或无铅焊料。使用合适的附着或接合工艺，将凸点材料接合到导电层176。在 一个实施例中，通过加热金属高于其熔点来回流凸点材料，以形成球形球或凸点188。在一些应用中，二次回流凸点188以改善到导电层176的电接触。在一个实施例中，在具有湿层、阻挡层和粘合层的凸点下金属化(UBM)上形成凸点188。凸点也可以压缩接合到导电层176。凸点188表示可在导电层176上形成的一类互连结构。互连结构也可以使用接合线、导电胶、纽扣凸点、微凸点或其他电互连。 
图4j也示出未在薄膜178的导电层176上形成凸点188的薄膜178的区域190。替代地，凸点188在区域190中的导电层176上被形成，并且随后从区域190被去除。在另一替代实施例中，一些凸点188在薄膜178的区域190中被形成并保持。取决于对于特定半导体器件的互连要求，区域190被配置有凸点188或没有凸点188。薄膜178的区域190对于要被安装在薄膜178的表面182上的第二半导体管芯或元件提供连接部位。在一个实施例中，区域190包括薄膜178的表面180，其与半导体管芯124所置于其上的薄膜178的区域正对。 
合起来，绝缘层170、174和186，以及导电层172、176，和导电凸点188形成互连结构192。包括在互连结构192内的绝缘和导电层的数量取决于电路布线设计的复杂度并随之变化。因此，互连结构192可以包括一个或多个绝缘和导电层以促进关于半导体管芯124的电互连。将另外被包括在背面互连结构或RDL中的元件可以被集成为互连结构192的部分，以简化制造并减少关于包括前面和背面互连或RDL两者的封装的制作成本。 
在图4k中，半导体管芯或元件200被安装到在薄膜178的区域190中的半导体管芯124上的互连结构192。每个半导体管芯200具有在朝向半导体管芯124并朝向薄膜178的表面182取向的有效表面202上形成的，且被电连接到垂直导电通孔184的导电层172和176的接触焊盘。有效表面202包含实现为在管芯内形成的且根据管芯的电学设计和功能来被电互连的有源器件、无源器件、导电层和电介质层的模拟或数字电路。例如，电路可以包括在有效表面202内形成的一个或多个晶体管、二极管和其他电路元件，以实现模拟电路或数字电路，诸如DSP、ASIC、存储器、应用处理器或其他信号处理电路。半导体管芯200可能包括分立器件。分立器件可以是有源器件，诸如晶体管和二极管，或无源器件，诸如用于RF信号处理的电容器、电阻器和电感器。半导体管芯200也可以包括封装的半导体管芯。在半导体管芯200上形成多个凸点204并将其 回流以将半导体管芯200的接触焊盘电连接到导电层176。在一个实施例中，半导体管芯200被实现为倒装芯片样式的器件。置于互连结构192上的半导体管芯200的高度低于或等于置于半导体管芯200的占位面积外侧的互连结构192上的凸点188的高度。在一个实施例中，凸点188的高度超过半导体管芯200的高度。 
图4l中，将可选的底部填充材料210置于半导体管芯200下。底部填充材料包括环氧树脂、环氧树脂粘合材料、聚合材料、膜或其他非导电材料。底部填充210是非导电的并在环境上保护半导体器件免受外部元素和污染物。 
在一个实施例中，在形成凸点188后，用锯条或激光切割设备212将复合衬底或重构的晶片156分割成各个半导体器件214。通过在复合衬底上安装附加半导体器件之前分割复合衬底156，通过在各个器件级而不是在重构的晶片级安装附加半导体管芯来实现各个半导体器件214的形成。替代地，如图4l中所示，在附加半导体器件被安装到复合衬底后，分割复合衬底156。 
图4m示出了分割后的各个半导体器件214。半导体器件214是具有置于互连结构192的薄膜178的相对侧上的半导体管芯的3D半导体结构。包括精细间距垂直导电通孔184的半导体器件214适应高密度半导体管芯，诸如以倒装芯片取向的宽I/O存储器件。半导体器件214也适应混合半导体管芯尺寸。例如，具有存储器功能的半导体管芯和应用处理器管芯可以被面对面集成到半导体器件214中。在一个实施例中，半导体管芯124包括应用处理器，并且半导体管芯200包括存储器。在另一实施例中，半导体管芯124包括存储器，并且半导体管芯200包括应用处理器。替代地，半导体管芯124和200包括其他信号处理电路、分立器件、元件或封装的器件。 
将半导体管芯124和200通过垂直导电通孔184电连接。半导体器件214通过薄膜178中的精细间距垂直导电通孔184在半导体管芯124和200之间提供电信号的垂直下拉式(drop-down)路由。在半导体器件214内的导电路径长度被减小到300μm或更小，且典型地低于100μm，其导致更高的速度和更有效率的器件。也减小了热路径长度。具有置于相对侧上的半导体管芯124和200的薄膜178减小了半导体器件214的总体封装高度。半导体器件214的厚度为0.5毫米(mm)或更小，且典型地薄如0.2mm，而使用传统THV衬底的封装厚度为0.7到1.4mm。更小的半导体器件214的封装轮廓通过减小翘曲并提供更短 的热路径而改善了半导体器件的热性能。具有薄膜层的半导体器件214的更小的封装轮廓减小了3D半导体结构的寄生电容。 
图4n图示出半导体器件214的替代实施例。将半导体管芯或元件216安装到薄膜178的区域190中的半导体管芯124上的互连结构192。将半导体管芯216与半导体管芯200类似地配置。半导体管芯216包括朝向半导体管芯124并朝向薄膜178的表面182取向且电连接到垂直导电通孔184的导电层172和176的有效表面。半导体管芯216被置于半导体管芯124的占位面积内的互连结构192上。替代地，半导体管芯216部分地或整体置于半导体管芯124的占位面积外侧。薄膜178提供电布线能力，使得半导体管芯可以被安装到以不同配置的薄膜178。在未被半导体管芯216占用的，或者在半导体管芯216的占位面积外侧的薄膜178区域中的薄膜178上形成凸点188。在一个实施例中，半导体管芯216窄于半导体管芯124。半导体管芯216的形状为要在薄膜178上形成的附加凸点188留出空间。邻近半导体管芯216的占位面积或在其外侧形成凸点188。凸点188也可在半导体管芯124的占位面积内被形成且与半导体管芯124的占位面积重叠。 
图5a-5n图示出形成包括具有精细间距互连的薄膜互连结构和安装在穿透硅通孔(TSV)半导体管芯上的半导体管芯的Fo-eWLB的工艺。图5a示出安装到载体或临时衬底222的TSV晶片220。载体222包含消耗基体材料，诸如硅、聚合物、氧化铍、玻璃或其他适合的低成本坚固的材料，以用于结构支撑。在载体222上形成交界层或双面带224作为临时粘性接合膜、蚀刻阻挡层或热释放层。 
TSV晶片220包括基体衬底材料226，诸如硅、锗、砷化镓、磷化铟或碳化硅，以用于结构支撑。在TSV晶片220上形成通过管芯间的晶片区域或锯道230所分离的多个半导体管芯或元件228。锯道230提供切割区域以将TSV晶片220分割成各个的半导体管芯228。半导体管芯228包括有效表面232和相对有效表面232的后表面234。有效表面232朝向载体222进行取向。有效表面232包含被实现为在管芯中形成的且根据管芯的电学设计和功能来电互连的有源器件、无源器件、导电层和电介质层的模拟或数字电路。例如，电路可以包括在有效表面232内形成的一个或多个晶体管、二极管和其他电路元件，以实现模拟电路或数字电路，诸如DSP、ASIC、存储器、应用处理器或其他信号处 理电路。半导体管芯228可能包括分立器件。分立器件可以是有源器件，诸如晶体管和二极管，或无源器件，诸如用于RF信号处理的电容器、电阻器和电感器。半导体管芯228也可以包括封装的半导体管芯。 
使用机械钻孔、激光钻孔或深反应离子蚀刻(DRIE)来穿过衬底226形成多个通孔236。通孔236贯穿TSV晶片220的衬底226。使用电解电镀、无电镀工艺或其他合适的金属沉积工艺来利用Al、Cu、Sn、Ni、Au、Ag、Ti、钨(W)、多晶硅或其他合适的导电材料填充通孔236以形成垂直z-方向导电TSV。 
图5b中，将多个半导体管芯或元件240安装在TSV晶片220上。半导体管芯240包括有效表面242和后表面244。有效表面242包含实现为在管芯中形成的且根据管芯的电学设计和功能来电互连的有源器件、无源器件、导电层和电介质层的模拟或数字电路。例如，电路可以包括在有效表面242内形成的一个或多个晶体管、二极管和其他电路元件，以实现模拟电路或数字电路，诸如DSP、ASIC、存储器、应用处理器或其他信号处理电路。半导体管芯240也可以包括分立器件或元件，诸如功率晶体管，或IPD，诸如电感器、电容器和电阻器，用于RF信号处理。半导体管芯240也可以包括封装的半导体管芯。在一个实施例中，半导体管芯228包括应用处理器且半导体管芯240包括存储器。在另一实施例中，半导体管芯228包括存储器，且半导体管芯240包括应用处理器。替代地，半导体管芯228和240包括其他信号处理电路、分立器件、元件或封装的器件。 
半导体管芯240被置于具有朝向半导体管芯228的后表面234取向的有效表面242的半导体管芯228上。在半导体管芯240的有效表面242上形成导电层246。使用诸如铜箔叠层、印刷、PVD、CVD、溅射、电解电镀和无电镀的金属沉积工艺来形成导电层246。导电层246可以是Al、Cu、Sn、Ni、Au、Ag、Ti、W或其他合适的导电材料的一层或多层。 
在半导体管芯228的后表面234上形成导电层248。使用诸如铜箔叠层、印刷、PVD、CVD、溅射、电解电镀和无电镀的金属沉积工艺来形成导电层248。导电层248可以是Al、Cu、Sn、Ni、Au、Ag、Ti、W或其他合适的导电材料的一层或多层。导电层248接触或被电连接到通孔236。 
使用蒸发、电解电镀、无电镀、球滴或丝网印刷工艺，来在导电层246或导电层248上沉积导电凸点材料。凸点材料可以是Al、Sn、Ni、Au、Ag、Pb、 Bi、Cu、焊料、及其组合，具有可选的助熔剂溶液。例如，凸点材料可以是共熔的Sn/Pb、高铅焊料或无铅焊料。使用合适的附着或结合工艺来将凸点材料接合到导电层246和248。在一个实施例中，通过加热金属高于其熔点来回流凸点材料，以形成球或凸点250。在一些应用中，二次回流凸点250以改善到导电层246和248的电接触。凸点250也可以被压缩接合或热压缩接合到导电层246和248。凸点250表示在导电层246和248上形成的一类互连结构。互连结构也可以使用纽扣凸点、微凸点或其他电互连。 
图5c中，利用锯条或激光切割工具260通过锯道230将TSV晶片220分割成各个的堆叠的半导体器件262。 
图5d中，第二临时衬底或载体264包含消耗基体材料，诸如硅、聚合物、氧化铍、玻璃或其他适合的低成本、坚固的材料，以用于结构支撑。在载体264上形成交界层或双面带266作为临时粘性接合膜或蚀刻阻挡层。使用与半导体管芯228朝向载体取向的有效表面232进行的取放操作来将堆叠半导体器件262放置在交界层266和载体264上并安装到交界层266和载体264。安装到载体264的堆叠半导体器件262构成复合衬底或重构的晶片268。 
图5e中，使用焊膏印刷、压缩模制、转移模制、液态密封模制、真空层压、膜辅助模制或其他合适的敷料器，来将密封剂或模制化合物270沉积在交界层266和载体264上以及堆叠半导体器件262上和周围。在半导体管芯240的后表面244上形成密封剂270，且在随后的背部研磨步骤中可以将其减薄。也可如此沉积密封剂270，使得密封剂与后表面244共面，且不覆盖后表面244。密封剂270可以是聚合物复合材料，诸如带填料的环氧树脂、带填料的环氧丙烯酸盐或带适当填料的聚合物。密封剂270是非导电的，提供物理支撑并在环境上保护半导体器件免受外部元素和污染物。 
图5f示出被密封剂270所覆盖的复合衬底或重构的晶片268。图5f中，使密封剂270的表面272经受利用研磨机274进行的可选的研磨操作以平坦化表面和减小密封剂的厚度。化学蚀刻也可以被用来去除和平坦化密封剂270。图5g示出去除密封剂270的一部分以露出半导体管芯240的后表面244。 
图5g中，通过化学蚀刻、机械剥落、CMP、机械研磨、热烘、UV光、激光扫描或湿剥离来从复合衬底268去除载体264和交界层266，以促进在半导体管芯228的有效表面232和半导体管芯周边附近的密封剂270上形成互连结构。 
图5h中，在半导体管芯228和密封剂270上形成绝缘或钝化层280。绝缘层280包括一层或多层有或没有填料的低温可固化聚合物电介质抗蚀剂(例如，在低于260摄氏度固化)、SiO2、Si3N4、SiON、Ta2O5、Al2O3或具有相似的绝缘和结构性质的其他材料。使用PVD、CVD、印刷、旋涂、喷涂、烧结、热氧化或其他适合的工艺来沉积绝缘层170。绝缘层280具有低于10μm的厚度并且典型地薄如4μm。通过曝光或显影工艺、LDA、蚀刻或其他适合的工艺来去除部分绝缘层280，以在有效表面232上形成开口。开口露出半导体管芯228的部分有效表面232和通孔236以用于随后的电互连。 
图5i中，将导电层282图案化并且沉积在绝缘层280上，沉积半导体管芯228上，并且置于绝缘层280中的开口内以填充开口并接触有效表面232和通孔236。一层或多层导电层282包括Al、Cu、Sn、Ni、Au、Ag、Ti/Cu、TiW/Cu、Ti/NiV/Cu、TiW/NiV/Cu或其他适合的导电材料。导电层282的沉积使用PVD、CVD、电解电镀、无电镀或其他适合的工艺。导电层282具有低于15μm的厚度并且典型地薄如3μm。导电层282操作为RDL以将电连接扇出并从堆叠半导体器件262延伸到堆叠半导体器件262外部的点。将导电层282的一部分电连接到半导体管芯228的有效表面232上的接触焊盘。将导电层282的另一部分电连接到通孔236。取决于堆叠半导体器件262的设计和功能，导电层282的其他部分可以在电学上是共同的，或被电隔离。 
图5j中，在绝缘层280和导电层282上形成绝缘或钝化层284。绝缘层284包含一层或多层有或没有填料的低温可固化聚合物电介质抗蚀剂(例如，在低于260摄氏度固化)、SiO2、Si3N4、SiON、Ta2O5、Al2O3或具有相似的绝缘和结构性质的其他材料。使用PVD、CVD、印刷、旋涂、喷涂、烧结、热氧化或其他适合的工艺来沉积绝缘层284。绝缘层284具有低于10μm的厚度且典型地薄如4μm。通过曝光或显影工艺、LDA、蚀刻或其他适合的工艺来去除部分绝缘层284以在绝缘层中形成开口，其露出部分导电层282以用于随后的电互连。 
图5k中，将导电层286图案化并且沉积在绝缘层284上，沉积在导电层282上，并且置于绝缘层284中的开口内，作为包括种子层的一层或多层，以填充开口以及接触和电连接到导电层282。一层或多层导电层176包括Al、Cu、Sn、Ni、Au、Ag、Ti/Cu、TiW/Cu、Ti/NiV/Cu、TiW/NiV/Cu或其他适合的导电材 料。导电层286的沉积使用PVD、CVD、电解电镀、无电镀或其他适合的工艺。导电层286具有低于15μm的厚度且典型地薄如3μm。在一个实施例中，导电层286的沉积包括利用种子层和光刻的选择性镀敷。导电层286操作为RDL以将电连接扇出并从堆叠半导体器件262延伸到堆叠半导体器件262外部的点。 
绝缘层280和284以及导电层282和286一起形成薄膜288。薄膜288构成互连结构。在一个替代实施例中，薄膜288可以包括少到一个导电层，诸如导电层282。在另一替代实施例中，薄膜288包括两个或更多个RDL层，诸如导电层282和286和类似于导电层282和286的附加导电层。薄膜288可以包括如对于为特定半导体器件所需要的互连密度和电学布线而言所必要的那样多的绝缘和导电层。 
薄膜288包括堆叠半导体器件262置于其上的表面290和与表面290相对的表面292。薄膜288具有低于50μm的厚度，其薄于典型地具有250到350μm厚度的传统的THV衬底。由均利用低于10μm厚度形成的绝缘和导电材料层形成薄膜288。绝缘和导电材料薄层允许紧邻薄层内相邻的水平和垂直互连来形成水平和垂直互连(例如，具有低于50μm的间距)。利用紧邻相邻的互连所形成的水平和垂直互连，在互连结构内实现了更高密度的互连。因为薄膜288包括更高密度的互连，薄膜288在将半导体器件集成到3D半导体结构方面提供更大的灵活性。高密度互连结构适应具有变化的凸点间距的半导体管芯，例如，来自多个制造源的半导体管芯。 
导电层282和286形成水平和垂直互连或穿过薄膜288的垂直导电通孔294。将水平和垂直互连如对于到半导体管芯或元件的连接或通过薄膜288路由电信号而言所必要的那样靠近在一起而形成。例如，导电层282和286可以包括导电迹线。紧邻第二导电迹线来形成第一导电迹线(例如，导电迹线之间的间距小于50μm)。导电迹线之间的精细间距允许在薄膜288内形成用于更多的导电迹线的空间，同时与传统THV衬底相比，每个薄膜层的薄度减小了互连结构的厚度。 
导电层282和286也形成垂直导电通孔294，其中紧邻第二垂直导电通孔来形成第一垂直导电通孔(例如，垂直导电通孔间的间距小于50μm)。导电层282包括垂直导电通孔294的第一部分，以及导电层286包括垂直导电通孔294的第二部分。垂直导电通孔294可从薄膜288的表面290延伸到表面292或者可 部分地穿过薄膜288形成垂直导电通孔294。垂直导电通孔294间的间距P小于50μm。在薄膜288中垂直导电通孔294间的间距P比传统THV衬底中导电通孔间的间距(其典型地是100μm或更大)更精细。 
在薄膜288中精细间距水平和垂直互连提供了更高的互连密度和I/O端数。薄膜288提供互连间距，其允许在倒装芯片取向中将高密度的半导体管芯安装到薄膜288。附加半导体管芯可以在面对背(face-to-back)的取向上被安装在薄膜288上。薄膜288在扇出设计中延伸超出半导体管芯228的占位面积以进一步增加I/O端数。薄膜288的薄度允许更小和更薄的总体半导体器件封装，其减小了翘曲并增加了器件速度。此外，高密度互连适应每个3D半导体结构的更多的电信号并提高了互连结构与更多种多样的半导体器件和元件类型的兼容性。 
图5l中，在绝缘层284和导电层286上形成可选的绝缘或钝化层296。绝缘层296包括一层或多层有或没有填料的低温可固化聚合物电介质抗蚀剂(例如，在低于260摄氏度固化)、SiO2、Si3N4、SiON、Ta2O5、Al2O3或具有相似的绝缘和结构性质的其他材料。使用PVD、CVD、印刷、旋涂、喷涂、烧结、热氧化或其他适合的工艺来沉积绝缘层296。通过曝光或显影工艺、LDA、蚀刻或其他适合的工艺来去除部分绝缘层296以在绝缘层中形成开口，其露出部分导电层286以用于随后的电互连。 
图5l中还示出了在绝缘层296中的开口内沉积在导电层286上的导电凸点材料。在导电层296上形成凸点298。替代地，如果薄膜288包括一个RDL层，诸如导电层282，则在所述单个RDL层上形成凸点298。可以在导电层282或284上或附加导电层上形成凸点298。在堆叠半导体器件262的占位面积外侧的薄膜288区域上形成凸点298。也可以在堆叠半导体器件262正下方的薄膜288区域中形成凸点298。在一个实施例中，凸点298在堆叠半导体器件262的占位面积内形成且与堆叠半导体器件262的占位面积重叠。 
使用蒸发、电解电镀、无电镀、球滴或丝网印刷工艺来形成凸点298。凸点材料可以是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料、及其组合，具有可选的助熔剂溶液。例如，凸点材料可以是共熔的Sn/Pb、高铅焊料或无铅焊料。使用合适的附着或接合工艺来将凸点材料接合到导电层286。在一个实施例中，通过加热金属高于其熔点来回流凸点材料，以形成球形球或凸点298。在一些应用中，二次回流凸点298以改善到导电层286的电接触。在一个实施例中，在具 有湿层、阻挡层和粘合层的UBM上形成凸点298。凸点也可以被压缩接合到导电层286。凸点298表示可在导电层286上形成的一类互连结构。互连结构也可以使用接合线、导电胶、纽扣凸点、微凸点或其他电互连。 
合起来，绝缘层280、284和296以及导电层282、286，和导电凸点298形成互连结构300。包括在互连结构300中的绝缘和导电层的数量取决于电路布线设计的复杂度并随之变化。因此，互连结构300可以包括一个或多个绝缘和导电层，以促进关于堆叠半导体器件262的电互连。另外被包括在背面互连结构或RDL中的元件可被集成为互连结构300的部分以简化制造并减少关于包括前面和背面互连或RDL两者的封装的制作成本。 
图5m中，用锯条或激光切割设备302来将复合衬底或重构的晶片268分割成各个半导体器件304。 
图5n示出分割后的各个半导体器件304。半导体器件304是具有置于互连结构300的薄膜288上的堆叠半导体管芯的3D半导体结构。将半导体管芯228和半导体管芯240电连接到垂直导电通孔294。将半导体管芯240通过导电层246和248、导电凸点250和半导体管芯228的通孔236电连接到垂直导电通孔294。将半导体管芯228和240通过垂直导电通孔294电连接到外部器件。包括精细间距垂直导电通孔294的半导体器件304适应高密度半导体管芯，诸如在TSV半导体管芯上以倒装芯片取向的宽I/O存储器件。半导体器件304也适应混合半导体管芯尺寸。例如，具有存储器功能的半导体管芯和应用处理器管芯可以被面对背地集成到半导体器件304中。 
半导体器件304通过互连结构300的薄膜288中的精细间距垂直导电通孔294提供用于半导体管芯228和240的电信号的垂直下拉式路由。在堆叠半导体器件262和外部器件间的导电路径长度被减小到300μm或更小，其导致更高的速度和更有效率的器件。也减小了热路径长度。薄膜288减小了半导体器件304的总体封装高度。半导体器件304的厚度为0.5mm或更小，且典型地薄如0.2mm，而使用传统THV衬底的封装厚度为0.7到1.4mm。半导体器件304的更小的封装轮廓通过减小翘曲和提供更短的热路径而改善了半导体器件的热性能。具有薄膜层的半导体器件304的更小的封装轮廓减小了3D半导体结构的寄生电容。 
图6a-6g图示出形成Fo-eWLB的工艺的替代实施例，在Fo-eWLB上可形 成具有精细间距互连的薄膜互联结构。图6a示出了安装到载体或临时衬底312的TSV半导体管芯310。载体312包含消耗基体材料，诸如硅、聚合物、氧化铍、玻璃或其他适合的低成本、坚固的材料，以用于结构支撑。在载体312上形成交界层或双面带314作为临时粘性接合膜、蚀刻阻挡层或热释放层。 
半导体管芯310包括基体衬底材料316，诸如硅、锗、砷化镓、磷化铟或碳化硅，以用于结构支撑。半导体管芯310包括有效表面318和与有效表面318相对的后表面320。有效表面318朝向载体312取向。有效表面318包含被实现为在管芯内形成的且根据管芯的电学设计和功能来电互连的有源器件、无源器件、导电层和电介质层的模拟或数字电路。例如，电路可以包括在有效表面318内形成的一个或多个晶体管、二极管和其他电路元件以实现模拟电路或数字电路，诸如DSP、ASIC、存储器、应用处理器或其他信号处理电路。半导体管芯310可以包括分立器件。分立器件可以是有源器件，诸如晶体管和二极管，或无源器件，诸如用于RF信号处理的电容器、电阻器和电感器。半导体管芯310也可以包括封装的半导体管芯。 
使用机械钻孔、激光钻孔或深反应离子蚀刻(DRIE)来穿过衬底226形成多个通孔322。通孔322贯穿衬底316。使用电解电镀、无电镀工艺或其他合适的金属沉积工艺来利用Al、Cu、Sn、Ni、Au、Ag、Ti、钨(W)、多晶硅或其他合适的导电材料填充通孔322以形成垂直z-方向导电TSV。放置于交界层314载体312上的半导体管芯310构成复合衬底或重构的晶片324。 
图6b中，使用焊膏印刷、压缩模制、转移模制、液态密封模制、真空层压、膜辅助模制或其他合适的敷料器，将密封剂或模制化合物330沉积在交界层314和载体312上以及半导体管芯310上和周围。在半导体管芯310的后表面320上形成密封剂330，且在随后的背部研磨步骤中可以将其减薄。也可如此沉积密封剂330，使得密封剂与后表面320共面且不覆盖后表面320。密封剂330可以是聚合物复合材料，诸如带填料的环氧树脂、带填料的环氧丙烯酸盐或带适当填料的聚合物。密封剂330是非导电的，提供物理支撑并在环境上保护半导体器件免受外部元素和污染物。 
图6c示出被密封剂330覆盖的复合衬底或重构的晶片324。图6c中，使密封剂330的表面332经受利用研磨机334进行的可选的减薄操作以平坦化表面和减小密封剂的厚度。化学蚀刻也可以被用来去除和平坦化密封剂330。图6c 示出去除密封剂330的一部分以露出半导体管芯310的后表面320。 
图6d中，在半导体管芯310上安装半导体管芯或元件340。半导体管芯340包括有效表面342和后表面344。有效表面342包含被实现为在管芯内形成的且根据管芯的电学设计和功能来电互连的有源器件、无源器件、导电层和电介质层的模拟或数字电路。例如，电路可以包括在有效表面342内形成的一个或多个晶体管、二极管和其他电路元件，以实现模拟或数字电路，诸如DSP、ASIC、存储器、应用处理器或其他信号处理电路。半导体管芯340可以包括分立器件。分立器件可以是有源器件，诸如晶体管和二极管，或无源器件，诸如用于RF信号处理的电容器、电阻器和电感器。半导体管芯340也可以包括封装的半导体管芯。在一个实施例中，半导体管芯310包括应用处理器且半导体管芯340包括存储器。在另一实施例中，半导体管芯310包括存储器，且半导体管芯340包括应用处理器。替代地，半导体管芯310和340包括其他信号处理电路、分立器件、元件或封装的器件。 
半导体管芯340被置于具有朝向半导体管芯310的后表面320取向的有效表面342的半导体管芯228上。在半导体管芯340的有效表面342上形成导电层346。使用诸如铜箔叠层、印刷、PVD、CVD、溅射、电解电镀和无电镀的金属沉积工艺来形成导电层346。导电层346可以是Al、Cu、Sn、Ni、Au、Ag、Ti、W或其他合适的导电材料的一层或多层。 
在半导体管芯310的后表面320上形成导电层348。使用诸如铜箔叠层、印刷、PVD、CVD、溅射、电解电镀和无电镀的金属沉积工艺来形成导电层348。导电层348可以是Al、Cu、Sn、Ni、Au、Ag、Ti、W或其他合适的导电材料的一层或多层。导电层348接触或被电连接到通孔322。 
使用蒸发、电解电镀、无电镀、球滴或丝网印刷工艺来在导电层346或导电层348上沉积导电凸点材料。凸点材料可以是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料、及其组合，具有可选的助熔剂溶液。例如，凸点材料可以是共熔的Sn/Pb、高铅焊料或无铅焊料。使用合适的附着或接合工艺来将凸点材料接合到导电层346和348。在一个实施例中，通过加热金属高于其熔点来回流凸点材料，以形成球或凸点350。在一些应用中，二次回流凸点350以改善到导电层346和348的电接触。凸点350也可以被压缩接合或热压缩接合到导电层346和348。凸点350表示在导电层346和348上形成的一类互连结构。互连结构也 可以使用纽扣凸点、微凸点或其他电互连。 
图6a-6g中未示出，使用焊膏印刷、压缩模制、转移模制、液态密封模制、真空层压、膜辅助模制或其他合适的敷料器，来将可选的密封剂或模制化合物沉积在半导体管芯340上和周围。可选的密封剂相似于密封剂330且在半导体管芯340的后表面344上和在半导体管芯310和密封剂330上形成。 
图6e中，通过化学蚀刻、机械剥落、CMP、机械研磨、热烘、UV光、激光扫描或湿剥离来从复合衬底324去除载体312和交界层314以促进在半导体管芯310的有效表面318和半导体管芯周边附近的密封剂330上形成互连结构。 
图6e中在复合衬底324的表面上形成薄膜互连结构的工艺如图5h-5l中所示的进行，以产生如图6f中所示的包括薄膜互连结构的复合衬底324。 
图6f中，绝缘或钝化层360与绝缘层280相似且在半导体管芯310和密封剂330上形成。绝缘层360具有低于10μm的厚度且典型地薄如4μm。通过曝光或显影工艺、LDA、蚀刻或其他适合的工艺来去除部分绝缘层360，以在有效表面318上形成开口。开口露出半导体管芯310的部分有效表面318和通孔322，以用于随后的电互连。 
导电层362与导电层282相似且被沉积在绝缘层360上，沉积在半导体管芯310上，并且被置于绝缘层280中的开口内，以填充开口并接触有效表面318和通孔322。导电层362具有低于15μm的厚度且典型地薄如3μm。导电层362操作为RDL以将电连接扇出并从半导体管芯310和340延伸到半导体管芯310和340外部的点。将导电层362的一部分电连接到半导体管芯310的有效表面318上的接触焊盘。将导电层362的另一部分电连接到通孔322。取决于半导体管芯310和340的设计和功能，导电层362的其他部分可以在电学上是共同的或被电隔离。 
绝缘层或钝化层364与绝缘层284相似且在绝缘层360和导电层362上形成。绝缘层364具有低于10μm的厚度和典型地薄如4μm。通过曝光或显影工艺、LDA、蚀刻或其他适合的工艺来去除部分绝缘层364，以在绝缘层中形成开口，其露出部分导电层362以用于随后的电互连。 
导电层366与导电层286相似且被沉积在绝缘层364上，沉积在导电层362上，并且被置于绝缘层364中的开口内，作为包括种子层的一层或多层，以填充开口并接触和电连接到导电层362。导电层366具有低于15μm的厚度且典型 地薄如3μm。在一个实施例中，导电层366的沉积包括利用种子层和光刻的选择性镀敷。导电层366操作为RDL以将电连接扇出并从半导体管芯310和340延伸到半导体管芯310和340外部的点。 
绝缘层360和364以及导电层362和366一起形成薄膜368，其与薄膜288相似。薄膜368构成互连结构。在替代实施例中，薄膜368可以包括少到一个导电层，诸如导电层362。薄膜368可以包括如对于为特定半导体器件所需要的互连密度和电学布线而言所必要的那样多的绝缘和导电层。 
薄膜368包括半导体管芯310和340置于其上的表面370和与表面370相对的表面372。薄膜368具有低于50μm的厚度，其薄于典型地具有250到350μm厚度的传统的THV衬底。薄膜368由绝缘和导电材料层形成，绝缘和导电材料层可以均利用小于10μm的厚度来形成。绝缘和导电材料薄层允许紧邻薄层内相邻的水平和垂直互连来形成水平和垂直互连(例如，具有低于50μm的间距)。利用紧邻相邻的互连所形成水平和垂直互连，在互连结构内实现了更高密度的互连。因为薄膜368包括更高密度的互连，薄膜368在将半导体器件集成到3D半导体结构方面提供更大的灵活性。高密度互连结构适应具有变化的凸点间距的半导体管芯，例如，来自多个制造源的半导体管芯。 
导电层362和366形成水平和垂直互连或穿过薄膜368的垂直导电通孔374。将水平和垂直互连如对于到半导体管芯或元件的连接或通过薄膜368路由电信号而言所必要的那样靠近在一起而形成。例如，导电层362和366可以包括导电迹线。紧邻第二导电迹线来形成第一导电迹线(例如，导电迹线之间的间距小于50μm)。导电迹线之间精细间距允许在薄膜368内形成用于更多的导电迹线的空间，同时与传统THV衬底相比，每个薄膜层的薄度减小了互连结构的厚度。 
导电层362和366还形成垂直导电通孔374，其中紧邻第二垂直导电通孔来形成第一垂直导电通孔(例如，垂直导电通孔间的间距小于50μm)。导电层362包括垂直导电通孔374的第一部分，以及导电层366包括垂直导电通孔374的第二部分。垂直导电通孔374可从薄膜368的表面370延伸到表面372或者可部分地穿过薄膜368形成垂直导电通孔374。垂直导电通孔374间的间距小于50μm。在薄膜368中的垂直导电通孔374间的间距比传统THV衬底中导电通孔间的间距(其典型地是100μm或更大)更精细。 
在薄膜368中精细间距水平和垂直互连提供了更高的互连密度和I/O端数。薄膜368提供互连间距，其允许在倒装芯片取向上将高密度的半导体管芯安装到薄膜368。附加半导体管芯可以在面对背的取向上被安装在薄膜368上。薄膜368在扇出设计中延伸超出半导体管芯310和340的占位面积以进一步增加I/O端数。薄膜368的薄度允许更小和更薄的总体半导体器件封装，其减小了翘曲并增加了器件速度。此外，高密度互连适应每个3D半导体结构的更多的电信号并提高了互连结构与更多种多样的半导体器件和元件类型的兼容性。 
可选的绝缘或钝化层376与绝缘层296相似且在绝缘层364和导电层366上形成。将导电凸点材料在绝缘层376中的开口内沉积在导电层366上。在导电层366上形成凸点378。替代地，如果薄膜368包括一个RDL层，诸如导电层362，则在单个RDL层上形成凸点378。可以在导电层362或364或附加导电层上形成凸点378。在半导体管芯310和340的占位面积外侧的薄膜368区域上形成凸点378。凸点378与凸点298相似且可以在半导体管芯310和340的占位面积正下面或与其重叠的薄膜368区域中形成。在一个实施例中，凸点378在半导体管芯310和340的占位面积内被形成并与半导体管芯310和340的占位面积重叠。凸点378表示在导电层366上形成的一类互连结构。互连结构也可以使用接合线、导电胶、纽扣凸点、微凸点或其他电互连。 
合起来，绝缘层360、364和376以及导电层362、366，和导电凸点378形成互连结构380。被包括在互连结构380中的绝缘和导电层的数量取决于电路布线设计的复杂度并随之变化。因此，互连结构380可以包括一个或多个绝缘和导电层以促进关于半导体管芯310和340的电互连。将另外被包括在背面互连结构或RDL中的元件可被集成为互连结构380的部分，以简化制造并减少关于包括前面和背面互连或RDL两者的封装的制作成本。 
用锯条或激光切割设备382来将复合衬底或重构的晶片324分割成各个半导体器件384。 
图6g示出分割后的各个半导体器件384。半导体器件384是具有置于互连结构380的薄膜368上的堆叠半导体管芯的3D半导体结构。将半导体管芯310和半导体管芯340电连接到垂直导电通孔374。将半导体管芯340通过导电层346和348、导电凸点350和半导体管芯310的通孔322电连接到垂直导电通孔374。将半导体管芯310和340通过垂直导电通孔374电连接到外部器件。包括 精细间距垂直导电通孔374的半导体器件384适应高密度半导体管芯，诸如在TSV半导体管芯上以倒装芯片取向的宽I/O存储器件。半导体器件384也适应混合半导体管芯尺寸。例如，具有存储器功能的半导体管芯和应用处理器管芯可以被面向背地集成到半导体器件384中。 
半导体器件384通过互连结构380的薄膜368中的精细间距垂直导电通孔374来提供用于半导体管芯310和340的电信号的垂直下拉式路由。在半导体管芯310和340与外部器件之间的导电路径长度被减小到300μm或更小，其导致更高的速度和更有效率的器件。也减小了热路径长度。薄膜368减小了半导体器件384的总体封装高度。半导体器件384的厚度为0.5mm或更小，且典型地薄如0.2mm，而使用传统THV衬底的封装厚度为0.7到1.4mm。半导体器件384的更小的封装轮廓通过减小翘曲并提供更短的热路径而改善了半导体器件的热性能。具有薄膜层的半导体器件384的更小的封装轮廓减小了3D半导体结构的寄生电容。 
尽管已经详细说明了本发明的一个或多个实施例，但本领域技术人员将认识到在不背离如下述权利要求中所阐述的本发明的范围的情况下，可以对那些实施例做出修改和改编。 

Claims (15)

1.一种制造半导体器件的方法，包括：
提供多个第一半导体管芯；
在第一半导体管芯的第一表面上和第一半导体管芯周围沉积密封剂；
在密封剂上和第一半导体管芯的与第一表面相对的第二表面上形成绝缘层；
在绝缘层上形成第一导电层；以及
在第一半导体管芯上布置第二半导体管芯且将其电连接到第一导电层。
2.权利要求1的方法，进一步包括在第一导电层上形成第二导电层以形成垂直导电通孔。
3.权利要求2的方法，其中垂直导电通孔间的间距小于50微米。
4.权利要求1的方法，进一步包括在第一半导体管芯的占位面积外的第一导电层上形成凸点。
5.权利要求1的方法，进一步包括在第一半导体管芯的第二表面上布置第二半导体管芯。
6.一种制造半导体器件的方法，包括：
提供第一半导体管芯；
在第一半导体管芯上沉积密封剂；
在第一半导体管芯上形成包括开口的绝缘层；
在第一半导体管芯上形成第一导电层；以及
在第一半导体管芯上布置第二半导体管芯且将其电连接到第一导电层。
7.权利要求6的方法，其中绝缘层的开口间的间距小于50微米。
8.权利要求6的方法，进一步包括穿过第一半导体管芯形成的穿透硅通孔(TSV)。
9.权利要求8的方法，进一步包括在第一半导体管芯的后表面上布置第二半导体管芯。
10.权利要求6的方法，进一步包括在第一半导体管芯的占位面积外的第一导电层上形成凸点。
11.一种半导体器件，包括：
第一半导体管芯；
在第一半导体管芯上形成的包括开口的第一绝缘层；
在第一半导体管芯上形成的第一导电层；以及
置于第一半导体管芯上的第二半导体管芯。
12.权利要求11的半导体器件，其中将第一和第二半导体管芯通过第一导电层电连接。
13.权利要求11的半导体器件，进一步包括在第一半导体管芯的占位面积外的第一导电层上形成凸点。
14.权利要求11的半导体器件，进一步包括置于第一半导体管芯的有效表面上的第二半导体管芯。
15.权利要求11的半导体器件，进一步包括穿过第一半导体管芯形成的穿透硅通孔(TSV)。
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