CN102157391A - 半导体器件和形成垂直互连的薄外形wlcsp的方法 - Google Patents

半导体器件和形成垂直互连的薄外形wlcsp的方法 Download PDF

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CN102157391A
CN102157391A CN2011100311350A CN201110031135A CN102157391A CN 102157391 A CN102157391 A CN 102157391A CN 2011100311350 A CN2011100311350 A CN 2011100311350A CN 201110031135 A CN201110031135 A CN 201110031135A CN 102157391 A CN102157391 A CN 102157391A
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semiconductor chip
semiconductor
interconnection structure
active surface
sealant
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CN102157391B (zh
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池熺朝
赵南柱
申韩吉
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Changdian Integrated Circuit Shaoxing Co ltd
Stats Chippac Pte Ltd
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Stats Chippac Pte Ltd
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Abstract

半导体晶圆具有多个第一半导体小片。第二半导体小片安装在第一半导体小片上。第一半导体小片的活性表面定向成朝向第二半导体小片的活性表面。密封剂沉积在第一半导体小片和第二半导体小片上。第二半导体小片的与活性表面相对的背面的一部分被移除。导电柱绕第二半导体小片形成。TSV可形成为穿过第一半导体小片。互连结构形成在第二半导体小片的背面、密封剂和导电柱上。互连结构与导电柱电连接。第一半导体小片的与活性表面相对的背面的一部分被移除。热沉或屏蔽层可形成在第一半导体小片的背面上。

Description

半导体器件和形成垂直互连的薄外形WLCSP的方法
技术领域
本发明总地涉及半导体器件，且更具体地涉及半导体器件和形成薄外形WLCSP的方法，该薄外形WLCSP包括面对面的半导体小片(die)，其具有在整个封装占据面积(footprint)上的垂直的互连能力。
背景技术
半导体器件常见于现代的电子产品。半导体器件在电气构件的数量和密度方面各有不同。离散的半导体器件通常包括一种类型的电气构件，例如，发光二极管(LED)，小信号晶体管，电阻器，电容器，电感器，和功率金属氧化物半导体场效应晶体管(MOSFET)。集成半导体器件通常包括上百万个电气构件。集成半导体器件的举例包括微控制器，微处理器，电荷耦合器件(CCD)，太阳能电池，和数字微镜器件(DMD)。
半导体器件执行很多功能，诸如高速计算，传送和接收电磁信号，控制电子器件，将阳光转换为电，和创建用于电视显示的视觉投射。半导体器件见于娱乐，通信，功率转换，网络，计算机，和消费者产品的领域。半导体器件还见于军事应用，航空，汽车，工业控制器，和办公室设备。
半导体器件利用半导体材料的电气属性。半导体材料的原子结构允许通过电场或基极电流的施加或通过掺杂的工艺操纵它的电传导性。掺杂将杂质引入半导体材料用以操纵和控制半导体器件的传导性。
半导体器件包括有源和无源电气结构。有源结构，包括双极和场效应晶体管，控制电流的流动。通过改变掺杂的水平和电场或基极电流的施加，晶体管促进或限制电流的流动。无源结构，包括电阻器，电容器，和电感器，创建执行各种电气功能所需的电压与电流之间的关系。无源和有源结构电连接以形成电路，使半导体器件能够执行高速计算和其它有用功能。
通常利用两个复杂的制造工艺制造半导体器件，即，前段制造，和后段制造，它们均潜在地包括几百个步骤。前段制造包括在半导体晶圆的表面上形成多个小片。各小片通常相同，并包括通过电连接有源和无源构件形成的电路。后段制造包括从制成的晶圆分割独立的小片，和封装小片，以提供结构上的支撑和环境上的隔离。
半导体制造的一个目的是生产更小的半导体器件。更小的器件通常消耗更少的功率，具有更高的性能，并可更有效率地生产。此外，更小的半导体器件具有更小的占据面积，这是更小的终端产品所希望的。可通过前段工艺上的改进获得更小的小片尺寸，使小片具有更小的、更高密度的有源和无源构件。后段工艺中，可通过电互连和封装材料上的改进使半导体器件封装具有更小的占据面积。
在包括堆叠的半导体小片的晶圆级芯片封装(WLCSP)中，可通过导电穿透硅通道(TSV：through silicon via)、通孔通道(THV：through hole via)或在密封剂(encapsulant)中的镀铜导电柱实现垂直的电互连。希望将WLCSP制作得尽可能薄。同时，应当最大化垂直的互连能力。TSV消耗硅区域，并减少用于电路的活性表面区域。在THV或密封剂中的导电柱的情况下，WLCSP绕下半导体小片的周长仅具有有限的垂直的互连，因为在下小片的占据面积内没有垂直的互连。薄外形的要求通过减少形成垂直的互连的占据面积限制了垂直的互连能力。
发明内容
存在对具有更强的垂直的互连能力的薄外形WLCSP的需求。因此，在一个实施例中，本发明为制造半导体器件的方法，包括以下步骤：提供具有多个第一半导体小片的半导体晶圆，第一半导体小片均具有活性表面，和将第二半导体小片安装到第一半导体小片上。第一半导体小片的活性表面定向成朝向第二半导体小片的活性表面。所述方法进一步包括以下步骤：在第一半导体小片和第二半导体小片上沉积(deposit)密封剂，移除第二半导体小片的与活性表面相对的背面的一部分，绕第二半导体小片形成导电柱，和在第二半导体小片的背面、密封剂和导电柱上形成互连结构。互连结构与导电柱电连接。所述方法进一步包括以下步骤：移除第一半导体小片的与活性表面相对的背面的一部分，和将半导体晶圆分割为单独的半导体器件。
在另一个实施例中，本发明为制造半导体器件的方法，包括以下步骤：提供具有多个第一半导体小片的半导体晶圆，第一半导体小片均具有活性表面，和将第二半导体小片安装到第一半导体小片上。第一半导体小片的活性表面定向成朝向第二半导体小片的活性表面。所述方法进一步包括以下步骤：绕第二半导体小片形成垂直的互连结构，在第一半导体小片和第二半导体小片上沉积密封剂，移除第二半导体小片的与活性表面相对的背面的一部分，和在第二半导体小片的背面、密封剂和垂直的互连结构上形成积层互连结构。积层互连结构与垂直的互连结构电连接。所述方法进一步包括以下步骤：移除第一半导体小片的与活性表面相对的背面的一部分，和将半导体晶圆分割为单独的半导体器件。
在另一个实施例中，本发明为制造半导体器件的方法，包括以下步骤：提供具有活性表面的第一半导体小片，和将第二半导体小片安装到第一半导体小片上。第一半导体小片的活性表面定向成朝向第二半导体小片的活性表面。所述方法进一步包括以下步骤：绕第二半导体小片形成垂直的互连结构，在第一半导体小片和第二半导体小片上沉积密封剂，移除第二半导体小片的与活性表面相对的背面的一部分，和在第二半导体小片的背面、密封剂和垂直的互连结构上形成积层互连结构。积层互连结构与垂直的互连结构电连接。所述方法进一步包括以下步骤：移除第一半导体小片的与活性表面相对的背面的一部分。
在又一个实施例中，本发明为半导体器件，包括具有活性表面的第一半导体小片。第二半导体小片安装在第一半导体小片上。第一半导体小片的活性表面定向成朝向第二半导体小片的活性表面。垂直的互连结构绕第二半导体小片形成。密封剂沉积在第一半导体小片和第二半导体小片上。积层互连结构形成在第二半导体小片的背面、密封剂和垂直的互连结构上。积层互连结构与垂直的互连结构电连接。
附图说明
图1图示了表面上安装有不同的类型的封装的PCB；
图2a-2c图示了安装在PCB上的代表性的半导体封装的进一步细节；
图3a-3l图示了形成在整个封装占据面积上具有垂直的互连能力的薄外形WLCSP的工艺；
图4图示了在整个封装占据面积上具有垂直的互连能力的薄外形WLCSP；
图5图示了在密封剂中形成的用于垂直的互连的突起和导电柱；
图6图示了在密封剂中形成的用于垂直的互连的杆和导电柱；
图7图示了安装在WLCSP的下半导体小片上的热沉；
图8a-8b图示了形成在WLCSP的下半导体小片上的TSV；
图9图示了安装在WLCSP的下半导体小片上的屏蔽层；
图10图示了安装成与WLCSP的下半导体小片面对面的并列半导体小片；
图11a-11d图示了在密封剂中形成导电柱的另一工艺；和
图12a-12e图示了用以在密封剂中形成导电柱的引线框插入器。
具体实施方式
在随后描述中，将参照附图以一个或更多实施例描述本发明，附图中，类似标号代表相同或相似元件。尽管以实现本发明的目的的最佳实施例的方式描述本发明，但本领域技术人员应当理解，意图覆盖包含于通过随附权利要求和随后公开和附图支持的等效物限定的替换物、变型物和等效物。
通常利用两个复杂的制造工艺制造半导体器件：前段制造和后段制造。前段制造包括在半导体晶圆的表面上形成多个小片。晶圆上的各小片均包括有源和无源电气构件，它们电连接形成功能性电路。有源电气构件，诸如晶体管和二极管，具有控制电流的流动的能力。无源电气构件，诸如电容器，电感器，电阻器，和变压器，创建用以执行电路功能所需的电压和电流之间的关系。
通过一系列的工艺步骤，包括掺杂，沉积，光刻，蚀刻，和平面化，将无源和有源构件形成在半导体晶圆的表面上。通过诸如离子注入或热扩散的技术，掺杂将杂质引入半导体材料。掺杂工艺改变有源器件的半导体材料的电传导性，将半导体材料转换为绝缘体、导体，或根据电场或基极电流动态地改变半导体材料传导性。晶体管包括根据需要配置的各种类型和程度的掺杂的区域，使晶体管能够在电场或基极电流的施加时促进或限制电流的流动。
有源和无源构件通过具有不同的电气属性的材料的层形成。可通过各种沉积技术形成层，所述沉积技术部分由沉积的材料的类型确定。例如，薄的薄膜沉积可包括化学气相沉积(CVD)，物理气相沉积(PVD)，电解镀，和非电解镀工艺。各层通常被图案化，以形成有源构件部分，无源构件部分，或构件之间的电连接部分。
可利用光刻对层进行图案化，包括在待图案化的层上沉积光敏材料，例如光阻材料。利用光将图案从光掩膜转移到光阻材料上。利用溶剂移除经受光的光阻材料图案的部分，暴露待图案化的下层(underlying layer)的部分。移除光阻材料的剩余部分，留下图案化的层。备选地，通过将材料直接沉积在通过利用诸如非电解镀和电解镀的技术的之前的沉积/蚀刻工艺形成的区域或空隙，对一些类型的材料进行图案化。
在已存在的图案上沉积薄的薄膜材料，可能扩大底部图案和创建非均匀平坦表面。生产更小的和更密集地封装的有源和无源构件需要均匀平坦表面。平面化可用于从晶圆的表面移除材料和生成均匀平坦表面。平面化包括用抛光垫抛光晶圆的表面。在抛光期间，研磨材料和腐蚀性化学品被添加到晶圆的表面。研磨材料的机械动作和化学品的腐蚀性动作的组合移除所有不规则表面形状，实现均匀平坦表面。
后段制造指将制成的晶圆切割或分割(singulate)为独立的小片，并然后为了结构上的支撑和环境上的隔离而封装小片。为了分割小片，沿晶圆的非功能性区域，称为锯道或划痕，对晶圆进行刻痕，使其断开。晶圆分割利用激光切割工具或锯条。分割之后，将独立的小片安装在封装基板上，所述封装基板包括用于与其它系统构件互连的插脚或接触垫(contact pad)。然后，形成在半导体小片上的接触垫与封装内的接触垫连接。电连接可通过焊料突起，柱形突起，导电胶，或引线结合实现。密封剂或其它模制材料沉积在封装上，以提供物理支撑和电隔离。制成的封装然后被插入电气系统，且其它系统构件可利用半导体器件的功能。
图1图示了具有芯片载体基板或印刷电路板(PCB)52的电子器件50，芯片载体基板或印刷电路板(PCB)52的表面上安装有多个半导体封装。电子器件50可具有一种类型的半导体封装，或多种类型的半导体封装，这取决于应用。出于说明的目的，图1中显示了不同的类型的半导体封装。
电子器件50可以是利用半导体封装以执行一个或更多电气功能的独立系统。备选地，电子器件50可以是更大的系统的子构件。例如，电子器件50可以是图像卡，网络接口卡，或可插入计算机的其它信号处理卡。半导体封装可包括微处理器，存储器，专用集成电路(ASIC)，逻辑电路，模拟电路，RF电路，离散器件，或其它半导体小片或电气构件。
在图1中，PCB52提供用于结构上的支撑和安装在PCB上的半导体封装的电互连的通用基板。利用蒸镀，电解镀，非电解镀，丝网印刷术，或其它适当的金属沉积工艺，将导电信号迹线54形成在PCB52的表面上或PCB52的层内。信号迹线54提供各半导体封装、安装的构件和其它外部系统构件之间的电连通。迹线54还提供功率和各半导体封装的接地连接。
在一些实施例中，半导体器件具有两个封装水平。第一水平封装为用于将半导体小片机械地和电气地附接于中间载体的技术。第二水平封装包括将中间载体机械地和电气地附接于PCB。在其它实施例中，半导体器件可仅具有第一水平封装，其中直接将小片机械地和电气地安装在PCB上。
出于说明的目的，显示了在PCB52上的第一水平封装的若干类型，包括引线结合封装56和倒装芯片58。此外，显示了安装在PCB52上的第二水平封装的若干类型，包括球栅阵列(BGA)60，突起芯片载体(BCC)62，双列直插封装(DIP)64，矩栅阵列(LGA)66，多芯片模块(MCM)68，四面扁平无引脚封装(QFN)70，和四面扁平封装72。依据系统要求，以第一和第二水平封装形式的任何组合构造的半导体封装的任何组合，以及其它电子构件，可与PCB52连接。尽管在一些实施例中，电子器件50包括单个附接的半导体封装，但是其它实施例需要多个互连的封装。通过单个基板上的一个或更多半导体封装的组合，制造商可将预制的构件结合于电子器件和系统中。因为半导体封装包括复杂的功能性，所以可利用更便宜的构件和流水线式的制造工艺制造电子器件。获得的器件更不易失效，且制造更加便宜，使得对消费者而言成本更低。
图2a-2c显示了示范性半导体封装。图2a图示了安装在PCB52上的DIP64的进一步细节。半导体小片74包括有源区域，所述有源区域包括实现为有源器件、无源器件、导电层和形成在小片内的介电层的模拟或数字电路，并根据小片的电气设计而电互连。例如，所述电路可包括一个或更多晶体管，二极管，电感器，电容器，电阻器，和形成在半导体小片74的有源区域内的其它电路元件。接触垫76为一层或更多层的导电材料，诸如铝(Al)，铜(Cu)，锡(Sn)，镍(Ni)，金(Au)，或银(Ag)，并与形成在半导体小片74内的电路元件电连接。在DIP64的装配期间，利用金-硅共晶层或粘着性材料诸如热环氧树脂或环氧树脂，将半导体小片74安装在中间载体78上。封装体包括绝缘封装材料，诸如聚合物或陶瓷。导体导线80和引线结合82提供半导体小片74和PCB52之间的电互连。密封剂84沉积在封装上，其通过防止水分和颗粒进入封装和污染小片74或引线结合82而用于环境上的保护。
图2b图示了安装在PCB52上的BCC62的进一步细节。利用底部填充材料或环氧树脂粘着性材料92，将半导体小片88安装在载体90上。引线结合94提供接触垫96和98之间的第一水平封装互连。模制复合物或密封剂100沉积在半导体小片88和引线结合94上，以提供用于器件的物理支撑和电隔离。利用适当的金属沉积工艺诸如电解镀或非电解镀，将接触垫102形成在PCB52的表面上，以防止氧化。接触垫102与PCB52中的一个或更多导电信号迹线54电连接。突起104形成在BCC62的接触垫98和PCB52的接触垫102之间。
在图2c中，通过倒装芯片形式的第一水平封装，将半导体小片58安装成向下面朝中间载体106。半导体小片58的有源区域108包括模拟或数字电路，所述模拟或数字电路实现为根据小片的电气设计形成的有源器件，无源器件，导电层，和介电层。例如，电路可包括一个或更多的晶体管，二极管，电感器，电容器，电阻器，和有源区域108内的其它电路元件。半导体小片58通过突起110与载体106电气地和机械地连接。
BGA60利用突起112通过BGA形式的第二水平封装与PCB52电气地和机械地连接。半导体小片58通过突起110、信号线114和突起112与PCB52中的导电信号迹线54电连接。模制复合物或密封剂116沉积在半导体小片58和载体106上，以便为器件提供物理支撑和电隔离。倒装芯片半导体器件提供从半导体小片58上的有源器件到PCB52上的传导路线的短的电传导路径，以便减少信号传播距离，降低电容，和改善总体电路性能。在另一实施例中，半导体小片58可利用倒装芯片形式的第一水平封装直接与PCB52机械地和电气地连接，而不使用中间载体106。
图3a-3l结合图1和2a-2c图示了形成薄外形WLCSP的工艺，所述薄外形WLCSP包括在整个封装占据面积上具有垂直的互连能力的面对面的半导体小片。图3a显示了半导体晶圆120，其具有基极基板材料，诸如硅，锗，砷化镓，磷化铟，或碳化硅，用于结构上的支撑。多个半导体小片或构件124形成在通过如上所述的锯道126分离的晶圆120上。形成晶圆的基板或载体128包括临时的或牺牲性的基底材料，诸如硅，聚合物，聚合物复合材料，金属，陶瓷，玻璃，玻璃环氧材料，氧化铍，或用于结构上的支撑的其它适当的低成本的刚性材料。显示了晶圆120安装在载体128上。
图3b显示了安装在载体128上的半导体晶圆120的一部分的横截面视图。各半导体小片124具有活性表面130，所述活性表面130包括实现为有源器件、无源器件、导电层和形成在小片内的介电层并根据小片的电气设计和功能而电互连的模拟或数字电路。例如，电路可包括一个或更多晶体管，二极管，和形成在活性表面130内的其它电路元件，以实现模拟电路或数字电路，诸如数字信号处理器(DSP)，ASIC，存储器，或其它信号处理电路。半导体小片124还可包括IPDS，诸如电感器，电容器，和电阻器，用于RF信号处理。接触垫132与活性表面130上的电路电连接。
在图3c中，利用锯条或激光切割工具136，可选凹槽134部分地切入半导体晶圆120的锯道126。凹槽134仅部分地延伸进入锯道126，并没有完全地切穿半导体晶圆120。凹槽允许将之后沉积的密封剂形成在半导体小片124的侧部。
继续参看图3b的半导体晶圆120，利用突起或微型突起140，将半导体小片138安装在接触垫132a上，如图3d所示。半导体小片138具有活性表面142，活性表面142包括实现为有源器件、无源器件、导电层和形成在小片内的介电层并根据小片的电气设计和功能而电互连的模拟或数字电路。例如，电路可包括一个或更多晶体管，二极管，和形成在活性表面142内的其它电路元件，以实现模拟电路或数字电路，诸如DSP，ASIC，存储器，或其它信号处理电路。半导体小片138可还包括IPDS，诸如电感器，电容器，和电阻器，用于RF信号处理。在一个实施例中，半导体小片138为倒装芯片类型器件。突起140与接触垫144连接，所述接触垫144与活性表面142上的电路电连接。
离散的半导体构件146与半导体晶圆120上的接触垫132b电连接。离散的半导体构件146可为有源器件，诸如晶体管和二极管，或无源器件，诸如电容器，电阻器，和电感器。
在图3e中，利用胶印刷，压缩模制，传递模制，液体密封剂模制，真空层压，旋转涂覆，或其它适当的施加器，将密封剂或模制复合物148沉积在半导体小片138和晶圆120上。密封剂148可为聚合物复合材料，诸如带有填料的环氧树脂，带有填料的环氧丙烯酸酯，或具有合适的填料的聚合物。密封剂148为非导电的，并在环境上保护半导体器件免受外部元件和污染物影响。在具有图3c中显示的可选凹槽134的情况下，密封剂148还被沉积进入凹槽，以在分割之后保护半导体小片124的侧部。
在图3f中，研磨机150从半导体小片138的与活性表面142相对的背面152移除了密封剂148和粒状材料的一部分。在研磨工艺之后，半导体小片138的背面152与密封剂148的顶表面共面。
在图3g中，利用激光钻孔，机械钻孔，或深反应离子蚀刻(DRIE)，在接触垫132c上，将多个通道154形成于密封剂148内。利用电解镀，非电解镀工艺，或其它适当的金属沉积工艺，在通道154内填充Al，Cu，Sn，Ni，Au，Ag，钛(Ti)，W，多晶硅，或其它适当的导电材料，以形成导电柱156，如图3h所示。导电柱156具有20-200微米(μm)的高度范围。
在图3i中，积层互连结构160形成在导电柱156、半导体小片138和密封剂148上。积层互连结构160包括通过PVD、CVD、印刷、旋转涂覆、喷涂涂覆或热氧化形成的绝缘或钝化层162。绝缘层162可为一层或多层二氧化硅(SiO2)、氮化硅(Si3N4)、氮氧化硅(SiON)、五氧化二钽(Ta2O5)、氧化铝(Al2O3)或具有类似的绝缘和结构属性的其它材料。利用图案化和PVD，CVD，电解镀，非电解镀工艺，或其它适当的金属沉积工艺，形成导电层164。导电层164可为一层或多层Al、Cu、Sn、Ni、Au、Ag或其它适当的导电材料。导电层164与导电柱156电连接，且部分地作为重新分布层(RDL)操作，以延伸导电柱的电连接。
在一个实施例中，集成无源器件(IPDS)，诸如电容器，电阻器，或电感器，可形成在积层互连结构160内。
在图3j中，基板或载体168包括临时或牺牲性基底材料，诸如硅，聚合物，聚合物复合物，金属，陶瓷，玻璃，玻璃环氧材料，氧化铍，或用于结构上的支撑的其它适当的低成本的刚性材料。图3a-3i描述组件被倒置，并随积层互连结构160一起被安装在载体168上。通过化学蚀刻，机械剥离，CMP，机械研磨，热焙(thermal bake)，激光扫描，或湿式剥离(wet stripping)，移除临时的载体128。
在图3k中，研磨机170从半导体小片124的与活性表面130相对的背面171移除过量的粒状材料。
在图3l中，基板或载体172包括临时的或牺牲性基底材料，诸如硅，聚合物，聚合物复合物，金属，陶瓷，玻璃，玻璃环氧材料，氧化铍，或用于结构上的支撑的其它适当的低成本的刚性材料。图3k描述的组件被颠倒，并随半导体小片124一起被安装在载体172上。通过化学蚀刻，机械剥离，CMP，机械研磨，热焙，激光扫描，或湿式剥离，移除临时的载体168。
利用蒸镀，电解镀，非电解镀，球降(ball drop)，或丝网印刷术工艺，将导电突起材料沉积在导电层164上。突起材料可为Al，Sn，Ni，Au，Ag，Pb，Bi，Cu，焊剂，及其组合，其具有可选的焊剂溶液。例如，突起材料可为共晶Sn/Pb，高铅焊剂，或无铅焊剂。利用适当的附接或结合工艺，将突起材料与导电层164结合。在一个实施例中，通过将材料加热至它的熔点以上，使突起材料回流，形成球或球形突起174。在一些应用中，突起174可二次回流，以改善与导电层164的电接触。突起还可与导电层164压缩结合。突起174代表可形成在导电层164上的互连结构的一种类型。互连结构还可利用结合引线，导电胶，柱形突起，微型突起，或其它电互连。
通过锯条或激光切割工具176穿过锯道126，分割半导体晶圆120，如图3l所示。切割通过半导体晶圆120，仅部分地进入载体172。通过化学蚀刻，机械剥离，CMP，机械研磨，热焙，激光扫描，或湿式剥离，移除临时的载体172，以完成独立的WLCSP180的分离。
图4显示了分割之后的WLCSP180。利用面对面(F2F)-小片对晶圆(D2W)结合工艺，制成WLCSP180，如图3a-3l所示。由于小片附接和密封工艺之后的半导体小片124和138的小片的后段研磨工艺，所以WLCSP180具有薄的封装外形，见图3f和3k。小片附接和密封之后的后段研磨实现薄的可靠的封装，其在操作期间更加不容易产生缺陷。导电柱156提供半导体小片124和138与积层互连结构160之间的电互连。半导体小片124通过突起140、接触垫132a和接触垫144与半导体小片138电连接。积层互连结构160提供全阵列互连占据面积，绕下半导体小片124的周长和下半导体小片的占据面积内。亦即，导电柱156和积层互连结构160的组合允许WLCSP180的整个占据面积用于垂直的互连，同时维持薄的封装外形。
图5显示了类似于图4的实施例，形成在密封剂148内的突起182和导电柱184在接触垫132c和积层互连结构160的导电层164之间。在该实施例中，通过利用如图3c的凹槽134，密封剂148覆盖半导体小片124的侧部。
图6显示了类似于图4的实施例，形成在密封剂148内的杆186和导电柱188在接触垫132c和积层互连结构160的导电层164之间。在该实施例中，通过利用如图3c的凹槽134，密封剂148覆盖半导体小片124的侧部。
图7显示了类似于图4的实施例，热沉190和可选热接口材料(TIM)191安装在半导体小片124的背面171上。热沉190可为Al，Cu，或高热传导性的另外的材料，以提供用于半导体小片124的散热。TIM191可为氧化铝，氧化锌，氮化硼，或粉末银。TIM191有助于由半导体小片124产生的热的分布和消散。
图8a显示了类似于图4的实施例，导电性穿透硅通道(TSV)192形成为穿过半导体小片124。利用激光钻孔，机械钻孔，或DRIE，在接触垫132c上，多个通道形成为穿过半导体小片124。利用电解镀，非电解镀工艺，或其它适当的金属沉积工艺，在通道内填充Al，Cu，Sn，Ni，Au，Ag，Ti，W，多晶硅，或其它适当的导电材料，以形成用于垂直的互连的导电TSV192。接触垫194形成在半导体小片124的背面171上，并与TSV192电连接。
在图8b中，利用蒸镀，电解镀，非电解镀，球降，或丝网印刷术工艺，将导电突起材料沉积在导电垫194上。突起材料可为Al，Sn，Ni，Au，Ag，Pb，Bi，Cu，焊剂，和其组合，其具有可选的焊剂溶液。例如，突起材料可为共晶Sn/Pb，高铅焊剂，或无铅焊剂。利用适当的附接或结合工艺，将突起材料与导电垫194结合。在一个实施例中，通过将材料加热至它的熔点以上，使突起材料回流，形成球或球形突起196。在一些应用中，使突起196二次回流，以改善与导电垫194的电接触。突起还可与导电垫194压缩结合。突起196代表可形成在导电垫194上的互连结构的一种类型。互连结构还可利用结合引线，导电胶，柱形突起，微型突起，或其它电互连。
半导体小片198通过突起200安装在积层互连结构160上。半导体小片198具有活性表面202，活性表面202包括实现为有源器件、无源器件、导电层和形成在小片内的介电层并根据小片的电气设计和功能电互连的模拟或数字电路。例如，电路可包括一个或更多的晶体管，二极管，和形成在活性表面202内的其它电路元件，以实现模拟电路或数字电路，诸如DSP，ASIC，存储器，或其它信号处理电路。半导体小片198还可包括IPDS，诸如电感器，电容器，和电阻器，用于RF信号处理。在一个实施例中，半导体小片198为倒装芯片类型器件。突起200与接触垫204连接，接触垫204与活性表面202上的电路电连接。
图9显示了类似于图8a的实施例，屏蔽层210形成在半导体小片124的背面171上。屏蔽层210可为Cu，Al，铁素体或羰基铁，不锈钢，镍银，低碳钢，硅铁钢，箔，环氧树脂，导电树脂，和能够阻隔或吸收EMI、RFI和其它器件之间的干扰的其它金属和复合物。屏蔽层210还可为非金属材料，诸如炭黑或铝片，以减少EMI和RFI的影响。屏蔽层210通过接触垫194、TSV192、导电柱156和积层互连结构160接地。
图10显示了图3b的进一步的实施例，利用突起或微型突起214，将两个并列的半导体小片212安装在接触垫132a上。半导体小片212具有活性表面216，活性表面216包括实现为有源器件、无源器件、导电层和形成在小片内的介电层并根据小片的电气设计和功能电互连的模拟或数字电路。例如，电路可包括一个或更多的晶体管，二极管，和形成在活性表面216内的其它电路元件，以实现模拟电路或数字电路，诸如DSP，ASIC，存储器，或其它信号处理电路。半导体小片212还可包括IPDS，诸如电感器，电容器，和电阻器，用于RF信号处理。在一个实施例中，半导体小片212为倒装芯片类型器件。突起214与接触垫218连接，接触垫218与活性表面216上的电路电连接。
离散的半导体构件220与半导体晶圆120上的接触垫132b电连接。离散的半导体构件220可为有源器件，诸如晶体管和二极管，或无源器件，诸如电容器，电阻器，和电感器。
图11a-11d显示了形成穿过密封剂的导电柱的另一工艺。作为图3d的进一步改进，光阻材料层222沉积在半导体小片138和半导体晶圆120上，如图11a所示。通过蚀刻工艺，暴露和移除接触垫132c上的光阻材料层222的一部分。利用电解镀，非电解镀，或选择性电镀工艺，将导电材料，诸如Cu，Al，钨(W)，Au，或焊剂，形成在光阻材料的移除部分上。将光阻材料层222剥离，留下具有20-200μm的高度范围的导电柱224。在另一实施例中，柱形突起堆叠在接触垫132c上。
在图11b中，利用胶印刷，压缩性模制，传递模制，液体密封剂模制，真空层压，旋转涂覆，或其它适当的施加器，将密封剂或模制复合物226沉积在半导体小片138和晶圆120上。密封剂226可为聚合物复合材料，诸如带有填料的环氧树脂，带有填料的环氧丙烯酸酯，或具有合适的填料的聚合物。密封剂226为非导电的，且在环境上保护半导体器件免受外部元件和污染物影响。
在图11c中，研磨机228从半导体小片138的与活性表面142相对的背面229移除密封剂226和粒状材料的一部分。在研磨工艺之后，半导体小片138的背面229与密封剂226的顶表面共面，如图11d所示。随后的装配工艺如图3i-3l所示，获得类似于图4的WLCSP。
图12a-12e显示了形成穿过密封剂的导电柱的又一工艺。作为图3d的进一步改进，引线框插入器230安装在半导体小片138上，并与半导体晶圆120上的垫132c连接，如图12a-12b所示。引线框插入器230包括从板233延伸至接触垫132c的垂直的部分或本体232。在图12c中，利用胶印刷，压缩模制，传递模制，液体密封剂模制，真空层压，旋转涂覆，或其它适当的施加器，将密封剂或模制复合物234沉积在引线框插入器230下方和半导体小片138和晶圆120上。密封剂234可为聚合物复合材料，诸如带有填料的环氧树脂，带有填料的环氧丙烯酸酯，或具有合适的填料的聚合物。密封剂234为非导电的，并在环境上保护半导体器件免受外部元件和污染物影响。在图12d中，研磨机236从半导体小片138的与活性表面142相对的背面238移除板233和密封剂234和粒状材料的一部分。在研磨工艺之后，半导体小片138的背面238与密封剂234的顶表面共面，如图12e所示。在研磨工艺之后，剩余的本体232构成密封剂234内的导电柱。随后的装配工艺如图3i-3l所示，获得类似于图4的WLCSP。
尽管已经详细图示了本发明的一个或更多实施例，但是本领域技术人员应当理解，在不脱离如所附权利要求所阐述的本发明的范围的情况下，可作出变型和改进。

Claims (25)

1. 一种制造半导体器件的方法，包括：
提供具有多个第一半导体小片的半导体晶圆，所述第一半导体小片均具有活性表面；
将第二半导体小片安装到所述第一半导体小片上，所述第一半导体小片的所述活性表面定向成朝向所述第二半导体小片的活性表面；
将密封剂沉积在所述第一半导体小片和所述第二半导体小片上；
移除所述第二半导体小片的与所述活性表面相对的背面的一部分；
绕所述第二半导体小片形成导电柱；
在所述第二半导体小片的所述背面、密封剂和导电柱上形成互连结构，所述互连结构与所述导电柱电连接；
移除所述第一半导体小片的与所述活性表面相对的背面的一部分；和
将所述半导体晶圆分割为单独的半导体器件。
2. 根据权利要求1所述的方法，其特征在于，所述方法进一步包括将离散的半导体构件安装到所述第一半导体小片上。
3. 根据权利要求1所述的方法，其特征在于，所述方法进一步包括形成穿过所述第一半导体小片的导电通道。
4. 根据权利要求1所述的方法，其特征在于，所述方法进一步包括在所述第一半导体小片的所述背面上形成热沉。
5. 根据权利要求1所述的方法，其特征在于，所述方法进一步包括在所述第一半导体小片的所述背面上形成屏蔽层。
6. 根据权利要求1所述的方法，其特征在于，所述方法进一步包括在所述第一半导体小片上安装并列的半导体小片。
7. 一种制造半导体器件的方法，包括：
提供具有多个第一半导体小片的半导体晶圆，所述第一半导体小片均具有活性表面；
将第二半导体小片安装到所述第一半导体小片上，所述第一半导体小片的所述活性表面定向成朝向所述第二半导体小片的活性表面；
绕所述第二半导体小片形成垂直的互连结构；
在所述第一半导体小片和所述第二半导体小片上沉积密封剂；
移除所述第二半导体小片的与所述活性表面相对的背面的一部分；
在所述第二半导体小片的所述背面、密封剂和垂直的互连结构上形成积层互连结构，所述积层互连结构与所述垂直的互连结构电连接；
移除所述第一半导体小片的与所述活性表面相对的背面的一部分；和
将所述半导体晶圆分割为单独的半导体器件。
8. 根据权利要求7所述的方法，其特征在于，所述方法进一步包括将离散的半导体构件安装到所述第一半导体小片上。
9. 根据权利要求7所述的方法，其特征在于，所述方法进一步包括形成穿过所述第一半导体小片的导电通道。
10. 根据权利要求7所述的方法，其特征在于，所述方法进一步包括在所述第一半导体小片的所述背面上形成热沉。
11. 根据权利要求7所述的方法，其特征在于，所述方法进一步包括在所述第一半导体小片的所述背面上形成屏蔽层。
12. 根据权利要求7所述的方法，其特征在于，所述垂直的互连结构包括导电柱，堆叠突起，杆和柱，或突起和柱。
13. 根据权利要求7所述的方法，其特征在于，形成所述垂直的互连结构包括：
在沉积所述密封剂之前，将引线框插入器安装在所述第一半导体小片和所述第二半导体小片上，所述引线框插入器包括板和从所述板延伸到所述第一半导体小片的本体；
绕所述引线框插入器的所述本体在所述第一半导体小片和所述第二半导体小片上沉积所述密封剂；和
移除所述板，留下所述密封剂内的所述本体作为绕所述第二半导体小片的导电柱。
14. 一种制造半导体器件的方法，包括：
提供具有活性表面的第一半导体小片；
将第二半导体小片安装到所述第一半导体小片上，所述第一半导体小片的所述活性表面定向成朝向所述第二半导体小片的活性表面；
绕所述第二半导体小片形成垂直的互连结构；
在所述第一和第二半导体小片上沉积密封剂；
移除所述第二半导体小片的与所述活性表面相对的背面的一部分；
在所述第二半导体小片的所述背面、密封剂和垂直的互连结构上形成积层互连结构，所述积层互连结构与所述垂直的互连结构电连接；和
移除所述第一半导体小片的与所述活性表面相对的背面的一部分。
15. 根据权利要求14所述的方法，其特征在于，所述方法进一步包括将离散的半导体构件安装到所述第一半导体小片上。
16. 根据权利要求14所述的方法，其特征在于，所述方法进一步包括形成穿过所述第一半导体小片的导电通道。
17. 根据权利要求14所述的方法，其特征在于，所述方法进一步包括在所述第一半导体小片的所述背面上形成热沉。
18. 根据权利要求14所述的方法，其特征在于，所述方法进一步包括在所述第一半导体小片的所述背面上形成屏蔽层。
19. 根据权利要求14所述的方法，其特征在于，所述垂直的互连结构包括导电柱，堆叠突起，杆和柱，或突起和柱。
20. 根据权利要求14所述的方法，其特征在于，形成所述垂直的互连结构包括：
在沉积所述密封剂之前，将引线框插入器安装在所述第一半导体小片和所述第二半导体小片上，所述引线框插入器包括板和从所述板延伸至所述第一半导体小片的本体；
在所述第一半导体小片和所述第二半导体小片上沉积所述密封剂；和
移除所述板，留下所述密封剂内的本体作为绕所述第二半导体小片的导电柱。
21. 一种半导体器件，包括：
具有活性表面的第一半导体小片；
安装在所述第一半导体小片上的第二半导体小片，所述第一半导体小片的所述活性表面定向成朝向所述第二半导体小片的活性表面；
绕所述第二半导体小片形成的垂直的互连结构；
沉积在所述第一半导体小片和所述第二半导体小片上的密封剂；和
形成在所述第二半导体小片的背面、密封剂和垂直的互连结构上的积层互连结构，所述积层互连结构与所述垂直的互连结构电连接。
22. 根据权利要求21所述的半导体器件，其特征在于，所述第一半导体小片和第二半导体小片的所述背面的一部分被移除。
23. 根据权利要求21所述的半导体器件，其特征在于，所述半导体器件进一步包括形成在所述第一半导体小片的所述背面上的热沉。
24. 根据权利要求21所述的半导体器件，其特征在于，所述半导体器件进一步包括形成在所述第一半导体小片的所述背面上的屏蔽层。
25. 根据权利要求21所述的半导体器件，其特征在于，所述垂直的互连结构包括导电柱，堆叠突起，杆和柱，或突起和柱。
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