CN105023916A - 晶片封装体及其制造方法 - Google Patents

晶片封装体及其制造方法 Download PDF

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Publication number
CN105023916A
CN105023916A CN201510193296.8A CN201510193296A CN105023916A CN 105023916 A CN105023916 A CN 105023916A CN 201510193296 A CN201510193296 A CN 201510193296A CN 105023916 A CN105023916 A CN 105023916A
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China
Prior art keywords
wafer
conductive pad
semiconductor wafer
semiconductor
connecting portion
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CN201510193296.8A
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English (en)
Inventor
刘建宏
温英男
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XinTec Inc
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XinTec Inc
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Publication of CN105023916A publication Critical patent/CN105023916A/zh
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Abstract

本发明提供一种晶片封装体及其制造方法，该晶片封装体包含半导体晶片、第一晶片、第一连接部、模塑层、重布局金属层以及封装层。半导体晶片具有至少一第一导电垫以及至少一第二导电垫设置于半导体晶片的上表面。第一晶片配置于上表面上，第一晶片具有至少第一晶片导电垫。第一连接部直接电性连接第一晶片导电垫与第一导电垫。模塑层覆盖上表面、第一晶片以及第一连接部，模塑层具有开口暴露出该第二导电垫。重布局金属层设置于开口内与第二导电垫电性连接，且重布局金属层延伸至模塑层上。封装层覆盖重布局金属层以及模塑层。本发明不仅于同一封装体内整合多个晶片，还可简化重布局金属层的图案布局。

Description

晶片封装体及其制造方法
技术领域
本发明关于一种封装体及其制造方法，且特别是有关于一种晶片封装体及其制造方法。
背景技术
晶片封装体已广泛运用于日常生活所需的各种电子产品中，特别是在计算机、手机、数字相机等。在上述诸多电子产品要求多功能、高效能，同时外型尚须轻薄短小的消费需求下，晶片封装体的积集度亦必须对应地提升。据此，具有多个晶片堆叠结构的晶片封装体成为晶片封装体工业相当热门的研发方向之一。
所谓具有多个晶片堆叠结构的晶片封装体，是指具有两个以上可执行相同或不同功能的单一晶片经堆叠方式而整合在单一晶片封装体中。如此两个以上执行相同或不同功能的单一晶片堆叠结构不仅可达成在电路密度的提高，尚有于单一晶片封装体内实行不同功能性(例如存储器、逻辑运算、特定应用集成电路)的多功能性，因此单一晶片封装体便可具有更高的效能，同时可用来执行多功能的整合应用。据此，具有多晶片堆叠结构的晶片封装体已被发展出以符合需求。
然而，多晶片堆叠结构的晶片封装体在结构设计上具有更高的复杂性，且对应上开多晶片堆叠结构的晶片封装体，在制造过程中所涉及制程的要求提高，导致成本增加，尚具有良率降低的风险。据此，一种更可靠、更适于量产的晶片封装体及其制造方法，是当今晶片封装工艺重要的研发方向之一。
发明内容
本发明提供一种晶片封装体及其制造方法，晶片封装体整合两个以上晶片的堆叠，使单一晶片封装体具有多功能、高效能的特性，而晶片之间先完成单一晶片封装体内部的电性连接，最后再由重布局金属层作为两片晶片堆叠结构的整体对外的电性连接。如此一来不仅于同一封装体内整合两个晶片以达到同一封装体具有多功能高效能的效果，同时亦可简化重布局金属层的图案布局，即重布局金属层不需同时直接电性连接半导体晶片以及第一晶片。据此，简化的重布局金属层的图案布局便可具有更大的设计弹性，还能有效降低生产成本。
本发明提出一种晶片封装体，包含半导体晶片、第一晶片、第一连接部、模塑层、重布局金属层以及封装层。半导体晶片具有至少一第一导电垫以及至少一第二导电垫设置于半导体晶片的上表面。第一晶片配置于上表面上，第一晶片具有至少第一晶片导电垫。第一连接部直接电性连接第一晶片导电垫与第一导电垫。模塑层覆盖上表面、第一晶片以及第一连接部，模塑层具有开口暴露出该第二导电垫。重布局金属层设置于开口内与第二导电垫电性连接，且重布局金属层延伸至模塑层上。封装层覆盖重布局金属层以及模塑层。
在本发明的一些实施方式中，上述晶片封装体进一步包含保护玻璃以及阻挡坝体。保护玻璃配置于半导体晶片与第一晶片之间。阻挡坝体具有高度夹设于保护玻璃以及半导体晶片之间。
在本发明的另一些实施方式中，上述晶片封装体进一步包含第二晶片以及第二连接部。第二晶片夹设于半导体晶片以及第一晶片之间，第二晶片具有至少一第二晶片导电垫。第二连接部电性连接第二晶片导电垫与第一导电垫。
在本发明的一些实施方式中，上述第二晶片的面积大于第一晶片的面积。
在本发明的另一些实施方式中，上述第二晶片是集成无源元件(IPD)、射频电路元件、模拟元件、数字元件、混合信号元件或微机电系统(MEMS)的开关或振荡器。
在本发明的另一些实施方式中，上述第二连接部与第一连接部分别连接不同第一导电垫。
在本发明的又一些实施方式中，上述晶片封装体进一步包含第二晶片以及第二连接部。第二晶片配置于上表面上与第一晶片相邻，第二晶片具有至少一第二晶片导电垫。第二连接部电性连接第二晶片导电垫与第一导电垫。
在本发明的又一些实施方式中，上述第二晶片是集成无源元件、射频电路元件、模拟元件、数字元件、混合信号元件或微机电系统的开关或振荡器。
在本发明的又一些实施方式中，上述第二连接部与第一连接部分别连接不同第一导电垫。
在本发明的一些实施方式中，上述晶片封装体进一步包含焊球设置于封装层上，封装层具有开口暴露出部分重布局金属层，焊球通过封装层的开口与重布局金属层电性连接。
在本发明的一些实施方式中，上述第一晶片是集成无源元件晶片、射频电路元件晶片、模拟元件晶片、数字元件晶片、混合信号元件或基于微机电系统的开关或振荡器晶片。
在本发明的一些实施方式中，上述半导体晶片的面积大于第一晶片的面积。
在本发明的一些实施方式中，上述晶片封装体进一步包含粘着层夹设于半导体晶片的上表面与第一晶片之间。
在本发明的一些实施方式中，上述粘着层包含银胶。
本发明另提出一种晶片封装体的制造方法，包含：提供半导体晶圆，该半导体晶圆具有多个半导体晶片相邻排列，半导体晶片具有至少一第一导电垫以及至少一第二导电垫设置于半导体晶片的上表面；形成多个第一晶片分别对应半导体晶片，第一晶片配置于上表面上，各第一晶片具有至少一第一晶片导电垫；形成多个第一连接部分别电性连接各第一晶片导电垫与各第一导电垫；形成模塑层覆盖上表面、第一晶片以及第一连接部，模塑层具有开口暴露出第二导电垫；形成重布局金属层于开口内与第二导电垫电性连接，且重布局金属层延伸至模塑层上；以及形成封装层覆盖重布局金属层以及模塑层。
在本发明的一些实施方式中，在形成第一晶片分别对应半导体晶片的步骤之前，进一步包含：形成多个支撑件分别对应各半导体晶片且配置于各半导体晶片上方；以及形成多个保护玻璃分别对应各支撑件上。
在本发明的另一些实施方式中，在形成第一晶片分别对应半导体晶片的步骤之后，进一步包含：形成多个第二晶片分别对应半导体晶片，第二晶片夹设于半导体晶片以及第一晶片之间，第二晶片具有至少一导电垫；以及形成多个第二连接部分别电性连接各第二晶片的导电垫与各第一导电垫。
在本发明的另一些实施方式中，上述第一晶片的面积大于第二晶片的面积。
在本发明的另一些实施方式中，上述第二晶片是集成无源元件、射频电路元件、模拟元件、数字元件、混合信号元件或微机电系统的开关或振荡器。
在本发明的另一些实施方式中，上述第二连接部与第一连接部分别连接不同第一导电垫。
在本发明的又一些实施方式中，在形成第一晶片分别对应半导体晶片的步骤之后，进一步包含：形成多个第二晶片分别对应半导体晶片，第二晶片配置于上表面上与第一晶片相邻，第二晶片具有至少一导电垫；以及形成多个第二连接部电性连接第二晶片的导电垫与第一导电垫。
在本发明的又一些实施方式中，上述第二晶片是集成无源元件、射频电路元件、模拟元件、数字元件、混合信号元件或微机电系统的开关或振荡器。
在本发明的又一些实施方式中，上述第二连接部与第一连接部分别连接不同第一导电垫。
在本发明的一些实施方式中，进一步包含形成焊球设置于封装层上，封装层具有开口暴露出部分重布局金属层，焊球通过封装层的开口与重布局金属层电性连接。
在本发明的一些实施方式中，上述第一晶片是集成无源元件、射频电路元件、模拟元件、数字元件、混合信号元件或基于微机电系统的开关或振荡器。
在本发明的一些实施方式中，上述半导体晶片的面积大于第一晶片的面积。
在本发明的一些实施方式中，进一步包含形成粘着层夹设于半导体晶片的上表面与第一晶片之间。
在本发明的一些实施方式中，上述粘着层包含银胶。
本发明的还提出一种晶片封装体，包含半导体晶片、第一晶片、第一连接部、模塑层、重布局金属层以及封装层。半导体晶片具有至少一第一导电垫以及至少一第二导电垫设置于半导体晶片的上表面。第一晶片配置于上表面上，第一晶片具有至少第一晶片导电垫。第一连接部直接电性连接第一晶片导电垫与第一导电垫。模塑层覆盖上表面、第一晶片以及第一连接部，模塑层具有开口暴露出该第二导电垫。重布局层设置于开口内与第二导电垫电性连接，且重布局层延伸至模塑层上。封装层覆盖重布局层以及模塑层。
在本发明的一些实施方式中，上述晶片封装体进一步包含保护层以及间隔体。保护层配置于半导体晶片与第一晶片之间。间隔体具有高度夹设于保护层以及半导体晶片之间。
在本发明的一些实施方式中，该保护层是指一保护玻璃，且该间隔体是指一阻挡坝体。
在本发明的一些实施方式中，该重布局层是指一重布局金属层。
附图说明
本发明的上述和其他态样、特征及其他优点参照说明书内容并配合附加图式得到更清楚的了解，其中：
图1是根据本发明一实施方式晶片封装体的局部剖面示意图。
图2是根据本发明另一实施方式晶片封装体的局部剖面示意图。
图3是根据本发明又一实施方式晶片封装体的局部剖面示意图。
图4是根据本发明一实施方式晶片封装体在制作过程中的俯视示意图。
图5～7是根据本发明一实施方式晶片封装体在制作过程中不同步骤的局部剖面示意图。
图8～10是根据本发明另一实施方式晶片封装体在制作过程中的局部剖面示意图。
图11～13是根据本发明又一实施方式晶片封装体在制作过程中的局部剖面示意图。
附图中符号的简单说明如下：
10：半导体晶圆               160：封装层
100：晶片封装体              162：开口
110：半导体晶片              170：保护玻璃
111：上表面                  180：阻挡坝体
112：第一导电垫              190：第二晶片
114：第二导电垫              192：第二晶片导电垫
120：第一晶片                200：晶片封装体
122：第一晶片导电垫           210：焊球
130：第一连接部              230：第二连接部
132：焊球部                  232：焊球部
134：焊线部                  234：焊线部
136：焊球部                  236：焊球部
140：模塑层                  300：晶片封装体
142：开口                    SL：切割道
150：重布局金属层            H：高度。
具体实施方式
为了使本揭示内容的叙述更加详尽与完备，下文针对了本发明的实施态样与具体实施例提出了说明性的描述，但这并非实施或运用本发明具体实施例的唯一形式。以下所揭露的各实施例，在有益的情形下可相互组合或取代，也可在一实施例中附加其他的实施例，而无须进一步的记载或说明。在以下描述中，将详细叙述许多特定细节以使读者能够充分理解以下的实施例。然而，可在无此等特定细节的情况下实践本发明的实施例。
图1是根据本发明一实施方式晶片封装体100的局部剖面示意图。请参照图1，晶片封装体100包含半导体晶片110、第一晶片120、第一连接部130、模塑层140、重布局层150以及封装层160。在本发明部分实施例中，该重布局层可以为一重布局金属层。半导体晶片110具有至少一第一导电垫112以及至少一第二导电垫114设置于半导体晶片110的上表面111。半导体晶片110例如可以是在硅(silicon)、锗(germanium)或其它III-V族元素半导体晶圆基材上，以晶圆级制程工艺所制作的半导体晶片110。半导体晶片110例如可以具有电子元件(图未绘示)位于半导体晶片110的内部，电子元件与配置于半导体晶片110的上表面111的各第一导电垫112以及各第二导电垫114具有电性连接。电性连接的方式例如可以是通过位于半导体晶片110内部的内连线结构(图未绘示)电性连接于电子元件。因此，第一导电垫112以及第二导电垫114可作为半导体晶片110中电子元件信号控制的输入(input)/输出(output)端。第一导电垫112以及第二导电垫114的材质例如可以是铝(aluminum)、铜(copper)或镍(nickel)或其他合适的导电材料。在本发明中电子元件例如可以是有源元件(active element)或无源元件(passive elements)、数字电路或模拟电路等集成电路的电子元件(electronic components)、微机电系统(Micro Electro MechanicalSystems,MEMS)、微流体系统(micro fluidic systems)、或利用热、光线及压力等物理量变化来测量的物理感测器(physical sensor)、射频元件(RFcircuits)、加速计(accelerators)、陀螺仪(gyroscopes)、微制动器(micro actuators)、表面声波元件、压力感测器(pressure sensors)，但不以此为限。
继续参照图1，第一晶片120配置于上表面111上，第一晶片120具有至少一第一晶片导电垫122。第一晶片120与前述半导体晶片110相似的是：第一晶片120亦具有电子元件(图未绘示)位于第一晶片120的内部，电子元件与配置于第一晶片120上表面111的第一晶片导电垫122具有电性连接。而电性连接的方式亦可以是通过位于第一晶片120内部的内连线结构(图未绘示)电性连接于电子元件。因此，第一晶片导电垫122即可作为第一晶片120中电子元件信号控制的输入/输出端。第一晶片导电垫122的材质例如可以是铝(aluminum)、铜(copper)或镍(nickel)或其他合适的导电材料。第一晶片120与前述半导体晶片110不同的地方在于：第一晶片120可以是尺寸较小的晶粒尺寸(die size)的各类元件晶片。在本发明的一些实施方式中，半导体晶片110的面积大于第一晶片120的面积。明确言之，如图1所示的半导体晶片110与第一晶片120的晶片堆叠结构，是半导体晶片110于其晶圆级尺寸封装制作过程中，将尺寸较小的第一晶片120堆叠于尺寸较大的半导体晶片110上方，再完成彼此之间的电性连接，使单一封装体中具有两个以上的晶片。如此整合两个以上的晶片(半导体晶片110与第一晶片120)的单一封装体，便可具有多功能、高效能的特性。据此，第一晶片120可视实际需求，选择不同功能的元件晶片与半导体晶片110做适当的组合搭配。在本发明的一些实施方式中，第一晶片120是集成无源元件(IPD)晶片、射频电路元件晶片、模拟元件晶片、数字元件晶片、混合信号元件晶片或基于微机电系统(MEMS)的开关或振荡器晶片。
继续参照图1，第一连接部130直接电性连接第一晶片导电垫122与第一导电垫112。承前所述，将第一晶片120堆叠于半导体晶片110上方后，第一晶片120与半导体晶片110两者之间的电性连接路径直接通过第一连接部130完成。换言之，第一连接部130的两端分别连接于第一晶片120的第一晶片导电垫122、以及半导体晶片110的第一导电垫112。如图1所示，第一连接部130例如可以是由焊球部132、136以及焊线部134所组成，其中焊球部132焊接于第一晶片120的第一晶片导电垫122上，焊球部136焊接于半导体晶片110的第一导电垫112，而焊线部134连接焊球部132、136。据此，即使得第一晶片120与半导体晶片110两者之间具有直接的电性连接。然而本发明的第一连接部130并不以此为限，第一连接部130亦可以是两端分别与第一晶片导电垫122、第一导电垫112直接接触的金属夹(metal clip)、导电带(conductive ribbon)、或是任何可以形成第一晶片导电垫122与第一导电垫112之间直接电性连接的样态。继续参照图1，模塑层140覆盖上表面111、第一晶片120以及第一连接部130，模塑层140具有开口142暴露出第二导电垫114。如图1所示，前述半导体晶片110、第一晶片120以及第一连接部130以模塑层140封装为一体。模塑层140例如可以是以模塑制程(molding process)将模塑材料覆盖上表面111、第一晶片120以及第一连接部130来形成。模塑材料可以是环氧树脂模塑化合物(epoxy molding compound，EMC)或是其他适合应用于模塑制程的模塑材料。
继续参照图1，重布局金属层150设置于开口142内与第二导电垫114电性连接，且重布局金属层150延伸至模塑层140上。重布局金属层150可作为独立的信号线路，控制半导体晶片110中第二导电垫114的信号输入或输出。重布局金属层150所使用的材料可以是铝、铜或其它合适的导电材料。重布局金属层150制作的方式可以是先以溅镀(sputtering)或蒸镀(evaporation)制程先沉积填满模塑层140的开口142并覆盖模塑层140以形成导电薄膜，再将导电薄膜以微影蚀刻的方式，形成具有预定重布局线路图案的重布局金属层150。如图1所示，封装层160覆盖重布局金属层150以及模塑层140。封装层160可将重布局金属层150包覆起来，以隔绝水气或其他污染物不致直接接触重布局金属层150，防止重布局金属层150因腐蚀而断线。封装层160所使用的材料可以是绿漆(solder mask)或其它合适的封装材料，顺应地沿着重布局金属层150以及模塑层140以涂布方式形成。在本发明的一些实施方式中，晶片封装体100进一步包含焊球210设置于封装层160上，如图1所示，封装层160具有开口162暴露出部分重布局金属层150，焊球210通过封装层160的开口162与重布局金属层150电性连接。焊球210的材料例如可以是锡或其他适合于焊接的金属或合金。焊球210作为晶片封装体100外接于印刷电路板(printedcircuit board,PCB)或其他中介片(interposer)的连接桥梁，据此由印刷电路板或其他中介片的输入/输出的电流信号即可通过焊球210、重布局金属层150以及半导体晶片110的第二导电垫114，对电子元件进行信号输入/输出控制。
如图1所示，在本发明的一些实施方式中，晶片封装体100进一步包含保护层170以及间隔体180。在本发明部分实施例，该保护层170可为一保护玻璃，且该间隔体180可为阻挡坝体。保护玻璃170配置于半导体晶片110以及第一晶片120之间。
阻挡坝体180具有高度H夹设于保护玻璃170以及半导体晶片110之间。换言之，阻挡坝体180圈绕出空腔在半导体晶片110的上表面111上方，此空腔用来搭配不同需求配置入例如微镜头模组或其他需要独立空间等元件模组，再由保护玻璃170盖住，而第一晶片120则配置于保护玻璃170上方。据此在本发明的一些实施方式中，晶片封装体100在整合半导体晶片110与第一晶片120以实现多功能晶片封装体的前提之下，还能组合例如微镜头模组或其他需要独立空间等元件模组以实现更多功能、还具有弹性的组合应用。
图2是根据本发明另一实施方式晶片封装体200的局部剖面示意图。请参照图2，晶片封装体200包含半导体晶片110、第一晶片120、第一连接部130、模塑层140、重布局金属层150以及封装层160。而上述各元件的材料以及连接关系与前述实施方式的晶片封装体100相似，在此即不重复赘述。晶片封装体200与前述实施方式的晶片封装体100不同之处在于，晶片封装体200进一步包含第二晶片190以及第二连接部230，其中第二晶片190夹设于半导体晶片110以及第一晶片120之间，第二晶片190具有至少一第二晶片导电垫192，以及第二连接部230电性连接第二晶片导电垫192与第一导电垫112。第二晶片190与前述半导体晶片110相似的是：第二晶片190亦具有电子元件(图未绘示)位于第二晶片190的内部，电子元件与配置于第二晶片190上表面的第二晶片导电垫192具有电性连接。而电性连接的方式亦可以是通过位于第二晶片190内部的内连线结构(图未绘示)电性连接于电子元件。因此，第二晶片导电垫192即可作为第二晶片190中电子元件信号控制的输入/输出端。第二晶片导电垫192的材质例如可以是铝、铜或镍或其他合适的导电材料。第二晶片190与前述半导体晶片110不同的地方在于：第二晶片190可以是尺寸较小的晶粒尺寸(die size)的各类元件晶片，至于第二晶片190与第一晶片120两者之间的尺寸大小关系可视实际需求作不同的搭配选用。如图2所示，在本发明的一些实施方式中，第二晶片190的面积大于第一晶片120的面积。明确言之，如图2所示的半导体晶片110、第一晶片120以及第二晶片190的晶片堆叠结构，是半导体晶片110于其晶圆级尺寸封装制作过程中，将尺寸较小的第二晶片190以及第一晶片120依序堆叠于尺寸较大的半导体晶片110上方，再完成彼此之间的电性连接，使单一晶片封装体中具有三个晶片，如此便整合三个的晶片(半导体晶片110、第一晶片120以及第二晶片190)的单一封装体，还可具有多功能、高效能的特性。此外，第二晶片190亦可视实际需求，选择不同功能的元件晶片与半导体晶片110以及第一晶片120做适当的组合搭配。在本发明的一些实施方式中，第二晶片190是集成无源元件(IPD)晶片、射频电路元件晶片、模拟元件晶片、数字元件晶片、混合信号元件晶片或基于微机电系统(MEMS)的开关或振荡器晶片。至于整合半导体晶片110、第一晶片120以及第二晶片190的电性连接亦可视实际需要作串联或并联等不同的电性连接方式，在本发明的一些实施方式中，第二连接部230与第一连接部130分别连接不同的第一导电垫112。如图2所示，第二连接部230例如可以是由焊球部232、236以及焊线部234所组成，其中焊球部232焊接于第二晶片190的第二晶片导电垫192上，焊球部236焊接于半导体晶片110的第一导电垫112，而焊线部234连接焊球部232、236。据此，即使得第二晶片190与半导体晶片110两者之间具有直接的电性连接。然而本发明的第二连接部230并不以此为限，第二连接部230亦可以是两端分别与第二晶片导电垫192、第一导电垫112直接接触的金属夹(metal clip)、导电带(conductive ribbon)、或是任何可以形成第二晶片导电垫192与第一导电垫112之间直接电性连接的样态。
图3是根据本发明又一实施方式晶片封装体300的局部剖面示意图。请参照图3，晶片封装体300包含半导体晶片110、第一晶片120、第一连接部130、模塑层140、重布局金属层150以及封装层160。而上述各元件的材料以及连接关系与前述实施方式的晶片封装体100相似，在此即不重复赘述。晶片封装体300与前述实施方式的晶片封装体100不同之处在于，晶片封装体300进一步包含第二晶片190以及第二连接部230，其中第二晶片190配置于上表面111上与第一晶片120相邻，第二晶片190具有至少一第二晶片导电垫192。第二连接部230电性连接第二晶片导电垫192与第一导电垫112。第二晶片190亦具有电子元件(图未绘示)位于第二晶片190的内部，电子元件与配置于第二晶片190上表面的第二晶片导电垫192具有电性连接。而电性连接的方式亦可以是通过位于第二晶片190内部的内连线结构(图未绘示)电性连接于电子元件。因此，第二晶片导电垫192即可作为第二晶片190中电子元件信号控制的输入/输出端。第二晶片导电垫192的材质例如可以是铝、铜或镍或其他合适的导电材料。第二晶片190与前述半导体晶片110不同的地方在于：第二晶片190可以是尺寸较小的晶粒尺寸(die size)的各类元件晶片，至于第二晶片190与第一晶片120两者之间的尺寸大小关可视实际需求作不同的搭配选用。明确言之，如图3所示的半导体晶片110、第一晶片120以及第二晶片190的晶片堆叠结构，是半导体晶片110于其晶圆级尺寸封装制作过程中，将尺寸较小的第二晶片190以及第一晶片120分别堆叠于尺寸较大的半导体晶片110上方，再完成彼此之间的电性连接，使单一晶片封装体中具有三个晶片，如此便整合三个的晶片(半导体晶片110、第一晶片120以及第二晶片190)的单一封装体，还可具有多功能、高效能的特性。此外，第二晶片190亦可视实际需求，选择不同功能的元件晶片与半导体晶片110以及第一晶片120做适当的组合搭配。在本发明的一些实施方式中，第二晶片190是集成无源元件(IPD)晶片、射频电路元件晶片、模拟元件晶片、数字元件晶片、混合信号元件晶片或基于微机电系统(MEMS)的开关或振荡器晶片。
综言之，请参照图1至图3，在本发明各实施方式中至少具有两片晶片，即半导体晶片110以及第一晶片120，堆叠而成一个晶片封装体。在此晶片封装体中，两片晶片之间先由第一连接部130作为封装体内部的电性连接，最后再由重布局金属层150作为两片晶片堆叠结构的整体对外的电性连接。如此一来不仅于同一封装体内整合两个晶片以达到同一封装体具有多功能高效能的效果，同时亦可简化重布局金属层150的图案布局，即重布局金属层150不需同时直接电性连接半导体晶片110以及第一晶片120，而仅需设计为直接电性连接半导体晶片110即可。至于第一晶片120的信号输入输出，则以内部第一连接部130搭配半导体晶片110作为控制。据此，简化的重布局金属层150的图案布局便可具有更大的设计弹性，例如在预定的面积上设计较大的线宽，以减少制作过程中可能产生的断线风险。至于本发明的晶片封装体的制造方法，将于以下段落中详述。
图4是根据本发明一实施方式晶片封装体在制作过程中的俯视示意图。请参照图4，提供半导体晶圆10具有多个半导体晶片110相邻排列，各半导体晶片110具有至少一第一导电垫112以及至少一第二导电垫114设置于半导体晶片110的上表面111。接着，形成多个第一晶片120分别对应各半导体晶片110，各第一晶片120配置于上表面111上，各第一晶片120具有至少一第一晶片导电垫122。如图4所示，半导体晶圆10具有多个半导体晶片110，各半导体晶片110以预定后续分割各半导体晶片110的切割道SL为边界相邻排列。在各半导体晶片110上形成各第一晶片120，即初步完成晶片堆叠的结构。据此可知，半导体晶片110在本发明的晶片封装体的制造方法中是晶圆层级的晶片，即在此阶段各半导体晶片110可视为半导体晶圆10的一部分而尚未分割，因此在分割的前后续各制程步骤均以晶圆级尺寸封装的制程进行。相对地，各第一晶片120则是晶粒层级的晶片，分别对应贴合于半导体晶圆10中各半导体晶片110上。第一晶片120与半导体晶片110的面积大小比例可视需求作适当地调整选择。在本发明的一些实施方式中，半导体晶片110的面积大于第一晶片120的面积。第一晶片120与半导体晶片110之间贴合的方式例如可以是，进一步形成粘着层夹设于半导体晶片110的上表面111以及第一晶片120之间。在本发明的一些实施方式中，粘着层包含银胶。
图5～7是根据本发明一实施方式晶片封装体在制作过程中不同步骤的局部剖面示意图。请先参照图5搭配图4，在本发明的一些实施方式中，在形成各第一晶片120分别对应各半导体晶片110的步骤之前，进一步包含形成多个阻挡坝体180分别对应各半导体晶片110且配置于各半导体晶片110上方。接着，形成多个保护玻璃170分别对应各阻挡坝体180上。如图5所示，在本发明的一些实施方式中进一步包含形成保护玻璃170以及阻挡坝体180。阻挡坝体180圈绕出空腔在半导体晶片110的上表面111上方，此空腔用来搭配不同需求配置入例如微镜头模组或其他需要独立空间等元件模组，再由保护玻璃170盖住，而第一晶片120则配置于保护玻璃170上方。据此晶片封装体100在整合半导体晶片110与第一晶片120以实现多功能晶片封装体的前提之下，还能组合例如微镜头模组或其他需要独立空间等元件模组以实现更多功能、还具有弹性的组合应用。如图5所示，形成多个第一连接部130分别电性连接各第一晶片导电垫122与各第一导电垫112。第一连接部130例如可以是由焊球部132、136以及焊线部134所组成，其中焊球部132焊接于第一晶片120的第一晶片导电垫122上，焊球部136焊接于半导体晶片110的第一导电垫112，而焊线部134连接焊球部132、136。据此，即使得第一晶片120与半导体晶片110两者之间具有直接的电性连接。然而第一连接部130亦可以是两端分别与第一晶片导电垫122、第一导电垫112直接接触的金属夹(metal clip)、导电带(conductive ribbon)、或是任何可以形成第一晶片导电垫122与第一导电垫112之间直接电性连接的样态。
请参照图6以及图7，在形成多个第一连接部130分别电性连接各第一晶片导电垫122与各第一导电垫112的步骤之后，接着形成模塑层140覆盖上表面111、第一晶片120以及第一连接部130。如图6所示，模塑层140将半导体晶片110、第一晶片120以及第一连接部130封装为一体。模塑层140例如可以是以模塑制程将模塑材料覆盖上表面111、第一晶片120以及第一连接部130形成。模塑材料可以是环氧树脂模塑化合物(epoxy molding compound，EMC)或是其他适合应用于模塑制程的模塑材料。接着如图7所示，以微影蚀刻制程使模塑层140具有开口142暴露出第二导电垫114。接着，形成重布局金属层150于开口142内与第二导电垫114电性连接，且重布局金属层150延伸至模塑层140上。最后，再参照图1所示，形成封装层160覆盖重布局金属层150以及模塑层140，即形成如图1所示的晶片封装体100。
另外，图8～10是根据本发明另一实施方式晶片封装体(参见图2)在制作过程中的局部剖面示意图，图11～13是根据本发明又一实施方式晶片封装体(参见图3)在制作过程中的局部剖面示意图，上述制作过程与图5～7所示的制作过程相似，在此即不重复赘述。
最后要强调的是，本发明所提供的晶片封装体整合两个以上晶片的堆叠，使单一晶片封装体具有多功能、高效能的特性，而晶片之间先完成单一晶片封装体内部的电性连接，最后再由重布局金属层作为两片晶片堆叠结构的整体对外的电性连接。如此一来不仅于同一封装体内整合两个晶片以达到同一封装体具有多功能高效能的效果，同时亦可简化重布局金属层的图案布局，即重布局金属层不需同时直接电性连接半导体晶片以及第一晶片。据此，简化的重布局金属层的图案布局便可具有更大的设计弹性，还能有效降低生产成本。
以上所述仅为本发明较佳实施例，然其并非用以限定本发明的范围，任何熟悉本项技术的人员，在不脱离本发明的精神和范围内，可在此基础上做进一步的改进和变化，因此本发明的保护范围当以本申请的权利要求书所界定的范围为准。

Claims (32)

1.一种晶片封装体，其特征在于，包含：
一半导体晶片，具有至少一第一导电垫以及至少一第二导电垫设置于该半导体晶片的一上表面；
一第一晶片，配置于该上表面上，且该第一晶片具有至少一第一晶片导电垫；
一第一连接部，直接电性连接该第一晶片导电垫与该第一导电垫；
一模塑层，覆盖该上表面、该第一晶片以及该第一连接部，该模塑层具有一开口暴露出该第二导电垫；
一重布局金属层，设置于该开口内与该第二导电垫电性连接，且该重布局金属层延伸至该模塑层上；以及
一封装层，覆盖该重布局金属层以及该模塑层。
2.根据权利要求1的晶片封装体，其特征在于，进一步包含：
一保护玻璃，配置于该半导体晶片与该第一晶片之间；以及
一阻挡坝体，具有一高度夹设于该保护玻璃以及该半导体晶片之间。
3.根据权利要求1的晶片封装体，其特征在于，进一步包含：
一第二晶片，夹设于该半导体晶片以及该第一晶片之间，该第二晶片具有至少一第二晶片导电垫；以及
一第二连接部，电性连接该第二晶片导电垫与该第一导电垫。
4.根据权利要求3的晶片封装体，其特征在于，该第二晶片的一面积大于该第一晶片的一面积。
5.根据权利要求3的晶片封装体，其特征在于，该第二晶片是一集成无源元件、一射频电路元件、一模拟元件、一数字元件、一混合信号元件或一微机电系统的开关或振荡器。
6.根据权利要求3的晶片封装体，其特征在于，该第二连接部与该第一连接部分别连接不同的该第一导电垫。
7.根据权利要求1的晶片封装体，其特征在于，进一步包含：
一第二晶片，配置于该上表面上且与该第一晶片相邻，该第二晶片具有至少一第二晶片导电垫；以及
一第二连接部，电性连接该第二晶片导电垫与该第一导电垫。
8.根据权利要求7的晶片封装体，其特征在于，该第二晶片是一集成无源元件、一射频电路元件、一模拟元件、一数字元件、一混合信号元件或一微机电系统的开关或振荡器。
9.根据权利要求7的晶片封装体，其特征在于，该第二连接部与该第一连接部分别连接不同的该第一导电垫。
10.根据权利要求1的晶片封装体，其特征在于，进一步包含一焊球设置于该封装层上，该封装层具有一开口暴露出部分该重布局金属层，该焊球通过该封装层的该开口与该重布局金属层电性连接。
11.根据权利要求1的晶片封装体，其特征在于，该第一晶片是一集成无源元件晶片、一射频电路元件晶片、一模拟元件晶片、一数字元件晶片、一混合信号元件或基于一微机电系统的开关或振荡器晶片。
12.根据权利要求1的晶片封装体，其特征在于，该半导体晶片的一面积大于该第一晶片的一面积。
13.根据权利要求1的晶片封装体，其特征在于，进一步包含一粘着层夹设于该半导体晶片的该上表面与该第一晶片之间。
14.根据权利要求13的晶片封装体，其特征在于，该粘着层包含银胶。
15.一种晶片封装体的制造方法，其特征在于，包含：
提供一半导体晶圆，该半导体晶圆具有多个半导体晶片相邻排列，该半导体晶片具有至少一第一导电垫以及至少一第二导电垫设置于该半导体晶片的一上表面；
形成多个第一晶片分别对应该多个半导体晶片，该多个第一晶片配置于该上表面上，各该第一晶片具有至少一导电垫；
形成多个第一连接部分别电性连接各该第一晶片的该导电垫与各该第一导电垫；
形成一模塑层覆盖该上表面、该第一晶片以及该第一连接部，该模塑层具有一开口暴露出该第二导电垫；
形成一重布局金属层于该开口内与该第二导电垫电性连接，且该重布局金属层延伸至该模塑层上；以及
形成一封装层覆盖该重布局金属层以及该模塑层。
16.根据权利要求15的晶片封装体的制造方法，其特征在于，在形成该多个第一晶片分别对应该多个半导体晶片的步骤之前，进一步包含：
形成多个支撑件分别对应各该半导体晶片且配置于各该半导体晶片上方；以及
形成多个保护玻璃分别对应各该支撑件且配置于各该支撑件上方。
17.根据权利要求15的晶片封装体的制造方法，其特征在于，在形成该多个第一晶片分别对应该多个半导体晶片的步骤之后，进一步包含：
形成多个第二晶片分别对应该多个半导体晶片，该第二晶片夹设于该半导体晶片以及该第一晶片之间，该第二晶片具有至少一导电垫；以及
形成多个第二连接部分别电性连接各该第二晶片的该导电垫与各该第一导电垫。
18.根据权利要求17的晶片封装体的制造方法，其特征在于，该第一晶片的一面积大于该第二晶片的一面积。
19.根据权利要求17的晶片封装体的制造方法，其特征在于，该第二晶片是一集成无源元件、一射频电路元件、一模拟元件、一数字元件、一混合信号元件或一微机电系统的开关或振荡器。
20.根据权利要求17的晶片封装体的制造方法，其特征在于，该第二连接部与该第一连接部分别连接不同的该第一导电垫。
21.根据权利要求15的晶片封装体的制造方法，其特征在于，在形成该多个第一晶片分别对应该多个半导体晶片的步骤之后，进一步包含：
形成多个第二晶片分别对应该多个半导体晶片，该第二晶片配置于该上表面上与该第一晶片相邻，该第二晶片具有至少一导电垫；以及
形成多个第二连接部分别电性连接各该第二晶片的该导电垫与各该第一导电垫。
22.根据权利要求21的晶片封装体的制造方法，其特征在于，该第二晶片是一集成无源元件、一射频电路元件、一模拟元件、一数字元件、一混合信号元件或一微机电系统的开关或振荡器。
23.根据权利要求21的晶片封装体的制造方法，其特征在于，该第二连接部与该第一连接部分别连接不同的该第一导电垫。
24.根据权利要求15的晶片封装体的制造方法，其特征在于，进一步包含形成一焊球设置于该封装层上，该封装层具有一开口暴露出部分该重布局金属层，该焊球通过该封装层的该开口与该重布局金属层电性连接。
25.根据权利要求15的晶片封装体的制造方法，其特征在于，该第一晶片是一集成无源元件、一射频电路元件、一模拟元件、一数字元件、一混合信号元件或基于一微机电系统的开关或振荡器。
26.根据权利要求15的晶片封装体的制造方法，其特征在于，该半导体晶片的一面积大于该第一晶片的一面积。
27.根据权利要求15的晶片封装体的制造方法，其特征在于，进一步包含形成一粘着层夹设于该半导体晶片的该上表面与该第一晶片之间。
28.根据权利要求27的晶片封装体的制造方法，其特征在于，该粘着层包含银胶。
29.一种晶片封装体，其特征在于，包含：
一半导体晶片，具有至少一第一导电垫以及至少一第二导电垫设置于该半导体晶片的一上表面；
一第一晶片，配置于该上表面上，且该第一晶片具有至少一第一晶片导电垫；
一第一连接部，直接电性连接该第一晶片导电垫与该第一导电垫；
一模塑层，覆盖该上表面、该第一晶片以及该第一连接部，该模塑层具有一开口暴露出该第二导电垫；
一重布局层，设置于该开口内与该第二导电垫电性连接，且该重布局层延伸至该模塑层上；以及
一封装层，覆盖该重布局层以及该模塑层。
30.根据权利要求29的晶片封装体，其特征在于，进一步包含：
一保护层，配置于该半导体晶片与该第一晶片之间；以及
一间隔体，具有一高度夹设于该保护层以及该半导体晶片之间。
31.根据权利要求30的晶片封装体，其特征在于，该保护层是指一保护玻璃，且该间隔体是指一阻挡坝体。
32.根据权利要求29的晶片封装体，其特征在于，该重布局层是指一重布局金属层。
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