CN102931102A - 多芯片晶圆级封装的方法 - Google Patents

多芯片晶圆级封装的方法 Download PDF

Info

Publication number
CN102931102A
CN102931102A CN2012100108356A CN201210010835A CN102931102A CN 102931102 A CN102931102 A CN 102931102A CN 2012100108356 A CN2012100108356 A CN 2012100108356A CN 201210010835 A CN201210010835 A CN 201210010835A CN 102931102 A CN102931102 A CN 102931102A
Authority
CN
China
Prior art keywords
semiconductor element
wafer
photosensitive material
material layer
group
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN2012100108356A
Other languages
English (en)
Other versions
CN102931102B (zh
Inventor
董志航
余俊辉
余振华
史达元
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN102931102A publication Critical patent/CN102931102A/zh
Application granted granted Critical
Publication of CN102931102B publication Critical patent/CN102931102B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4871—Bases, plates or heatsinks
    • H01L21/4882—Assembly of heatsink parts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H01L2224/02311—Additive methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02381—Side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/0346—Plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08135—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/08145—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/08146—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bonding area connecting to a via connection in the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73217—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/82009—Pre-treatment of the connector or the bonding area
    • H01L2224/8203—Reshaping, e.g. forming vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06524—Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06548—Conductive via connections through the substrate, container, or encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06568—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices decreasing in size, e.g. pyramidical stack
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06589—Thermal management, e.g. cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本发明公开一种多芯片晶圆级封装的方法，该方法包括：使用多个感光材料层形成重配置晶圆。在感光材料层中嵌入多个半导体芯片和晶圆。而且，在感光材料层中形成多种组件通孔。嵌入感光材料层中的每个半导体芯片均通过由组件通孔形成的连接路径连接至输入/输出焊盘。

Description

多芯片晶圆级封装的方法
技术领域
本发明涉及半导体技术领域，更具体地说，涉及多芯片晶圆级封装的方法。
背景技术
由于多种电子部件(例如，晶体管、二极管、电阻器、电容器等)的集成密度的不断改进，导致半导体工业经历了快速的成长。对于大部分来说，集成密度的该改进来自最小特征尺寸的重复减小，这允许更多部件被集成到给定区域中。随着最近甚至更小的电子器件的要求的增长，需要更小的半导体管芯和半导体管芯的更有创造性的封装技术。
随着半导体技术的发展，基于多芯片晶圆级封装的半导体器件已经出现，作为进一步减小半导体芯片的物理尺寸有效的选择。在基于晶圆级封装的半导体器件中，有源电路(诸如，逻辑电路、存储器、处理器电路等)在不同晶圆上制造，并且每个晶圆管芯都使用拾取与放置技术被堆叠在另一晶圆管芯的顶部上。可以通过采用多芯片半导体器件实现更高密度。而且，多芯片半导体器件可以实现更小的形状系数(form factor)、成本效率、增加的性能和更低的功率消耗。
多芯片半导体器件可以包括：顶部有源电路层、底部有源电路层和多个中间层(inter layer)。在多芯片半导体器件中，两个管芯(die)通过多个微凸块被接合到一起并且通过多个硅通孔相互电连接。微凸块和硅通孔提供在多芯片半导体器件的垂直轴上的电互连。结果，两个半导体管芯之间的信号路径比传统多芯片器件中的更短，传统多芯片器件中，不同管芯使用互连技术(诸如，基于线接合的芯片堆叠封装)被接合到一起。多芯片半导体器件可以包括堆叠在一起的多种半导体管芯。多个半导体管芯在晶圆被切割之前被封装。晶圆级封装技术具有一些优点。在晶圆级封装多个半导体管芯的一个有益特征是多芯片晶圆级封装技术可以降低制造成本。基于晶圆级封装的多芯片半导体器件的另一有益特征在于，通过采用微凸块和硅通孔减少寄生损失。
发明内容
根据本发明，提供一种方法，包括：在晶圆的顶面上附着第一半导体管芯；在所述第一半导体管芯上附着第二半导体管芯；通过将所述第一半导体管芯和所述第二半导体管芯嵌入第一感光材料层，形成重配置晶圆；以及在所述第一感光材料层中形成第一组组件通孔。
优选地，该方法进一步包括：使用粘着层在底层上附着所述晶圆；以及将所述底层与所述晶圆分离。
优选地，该方法进一步包括：使用第一粘着层将所述第二半导体芯片附着至所述第一半导体管芯；使用第二粘着层以背面对正面的方式将所述第一半导体管芯附着至所述晶圆；在所述第一感光材料层的顶部上形成第一重分配层；以及在所述第一重分配层的顶部上形成多个焊球。
优选地，该方法进一步包括：使用多个金属凸块以正面对正面的方式将所述第二半导体管芯附着至所述第一半导体管芯；以及使用多个金属凸块以正面对正面的方式将所述第一半导体管芯附着至所述晶圆。
优选地，该方法进一步包括：在所述第二半导体管芯的一侧和所述第一感光材料层的正面之间形成第一组开口；在所述第一半导体管芯的一侧和所述第一感光材料层的所述正面之间形成第二组开口；以及在所述晶圆的一侧和所述第一感光材料层的所述正面之间形成第三组开口。
优选地，该方法进一步包括：在所述第一组开口中电镀导电材料；在所述第二组开口中电镀导电材料；以及在所述第三组开口中电镀导电材料。
优选地，该方法进一步包括：将所述重配置晶圆切割为多个封装件，其中，每个封装件都包括多个半导体管芯。
根据本发明的另一方面，提供一种方法，包括：在第二晶圆的顶面上附着半导体管芯；通过将所述第二晶圆和所述半导体管芯嵌入到第一感光材料层中，形成第一重配置晶圆；将所述第一重配置晶圆切割为多个多管芯结构；在第一晶圆的顶面上附着所述多个多管芯结构；通过将所述多个多管芯结构嵌入到第二感光材料层中，形成第二重配置晶圆；以及在所述第二感光材料层中形成第一组组件通孔。
优选地，该方法进一步包括：使用第一粘着层在第一底层上附着所述第一晶圆；以及使所述第一底层与所述第一晶圆分离。
优选地，该方法进一步包括：使用第三粘着层将所述半导体管芯附着至所述第二晶圆；使用第四粘着层以背面对正面的方式将所述多个多管芯结构附着至所述第一晶圆；在所述第一感光材料层的顶部上形成第一重分配层；在所述第二感光材料层的顶部上形成第二重分配层；以及在所述第二重分配层的顶部上形成多个焊球。
优选地，该方法进一步包括：使用多个金属凸块以正面对正面的方式将所述半导体管芯附着至所述第二晶圆；使用多个金属凸块以正面对正面的方式将所述多个多管芯结构附着至所述第一晶圆。
优选地，该方法进一步包括：在所述半导体管芯的一侧和所述第一感光材料层的正面之前形成第一组开口；在所述第二晶圆的一侧和所述第一感光材料层的所述正面之间形成第二组开口；在所述第一晶圆的一侧和所述第二感光材料层的正面之间形成第三组开口；以及在所述第二感光材料层的所述正面和所述第一感光材料层的所述正面之间形成第四组开口。
优选地，该方法进一步包括：在所述第一组开口中电镀导电材料；在所述第二组开口中电镀导电材料；在所述第三组开口中电镀导电材料；以及在所述第四组开口中电镀导电材料。
优选地，该方法进一步包括：将所述第二重配置晶圆切割为多个封装件，其中，每个封装件都包括多个半导体管芯。
根据本发明的再一方面，提供一种方法，包括：在晶圆的顶面上附着第一半导体管芯；通过将所述第一半导体管芯嵌入第一感光材料层中，形成第一重配置晶圆；在所述第一感光材料层中形成第一组组件通孔；在所述第一感光材料层上附着第二半导体管芯；在所述第一感光材料层的顶部上形成第二感光材料层，其中，所述第二半导体管芯被嵌入所述第二感光材料层中；以及在所述第二感光材料层中形成第二组组件通孔。
优选地，该方法进一步包括：在第一底层上附着所述晶圆。
优选地，该方法进一步包括：使用第一粘着层将所述第二半导体管芯附着至所述第一半导体管芯；使用第二粘着层以背面对正面的方式将所述第一半导体管芯附着至所述晶圆；在所述第一感光材料层的顶部上形成第一重分配层；在所述第二感光材料层的顶部上形成第二重分配层；以及在所述第二重分配层的顶部上形成多个焊球。
优选地，该方法进一步包括：使用多个金属凸块将所述第二半导体管芯的顶面附着至所述第一重分配层；以及使用多个金属凸块以正面对正面的方式将所述第一半导体管芯附着至所述晶圆。
优选地，该方法进一步包括：使所述第一组组件通孔和所述第二组组件通孔互连。
优选地，该方法进一步包括：通过将所述第一重配置晶圆和所述第二半导体管芯嵌入到所述第二感光材料层中，形成第二重配置晶圆；以及将所述第二重配置晶圆切割为多个封装件，其中，每个封装件都包括多个半导体管芯。
附图说明
为了更完整地理解本发明及其优点，现在结合附图对以下说明作出参考。
图1是根据一实施例的多芯片半导体器件的横截面图；
图2A-图2E是根据一实施例的在制造多芯片半导体器件中的中间阶段的横截面图；
图3A-图3I是根据另一实施例的在制造多芯片半导体器件中的中间阶段的横截面图；以及
图4A-图4H是根据还有的另一实施例的在制造多芯片半导体器件中的中间阶段的横截面图。
除非另外指出，不同附图中的相应数字和符号通常是指相应部件。附图被绘制以清楚地示出多种实施例的相关方面，并且不必须按比例绘制。
具体实施方式
下面，详细讨论本发明各实施例的制造和使用。然而，应该理解，本发明提供了许多可以在各种具体环境中实现的可应用的概念。所讨论的具体实施例仅仅示出了制造和使用本发明的具体方式，而不用于限制本发明的范围。
本披露将关于特定上下文中的实施例(多芯片晶圆级半导体封装)描述。然而，实施例还可以应用至多种半导体器件。
首先参考图1，示出根据一实施例的多芯片半导体器件的横截面图。多芯片半导体器件100包括第一半导体管芯131、第二半导体管芯132和第三半导体管芯133。如图1中所示，第一半导体管芯131、第二半导体管芯132和第三半导体管芯133被堆叠在一起，以形成多芯片半导体器件100。更特别地，第二半导体管芯132的背面使用第一粘着层126附着至第一半导体管芯131的正面。类似地，第三半导体管芯133的背面使用第二粘着层124附着至感光材料层108。
多芯片半导体器件100进一步包括多个焊球110，作为使用多个凸块下金属化(UBM)结构112装配在多芯片半导体器件100的顶部上的输入/输出(I/O)焊盘。为了给出多个实施例发明角度的基本理解，第一半导体管芯131、第二半导体管芯132和第三半导体管芯133不被详细地绘制。然而，应该注意，第一半导体管芯131、第二半导体管芯132和第三半导体管芯133可以包括基本半导体层，诸如，有源电路层、基板层、层间电介质(ILD)层和金属间电介质(IMD)层(未示出)。
根据一实施例，第一半导体管芯131可以包括多个逻辑电路，诸如，中央处理单元(CPU)、图形处理单元(GPU)等。第二半导体管芯132和第三半导体管芯133可以包括多个存储器电路，诸如，静态随机存取存储器(SRAM)和动态随机存取存储器(DRAM)等。应该注意，第一半导体管芯131、第二半导体管芯132和第三半导体管芯133可以具有多个实施例，其也在本披露的范围内。
多芯片半导体器件100可以包括两个感光材料层106和108。感光材料层106形成在感光材料层108的顶部上。如图1中所示，第二半导体管芯132被嵌入感光材料层108中。第三半导体管芯133被嵌入感光材料层106中。感光材料层106可以进一步包括多个组件通孔(TAV，throughassembly via)102、104和116。应该注意，如图1中所示，TAV 104和TAV116都形成在感光材料层106中。然而，TAV 116形成在第三半导体管芯133和多芯片半导体器件100的焊球侧之间。相反地，TAV 104形成穿过感光材料层106，并且进一步连接至形成在感光材料层108的顶部上的第二重分配层134。同样地，TAV 102形成穿过感光材料层106，并且进一步连接至形成在感光材料层108中的TAV。以下参考图2-图4详细地描述感光材料层106、108和在每层中的各个TAV的形成处理。
第一半导体管芯131的有源电路层(未示出)通过多个TAV 102、104和重分配层114和134连接至焊球110。更特别地，第二重分配层134、TAV102、TAV 104和第一重分配层114可以形成多种连接路径，使得第一半导体管芯131的有源电路可以与焊球110连接。类似地，第一重分配层114、第二重分配层134和TAV 104、116可以形成多种连接路径，使得第二半导体管芯132和第三半导体管芯133的有源电路(未示出)可以与焊球110连接。
多芯片半导体器件100可以包括形成在第一半导体管芯131的背面上的底平面底层120。底平面底层120可以由导电材料形成，诸如，铜、银、金、钨、铝、其结合等。可替换地，底平面底层120可以由多种材料形成，诸如，玻璃、硅、陶瓷、聚合体等。根据一实施例，底平面底层120可以通过粘合剂122(诸如，包括环氧树脂等的热界面材料)粘合在半导体管芯131的背面上。
如在图1中所示，底层120邻近第一半导体管芯131直接形成。从而，底层120可以帮助消散从第一半导体管芯131产生的热。结果，底层120可以帮助减小第一半导体管芯131的结温温度(junction temperature)。与不具有底层的半导体管芯相比，第一半导体管芯131受益于来自底层120的散热，使得第一半导体管芯131的可靠性和性能可以被改进。根据一实施例，底层120的厚度在5um至50um的范围内。应该注意，底层的厚度的范围被选择纯粹用于演示目的，并且不旨在将本披露的多种实施例限制到任何特定厚度。本领域技术人员将认识到多种改变、替换和修改。
将进一步注意，本领域技术人员将认识到多管芯半导体器件100的堆叠结构可以具有多种改变、替换和修改。例如，第二半导体管芯132可以使用多个金属凸块(未示出)被面对面地附着至第一半导体管芯131。类似地，第三半导体管芯133可以被翻转(flip)。结果，在第三半导体管芯133和第二半导体管芯132之间存在面对面堆叠结构。
图2A-图2E是根据一实施例的制造多芯片半导体器件的中间阶段的横截面图。图2A示出晶圆平面141的横截面图。如图2A中所示，晶圆平面141可以进一步包括多个金属焊盘204，其连接件通过重分配层202被重新分配。晶圆平面141可以包括多个第一半导体管芯，诸如131。而且，每个第一半导体管芯131都可以包括有源电路层、基板层、ILD层和IMD层(未示出)。金属焊盘204和重分配层202提供用于晶圆平面41的有源电路层的多种连接路径。
图2B示出在晶圆平面141的顶部上堆叠第二半导体管芯132和第三半导体管芯133的处理。第二半导体管芯132的背面通过采用第一粘合剂126(诸如，环氧树脂、热界面材料等)附着至晶圆平面141的顶部。类似地，第三半导体管芯133的背面通过采用第二粘合剂124附着至第二半导体管芯132的顶部。注意，第二粘合剂124可以与第一粘合剂126相同。可替换地，第二粘合剂124可以与第一粘合剂126不同。
图2C示出感光材料层106的横截面图。感光材料层106形成在晶圆平面141的顶部上。如图2C中所示，第二半导体管芯132和第三半导体管芯133被嵌入感光材料层106中。感光材料层可以包括聚苯并噁唑(PBO)、SU-8感光环氧树脂、薄膜型聚合体材料等。
图2C进一步示出在感光材料层106中形成多个开口的横截面图。考虑电和热的需求，感光材料层106的选择区域被曝光。结果，被曝光的感光区域的物理特性改变。根据一实施例，被曝光区域的物理特性的改变将导致，当显影剂溶液被应用至感光材料层106时，暴光区域被蚀刻掉。结果，形成多种开口252。在感光材料层106中形成开口252涉及光刻操作(其已知)，并且从而在此不进一步详细地论述。
图2D示出多个TAV和重分配层的形成。如图2D中所示，导电材料使用电化学镀处理填充开口252(未示出，但是在图2C中示出)。结果，多个TAV 102、104和116形成在感光材料层106中。导电材料可以是铜，但是可以是任何合适导电材料，诸如，铜合金、铝、钨、银及其结合。为了重新分配与TAV 102、104和116的电连接，第一重分配层114可以形成在感光材料层106的顶部上。第一重分配层114可以通过电化学镀方法形成。应该注意，第一重分配层114可以与TAV 102、104和116同时形成。可替换地，第一重分配层114可以在形成TAV 102、104和116之后形成。
图2E示出多个UBM结构和互连焊盘的形成。多个UBM结构112形成在重分配层114的顶部。UBM结构112可以帮助防止多芯片半导体器件的焊球和集成电路之间的扩散，同时提供低阻抗电连接。互连焊盘提供连接多芯片半导体器件与外部电路(未示出)的有效方式。互连焊盘是多芯片半导体器件的I/O焊盘。根据一实施例，互连焊盘可以是多个焊球110。可替换地，互连焊盘可以是多个接点栅格阵列(LGA)焊盘。图2E进一步示出使用切割处理将重配置晶圆分为多个多管芯结构的处理。切割处理在本领域中已知，并且从而在此不再详细地论述。
图3A-图3I是根据另一实施例的在制造多芯片半导体器件中的中间阶段的横截面图。图3A示出放置晶圆平面142的横截面图。如图3A中所示，晶圆平面142可以进一步包括多个金属焊盘304，其连接件通过重分配层302被重新分配。晶圆平面142可以进一步包括多个第二半导体管芯132。图3B示出在晶圆平面142的顶部上堆叠第三半导体管芯133的处理。第三半导体管芯133的背面通过采用第二粘合剂124被粘合在晶圆平面142的顶部上。
图3C示出感光材料层108的横截面图。感光材料层108形成在晶圆平面142的顶部上。如图3C中所示，第三半导体管芯133被嵌入感光材料层108中。感光材料可以包括聚苯并噁唑(PBO)、SU-8感光环氧树脂、薄膜型聚合体材料等。图3C进一步示出在感光材料层108中形成多个开口352的横截面图。感光材料层108中的开口352的形成类似于图2C中所示的开口252的形成，从而不再进一步详细地描述以避免重复。
图3D示出多个TAV和重分配层的形成。如图3D中所示，TAV 104、116和重分配层134可以通过电化学镀处理形成，其以上已经参考图2D被描述，从而不再重复。图3D进一步示出使用切割处理将重配置晶圆分为多个多管芯结构302的处理。切割处理在本领域中已知，从而在此不再详细地论述。
图3E示出晶圆平面141的横截面图。如图3E中所示，晶圆平面141可以进一步包括多个金属焊盘204，其连接件通过重分配层202被重新分配。晶圆平面141可以进一步包括多个第一半导体管芯131。图3F示出在晶圆平面141的顶部上堆叠多管芯结构302的处理。多管芯结构302的形成已经关于图3D在以上描述了。如图3D所示，多管芯结构302使得顶部具有感光层，其中，第三半导体管芯133被嵌入感光层中。多管芯结构302的背面通过采用第一粘合剂126被粘合在晶圆平面141的顶部上。
图3G示出感光材料层106的横截面图。感光材料层106形成在晶圆平面141的顶部上。如图3G中所示，第二半导体管芯132和第三半导体管芯133被嵌入感光材料层106中。图3G进一步示出在感光材料层106中形成多个开口的横截面图。形成感光材料层和感光材料层中的多个开口的处理已经关于图2C在以上描述，从而在此不再详细地论述以避免重复。
图3H示出感光材料层106中的多个TAV和感光材料层106的顶部上的重分配层的形成。在感光层中形成多个TAV和重分配层的处理在以上关于图2D进行了描述，并且从而不再进一步详细地描述。图3I示出多个UBM结构和互连焊盘的形成。图3I进一步示出使用切割处理形成多管芯结构312。形成UBM结构和互连焊盘并且将重配置晶圆分为多个多管芯结构312的处理类似于图2E。
图4A-图4H是根据又一实施例的在制造多芯片半导体器件中的中间阶段的横截面图。图4A示出晶圆平面141的横截面图，其类似于图2A。图4B示出在晶圆平面141的顶部上堆叠第二半导体管芯132的处理。第二半导体管芯132的背面通过采用第一粘合剂126被粘合到第一半导体管芯131的顶部上。
图4C示出感光材料层108的横截面图。感光材料层108形成在晶圆平面141的顶部上。如图4C中所示，第二半导体管芯132被嵌入感光材料层108中。图4C进一步示出在感光材料层108中形成多个开口452的横截面图。形成多个开口452的处理类似于图2C中所示的形成开口252的处理，并且从而在此不再进一步详细地论述。
图4D示出多个TAV和第二重分配层的形成。类似于图2D中所示的处理，多个TAV 102、104和第二重分配层134通过电化学镀方法形成。图4E示出在感光材料层108的顶部上堆叠第三半导体管芯13的处理。第三半导体管芯133的背面通过采用第二粘合剂124被粘合在感光材料层108的顶部上。
图4F示出感光材料层106的横截面图。感光材料层106形成在感光材料层108的顶部上。如图4F中所示，第三半导体管芯133被嵌入感光材料层106中。形成感光材料层和开口的处理以上关于图2C进行了描述，从而不再详细地论述以避免重复。图4G示出在感光材料层106中形成多个TAV的横截面图。形成TAV 102、104、106的处理类似于图2D中所示的处理。
图4H示出多个UBM结构和互连焊盘的形成。多个UBM结构形成在重分配层114和焊球110之间。图4H进一步示出使用切割处理将重配置晶圆分为多个多管芯结构412的处理。切割处理在本领域中已知，并且从而在此不再详细地论述。
虽然已经详细地描述了本披露的实施例及其优点，但是在不脱离由所附权利要求限定的本披露的精神和范围的情况下，在此可以做出多种改变、替换和更改。
而且，本申请的范围并不仅限于本说明书中描述的工艺、机器、制造、材料组分、装置、方法和步骤的特定实施例。作为本领域普通技术人员应理解，通过本发明，现有的或今后开发的用于执行与根据本发明所采用的所述相应实施例基本相同的功能或获得基本相同结果的工艺、机器、制造，材料组分、装置、方法或步骤根据本发明可以被使用。因此，所附权利要求应该包括在这样的工艺、机器、制造、材料组分、装置、方法或步骤的范围内。

Claims (10)

1.一种方法，包括：
在晶圆的顶面上附着第一半导体管芯；
在所述第一半导体管芯上附着第二半导体管芯；
通过将所述第一半导体管芯和所述第二半导体管芯嵌入第一感光材料层，形成重配置晶圆；以及
在所述第一感光材料层中形成第一组组件通孔。
2.根据权利要求1所述的方法，进一步包括：
使用粘着层在底层上附着所述晶圆；以及
将所述底层与所述晶圆分离。
3.根据权利要求1所述的方法，进一步包括：
使用第一粘着层将所述第二半导体芯片附着至所述第一半导体管芯；
使用第二粘着层以背面对正面的方式将所述第一半导体管芯附着至所述晶圆；
在所述第一感光材料层的顶部上形成第一重分配层；以及
在所述第一重分配层的顶部上形成多个焊球。
4.根据权利要求1所述的方法，进一步包括：
使用多个金属凸块以正面对正面的方式将所述第二半导体管芯附着至所述第一半导体管芯；以及
使用多个金属凸块以正面对正面的方式将所述第一半导体管芯附着至所述晶圆。
5.根据权利要求1所述的方法，进一步包括：
在所述第二半导体管芯的一侧和所述第一感光材料层的正面之间形成第一组开口；
在所述第一半导体管芯的一侧和所述第一感光材料层的所述正面之间形成第二组开口；以及
在所述晶圆的一侧和所述第一感光材料层的所述正面之间形成第三组开口。
6.根据权利要求5所述的方法，进一步包括：
在所述第一组开口中电镀导电材料；
在所述第二组开口中电镀导电材料；以及
在所述第三组开口中电镀导电材料。
7.根据权利要求1所述的方法，进一步包括：
将所述重配置晶圆切割为多个封装件，其中，每个封装件都包括多个半导体管芯。
8.一种方法，包括：
在第二晶圆的顶面上附着半导体管芯；
通过将所述第二晶圆和所述半导体管芯嵌入到第一感光材料层中，形成第一重配置晶圆；
将所述第一重配置晶圆切割为多个多管芯结构；
在第一晶圆的顶面上附着所述多个多管芯结构；
通过将所述多个多管芯结构嵌入到第二感光材料层中，形成第二重配置晶圆；以及
在所述第二感光材料层中形成第一组组件通孔。
9.根据权利要求8所述的方法，进一步包括：
使用第一粘着层在第一底层上附着所述第一晶圆；以及
使所述第一底层与所述第一晶圆分离。
10.一种方法，包括：
在晶圆的顶面上附着第一半导体管芯；
通过将所述第一半导体管芯嵌入第一感光材料层中，形成第一重配置晶圆；
在所述第一感光材料层中形成第一组组件通孔；
在所述第一感光材料层上附着第二半导体管芯；
在所述第一感光材料层的顶部上形成第二感光材料层，其中，所述第二半导体管芯被嵌入所述第二感光材料层中；以及
在所述第二感光材料层中形成第二组组件通孔。
CN201210010835.6A 2011-08-10 2012-01-11 多芯片晶圆级封装的方法 Active CN102931102B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/206,602 2011-08-10
US13/206,602 US20130040423A1 (en) 2011-08-10 2011-08-10 Method of Multi-Chip Wafer Level Packaging

Publications (2)

Publication Number Publication Date
CN102931102A true CN102931102A (zh) 2013-02-13
CN102931102B CN102931102B (zh) 2016-12-14

Family

ID=47645876

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201210010835.6A Active CN102931102B (zh) 2011-08-10 2012-01-11 多芯片晶圆级封装的方法

Country Status (2)

Country Link
US (2) US20130040423A1 (zh)
CN (1) CN102931102B (zh)

Cited By (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104051399A (zh) * 2013-03-15 2014-09-17 台湾积体电路制造股份有限公司 晶圆级芯片尺寸封装中间结构装置和方法
CN105023916A (zh) * 2014-04-22 2015-11-04 精材科技股份有限公司 晶片封装体及其制造方法
CN105097744A (zh) * 2014-05-09 2015-11-25 精材科技股份有限公司 晶片封装体及其制造方法
CN105097790A (zh) * 2014-05-09 2015-11-25 精材科技股份有限公司 晶片封装体及其制造方法
CN105097736A (zh) * 2014-05-09 2015-11-25 台湾积体电路制造股份有限公司 利用后通孔工艺的3d衬底上晶圆上芯片结构
US9412678B2 (en) 2013-03-08 2016-08-09 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for 3D IC package
CN105895599A (zh) * 2015-02-18 2016-08-24 阿尔特拉公司 具有双侧堆叠结构的集成电路封装
CN106449590A (zh) * 2016-11-08 2017-02-22 华进半导体封装先导技术研发中心有限公司 一种半导体存储模块及其制作方法
CN106653628A (zh) * 2016-11-08 2017-05-10 华进半导体封装先导技术研发中心有限公司 一种半导体存储器及其制作方法
CN106952831A (zh) * 2016-01-06 2017-07-14 台湾积体电路制造股份有限公司 使用热与机械强化层的装置及其制造方法
CN107301981A (zh) * 2016-04-15 2017-10-27 台湾积体电路制造股份有限公司 集成的扇出型封装件以及制造方法
CN107622982A (zh) * 2016-07-13 2018-01-23 台湾积体电路制造股份有限公司 芯片封装结构
US10096571B2 (en) 2014-04-30 2018-10-09 Taiwan Semiconductor Manufacturing Company, Ltd. Chip-on-wafer package and method of forming same
CN108780791A (zh) * 2016-03-01 2018-11-09 索尼公司 半导体装置、电子模块、电子设备和用于生产半导体装置的方法
CN109196640A (zh) * 2016-06-29 2019-01-11 英特尔公司 用于不同尺寸的管芯的多芯片封装
US10269619B2 (en) 2013-03-15 2019-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer level chip scale packaging intermediate structure apparatus and method
US10373885B2 (en) 2014-04-30 2019-08-06 Taiwan Semiconductor Manufacturing Company, Ltd. 3D stacked-chip package
CN111276468A (zh) * 2018-12-05 2020-06-12 台湾积体电路制造股份有限公司 半导体结构及其形成方法
CN112018060A (zh) * 2019-05-31 2020-12-01 台湾积体电路制造股份有限公司 集成电路器件及其形成方法
US11469215B2 (en) 2016-07-13 2022-10-11 Taiwan Semiconductor Manufacturing Co., Ltd. Chip package structure with molding layer and method for forming the same
US11502062B2 (en) 2019-05-31 2022-11-15 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and method
US11532594B2 (en) 2015-09-21 2022-12-20 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated fan-out package and the methods of manufacturing
US11532529B2 (en) 2015-09-21 2022-12-20 Taiwan Semiconductor Manufacturing Company Ltd. Method of manufacturing an integrated fan-out package having fan-out redistribution layer (RDL) to accommodate electrical connectors
US12094847B2 (en) 2020-11-17 2024-09-17 Samsung Electronics Co., Ltd. Semiconductor package and method of manufacturing the same

Families Citing this family (51)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8058101B2 (en) 2005-12-23 2011-11-15 Tessera, Inc. Microelectronic packages and methods therefor
US8482111B2 (en) 2010-07-19 2013-07-09 Tessera, Inc. Stackable molded microelectronic packages
KR101128063B1 (ko) 2011-05-03 2012-04-23 테세라, 인코포레이티드 캡슐화 층의 표면에 와이어 본드를 구비하는 패키지 적층형 어셈블리
US8836136B2 (en) 2011-10-17 2014-09-16 Invensas Corporation Package-on-package assembly with wire bond vias
US8835228B2 (en) 2012-05-22 2014-09-16 Invensas Corporation Substrate-less stackable package with wire-bond interconnect
US9502390B2 (en) 2012-08-03 2016-11-22 Invensas Corporation BVA interposer
US9446943B2 (en) 2013-05-31 2016-09-20 Stmicroelectronics S.R.L. Wafer-level packaging of integrated devices, and manufacturing method thereof
US9312233B2 (en) * 2013-06-27 2016-04-12 Intel Corporation Method of forming molded panel embedded die structure
US9167710B2 (en) 2013-08-07 2015-10-20 Invensas Corporation Embedded packaging with preformed vias
US20150076714A1 (en) * 2013-09-16 2015-03-19 Invensas Corporation Microelectronic element with bond elements to encapsulation surface
US9583456B2 (en) 2013-11-22 2017-02-28 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US9583411B2 (en) 2014-01-17 2017-02-28 Invensas Corporation Fine pitch BVA using reconstituted wafer with area array accessible for testing
US10381326B2 (en) 2014-05-28 2019-08-13 Invensas Corporation Structure and method for integrated circuits packaging with increased density
KR101640076B1 (ko) * 2014-11-05 2016-07-15 앰코 테크놀로지 코리아 주식회사 웨이퍼 레벨의 칩 적층형 패키지 및 이의 제조 방법
US9595496B2 (en) 2014-11-07 2017-03-14 Qualcomm Incorporated Integrated device package comprising silicon bridge in an encapsulation layer
US9802813B2 (en) 2014-12-24 2017-10-31 Stmicroelectronics (Malta) Ltd Wafer level package for a MEMS sensor device and corresponding manufacturing process
DE102015102535B4 (de) * 2015-02-23 2023-08-03 Infineon Technologies Ag Verbundsystem und Verfahren zum haftenden Verbinden eines hygroskopischen Materials
US9888579B2 (en) 2015-03-05 2018-02-06 Invensas Corporation Pressing of wire bond wire tips to provide bent-over tips
US9502372B1 (en) 2015-04-30 2016-11-22 Invensas Corporation Wafer-level packaging using wire bond wires in place of a redistribution layer
TWI620296B (zh) * 2015-08-14 2018-04-01 矽品精密工業股份有限公司 電子封裝件及其製法
US20170098629A1 (en) 2015-10-05 2017-04-06 Mediatek Inc. Stacked fan-out package structure
US10490528B2 (en) 2015-10-12 2019-11-26 Invensas Corporation Embedded wire bond wires
US9490222B1 (en) 2015-10-12 2016-11-08 Invensas Corporation Wire bond wires for interference shielding
US10332854B2 (en) 2015-10-23 2019-06-25 Invensas Corporation Anchoring structure of fine pitch bva
US10181457B2 (en) 2015-10-26 2019-01-15 Invensas Corporation Microelectronic package for wafer-level chip scale packaging with fan-out
EP3168870A1 (en) * 2015-11-11 2017-05-17 Nexperia B.V. Semiconductor device and method of making a semiconductor device
US10043779B2 (en) 2015-11-17 2018-08-07 Invensas Corporation Packaged microelectronic device for a package-on-package device
US10141291B2 (en) * 2015-11-30 2018-11-27 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and method of manufacturing the same
US9984992B2 (en) 2015-12-30 2018-05-29 Invensas Corporation Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces
US20170287870A1 (en) * 2016-04-01 2017-10-05 Powertech Technology Inc. Stacked chip package structure and manufacturing method thereof
US10304802B2 (en) 2016-05-02 2019-05-28 International Business Machines Corporation Integrated wafer-level processing system
US10068853B2 (en) * 2016-05-05 2018-09-04 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package and method of fabricating the same
US9935075B2 (en) 2016-07-29 2018-04-03 Invensas Corporation Wire bonding method and apparatus for electromagnetic interference shielding
US10177078B2 (en) * 2016-11-28 2019-01-08 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming chip package structure
US10299368B2 (en) 2016-12-21 2019-05-21 Invensas Corporation Surface integrated waveguides and circuit structures therefor
US10672729B2 (en) * 2017-03-30 2020-06-02 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and method of forming package structure
US10763239B2 (en) * 2017-10-27 2020-09-01 Taiwan Semiconductor Manufacturing Co., Ltd. Multi-chip wafer level packages and methods of forming the same
TWI647808B (zh) * 2017-11-13 2019-01-11 旺宏電子股份有限公司 無銲墊外扇晶粒堆疊結構及其製作方法
US10566301B2 (en) 2017-11-17 2020-02-18 General Electric Company Semiconductor logic device and system and method of embedded packaging of same
US10396053B2 (en) * 2017-11-17 2019-08-27 General Electric Company Semiconductor logic device and system and method of embedded packaging of same
US10276523B1 (en) 2017-11-17 2019-04-30 General Electric Company Semiconductor logic device and system and method of embedded packaging of same
US10211141B1 (en) 2017-11-17 2019-02-19 General Electric Company Semiconductor logic device and system and method of embedded packaging of same
US10510634B2 (en) * 2017-11-30 2019-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method
US10510705B2 (en) * 2017-12-29 2019-12-17 Advanced Semiconductor Engineering, Inc. Semiconductor package structure having a second encapsulant extending in a cavity defined by a first encapsulant
US10510650B2 (en) * 2018-02-02 2019-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacturing semiconductor device packaging structure having through interposer vias and through substrate vias
US11532533B2 (en) 2019-10-18 2022-12-20 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit package and method
US11444059B2 (en) * 2019-12-19 2022-09-13 Micron Technology, Inc. Wafer-level stacked die structures and associated systems and methods
DE102020204773A1 (de) * 2020-04-15 2021-10-21 Robert Bosch Gesellschaft mit beschränkter Haftung Sensoranordnung, umfassend eine Mehrzahl von einzelnen und separaten Sensorelementen
US11164853B1 (en) * 2021-02-08 2021-11-02 Xintec Inc. Chip package and manufacturing method thereof
US11776908B2 (en) 2021-04-15 2023-10-03 Micron Technology, Inc. Semiconductor die edge protection for semiconductor device assemblies and associated systems and methods
GB2618627A (en) * 2022-05-06 2023-11-15 Cirrus Logic Int Semiconductor Ltd Electronic circuit fabrication

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1579020A (zh) * 2001-12-07 2005-02-09 富士通株式会社 半导体器件及其制造方法
US20080246126A1 (en) * 2007-04-04 2008-10-09 Freescale Semiconductor, Inc. Stacked and shielded die packages with interconnects
US7550857B1 (en) * 2006-11-16 2009-06-23 Amkor Technology, Inc. Stacked redistribution layer (RDL) die assembly package
US20090289356A1 (en) * 2008-05-23 2009-11-26 Stats Chippac, Ltd. Wirebondless Wafer Level Package with Plated Bumps and Interconnects
US7671457B1 (en) * 2002-05-01 2010-03-02 Amkor Technology, Inc. Semiconductor package including top-surface terminals for mounting another semiconductor package
US20100155920A1 (en) * 2008-12-24 2010-06-24 Samsung Electronics Co., Ltd. Stacked semiconductor package, semiconductor package module and method of manufacturing the stacked semiconductor package
US20100193932A1 (en) * 2009-02-05 2010-08-05 Joon Seok Kang Wafer level package for heat dissipation and method of manufacturing the same
CN101877348A (zh) * 2009-03-06 2010-11-03 通用电气公司 用于堆叠的管芯嵌入式芯片堆积的系统和方法

Family Cites Families (54)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4811082A (en) 1986-11-12 1989-03-07 International Business Machines Corporation High performance integrated circuit packaging structure
US5075253A (en) 1989-04-12 1991-12-24 Advanced Micro Devices, Inc. Method of coplanar integration of semiconductor IC devices
US4990462A (en) 1989-04-12 1991-02-05 Advanced Micro Devices, Inc. Method for coplanar integration of semiconductor ic devices
US5380681A (en) 1994-03-21 1995-01-10 United Microelectronics Corporation Three-dimensional multichip package and methods of fabricating
US6002177A (en) 1995-12-27 1999-12-14 International Business Machines Corporation High density integrated circuit packaging with chip stacking and via interconnections
US6213376B1 (en) 1998-06-17 2001-04-10 International Business Machines Corp. Stacked chip process carrier
US6281042B1 (en) 1998-08-31 2001-08-28 Micron Technology, Inc. Structure and method for a high performance electronic packaging assembly
US6271059B1 (en) 1999-01-04 2001-08-07 International Business Machines Corporation Chip interconnection structure using stub terminals
US6461895B1 (en) 1999-01-05 2002-10-08 Intel Corporation Process for making active interposer for high performance packaging applications
US6229216B1 (en) 1999-01-11 2001-05-08 Intel Corporation Silicon interposer and multi-chip-module (MCM) with through substrate vias
US6243272B1 (en) 1999-06-18 2001-06-05 Intel Corporation Method and apparatus for interconnecting multiple devices on a circuit board
US6355501B1 (en) 2000-09-21 2002-03-12 International Business Machines Corporation Three-dimensional chip stacking assembly
KR100364635B1 (ko) 2001-02-09 2002-12-16 삼성전자 주식회사 칩-레벨에 형성된 칩 선택용 패드를 포함하는 칩-레벨3차원 멀티-칩 패키지 및 그 제조 방법
KR100394808B1 (ko) 2001-07-19 2003-08-14 삼성전자주식회사 웨이퍼 레벨 적층 칩 패키지 및 그 제조 방법
KR100435813B1 (ko) 2001-12-06 2004-06-12 삼성전자주식회사 금속 바를 이용하는 멀티 칩 패키지와 그 제조 방법
DE10200399B4 (de) 2002-01-08 2008-03-27 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Erzeugung einer dreidimensional integrierten Halbleitervorrichtung und dreidimensional integrierte Halbleitervorrichtung
US6975016B2 (en) 2002-02-06 2005-12-13 Intel Corporation Wafer bonding using a flexible bladder press and thinned wafers for three-dimensional (3D) wafer-to-wafer vertical stack integration, and application thereof
US6887769B2 (en) 2002-02-06 2005-05-03 Intel Corporation Dielectric recess for wafer-to-wafer and die-to-die metal bonding and method of fabricating the same
US6661085B2 (en) 2002-02-06 2003-12-09 Intel Corporation Barrier structure against corrosion and contamination in three-dimensional (3-D) wafer-to-wafer vertical stack
US6762076B2 (en) 2002-02-20 2004-07-13 Intel Corporation Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices
JP4363823B2 (ja) * 2002-07-04 2009-11-11 富士通マイクロエレクトロニクス株式会社 半導体装置の実装システム
US6600222B1 (en) 2002-07-17 2003-07-29 Intel Corporation Stacked microelectronic packages
US6790748B2 (en) 2002-12-19 2004-09-14 Intel Corporation Thinning techniques for wafer-to-wafer vertical stacks
US6908565B2 (en) 2002-12-24 2005-06-21 Intel Corporation Etch thinning techniques for wafer-to-wafer vertical stacks
US20040212080A1 (en) * 2003-04-22 2004-10-28 Kai-Chi Chen [chip package structure and process for fabricating the same]
US6924551B2 (en) 2003-05-28 2005-08-02 Intel Corporation Through silicon via, folded flex microelectronic package
US6946384B2 (en) 2003-06-06 2005-09-20 Intel Corporation Stacked device underfill and a method of fabrication
JP4016340B2 (ja) * 2003-06-13 2007-12-05 ソニー株式会社 半導体装置及びその実装構造、並びにその製造方法
US7320928B2 (en) 2003-06-20 2008-01-22 Intel Corporation Method of forming a stacked device filler
KR100537892B1 (ko) * 2003-08-26 2005-12-21 삼성전자주식회사 칩 스택 패키지와 그 제조 방법
US7345350B2 (en) 2003-09-23 2008-03-18 Micron Technology, Inc. Process and integration scheme for fabricating conductive components, through-vias and semiconductor components including conductive through-wafer vias
KR100621992B1 (ko) 2003-11-19 2006-09-13 삼성전자주식회사 이종 소자들의 웨이퍼 레벨 적층 구조와 방법 및 이를이용한 시스템-인-패키지
KR100570514B1 (ko) 2004-06-18 2006-04-13 삼성전자주식회사 웨이퍼 레벨 칩 스택 패키지 제조 방법
KR100618837B1 (ko) 2004-06-22 2006-09-01 삼성전자주식회사 웨이퍼 레벨 패키지를 위한 얇은 웨이퍼들의 스택을형성하는 방법
US7307005B2 (en) 2004-06-30 2007-12-11 Intel Corporation Wafer bonding with highly compliant plate having filler material enclosed hollow core
US7087538B2 (en) 2004-08-16 2006-08-08 Intel Corporation Method to fill the gap between coupled wafers
TWI260056B (en) 2005-02-01 2006-08-11 Phoenix Prec Technology Corp Module structure having an embedded chip
US7317256B2 (en) 2005-06-01 2008-01-08 Intel Corporation Electronic packaging including die with through silicon via
US7557597B2 (en) 2005-06-03 2009-07-07 International Business Machines Corporation Stacked chip security
US7402515B2 (en) 2005-06-28 2008-07-22 Intel Corporation Method of forming through-silicon vias with stress buffer collars and resulting devices
US7432592B2 (en) 2005-10-13 2008-10-07 Intel Corporation Integrated micro-channels for 3D through silicon architectures
US7528494B2 (en) 2005-11-03 2009-05-05 International Business Machines Corporation Accessible chip stack and process of manufacturing thereof
US7410884B2 (en) 2005-11-21 2008-08-12 Intel Corporation 3D integrated circuits using thick metal for backside connections and offset bumps
US7402442B2 (en) 2005-12-21 2008-07-22 International Business Machines Corporation Physically highly secure multi-chip assembly
US7279795B2 (en) 2005-12-29 2007-10-09 Intel Corporation Stacked die semiconductor package
US20080136004A1 (en) 2006-12-08 2008-06-12 Advanced Chip Engineering Technology Inc. Multi-chip package structure and method of forming the same
US20080174008A1 (en) 2007-01-18 2008-07-24 Wen-Kun Yang Structure of Memory Card and the Method of the Same
US7576435B2 (en) 2007-04-27 2009-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Low-cost and ultra-fine integrated circuit packaging technique
CN201130749Y (zh) 2007-08-17 2008-10-08 富士康(昆山)电脑接插件有限公司 电池连接器
KR101213175B1 (ko) 2007-08-20 2012-12-18 삼성전자주식회사 로직 칩에 층층이 쌓인 메모리장치들을 구비하는반도체패키지
KR101501739B1 (ko) * 2008-03-21 2015-03-11 삼성전자주식회사 반도체 패키지 제조 방법
US7989356B2 (en) * 2009-03-24 2011-08-02 Stats Chippac, Ltd. Semiconductor device and method of forming enhanced UBM structure for improving solder joint reliability
US8076184B1 (en) * 2010-08-16 2011-12-13 Stats Chippac, Ltd. Semiconductor device and method of forming wafer-level multi-row etched leadframe with base leads and embedded semiconductor die
US8288203B2 (en) * 2011-02-25 2012-10-16 Stats Chippac, Ltd. Semiconductor device and method of forming a wafer level package structure using conductive via and exposed bump

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1579020A (zh) * 2001-12-07 2005-02-09 富士通株式会社 半导体器件及其制造方法
US7671457B1 (en) * 2002-05-01 2010-03-02 Amkor Technology, Inc. Semiconductor package including top-surface terminals for mounting another semiconductor package
US7550857B1 (en) * 2006-11-16 2009-06-23 Amkor Technology, Inc. Stacked redistribution layer (RDL) die assembly package
US20080246126A1 (en) * 2007-04-04 2008-10-09 Freescale Semiconductor, Inc. Stacked and shielded die packages with interconnects
US20090289356A1 (en) * 2008-05-23 2009-11-26 Stats Chippac, Ltd. Wirebondless Wafer Level Package with Plated Bumps and Interconnects
US20100155920A1 (en) * 2008-12-24 2010-06-24 Samsung Electronics Co., Ltd. Stacked semiconductor package, semiconductor package module and method of manufacturing the stacked semiconductor package
US20100193932A1 (en) * 2009-02-05 2010-08-05 Joon Seok Kang Wafer level package for heat dissipation and method of manufacturing the same
CN101877348A (zh) * 2009-03-06 2010-11-03 通用电气公司 用于堆叠的管芯嵌入式芯片堆积的系统和方法

Cited By (49)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9412678B2 (en) 2013-03-08 2016-08-09 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for 3D IC package
US12051616B2 (en) 2013-03-15 2024-07-30 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer level chip scale packaging intermediate structure apparatus and method
US10269619B2 (en) 2013-03-15 2019-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer level chip scale packaging intermediate structure apparatus and method
CN104051399A (zh) * 2013-03-15 2014-09-17 台湾积体电路制造股份有限公司 晶圆级芯片尺寸封装中间结构装置和方法
CN104051399B (zh) * 2013-03-15 2018-06-08 台湾积体电路制造股份有限公司 晶圆级芯片尺寸封装中间结构装置和方法
US11037819B2 (en) 2013-03-15 2021-06-15 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer level chip scale packaging intermediate structure apparatus and method
US11631611B2 (en) 2013-03-15 2023-04-18 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer level chip scale packaging intermediate structure apparatus and method
CN105023916A (zh) * 2014-04-22 2015-11-04 精材科技股份有限公司 晶片封装体及其制造方法
US10096571B2 (en) 2014-04-30 2018-10-09 Taiwan Semiconductor Manufacturing Company, Ltd. Chip-on-wafer package and method of forming same
US10373885B2 (en) 2014-04-30 2019-08-06 Taiwan Semiconductor Manufacturing Company, Ltd. 3D stacked-chip package
US10971417B2 (en) 2014-04-30 2021-04-06 Taiwan Semiconductor Manufacturing Company, Ltd. 3D stacked-chip package
US9754918B2 (en) 2014-05-09 2017-09-05 Taiwan Semiconductor Manufacturing Company, Ltd. 3D chip-on-wafer-on-substrate structure with via last process
US9761510B2 (en) 2014-05-09 2017-09-12 Xintec Inc. Chip package and method for forming the same
US10535631B2 (en) 2014-05-09 2020-01-14 Taiwan Semiconductor Manufacturing Company, Ltd. 3D Chip-on-wager-on-substrate structure with via last process
CN105097736A (zh) * 2014-05-09 2015-11-25 台湾积体电路制造股份有限公司 利用后通孔工艺的3d衬底上晶圆上芯片结构
CN105097790A (zh) * 2014-05-09 2015-11-25 精材科技股份有限公司 晶片封装体及其制造方法
CN105097744A (zh) * 2014-05-09 2015-11-25 精材科技股份有限公司 晶片封装体及其制造方法
CN105097790B (zh) * 2014-05-09 2018-12-04 精材科技股份有限公司 晶片封装体及其制造方法
CN105097736B (zh) * 2014-05-09 2018-12-07 台湾积体电路制造股份有限公司 利用后通孔工艺的3d衬底上晶圆上芯片结构
US10157882B2 (en) 2014-05-09 2018-12-18 Taiwan Semiconductor Manufacturing Company, Ltd. 3D chip-on-wafer-on-substrate structure with via last process
CN105895599A (zh) * 2015-02-18 2016-08-24 阿尔特拉公司 具有双侧堆叠结构的集成电路封装
US11532594B2 (en) 2015-09-21 2022-12-20 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated fan-out package and the methods of manufacturing
US11532529B2 (en) 2015-09-21 2022-12-20 Taiwan Semiconductor Manufacturing Company Ltd. Method of manufacturing an integrated fan-out package having fan-out redistribution layer (RDL) to accommodate electrical connectors
US11538788B2 (en) 2015-09-21 2022-12-27 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated fan-out stacked package with fan-out redistribution layer (RDL)
US12080615B2 (en) 2015-09-21 2024-09-03 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacturing an integrated fan-out package having fan-out redistribution layer (RDL) to accommodate electrical connectors
US11469218B2 (en) 2016-01-06 2022-10-11 Taiwan Semiconductor Manufacturing Company, Ltd. Devices employing thermal and mechanical enhanced layers and methods of forming same
US10347606B2 (en) 2016-01-06 2019-07-09 Taiwan Semiconductor Manufacturing Company, Ltd. Devices employing thermal and mechanical enhanced layers and methods of forming same
CN106952831A (zh) * 2016-01-06 2017-07-14 台湾积体电路制造股份有限公司 使用热与机械强化层的装置及其制造方法
CN106952831B (zh) * 2016-01-06 2020-01-03 台湾积体电路制造股份有限公司 使用热与机械强化层的装置及其制造方法
US10811394B2 (en) 2016-01-06 2020-10-20 Taiwan Semiconductor Manufacturing Company, Ltd. Devices employing thermal and mechanical enhanced layers and methods of forming same
CN108780791A (zh) * 2016-03-01 2018-11-09 索尼公司 半导体装置、电子模块、电子设备和用于生产半导体装置的方法
US11355444B2 (en) 2016-03-01 2022-06-07 Sony Corporation Semiconductor device, electronic module, electronic apparatus each having stacked embedded active components in multilayer wiring board and method for producing the semiconductor device having the same
CN107301981A (zh) * 2016-04-15 2017-10-27 台湾积体电路制造股份有限公司 集成的扇出型封装件以及制造方法
CN107301981B (zh) * 2016-04-15 2020-07-10 台湾积体电路制造股份有限公司 集成的扇出型封装件以及制造方法
CN109196640A (zh) * 2016-06-29 2019-01-11 英特尔公司 用于不同尺寸的管芯的多芯片封装
US11756931B2 (en) 2016-07-13 2023-09-12 Taiwan Semiconductor Manufacturing Company, Ltd. Chip package structure with molding layer
US10734357B2 (en) 2016-07-13 2020-08-04 Taiwan Semiconductor Manufacturing Co., Ltd. Chip package structure with molding layer
US11469215B2 (en) 2016-07-13 2022-10-11 Taiwan Semiconductor Manufacturing Co., Ltd. Chip package structure with molding layer and method for forming the same
CN107622982A (zh) * 2016-07-13 2018-01-23 台湾积体电路制造股份有限公司 芯片封装结构
CN106653628A (zh) * 2016-11-08 2017-05-10 华进半导体封装先导技术研发中心有限公司 一种半导体存储器及其制作方法
CN106449590B (zh) * 2016-11-08 2019-08-09 华进半导体封装先导技术研发中心有限公司 一种半导体存储模块及其制作方法
CN106653628B (zh) * 2016-11-08 2019-07-16 华进半导体封装先导技术研发中心有限公司 一种半导体存储器及其制作方法
CN106449590A (zh) * 2016-11-08 2017-02-22 华进半导体封装先导技术研发中心有限公司 一种半导体存储模块及其制作方法
CN111276468A (zh) * 2018-12-05 2020-06-12 台湾积体电路制造股份有限公司 半导体结构及其形成方法
US11894309B2 (en) 2018-12-05 2024-02-06 Taiwan Semiconductor Manufacturing Company, Ltd. System on integrated chips (SoIC) and semiconductor structures with integrated SoIC
US11502062B2 (en) 2019-05-31 2022-11-15 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and method
CN112018060A (zh) * 2019-05-31 2020-12-01 台湾积体电路制造股份有限公司 集成电路器件及其形成方法
US12057439B2 (en) 2019-05-31 2024-08-06 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit packages
US12094847B2 (en) 2020-11-17 2024-09-17 Samsung Electronics Co., Ltd. Semiconductor package and method of manufacturing the same

Also Published As

Publication number Publication date
US9679882B2 (en) 2017-06-13
US20160155731A1 (en) 2016-06-02
CN102931102B (zh) 2016-12-14
US20130040423A1 (en) 2013-02-14

Similar Documents

Publication Publication Date Title
CN102931102A (zh) 多芯片晶圆级封装的方法
US11276645B2 (en) Encapsulation of a substrate electrically connected to a plurality of pin arrays
CN102931173A (zh) 多芯片晶圆级封装
KR101884971B1 (ko) 더미 다이들을 갖는 팬-아웃 적층 시스템 인 패키지(ｓｉｐ) 및 그 제조 방법
US10381326B2 (en) Structure and method for integrated circuits packaging with increased density
CN103208482B (zh) 通孔组件模块及其形成方法
KR102661959B1 (ko) 반도체 장치 및 이를 포함하는 반도체 패키지
TW202404430A (zh) 半導體核心組件
CN105845636A (zh) 在用于接合管芯的中介层中的具有不同尺寸的tsv
CN105118823A (zh) 一种堆叠型芯片封装结构及封装方法
Lau Recent advances and new trends in nanotechnology and 3D integration for semiconductor industry
US9548219B2 (en) Semiconductor package and fabrication method thereof and carrier structure
CN104867909B (zh) 用于有源装置的嵌入式管芯再分布层
US9553080B1 (en) Method and process for integration of TSV-middle in 3D IC stacks
KR101123804B1 (ko) 반도체 칩 및 이를 갖는 적층 반도체 패키지
CN104733381A (zh) 一种晶圆硅穿孔互连工艺
CN104051411B (zh) 叠层封装结构
US20180158774A1 (en) Fabrication method of semiconductor substrate
KR20090084645A (ko) 스택 패키지의 제조방법
Zheng et al. 3D stacked package technology and its application prospects
TW201428931A (zh) 三維晶片堆疊結構
US20230230902A1 (en) Semiconductor package structure and manufacturing method thereof
TWI409933B (zh) 晶片堆疊封裝結構及其製法
US11289440B1 (en) Combination-bonded die pair packaging and associated systems and methods
Sakai et al. Design and demonstration of large 2.5 D glass interposer for high bandwidth applications

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant