CN1579020A - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

Info

Publication number
CN1579020A
CN1579020A CNA018238653A CN01823865A CN1579020A CN 1579020 A CN1579020 A CN 1579020A CN A018238653 A CNA018238653 A CN A018238653A CN 01823865 A CN01823865 A CN 01823865A CN 1579020 A CN1579020 A CN 1579020A
Authority
CN
China
Prior art keywords
mentioned
terminal
semiconductor device
semiconductor chip
wiring pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CNA018238653A
Other languages
English (en)
Other versions
CN100350607C (zh
Inventor
松木浩久
爱场喜孝
佐藤光孝
冈本九弘
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Socionext Inc
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of CN1579020A publication Critical patent/CN1579020A/zh
Application granted granted Critical
Publication of CN100350607C publication Critical patent/CN100350607C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02379—Fan-out arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05026—Disposition the internal layer being disposed in a recess of the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05541—Structure
    • H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05655—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13024—Disposition the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24226—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73209—Bump and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73217—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/82009—Pre-treatment of the connector or the bonding area
    • H01L2224/8203—Reshaping, e.g. forming vias
    • H01L2224/82035—Reshaping, e.g. forming vias by heating means
    • H01L2224/82039—Reshaping, e.g. forming vias by heating means using a laser
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06506—Wire or wire-like electrical connections between devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06524—Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
    • H01L2225/06586—Housing with external bump or bump-like connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01011—Sodium [Na]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01028—Nickel [Ni]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01057—Lanthanum [La]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

半导体器件，包含：在一面上具有第1端子(7)的第1半导体芯片(5)；比第1半导体芯片(5)大，重叠第1半导体芯片(5)并且在一面上具有第2端子(3)的第2半导体芯片(1a)；被形成在第2半导体芯片(1a)上覆盖第1半导体芯片(5)的绝缘膜(10)；在绝缘膜(10)中至少被形成在第1半导体芯片(5)的周边区域上的多个孔(10a)；在孔(10a)的内周面以及底面上形成膜状并且与上述第2半导体芯片(1a)的第2端子(3)电连接的孔(11a)；被形成在绝缘膜(10)的上表面上的布线图案(11b)；被连接在布线图案(11b)上的外部端子(14)。

Description

半导体器件及其制造方法
技术领域
本发明涉及半导体器件及其制造方法，更详细地说涉及具有多个半导体芯片的半导体器件及其制造方法。
背景技术
对于下一代包含手机和移动式PC的便携信息终端设备，小型·轻量·薄型化的提高已成为首要问题。因而，为了提高今后预计高成长的便携信息终端的竞争力，重要的是可以实现进一步小型·轻量·薄型化的高密度安装技术的开发。
作为高密度安装技术有倒装芯片安装、多芯片组件和叠层衬底等各种技术。进而，从想在封装中承载多个功能这一需求出发，进行了叠层半导体芯片这种构造的芯片尺寸封装(CSP)的技术开发，进而，开发了不使用插入衬底的晶片级CSP。
晶片级CSP例如具有图1所示那样的构造。
在图1中，在第1半导体器件芯片101上形成布线102，在该布线102之上经由焊球103安装有第2半导体器件芯片104上。该第2半导体器件芯片104比第1半导体器件芯片101还小。
另外，在第1半导体器件芯片101上的布线102中，在第2半导体器件芯片104的周围区域上连接有插针状的端子(通路)105。进而，在第1半导体器件芯片101的上表面上，用于封装第2半导体器件芯片104的封装树脂106的厚度被形成为端子105的上端露出那样的厚度。在该端子105的上端连接焊球107。
但是，图1所示的端子105因为用电镀法形成在布线102上，所以端子105的形成需要时间，CSP形成的生产能力差。
另外，端子105的形成区域因为被限定在第2半导体器件芯片104的外围，所以不希望端子105的数量增加。
发明内容
本发明的目的在于提供一种在多个半导体芯片的叠层构造中扩展外部端子的形成区域的同时，可以容易地形成外部端子的半导体器件。
上述课题通过具有以下部分的半导体器件解决，在一面上具有第1端子的第1半导体芯片；比上述第1半导体芯片大，重叠上述第1半导体芯片并且一边具有第2端子的第2半导体芯片；被形成在上述第2半导体芯片上覆盖上述第1半导体芯片的绝缘膜；被形成在上述绝缘膜上的多个孔；在上述孔的内周面以及底面被形成膜状并且与上述第1端子以及上述第2端子的至少一方电连接的导电性通路；被形成在上述绝缘膜上表面上的第1布线图案；被形成在上述第1布线图案上的外部端子。
如果采用本发明则在叠层大小不同的第1以及第2半导体芯片的构造的半导体器件中，在第2半导体芯片上形成覆盖第1半导体芯片的绝缘膜，在绝缘膜上形成孔，在孔中形成膜状的通路，在绝缘膜上形成布线图案。
因而，因为未完全填充孔而形成了膜状的通路，所以可以以短时间形成通路，而且可以用同一导电膜构成布线图案和通路，可以减少膜形成的工序。
另外，如果把绝缘膜上的布线图案引出到第1半导体芯片的上方，在其上形成外部端子，则可以抑制绝缘膜上的多个外部端子的窄间距化，而后可以增加外部端子的数量。
在孔内通过用绝缘膜覆盖通路可以防止通路的腐蚀。另外，在绝缘膜上的第1布线图案中，通过除去和外部端子连接的部分用另一绝缘膜覆盖，可以防止第1布线图案的迁移短路和腐蚀。
可是，不管把形成第1半导体芯片的第1端子的电路面相对形成有第2半导体芯片的第2端子的电路面配置为朝上还是朝下，都可以用同样的技术制成叠层晶片级封装，而且，可以分开面朝上、面朝下使用，因为可以实现具有多种功能的半导体器件的叠加所以有用。
另外，因为在第1以及第2半导体芯片的上方有第1布线图案，所以可以在自由的位置上形成外部端子，可以应对多插针构造。
进而，通过使具有上述那样的布线图案和通路的绝缘膜多层化，和重叠上述的构造，可以安置多个半导体芯片。
附图说明
图1是展示以往构造的半导体器件的断面图。
图2(a)～(c)是本发明的实施方式1的半导体器件的制造工序(其1)。
图3(a)～(c)是本发明的实施方式1的半导体器件的制造工序(其2)。
图4(a)、(b)是本发明的实施方式1的半导体器件的制造工序(其3)。
图5(a)、(b)是本发明的实施方式1的半导体器件的制造工序(其4)。
图6(a)是展示构成本发明的实施方式1的半导体器件的半导体晶片的断面图。
图6(b)是展示构成本发明的实施方式1的半导体器件的半导体器件芯片的断面图。
图7是展示本发明的实施方式1的半导体器件的断面图。
图8是展示本发明的实施方式1的具有多层布线构造的半导体器件的断面图。
图9(a)、(b)是本发明的实施方式2的半导体器件的制造工序的断面图(其1)。
图10是展示本发明的实施方式2的半导体器件的断面图。
图11(a)～(c)是本发明的实施方式3的半导体器件的制造工序的断面图(其1)。
图12(a)、(b)是本发明的实施方式3的半导体器件的制造工序的断面图(其2)。
图13(a)、(b)是本发明的实施方式3的半导体器件的制造工序的断面图(其3)。
图14是展示本发明的实施方式3的半导体器件的断面图。
图15是展示本发明的实施方式4的第1半导体器件的断面图。
图16是展示本发明的实施方式4的第2半导体器件的断面图。
具体实施方式
以下根据附图说明本发明的实施方式。
(实施方式1)
图2～图5是展示本发明的实施方式1的多芯片封装(MCP)的形成工序的断面图。
首先，如图2(a)所示，准备在多个器件区域A上分别形成第1半导体电路(未图示)的半导体晶片1。半导体晶片1如图6(a)的局部放大图所示，在其上面具有保护绝缘膜2，在该保护绝缘膜2上形成使第1端子(导电性焊盘)3露出的开口2a，而该第1端子与半导体器件的内部布线(未图示)电连接。第1端子3用铝、铜等形成。
进而，半导体晶片1例如是硅晶片，在后工序中被切断为各个第1半导体电路，以器件区域A为单位进行分割。
接着，如图2(b)所示，在保护绝缘膜2和第1端子3上形成厚度0.5μm的钛和镍双层构造的金属膜，进而，用光刻法构图该金属膜由此形成第1再布线图案4。该第1再布线图案4是从第1端子3上面引出到保护绝缘膜2上面的导电图案。
其后，如图6(b)所示，准备形成有第2半导体电路(未图示)的第1半导体器件芯片5。第1半导体器件芯片5是比半导体晶片1的器件区域A还小的例如硅芯片，在其上面具有保护绝缘膜6。在保护绝缘膜6上形成使第2端子7露出的开口6a，该第2端子7与第1半导体器件芯片5内部的布线(未图示)连接。另外，在该保护绝缘膜6上面形成从第2端子7上面引出的第2再布线图案8。
而后，如图2(c)所示，把第1半导体器件芯片5的下面借助管芯键合剂(粘接剂)9键合在半导体晶片1的半导体器件区域A的中央。
以下，如图3(a)所示，在半导体晶片1上表面上形成环氧树脂、聚酰亚胺那样的树脂绝缘层10，使其比第1半导体芯片5还高10～20μm左右。由此，第1半导体芯片5由树脂绝缘膜10覆盖。
树脂绝缘层10在半导体晶片1上用旋转涂布、印刷、叠层法等形成。例如，当采用叠层法的情况下需要充分调整树脂绝缘层的膜厚等，在第1半导体器件芯片5上和其周围想办法不使气泡进入。
另外，当因树脂绝缘层10的材料特性使得树脂绝缘层10的表面平坦化困难的情况下，在把树脂绝缘层10形成在半导体晶片1上后，希望通过使用后研磨技术的机械性研磨、化学机械研磨(CMP)或者抛光等平坦化树脂绝缘层10的上表面。例如在把环氧树脂和聚酰亚胺等构成的树脂绝缘层10在半导体晶体1上例如形成为120～150μm厚度后，用机械性研磨或者化学机械研磨法平坦化树脂绝缘膜10的上表面。
以下，如图3(b)所示，在树脂绝缘层10中，在第1再布线图案4和第2再布线图案8上分别形成直径80～100μm的通路口(贯通口)10a。
作为树脂绝缘层10，当选择感光性树脂材料的情况下，在非感光光线的环境下进行半导体晶片1上的树脂绝缘层10的形成后，用通路孔形成用的曝光掩模曝光树脂绝缘层10，通过进一步使用碳酸钠(NaCO3)等的无机碱液显影来容易地形成通路孔10a。
如果通过这种曝光、显影形成通路孔10a，则通路孔10a因为成为如上部宽阔那样的锥形状，所以容易进行在后述的通路孔10a内的各种处理。这种情况下，因为通路孔10a之下的第1端子3未被第1再布线图案4覆盖，所以防止了第1端子3被无机碱液腐蚀。
另一方面，当作为树脂绝缘层10的构成材料选择非感光性材料的情况下，适宜的方法是通过在树脂绝缘层10的规定位置上照射激光等的高能量形成通路孔10a。当用激光形成通路孔10a的情况下，在通路孔10a下因为第1端子3和保护绝缘膜2被作为硬质金属的第1再布线图案4覆盖，所以由铝、铜等比较软的导电材料构成的第1端子3和其周边的保护绝缘膜2由激光照射被除去，没有劣化的可能性。
进而，通路孔10a也可以通过钻孔形成。
以下，如图3(c)所示，用稀释溶剂活性化树脂绝缘层10的表面，其后通过无电解电镀在树脂绝缘层10的上表面和通路孔10a的内周面以及底面上形成厚度0.5～1.0μm的金属膜11，例如铜膜。这种厚度的金属膜11与通过电镀形成图1所示的外部端子105的情况相比在极短的时间形成。这种情况下，金属膜11在通路孔10a内连接在第1再布线图案4之上。进而，金属膜也可以是多层构造。
进而，当想把金属膜11形成为3～5μm厚度的情况下，可以采用在用无电解电镀法暂时形成薄的膜后，用电解电镀法形成厚膜的方法。另外，当树脂绝缘层10由环氧树脂和聚酰亚胺等构成的情况下，在树脂绝缘层10的上表面和通路孔10a内表面上采用无电解电镀法生长金属膜11是容易的。
此后如图4(a)所示，通过用光刻法构图金属膜11，在把通路孔10a内的金属膜11作为通路11a剩下的同时，把树脂绝缘层10上面的金属膜11的图案用作第3再生图案11b。由此，树脂绝缘层10上面的多个第3再布线图案11b分别经由通路11a以及第2再布线图案8与第1半导体器件芯片5的端子7电连接，并且，经由通路11a以及第1再布线图案4与半导体晶片1的端子3电连接。另外，第1半导体器件芯片5的端子6经由通路11a和第3再布线图案11b与半导体晶片1的端子3电连接。进而，通路11a虽然与第3再布线11b连接，但也可以有不连接的部分。
以下如图4(b)所示，通过在树脂绝缘层10的开口部分10a内使用滑动辊或者用印刷法埋入非感光性的环氧树脂，形成埋入绝缘层12。由此，在开口部分10a内通路11a用埋入绝缘层12覆盖。
接着如图5(a)所示，把由感光性环氧树脂或者感光性酚醛清漆树脂等构成的绝缘性的树脂覆盖膜13形成在树脂绝缘层10、第3再布线图案11b以及埋入绝缘层12之上。树脂覆盖膜13通过使用滑动辊或者印刷法在非感光光线的气氛中被涂布在树脂绝缘层10上。树脂覆盖膜13防止第3再布线图案11b的腐蚀，防止第3再布线图案10b的迁移短路。
进而，通过曝光、显影构图树脂覆盖膜13，形成使第3再布线图案11b的端子部分露出的开口部分13a。
其后如图5(b)，通过树脂覆盖膜13的开口13a把焊料突点等的外部端子14连接在第3再布线图案11b上。这种情况下，外部端子14因为被形成在树脂覆盖膜13的开口13a中，所以防止了位置偏移，或者定位也很容易。这种情况下，如果曝光、显影，则开口13a因为是上部宽大的锥形状，所以第3再布线图案11b上的球状的外部端子14的定位和连接容易。
其后，通过切割图5(b)所示的半导体晶片1的半导体电路区域A之间的边界，把半导体晶片分割成多个第2半导体器件芯片1a，由此形成多个图7所示的MCP型的半导体器件。这种情况下，第2半导体器件芯片1a的侧面不被树脂绝缘层10覆盖而露出。
进而，在分割半导体晶片1前，也可以通过机械研磨法或者化学机械研磨法研磨其下表面。
如果采用以上的半导体器件，则在被形成在第2半导体器件芯片1a上面的树脂绝缘层10中，在第1半导体芯片5的周围形成通路孔10a的同时，把被形成在该通路孔10a的内周面以及底面上的半导体膜作为通路11a使用，与此同时，在树脂绝缘层10的上面使用其导电膜作为再布线图案11b。
因而，要形成在通路孔10a内的通路11a的形成，因为采用金属膜11的形成这一工序，所以与完全埋入通路孔那样的以往构造相比可以在短时间内形成。
另外，在形成通路11a的金属膜11中被形成在树脂绝缘层10上面上的部分通过构图作为再布线图案11b使用。因此，在第1半导体器件5的上方也形成有外部端子14，可以比以往增加外部端子14的数量，而且，可以缓和外部端子14的窄间距化。
进而，因为通路11a和再布线图案11b双方都用同样的金属膜11形成，所以与各自分别形成的情况相比生产能力得到改善。
进而，在上述的例子中，在半导体晶片1上接合第1半导体器件芯片5，其后，在形成树脂绝缘膜10、通路11a、第3再布线图案11b、保护覆盖膜13、外部端子14后分割半导体晶片1。但是，在把半导体晶片1分割成多个第2半导体器件晶片1a后，在第2半导体芯片1a上接合第2半导体芯片5，其后，也可以形成树脂绝缘层10、通路11a、第3再布线图案11b、保护覆盖膜13、外部端子14，由此也可以形成和图7所示相同构造的半导体器件。这种情况下，第2半导体器件芯片1a的侧面用树脂膜10覆盖。
另外如图8所示，也可以把具有树脂绝缘层10和通路11a和再布线图案11b的布线构造层设置成2层以上的多层构造，这种情况下，在最上面的树脂绝缘层10上形成保护覆盖膜13和外部端子14。这种情况下，上下再布线图案11b之间与高速信号处理对应地相互交叉配置。这样的多层布线构造也可以在以下所示的实施方式中采用。
(实施方式2)
在实施方式1中，在形成通路11a和再布线图案11b后，在通路孔10a内形成埋入绝缘层12，其后在树脂绝缘层10上形成树脂覆盖膜13。但是，也可以同时形成埋入绝缘层12和树脂覆盖膜13。
例如如图9(a)所示，在把感光性的树脂膜15，例如环氧树脂同时涂布在通路孔10a内和树脂绝缘层10上后，曝光、显影树脂膜15形成使第3再布线图案11b的端子部分露出的开口15a。
其后如图9(b)所示，通过树脂膜15的开口15a把外部端子14接合在再布线图案11b上。
如果采用本实施方式，则通路孔10a内的环氧树脂被作为埋入绝缘层使用，树脂绝缘层10上的环氧树脂被作为树脂覆盖膜使用，可以同时形成埋入绝缘层和树脂覆盖膜，与实施方式1相比减少了绝缘膜形成工序。
其后，通过切断半导体电路区域A之间的边界，可以形成图10所示的半导体器件。这种情况下，第2半导体器件芯片1a的侧面未被树脂绝缘层10覆盖而露出。
(实施方式3)
当在实施方式1所示的半导体晶片1上未形成第1再布线图案3的情况下，采用以下那样的工序。
首先，如图11(a)、(b)所示，在半导体晶片1上的保护绝缘膜2的开口2a内的端子3上用无电解电镀法有选择地形成3～5μm厚度的由镍磷(NiP)、镍、金等构成的被覆导电层16。
其后如图11(c)所示，用和实施方式1同样的方法在半导体晶片1上安装第1半导体器件芯片5。作为第1半导体器件芯片5，使用在其上面的保护绝缘膜6的第2端子7上不形成再布线图案，而形成NiP被覆导电膜17的构造的器件。
接着如图12(a)所示，如覆盖第1半导体器件芯片5那样在半导体晶片1上形成树脂绝缘层10。对于树脂绝缘层10的形成和其平坦化，采用和实施方式1一样的方法。
进而如图12(b)所示，在树脂绝缘层10中在第1半导体器件芯片5上和半导体晶片1的各自的端子3、7上的被覆导电体层16、17上形成通路孔10a。
通路孔10a采用和实施方式1一样的方法。即，当用感光材料构成树脂绝缘层10的情况下用曝光以及显影形成，或者，当用非感光性材料构成的情况下通过激光照射形成。这种情况下，在通路孔10a的下方由铜和铝形成的端子3、7分别用被覆导电层16、17保护，不直接接触显影液或者被激光直接曝光，防止因显影或者激光引起的劣化。进而，通路孔10a也可以通过钻孔形成。
其后如图13(a)所示，经过和实施方式1同样的工序，在通路孔10a内形成通路11a，在树脂绝缘层10上形成再布线图案11b。进而如图13(b)所示，形成埋入绝缘膜12、覆盖绝缘膜13、外部端子14。进而，埋入绝缘膜12、覆盖绝缘膜13也可以如实施方式2所示由同样的树脂膜15同时形成。
其后，按各器件区域A把半导体晶片1分割为多个第2半导体器件芯片1a，则形成图14所示的半导体器件。这种情况下，第2半导体器件芯片1a的侧面未被树脂绝缘层10覆盖而露出。
如果采用以上那样的工序，则可以通过被覆导电层16、17防止为了在树脂绝缘层10上形成通路孔10a而使用的无机碱对端子3、7的供给，或者可以通过被覆导电层16、17防止为了形成通路孔10a而使用的激光对端子3、7的照射，可以防止端子3、7的劣化。
进而，虽然可以在第1半导体芯片5和半导体晶片1的一方上形成再布线图案，但需要用被被覆导电层16、17覆盖未用再布线图案覆盖的端子3、7。
(实施方式4)
图6(b)所示的第1半导体器件芯片5可以不经由树脂绝缘层10上面的再布线图案11b，而通过引线或者焊球等与半导体晶片1的端子3连接。
例如如图15所示，也可以采用在第1半导体器件芯片5的端子7上不形成再布线图案而形成镍磷的被覆导电层17，通过引线键合法用金(导电性)丝21连接其被覆导电层17和半导体晶片(第2半导体器件芯片1a)上的再布线图案4的构造。这种情况下，在第1半导体器件芯片5上在树脂绝缘层10上不形成通路孔10a。
另外如图16所示，也可以在第1半导体器件芯片5的端子7上连接焊料突点(外部端子)22，把该焊料突点22连接在半导体晶片1(第2半导体器件芯片1a)上的再布线图案4上。这种情况下，在第1半导体器件芯片5上在树脂绝缘层10内也不形成通路孔10a。
在图15、16所示的树脂绝缘层10中虽然在第1半导体器件芯片5的上方未形成通路孔10a，但在树脂绝缘层10上形成再布线图案11b，在其上接合外部端子14。
因而，树脂绝缘层10上的外部端子14的形成区域比以往还宽，还可以比以往增加外部端子14的数目，而且，缓和了外部端子14的窄间距化。
如上所述如果采用本发明，因为，在叠层大小不同的第1以及第2半导体芯片的构造的半导体器件中，形成在第2半导体芯片上覆盖第1半导体芯片的绝缘膜，在绝缘膜上形成孔，在孔中形成膜状的通路，在绝缘膜上形成布线图案，所以，可以短时间形成通路，而且可以用同样的导电膜构成布线图案和通路，可以减少膜形成工序。
另外，因为把绝缘膜上的布线图案引出到第1半导体芯片上，在其上形成外部端子，所以可以抑制在绝缘膜上的多个外部端子的窄芯片化，而且可以增加外部端子数。
进而，通过用绝缘膜覆盖孔内的通路可以防止通路的腐蚀，另外，在绝缘膜上的第1布线图案中，通过除去和外部端子连接的部分用另一绝缘膜覆盖，可以防止第1布线图案的迁移短路和腐蚀。

Claims (20)

1.一种半导体器件，其特征在于包含：
在一面上具有第1端子的第1半导体芯片；
比上述第1半导体芯片大，重叠上述第1半导体芯片并且在一面上具有第2端子的第2半导体芯片；
形成在上述第2半导体芯片上且覆盖上述第1半导体芯片的绝缘膜；
形成在上述绝缘膜上的多个孔；
在上述孔的内周面以及底面上形成为膜状并且与上述第1端子和上述第2端子中的至少一个电连接的导电性通路；
形成在上述绝缘膜上表面上的第1布线图案；
形成在上述第1布线图案上的外部端子。
2.权利要求1所述的半导体器件，其特征在于：把上述第1端子和上述第2端子设置成同样方向来将上述第1半导体芯片安置在上述第2半导体芯片上。
3.权利要求2所述的半导体器件，其特征在于：上述第1半导体芯片的上述第1端子经由导电性引线和上述第2半导体芯片的上述第2端子连接。
4.权利要求2或者3所述的半导体器件，其特征在于：上述第1半导体芯片的上述第1端子经由上述第1布线图案和上述通路与上述第2半导体芯片的上述第2端子电连接。
5.权利要求2～权利要求4中的任一项所述的半导体器件，其特征在于：上述第1半导体芯片经由粘接剂被安置在上述第2半导体芯片上。
6.权利要求1所述的半导体器件，其特征在于：上述第1半导体芯片和上述第2半导体芯片的具有上述第1端子的表面和具有上述第2端子的表面相互面对重叠。
7.权利要求6所述的半导体器件，其特征在于：在上述第2半导体芯片上形成有与上述第2端子电连接的第3布线图案，进而在该第3布线图案上经由导电材料连接上述第1半导体芯片的上述第1端子。
8.权利要求1所述的半导体器件，其特征在于：在上述第1端子和上述第2端子中的至少一个上形成有第2布线图案，上述通路被形成在该第2布线图案上。
9.权利要求1～权利要求8中的任一项所述的半导体器件，其特征在于：上述第1端子、上述第2端子中的至少一个经由被覆导电层与上述通路连接。
10.权利要求1～权利要求9中的任一项所述的半导体器件，其特征在于：上述通路和上述第1布线图案相互连接。
11.权利要求1～权利要求10中的任一项所述的半导体器件，其特征在于：在上述孔内上述通路被绝缘膜埋入。
12.权利要求1～权利要求11中的任一项所述的半导体器件，其特征在于：上述第1布线图案除去和上述外部端子连接的连接部分外，在上述绝缘膜上由覆盖绝缘膜覆盖。
13.权利要求1～权利要求12中的任一项所述的半导体器件，其特征在于：在上述孔内，在上述通路上和上述第1布线中的除去和上述外部端子连接的连接部分的区域上用同样的绝缘膜覆盖。
14.权利要求1～权利要求13中的任一项所述的半导体器件，其特征在于：上述第2半导体芯片的侧面露出。
15.一种半导体器件的制造方法，包含：
把具有第1端子的第1半导体芯片安装在比它大并且具有第2端子的半导体衬底上的工序；
在上述半导体衬底上形成覆盖上述第1半导体芯片的绝缘膜的工序；
在上述绝缘膜上形成孔的工序；
在上述孔内和上述绝缘膜上形成导电膜的工序；
构图上述导电膜，在上述孔内作为通路保留且在上述绝缘膜上形成布线的工序；以及
在上述第1布线上连接外部端子的工序。
16.权利要求15所述的半导体器件的制造方法，其特征在于：在上述第1端子和上述第2端子中的至少一个上形成金属图案，在该金属图案上形成上述孔。
17.权利要求16所述的半导体器件的制造方法，其特征在于：上述金属图案是布线图案。
18.权利要求15～权利要求17中的任一项所述的半导体器件的制造方法，其特征在于：上述孔的形成可以用激光照射法、光蚀刻法和钻孔法中的任意一种方法形成。
19.权利要求15～权利要求18中的任一项所述的半导体器件的制造方法，其特征在于：上述导电膜是由电镀法形成的金属膜。
20.权利要求15～权利要求19中的任一项所述的半导体器件的制造方法，其特征在于：上述绝缘膜是环氧树脂或者聚酰亚胺树脂。
CNB018238653A 2001-12-07 2001-12-07 半导体器件及其制造方法 Expired - Fee Related CN100350607C (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2001/010722 WO2003049184A1 (en) 2001-12-07 2001-12-07 Semiconductor device and method for manufacturing the same

Publications (2)

Publication Number Publication Date
CN1579020A true CN1579020A (zh) 2005-02-09
CN100350607C CN100350607C (zh) 2007-11-21

Family

ID=11738006

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB018238653A Expired - Fee Related CN100350607C (zh) 2001-12-07 2001-12-07 半导体器件及其制造方法

Country Status (6)

Country Link
US (2) US7084513B2 (zh)
EP (1) EP1455392A4 (zh)
JP (1) JP4182189B2 (zh)
KR (1) KR100636259B1 (zh)
CN (1) CN100350607C (zh)
WO (1) WO2003049184A1 (zh)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102931102A (zh) * 2011-08-10 2013-02-13 台湾积体电路制造股份有限公司 多芯片晶圆级封装的方法
US8461940B2 (en) 2008-02-18 2013-06-11 Murata Manufacturing Co., Ltd. Elastic wave device and method for manufacturing the same
CN103383927A (zh) * 2012-05-03 2013-11-06 三星电子株式会社 半导体封装及其形成方法
CN103996630A (zh) * 2013-02-19 2014-08-20 台湾积体电路制造股份有限公司 封装半导体器件和封装器件及方法
US8847377B2 (en) 2008-01-02 2014-09-30 SK Hynix Inc. Stacked wafer level package having a reduced size

Families Citing this family (74)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6710454B1 (en) 2000-02-16 2004-03-23 Micron Technology, Inc. Adhesive layer for an electronic apparatus having multiple semiconductor devices
EP1455392A4 (en) * 2001-12-07 2008-05-07 Fujitsu Ltd SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
US7633765B1 (en) * 2004-03-23 2009-12-15 Amkor Technology, Inc. Semiconductor package including a top-surface metal layer for implementing circuit features
US9691635B1 (en) 2002-05-01 2017-06-27 Amkor Technology, Inc. Buildup dielectric layer having metallization pattern semiconductor package fabrication method
US7548430B1 (en) 2002-05-01 2009-06-16 Amkor Technology, Inc. Buildup dielectric and metallization process and semiconductor package
US8349276B2 (en) 2002-09-24 2013-01-08 Duke University Apparatuses and methods for manipulating droplets on a printed circuit board
KR100574947B1 (ko) * 2003-08-20 2006-05-02 삼성전자주식회사 Ｂｇａ 패키지, 그 제조방법 및 ｂｇａ 패키지 적층 구조
JP4271590B2 (ja) * 2004-01-20 2009-06-03 新光電気工業株式会社 半導体装置及びその製造方法
US10811277B2 (en) 2004-03-23 2020-10-20 Amkor Technology, Inc. Encapsulated semiconductor package
US11081370B2 (en) 2004-03-23 2021-08-03 Amkor Technology Singapore Holding Pte. Ltd. Methods of manufacturing an encapsulated semiconductor device
TWI250596B (en) 2004-07-23 2006-03-01 Ind Tech Res Inst Wafer-level chip scale packaging method
DE102004048203A1 (de) * 2004-09-30 2005-12-29 Infineon Technologies Ag Stapelbares elektronisches Bauteil mit Durchgangskontaktierungen
US20060237828A1 (en) * 2005-04-22 2006-10-26 Robinson William D System and method for enhancing wafer chip scale packages
US9601474B2 (en) 2005-07-22 2017-03-21 Invensas Corporation Electrically stackable semiconductor wafer and chip packages
JP4395775B2 (ja) * 2005-10-05 2010-01-13 ソニー株式会社 半導体装置及びその製造方法
TWI284976B (en) * 2005-11-14 2007-08-01 Via Tech Inc Package, package module and manufacturing method of the package
JP2007207921A (ja) * 2006-01-31 2007-08-16 Stanley Electric Co Ltd 表面実装型光半導体デバイスの製造方法
US7884464B2 (en) * 2006-06-27 2011-02-08 Advanced Chip Engineering Technologies Inc. 3D electronic packaging structure having a conductive support substrate
WO2008014633A1 (en) 2006-06-29 2008-02-07 Intel Corporation Apparatus, system, and method for wireless connection in integrated circuit packages
KR100800476B1 (ko) * 2006-07-11 2008-02-04 삼성전자주식회사 반도체 패키지 및 그 제조방법과 반도체 모듈 및 그제조방법
TWI302732B (en) * 2006-08-03 2008-11-01 Unimicron Technology Corp Embedded chip package process and circuit board with embedded chip
TWI335658B (en) * 2006-08-22 2011-01-01 Advanced Semiconductor Eng Stacked structure of chips and wafer structure for making same
DE102007030986A1 (de) * 2006-10-25 2008-04-30 Robert Bosch Gmbh Elekrisches Bauelement mit Kontaktmitteln
US7550857B1 (en) 2006-11-16 2009-06-23 Amkor Technology, Inc. Stacked redistribution layer (RDL) die assembly package
US8178982B2 (en) 2006-12-30 2012-05-15 Stats Chippac Ltd. Dual molded multi-chip package system
US8304923B2 (en) * 2007-03-29 2012-11-06 ADL Engineering Inc. Chip packaging structure
KR100871380B1 (ko) * 2007-06-18 2008-12-02 주식회사 하이닉스반도체 수동소자가 탑재된 반도체 패키지
JP5215605B2 (ja) * 2007-07-17 2013-06-19 ラピスセミコンダクタ株式会社 半導体装置の製造方法
US8293587B2 (en) * 2007-10-11 2012-10-23 International Business Machines Corporation Multilayer pillar for reduced stress interconnect and method of making same
KR20090055316A (ko) * 2007-11-28 2009-06-02 삼성전자주식회사 반도체 패키지와, 이를 구비하는 전자 기기 및 반도체패키지의 제조방법
KR100910233B1 (ko) * 2008-01-02 2009-07-31 주식회사 하이닉스반도체 적층 웨이퍼 레벨 패키지
US8637341B2 (en) * 2008-03-12 2014-01-28 Infineon Technologies Ag Semiconductor module
US8362617B2 (en) * 2008-05-01 2013-01-29 Infineon Technologies Ag Semiconductor device
US7888184B2 (en) * 2008-06-20 2011-02-15 Stats Chippac Ltd. Integrated circuit packaging system with embedded circuitry and post, and method of manufacture thereof
US8354304B2 (en) * 2008-12-05 2013-01-15 Stats Chippac, Ltd. Semiconductor device and method of forming conductive posts embedded in photosensitive encapsulant
US20100148337A1 (en) * 2008-12-17 2010-06-17 Yong Liu Stackable semiconductor package and process to manufacture same
US8003445B2 (en) * 2009-03-26 2011-08-23 Stats Chippac Ltd. Integrated circuit packaging system with z-interconnects having traces and method of manufacture thereof
JP5165006B2 (ja) * 2010-01-25 2013-03-21 株式会社テラミクロス 半導体装置の製造方法
US8138014B2 (en) * 2010-01-29 2012-03-20 Stats Chippac, Ltd. Method of forming thin profile WLCSP with vertical interconnect over package footprint
US8455300B2 (en) 2010-05-25 2013-06-04 Stats Chippac Ltd. Integrated circuit package system with embedded die superstructure and method of manufacture thereof
US8343810B2 (en) * 2010-08-16 2013-01-01 Stats Chippac, Ltd. Semiconductor device and method of forming Fo-WLCSP having conductive layers and conductive vias separated by polymer layers
JP5703010B2 (ja) 2010-12-16 2015-04-15 新光電気工業株式会社 半導体パッケージ及びその製造方法
US8765525B2 (en) * 2011-06-16 2014-07-01 Stats Chippac Ltd. Method of manufacturing an integrated circuit packaging system including lasering through encapsulant over interposer
TWI469292B (zh) * 2011-07-26 2015-01-11 萬國半導體股份有限公司 應用雙層引線框架的堆疊式功率半導體裝置及其製備方法
US8487421B2 (en) * 2011-08-01 2013-07-16 Tessera, Inc. Microelectronic package with stacked microelectronic elements and method for manufacture thereof
US8901730B2 (en) 2012-05-03 2014-12-02 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus for package on package devices
US9177899B2 (en) * 2012-07-31 2015-11-03 Mediatek Inc. Semiconductor package and method for fabricating base for semiconductor package
TWI562295B (en) 2012-07-31 2016-12-11 Mediatek Inc Semiconductor package and method for fabricating base for semiconductor package
US10991669B2 (en) 2012-07-31 2021-04-27 Mediatek Inc. Semiconductor package using flip-chip technology
US9953907B2 (en) * 2013-01-29 2018-04-24 Taiwan Semiconductor Manufacturing Company, Ltd. PoP device
US8970023B2 (en) 2013-02-04 2015-03-03 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and methods of forming same
KR101488590B1 (ko) 2013-03-29 2015-01-30 앰코 테크놀로지 코리아 주식회사 반도체 디바이스 및 그 제조 방법
US9446943B2 (en) 2013-05-31 2016-09-20 Stmicroelectronics S.R.L. Wafer-level packaging of integrated devices, and manufacturing method thereof
US9653442B2 (en) * 2014-01-17 2017-05-16 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and methods of forming same
US9704841B2 (en) 2014-03-26 2017-07-11 United Microelectronics Corp. Method of packaging stacked dies on wafer using flip-chip bonding
US9330994B2 (en) 2014-03-28 2016-05-03 Stats Chippac, Ltd. Semiconductor device and method of forming RDL and vertical interconnect by laser direct structuring
KR102161776B1 (ko) * 2014-03-28 2020-10-06 에스케이하이닉스 주식회사 적층 패키지
JP6317629B2 (ja) * 2014-06-02 2018-04-25 株式会社東芝 半導体装置
US11239138B2 (en) * 2014-06-27 2022-02-01 Taiwan Semiconductor Manufacturing Company Methods of packaging semiconductor devices and packaged semiconductor devices
US10177115B2 (en) 2014-09-05 2019-01-08 Taiwan Semiconductor Manufacturing Company, Ltd. Package structures and methods of forming
KR102352237B1 (ko) 2014-10-23 2022-01-18 삼성전자주식회사 팬 아웃 웨이퍼 레벨 패키지의 제조 방법 및 그의 구조
US9802813B2 (en) 2014-12-24 2017-10-31 Stmicroelectronics (Malta) Ltd Wafer level package for a MEMS sensor device and corresponding manufacturing process
US9627311B2 (en) 2015-01-22 2017-04-18 Mediatek Inc. Chip package, package substrate and manufacturing method thereof
US20170098629A1 (en) 2015-10-05 2017-04-06 Mediatek Inc. Stacked fan-out package structure
US11037904B2 (en) 2015-11-24 2021-06-15 Taiwan Semiconductor Manufacturing Company, Ltd. Singulation and bonding methods and structures formed thereby
KR101803929B1 (ko) 2016-03-10 2018-01-11 주식회사 소프트에피 근자외선 발광 반도체 발광소자 및 이에 사용되는 3족 질화물 반도체 템플릿
US10068853B2 (en) * 2016-05-05 2018-09-04 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package and method of fabricating the same
US10177078B2 (en) * 2016-11-28 2019-01-08 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming chip package structure
US10510722B2 (en) * 2017-06-20 2019-12-17 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and method for manufacturing the same
US10879220B2 (en) * 2018-06-15 2020-12-29 Taiwan Semiconductor Manufacturing Company, Ltd. Package-on-package structure and manufacturing method thereof
CN110875294B (zh) * 2018-08-29 2024-01-23 恒劲科技股份有限公司 半导体装置的封装结构及其制造方法
CN111341750B (zh) * 2018-12-19 2024-03-01 奥特斯奥地利科技与系统技术有限公司 包括有导电基部结构的部件承载件及制造方法
US11063019B2 (en) * 2019-07-17 2021-07-13 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure, chip structure and method of fabricating the same
US11735554B2 (en) * 2020-08-14 2023-08-22 Sj Semiconductor (Jiangyin) Corporation Wafer-level chip scale packaging structure having a rewiring layer and method for manufacturing the wafer-level chip scale packaging structure

Family Cites Families (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2593965B2 (ja) * 1991-01-29 1997-03-26 三菱電機株式会社 半導体装置
JP3397542B2 (ja) * 1994-10-03 2003-04-14 株式会社東芝 半導体チップと一体化した半導体パッケ−ジ及びその製造方法
US5892273A (en) * 1994-10-03 1999-04-06 Kabushiki Kaisha Toshiba Semiconductor package integral with semiconductor chip
US5886412A (en) * 1995-08-16 1999-03-23 Micron Technology, Inc. Angularly offset and recessed stacked die multichip device
JP3644662B2 (ja) * 1997-10-29 2005-05-11 株式会社ルネサステクノロジ 半導体モジュール
US6025995A (en) * 1997-11-05 2000-02-15 Ericsson Inc. Integrated circuit module and method
JP3481444B2 (ja) * 1998-01-14 2003-12-22 シャープ株式会社 半導体装置及びその製造方法
JP3512657B2 (ja) * 1998-12-22 2004-03-31 シャープ株式会社 半導体装置
JP2000223645A (ja) * 1999-02-01 2000-08-11 Mitsubishi Electric Corp 半導体装置
US6291884B1 (en) * 1999-11-09 2001-09-18 Amkor Technology, Inc. Chip-size semiconductor packages
KR100347135B1 (ko) * 1999-12-24 2002-07-31 주식회사 하이닉스반도체 웨이퍼 레벨의 멀티칩 패키지 및 그 제조방법
US6348728B1 (en) 2000-01-28 2002-02-19 Fujitsu Limited Semiconductor device having a plurality of semiconductor elements interconnected by a redistribution layer
JP3996315B2 (ja) * 2000-02-21 2007-10-24 松下電器産業株式会社 半導体装置およびその製造方法
JP3651346B2 (ja) * 2000-03-06 2005-05-25 カシオ計算機株式会社 半導体装置およびその製造方法
JP3772066B2 (ja) * 2000-03-09 2006-05-10 沖電気工業株式会社 半導体装置
KR100559664B1 (ko) * 2000-03-25 2006-03-10 앰코 테크놀로지 코리아 주식회사 반도체패키지
JP4178715B2 (ja) * 2000-04-14 2008-11-12 松下電器産業株式会社 半導体装置およびその製造方法
JP2002009236A (ja) * 2000-06-21 2002-01-11 Shinko Electric Ind Co Ltd 多層半導体装置及びその製造方法
US6452278B1 (en) * 2000-06-30 2002-09-17 Amkor Technology, Inc. Low profile package for plural semiconductor dies
JP2002043503A (ja) * 2000-07-25 2002-02-08 Nec Kyushu Ltd 半導体装置
JP2002050721A (ja) * 2000-08-03 2002-02-15 Hitachi Cable Ltd 電子装置及びその製造方法
TW454287B (en) * 2000-12-06 2001-09-11 Siliconware Precision Industries Co Ltd Multi-media chip package and its manufacture
TW502408B (en) * 2001-03-09 2002-09-11 Advanced Semiconductor Eng Chip with chamfer
US6734568B2 (en) * 2001-08-29 2004-05-11 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the same
TW550997B (en) * 2001-10-18 2003-09-01 Matsushita Electric Ind Co Ltd Module with built-in components and the manufacturing method thereof
EP1455392A4 (en) * 2001-12-07 2008-05-07 Fujitsu Ltd SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
JP3904541B2 (ja) * 2003-09-26 2007-04-11 沖電気工業株式会社 半導体装置内蔵基板の製造方法

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8847377B2 (en) 2008-01-02 2014-09-30 SK Hynix Inc. Stacked wafer level package having a reduced size
US8461940B2 (en) 2008-02-18 2013-06-11 Murata Manufacturing Co., Ltd. Elastic wave device and method for manufacturing the same
CN102931102A (zh) * 2011-08-10 2013-02-13 台湾积体电路制造股份有限公司 多芯片晶圆级封装的方法
CN103383927A (zh) * 2012-05-03 2013-11-06 三星电子株式会社 半导体封装及其形成方法
CN103996630A (zh) * 2013-02-19 2014-08-20 台湾积体电路制造股份有限公司 封装半导体器件和封装器件及方法
CN103996630B (zh) * 2013-02-19 2017-04-26 台湾积体电路制造股份有限公司 封装半导体器件和封装器件及方法

Also Published As

Publication number Publication date
EP1455392A1 (en) 2004-09-08
US20060246623A1 (en) 2006-11-02
EP1455392A4 (en) 2008-05-07
KR100636259B1 (ko) 2006-10-19
US7084513B2 (en) 2006-08-01
US20050001329A1 (en) 2005-01-06
US7759246B2 (en) 2010-07-20
JP4182189B2 (ja) 2008-11-19
WO2003049184A1 (en) 2003-06-12
CN100350607C (zh) 2007-11-21
JPWO2003049184A1 (ja) 2005-04-21
KR20040071177A (ko) 2004-08-11

Similar Documents

Publication Publication Date Title
CN100350607C (zh) 半导体器件及其制造方法
CN1505147A (zh) 电子部件封装结构和生产该结构的方法
US9806050B2 (en) Method of fabricating package structure
CN1241252C (zh) 半导体装置及其制造方法、电路基片和电子仪器
CN100343965C (zh) 具有上下导电层的导通部的半导体装置及其制造方法
US20080290496A1 (en) Wafer level system in package and fabrication method thereof
CN1523665A (zh) 半导体装置及其制造方法
CN1187806C (zh) 电路装置的制造方法
CN1921108A (zh) 半导体封装及其制造方法
CN1574257A (zh) 半导体装置及其制造方法
CN1458815A (zh) 金属芯基板及其制造工艺
CN1543674A (zh) 带有埋设电感器的无引线芯片承载器的制造结构和方法
CN1929122A (zh) 半导体封装及其制造方法
CN1368757A (zh) 半导体装置和制造半导体设备的方法
CN1758430A (zh) 半导体器件和半导体器件的制造方法
CN1525544A (zh) 利用无引线电镀工艺制造的封装基片及其制造方法
CN1716601A (zh) 半导体器件和半导体晶片及其制造方法
CN1747630A (zh) 基板制造方法和电路板
CN1191619C (zh) 电路装置及其制造方法
CN1758431A (zh) 晶背上具有整合散热座的晶圆级封装以及晶片的散热方法
CN1191618C (zh) 电路装置的制造方法
CN1767178A (zh) 半导体载板及其制造方法与半导体封装组件
CN1186808C (zh) 电路装置的制造方法
CN101076890A (zh) 具有嵌埋于介电材料表面中的金属痕迹的相互连接元件的结构及其制造方法
CN1509134A (zh) 电路装置、电路模块及电路装置的制造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
C41 Transfer of patent application or patent right or utility model
TR01 Transfer of patent right

Effective date of registration: 20081219

Address after: Tokyo, Japan

Patentee after: Fujitsu Microelectronics Ltd.

Address before: Kanagawa, Japan

Patentee before: Fujitsu Ltd.

ASS Succession or assignment of patent right

Owner name: FUJITSU MICROELECTRONICS CO., LTD.

Free format text: FORMER OWNER: FUJITSU LIMITED

Effective date: 20081219

C56 Change in the name or address of the patentee

Owner name: FUJITSU SEMICONDUCTOR CO., LTD.

Free format text: FORMER NAME: FUJITSU MICROELECTRON CO., LTD.

CP01 Change in the name or title of a patent holder

Address after: Kanagawa

Patentee after: FUJITSU MICROELECTRONICS Ltd.

Address before: Kanagawa

Patentee before: Fujitsu Microelectronics Ltd.

CP02 Change in the address of a patent holder

Address after: Kanagawa

Patentee after: Fujitsu Microelectronics Ltd.

Address before: Tokyo, Japan

Patentee before: Fujitsu Microelectronics Ltd.

ASS Succession or assignment of patent right

Owner name: SUOSI FUTURE CO., LTD.

Free format text: FORMER OWNER: FUJITSU SEMICONDUCTOR CO., LTD.

Effective date: 20150515

C41 Transfer of patent application or patent right or utility model
TR01 Transfer of patent right

Effective date of registration: 20150515

Address after: Kanagawa

Patentee after: SOCIONEXT Inc.

Address before: Kanagawa

Patentee before: FUJITSU MICROELECTRONICS Ltd.

CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20071121

Termination date: 20181207

CF01 Termination of patent right due to non-payment of annual fee