CN1505147A - 电子部件封装结构和生产该结构的方法 - Google Patents
电子部件封装结构和生产该结构的方法 Download PDFInfo
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- CN1505147A CN1505147A CNA200310118745A CN200310118745A CN1505147A CN 1505147 A CN1505147 A CN 1505147A CN A200310118745 A CNA200310118745 A CN A200310118745A CN 200310118745 A CN200310118745 A CN 200310118745A CN 1505147 A CN1505147 A CN 1505147A
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- wiring pattern
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- insulating barrier
- connecting terminal
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- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
- H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
- H05K1/186—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or connecting to patterned circuits before or during embedding
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Abstract
包括了包含预定布线图样的布线基片;电子部件,其元件形成表面上的连接终端被倒装连接到布线图样上;用来覆盖电子部件的绝缘层;在电子部件的预定部位和位于连接终端上的绝缘层中形成的通路孔;在绝缘层上形成的、并通过通路孔连接到连接终端的叠加布线图样。
Description
发明领域
本发明涉及一种电子部件封装结构和生产该结构的方法,更具体来说,涉及具有这种由多个电子部件相互连接在一起、并被埋入到一个绝缘层中的结构的电子部件封装结构,以及生产这种产品的方法。
背景技术
LSI技术作为实现多媒体装置的关键技术,向着更高的数据传输速率和更大的数据传输能力不断地发展。因此,作为LSI和电子装置之间的接口,更高密度的封装技术也在不断地发展。
为了适应进一步的更高密度的要求,开发出了多片封装(半导体装置)技术,其中,多个半导体芯片在基片(substrate)上从三维方向上被压制成薄片(laminate)并被封装。作为举例,提出了具有这样结构的半导体装置:多个半导体芯片在三维方向上安装在布线基片(wiring substrate)上,而它们分别埋入到绝缘层中,并且多个半导体芯片通过在绝缘层和布线图样中形成的通路孔相互连接到一起。例如,在专利申请文献(KOKAI)2001-196525(专利文献1)、专利申请文献(KOKAI)2001-177045(专利文献2),和专利申请文献(KOKAI)2001-323645(专利文献3)中,提出了这样的半导体装置。
近年来,为了适应更高密度的封装,目前正在研究一种结构,其中,埋在绝缘层中、通过形成在半导体芯片和绝缘层中的通路孔(via hole)而相互连接在一起的多个半导体芯片被封装起来。上述的专利文献1至3都与多个半导体芯片通过形成于绝缘层中的通路孔而相互连接在一起的结构有关。没有考虑上述封装结构。
发明内容
本发明的一个目标是提供一种电子部件封装结构,在该结构中,电子部件被埋入到绝缘层中,并且多个电子部件通过在电子部件和绝缘层中形成的通路孔而相互连接在一起;并使得可以以一种简单的方法生产该结构,以及一种生产该结构的方法。
本发明涉及一种电子部件封装结构,它包括:包含预定布线图样的布线基片;电子部件,在它的元件形成表面上的连接终端,被倒装(filp-chip)连接到布线图样上;用来覆盖电子部件的绝缘层;形成于电子部件的预定部位和位于连接终端上的绝缘层中的通路孔;形成于绝缘层上面、并通过通路孔连接到连接终端的叠加布线图样(overlying wiring pattern)。
在本发明的电子部件封装结构中,首先,电子部件(半导体芯片,或者诸如此类)的连接终端被倒装连接到布线基片上的布线图样。之后,形成用来覆盖电子部件的绝缘层。之后,通过用RIE(活性离子腐蚀)或者激光连续蚀刻电子部件和位于连接终端上的绝缘层的预定部位,从而形成通路孔,连接终端从每个通路孔中暴露出来。之后,通过形成在电子部件和绝缘层中的通路孔连接到连接终端上的叠加布线图样被形成于绝缘层上。
用这种方式,在本发明的电子部件封装结构中,例如,通过一个蚀刻步骤,通路孔被连续形成在绝缘层和电子部件中,并且,通过一个电镀步骤,形成了通过通路孔连接到连接终端上、并延伸到绝缘层上面的叠加布线图样。也就是说,由于本发明的电子部件封装结构是通过非常简单的生产方法来生产的,它的生产成本降低了,并防止了生产中指定交付日期的延迟。
在本发明的一种优选模式中,厚度被变薄到大约150μm或者更少的半导体芯片被用作电子部件。此外,与电子部件同样的结构体、绝缘层、以及叠加布线图样形成于布线基片的布线图样上面,它们可以以多层方式,在叠加布线图样上被重复n次(n是为1或者更大的整数),并且多个电子部件可以通过通路孔相互连接到一起。
在这种情况下,由于电子部件封装结构的总厚度可以被降低,这样的封装结构可以适应于更高的密度。此外,由于上面和下面的电子部件通过在垂直方向上的布线而相互连接到一起,比起在半导体芯片通过导线连接的情况下,或者在侧向(lateral direction)上提供了伴随以布线路由(wiring routing)的线路的情况下,布线长度可以有所缩短。结果是,在高频应用中的半导体装置可以适应更高速率的信号。
本发明也涉及一种生产电子部件封装结构的方法,该方法包括以下步骤:将在元件形成表面上具有连接终端的电子部件的连接终端倒装连接到形成于底部基片(base substrate)的上面或者上方(onor over)的布线图样;形成用来覆盖电子部件的绝缘层;通过在预定部位从绝缘层的上表面蚀刻到电子部件的元件形成表面,形成深度到达连接终端的通路孔;在绝缘层上形成叠加布线图样,它通过通路孔连接到连接终端。
如上所述,通过使用本发明的生产电子部件封装结构的方法,生产本发明的电子部件封装结构可以很简单地实现。
在本发明的一个优选模式中,形成叠加布线图样的步骤包括以下步骤:在绝缘层上形成在包括通路孔的预定部位中具有开口部分(opening portion)的保护层(resist film);通过使用布线图样和作为电镀电源层而连接到布线图样的电子部件的连接终端的电镀方法,应用从通路孔的底部部分暴露出来的连接终端向上的镀层(plating),在通路孔和保护层的开口部分中形成导电层图样,并除去保护层,以获得叠加布线图样。
通过这样做,在从通路孔和保护层的开口部分中形成导电层图样的步骤中,通过顺序地应用从通路孔的底部部分暴露出来的连接终端向上的镀层,从而形成导电层图样。这样,导电层图样被填充并形成,而不会在通路孔中形成空隙。其结果是,由于在电子部件的连接终端和叠加布线图样之间,通过通路孔进行连接的可靠性可以获得改善,电子部件封装结构生产的产量可以获得提高。
附图说明
附图1A至1K是生产本发明的第一个实施例的电子部件封装结构的方法的侧视图。
附图2A至2L是生产本发明的第二个实施例的电子部件封装结构的方法的侧视图,其中附图2I是通过从附图2H的顶部看过去而描绘的透视平面图。
附图3是本发明的第二个实施例的电子部件封装结构的另一种模式的侧视图侧视图。
具体实施方式
在下文中,将通过参考附图,对本发明的实施例进行阐述。
(第一个实施例)
附图1A至1K是按照步骤的顺序排列的,示出了生产本发明的第一个实施例的电子部件封装结构的方法的侧视图。在生产本发明的第一个实施例的电子部件封装结构的方法中,首先,如附图1A所示,准备好半导体晶片10,在它上面形成有预定元件、多层布线等(图中未显示)。由铝(Al)或者类似材料制成的连接垫10a形成于半导体晶片10的元件形成表面上,以暴露在外。这样,如附图1B所示,通过打磨半导体晶片10的元件非形成表面(后表面),半导体晶片10的厚度被减少到大约150μm或者更少。
之后,如附图1C中所示,在对应于连接垫10a的预定部位的部分具有开口部分12a的保护层12形成于半导体晶片10的后表面之上。之后,通过RIE(活性离子腐蚀),并使用保护层12作为掩模,半导体晶片10从后表面侧被蚀刻。这样,就形成了通路孔10b,每个通路孔10b的深度到达位于半导体晶片的元件形成表面侧上面的连接垫10a。
之后,如附图1D所示,保护层12被除去。之后,通过CVD或者类似方法,由氧化硅层或者类似材料构成的无机绝缘层14被形成于通路孔10b的内表面以及半导体晶片10的后表面上。之后,通过激光或者类似方法,无机绝缘层14被从通路孔10b的底部部分去除。这样,连接垫10a(在附图1D中,这部分由A表示)被从通路孔10b的底部暴露出来。形成无机绝缘层14是为了使填充在通路孔10b中的半导体与半导体晶片10隔离。
之后,如附图1E所示,通过非电解镀(electroless plating)或者阴极空隙喷镀(sputter)的方法,晶粒铜层(seed Cu film)(未示出)被形成于通路孔10b的内表面和半导体晶片10的后表面上。之后,在包含通路孔10b的预定部位具有开口部分12a的保护层12被形成于晶粒铜层上面。之后,通过使用晶粒铜层作为电镀电源层进行电镀,铜层图样16a形成于通路孔10b和保护层12的开口部分12a中。
之后,如附图1F所示,保护层12被去除。之后,通过使用铜层图样16a作为掩模来蚀刻晶粒铜层,形成了通过通路孔10b连接到连接垫10a的贯通电极16。之后,如附图1G所示,通过切割半导体晶片10,获得了被分成单独的一片的半导体芯片20。连接到半导体芯片20的连接垫10a的凸起(bump)11在半导体晶片10被切割之前或之后形成。连接垫10a和凸起11是连接终端的一个例子。这样,除了半导体芯片20,还可以使用不同的电子部件,比如电容器或者类似部件。
之后,如附图1H所示,准备好了布线基片40,半导体芯片20安装在其上面。在此布线基片40中,在树脂构成的底部基片30中有通孔30a,之后,连接到底部基片30的第一布线图样32的通孔电镀层(through-hole plating layer)30b被分别形成于通孔30a的内表面之上,之后通孔被以树脂体(resin body)30c填充。
也具有通路孔34x的第一个夹层绝缘层(interlayer insulatingfilm)34被形成于第一布线图样32之上。之后,第二布线图样32a形成于第一个夹层绝缘层34上面,每个第二布线图样都通过通路孔34x连接到第一个布线图样32上。
之后,如附图1I所示,半导体芯片20的突起11被倒装焊接到布线基片40的第二布线图样32a上。之后,未充满的树脂18被填充到半导体芯片20与第二布线图样32a和第一个夹层绝缘层34之间的空隙(clearances)中。
之后,形成了用来覆盖半导体芯片20的第二个夹层绝缘层34a。之后,位于半导体芯片20的贯通电极16上面的、第二个夹层绝缘层34a的预定部分被激光或者类似方法蚀刻。这样,形成了第二通路孔34y,每个第二通路孔的深度都可以到达贯通电极16的上表面。
之后,如附图1J所示,通过与用来在上面的半导体晶片10的通路孔10b中形成贯通电极16的方法相同的方法(半添加(semi-additive)方法,或者类似方法),形成了通过第二通路孔34y连接到贯通电极16的第三布线图样32b(叠加布线图样)。
这样,在这之后,从将上述半导体芯片20的凸起11倒装焊接到第二布线图样32a上面的步骤,到形成第三布线图样32b的步骤,其中的各个步骤可以以预定次数重复。这样,多个半导体芯片20逐个被埋入夹层绝缘层中,并被三维封装,并且多个半导体芯片20通过形成于半导体芯片20和夹层绝缘层之中的通路孔而相互连接到一起。
这样,如附图1K所示,形成了焊接保护层21,它在第三布线图样32b的连接部位具有开口部分。之后,通过非电解镀,在第三布线图样的连接部位形成了镍/金(Ni/Au)层42。
之后,具有凸起11的叠加半导体芯片20a的凸起11被倒装焊接到第三布线图样32b的镍/金层42上。通过上述安排,就获得了本实施例的电子部件封装结构1。
在第一个实施例的电子部件封装结构1中,其厚度薄到大约150μm(最好为大约50μm)的半导体芯片20被倒装连接到第二布线图样32a,同时这样的芯片被埋入第二个夹层绝缘层34a中。之后,在半导体芯片20中形成了通路孔10b,之后,通过通路孔10b,元件形成表面上的连接垫10a被连接到后表面上的贯通电极16。覆盖半导体芯片20的第二个夹层绝缘层34a之中也形成了通路孔34y,之后,通过通路孔34y,形成了连接到贯通电极16的第三布线图样32b。
此外,每个具有类似结构的多个半导体芯片20可以在三维方向上被堆叠成一个多层结构,之后,这些半导体芯片20可以通过形成于这些芯片之中的贯通电极16以及形成于夹层绝缘层之中的通路孔相互连接到一起。
此外,叠加半导体芯片20a的凸起11被倒装焊接到第三布线图样32b的镍/金层42上。
当封装结构被这样构造时,不仅可以降低电子部件封装结构的总厚度,而且半导体芯片20的上下表面可以通过垂直方向上的线路相互连接到一起。这样,相较于半导体芯片通过导线连接的情况,或者在侧向上提供与布线路由相结合的线路的情况,布线长度可以被缩短。结果是,在高频应用中,半导体装置可以适应信号的更高速率。
(第二个实施例)
附图2A至2L是按照步骤的顺序显示的,示出了生产本发明的第二个实施例的电子部件封装结构的方法的侧视图。在上述的第一个实施例中,具有贯通电极16的第一个半导体芯片20被倒装在布线基片40上,之后形成第二个夹层绝缘层34a,之后,形成通路孔34y,以暴露贯通电极16。之后,通过第二个夹层绝缘层34a中的通路孔34y连接到位于半导体芯片20的后表面上面的贯通电极16的第三布线图样32b在第二个夹层绝缘层34a上形成。
用这种方法,在第一个实施例中,为了形成通过通路孔连接到半导体芯片20的连接垫10a上的第三布线图样32b,以上升到第二个夹层绝缘层34a上,首先,必须分别通过独立的步骤(需要两次形成通路孔的步骤(RIE步骤和激光步骤)),在半导体芯片20和第二个夹层绝缘层34a中形成通路孔10b、34y。此外,必须在半导体芯片20的通路孔10b中形成贯通电极16,并且,必须在后面的步骤中(需要两次电镀步骤),在第二个夹层绝缘层34a中的通路孔34y中形成第三布线图样32b。
在上述的RIE步骤(或者激光步骤)和电镀步骤中使用的生产设备相当昂贵。这样,如第一个实施例一样,如果RIE或者电镀步骤的工时增加,那么就需要沉重的设备投资,其结果是,可以预料到这种情况导致了生产投资的增加。此外,在一些情况下,这样的缺点会导致,由于生产工时增加了,因而指定的交付日期被延迟。
第二个实施例的生产电子部件封装结构的方法可以克服这样的缺点。
在本发明的第二个实施例的生产电子部件封装结构的方法中,首先,如附图2A所示,准备好用于生产组合布线基片(built-upwiring substrate)的底部基片30。底部基片30用绝缘材料制成,例如树脂或者类似材料。之后,在底部基片30中形成了通孔30a。连接到设置在底部基片30的两个表面上的第一布线图样32的通孔电镀层30b形成于通孔30a之中。树脂体30c被填充在通孔30a的孔中。
之后,用来覆盖第一个布线图样32的第一个夹层绝缘层34分别形成于底部基片30的两个表面上。如同第一个夹层绝缘层34,采用了例如环氧树脂、聚酰亚胺树脂、聚亚苯基醚树脂(polyphenyleneether resin)或者类似的材料。换言之,通过分别在位于底部基片30的两个表面上的第一布线图样32上面层压一个树脂膜,之后在80至140℃下进行退火处理,从而形成树脂层。
这样,树脂层作为第一个夹层绝缘层34,除了上述层压树脂膜的方法之外,还可以通过螺旋涂层(spin coating)方法,或者印刷方法而形成。除了树脂层外,还可以使用无机绝缘层,例如氧化硅层或者由CVD方法形成的类似的层。
之后,通过用激光分别蚀刻位于在底部基片30的两个表面侧上的第一布线图样32上面的第一个夹层绝缘层的预定部位,形成了第一通路孔34x。之后,例如通过半添加方法,第二布线图样32a被分别形成于位于底部基片30的两个表面侧上面的第一个夹层绝缘层34之上,每个第二布线图样32a都通过第一通路孔34x连接到第一布线图样上。
更具体来说,第一个晶粒铜层(未示出)通过非电解镀或者阴极空隙喷镀的方法形成于第一个通路孔34x和第一个夹层绝缘层34的内表面上。之后,具有对应于第二布线图样的开口部分的保护层(未示出)被形成于晶粒铜层上面。之后,通过使用晶粒铜层作为电镀电源层进行电镀,铜层图样(未示出)形成于保护层的开口部分之中,
之后,保护层被去除,之后,通过使用铜层图样作为掩模来蚀刻晶粒铜层,形成了第二布线图样32a。这样,还可以通过消去方法(subtractive method)或者全添加方法(full additive method),而不是半添加方法,来形成第二布线图样32a。
之后,如附图2B所示,准备好具有连接垫10a和连接到元件形成表面上的凸起的半导体芯片20。换言之,如同上述第一个实施例中的附图1A和1B,具有预定元件和连接垫10a、并且厚度大约为400μm的半导体晶片10的元件非形成表面(后表面)被打磨。这样,半导体晶片10的厚度被缩减到大约150μm或者更少,(最好是50μm或者更少)。之后,通过切割半导体晶片10获得了被分成单独的一片的半导体芯片20。半导体芯片20的凸起11在半导体晶片被切割之前或者之后形成。
这样,连接垫10a和凸起11是连接终端的一个例子。半导体晶片10也是作为电子部件的一个例子而被列出。但是,除了这些之外,还可以使用各种电子部件,比如电容器或者类似部件。
在第二个实施例中,通路孔不是在这时被形成于半导体芯片20中。如上所述,通路孔在半导体芯片20被安装之后形成。
之后,与附图2B中所示的类似,半导体芯片20的突起11被倒装焊接到第二布线图样32a上。之后,未充满的树脂18被填充到半导体芯片20与第二布线图样32a以及第一个夹层绝缘层34之间的空隙中。或者,在半导体芯片20被焊接之前,先把绝缘树脂(NCF或NCP)涂敷到包含半导体芯片20的被安装部分的区域之中,之后它们可以在该树脂的介入下被倒装焊接在一起。
之后,如附图2C所示,第二个夹层绝缘层34a被形成于半导体芯片20和第二布线图样32a之上。这样,半导体芯片20被埋入第二个夹层绝缘层34a。第二个夹层绝缘层34a是使用与上述第一个夹层绝缘层34同样的材料和方法而形成的。此时,第二个夹层绝缘层34a也被形成于位于底部基片30的没有安装半导体芯片20的表面上的第二布线图样32a之上。
之后,如附图2D所示,通过光蚀刻法(photolithography)形成保护层13,它具有开口部分13a,以暴露位于半导体芯片20的连接垫10a上面的第二个夹层绝缘层34a的预定部分。之后,采用保护层13作为掩膜,第二个夹层绝缘层34a和半导体芯片20通过RIE(活性离子腐蚀)被蚀刻。这样,就形成了通路孔36,它们每个深度都到达半导体芯片20的连接垫10a。
下面将详细描述本步骤的一个优选模式。首先,第二个夹层绝缘层(树脂层)34a在RIE条件下被蚀刻,其中使用氧(O2)作为蚀刻气体,压力设定为10到100Pa,阶段温度(stage temperature)被设定为从室温到大约100℃。之后,半导体芯片(硅芯片)20在RIE条件下被蚀刻,其中使用六氟化硫(SF6)作为蚀刻气体,压力设定为10到100Pa,阶段温度被设定为从室温到大约100℃。同时,蚀刻被由铝(Al)或者类似材料制成的连接垫10a终止。之后,去除保护层13。
在这个RIE步骤中,第二个夹层绝缘层34a和半导体芯片20可以分别在同一RIE装置的不同的室(chamber)中被蚀刻,或者它们可以在交换过蚀刻气体之后,在同一个室中被蚀刻。
在该步骤中,如附图2E所示,通路孔36可以通过激光形成,以代替上述的RIE。作为这种情况的一个优选模式,第二个夹层绝缘层(树脂层)34a和半导体芯片(硅芯片)20可以通过YAG激光在同样的条件下被连续蚀刻,其中YAG激光的振动波长为355nm,频率为1000到5000Hz。在这种情况下,通过激光进行的蚀刻也由连接板10a终止。
通过这种方法,在生产本实施例的电子部件封装结构的方法中,在第二个夹层绝缘层34a被形成于半导体芯片20上之后使用RIE或者激光,这样,通过连续蚀刻第二个夹层绝缘层34a和半导体芯片20形成了通路孔36。就是说,通过很简单的方法,通路孔36被同时形成于第二个夹层绝缘层34a和半导体芯片20中。
这样,在上述第一个实施例中,由于通路孔10b必须通过蚀刻被减薄且硬度很小的半导体晶片10而形成,如果考虑到在用RIE或者类似装置蚀刻被减薄的半导体晶片10中的处理等等,对于减少厚度就有一个限制。然而,在第二个实施例中,由于通路孔36的形成环境中,被减薄的半导体芯片20安装在硬度很大的布线基片40上,从半导体晶片10的厚度可以比第一个实施例减少的观点来看,第二个实施例更加便利。
之后,如附图2F所示,通过CVD或者类似方法,由氧化硅层或者类似物质构成的无机绝缘层38被形成于通路孔36的内表面和第二个夹层绝缘层34a的上表面。形成这种无机绝缘层38是为了将半导体芯片20与后面步骤中填充在通路孔36中的导体隔开。这样,由于无机绝缘层38也被作为夹层绝缘层,有时包含无机绝缘层38的第二个夹层绝缘层34a也被称为第二个夹层绝缘层34a(绝缘层)。
之后,如附图2G所示,在通路孔36的底部部分的无机绝缘层38被激光或者类似方法蚀刻并去除。这样,半导体芯片20的连接垫10a的一部分(在附图2G中由B表示的部分)从通路孔36的底部部分暴露出来。
之后,下面将会解释通过电镀形成第三布线图样的方法,其中第三布线图样通过通路孔36连接到半导体芯片20的连接垫10a。在本实施例中,如附图2H所示,第二布线图样32a连接到位于在形成第三布线图样之前的外部圆周部分之上的外部框架布线部分(outer-frame wiring portion)33,并且,用于提供电镀电流的电镀电源部分33x也被限定在外部框架布线部分33之内。开口部分34x通过蚀刻第二个夹层绝缘层34a和位于电镀电源部分33x之上的无机绝缘层38而形成。这样,电镀电源部分33x从开口部分34x的内侧暴露出来。
之后,电镀装置的阴极电极15通过电镀连接到外部框架布线部分33的电镀电源部分33x,之后,连接到外部框架布线装置33的第二布线图样32a起到电镀电源层的作用。就是说,电镀电流通过第二布线图样32a和连接到第二布线图样32a的半导体芯片20的凸起11供给半导体芯片20的连接垫10a。
附图2I描绘了通过从附图2H的顶部透视其结构的透视图。这样,附图2H相应于在附图2I中沿着I-I方向的侧视图和在附图2I中沿着II-II方向的侧视图的合成视图。在附图2I中,保护层19被省略而没有表示出来。
如附图2I所示,半导体芯片20的突起11被焊接到梳齿状的第二布线图样32a上。这些第二布线图样32a被连接到外部框架布线部分33,外部框架部分33设置在半导体芯片20的封装区域的外部周边部分上面。此外,开口部分34x被形成于限定在外部框架布线部分33内的电镀电源部分33x中,之后,电镀装置的阴极电极15连接到电镀电源部分33x。之后,如上所述,电镀电流从电镀电源部分33x,通过第二布线图样32a和凸起11,提供给从通路孔36的底部部分暴露出来的连接垫10a。
尽管没有在附图2I中明确示出,多个半导体芯片20被安装在多个安装区域中,并具有各自相似的结构,并且,在多个安装区域中的各个第二布线图样32a被连接到上述外部框架布线部分33。以这种方式,有可能同时向形成于多个安装区域之中的第二布线图样32a提供电镀电流。
为了将外部框架布线部分33中的电镀电源部分33x暴露出来,在上述形成通路孔36的步骤和从通路孔36的底部部分去除无机绝缘层38的步骤中,第二个夹层绝缘层34a和在电镀电源部分33x上面的无机绝缘层38可以在各自的步骤中同时被蚀刻。
之后,如附图2H所示,用来作为电镀掩膜的保护层19在无机绝缘层38上面被形成图样(is patterned)。保护层19形成了这样的图样,使得在外部框架布线部分33中的电镀电源部分33x被暴露出来,并且开口部分19a被形成于包含通路孔36的预定部位之中。
之后,通过对铜层使用电镀装置,使阴极电极15连接到在外部框架布线部分33中的电镀电源部分33x,之后使用保护层19作为掩膜开始对铜层进行电镀。
此时,如上所述,由于作为电镀电源层的第二布线图样32a通过半导体芯片20的突起11电气连接到连接垫10a,电镀电流被提供给半导体芯片20的连接垫10a。
因此,铜层(导电层)朝着从连接垫10a的上表面往上的部位顺序形成,其中连接垫10a是从通路孔36的底部部分中暴露出来的(从底部向上的系统)。也就是,在铜层(导电层)被填充在通路孔36中之后,铜层图样(导电层图样)被形成于保护层19的开口部分19a。之后,保护层19被去除。
这样,如附图2J所示,形成铜塞(Cu plug)31和第三布线图样32b,并且半导体芯片20的连接垫10a和第三布线图样32b通过通路孔36电气连接到一起。
用这种方法,由于铜层是通过使用从通路孔36的底部部分中暴露出来的连接垫10a作为电镀电源层,从通路孔36的底部部分开始向上顺序形成的,就避免了在通路孔36中生成空隙,从而,铜层被稳定地填充在通路孔36中。这样,即使通路孔36具有很高的长度直径比(aspect ratio),即直径大约为20μm或者更少,而深度大约为40μm或者更多,也可以避免生成空隙,这样,提高了连接垫10a和第三布线图样32b之间的电连接的可靠性。
在这种情况下,在形成第三布线图样32b的步骤中,可以使用在上面形成第二布线图样32a的步骤中解释过的半添加方法,或者消去方法,或者全添加方法。
之后,第二个通路孔34y被形成于没有安装半导体芯片20的底部基片30的表面侧上的第二个夹层绝缘层34a中。之后,形成第三布线图样32b,每个第三布线图样都通过第二通路孔34y连接到第二个布线图样32a。
之后,如附图2K所示,在底部基片30的两个表面侧都形成了焊接保护层21,它在位于第三布线图样32b的连接部分32x处具有开口部分21a,之后,镍/金层42通过使用焊接保护层21作为掩膜而进行的无电解镀,被形成于位于底部基片30的两个表面侧之上的第三布线图样32b的连接部分32x中。
之后,具有突起11的叠加半导体芯片20a的突起11被倒装焊接在位于第三布线图样32b上面的镍/金层42上。
之后,附图2K中的结构体(structural body)被分成预定区域,每个预定区域包括预定数目的半导体芯片20。此时,连接到上述第二布线图样32a的外部框架布线部分33被到去。这样,在其上形成了焊接保护层21的、附图2J中的结构体被分开之后,叠加半导体芯片20a可以被安装。
结果是,如附图2L所示,获得了本发明的第二个实施例的电子部件封装结构1a。在本实施例的电子部件封装结构1a中,LGA(搭接排板栅格阵列)结构类型被简化了。这样,焊接球被安装在位于安装基片(mounting substrate)(母板)上面的布线垫(wiringpads)上,之后,焊接球电气连接到位于电子部件封装结构1a的后表面侧上的第三布线图样32b上。否则,相反地,凸起可以被安装在电子部件封装结构1a的第三布线图样32b的连接部分32x上。
接下来,下面将举例说明第二个实施例的另一种模式。附图3是本发明的第二个实施例的电子部件封装结构的另一种模式的侧视图。在附图3中,与在附图2L中同样的附图标记被分配给同样的元件,并且此处省略了对它们的解释。
换言之,从上面在附图2B中安装半导体芯片20的步骤,到在附图2J中形成第三布线图样32b的步骤,其中的各个步骤可以在上述附图2J中的步骤之后(在形成了第三布线图样32b之后)被重复n次(n是为1或者更大的整数)。此外,在附图2L中,可以在未安装半导体芯片20的底部基片30的表面侧安装一片或者更多的半导体芯片20,以具有同样的结构。
附图3中显示了电子部件封装结构1b,作为上述另一个模式的例子。两个半导体芯片20安装在底部基片30的一个表面侧,处于这样一种状态:这两个半导体芯片分别埋入第二个、第三个夹层绝缘层34a、34b,并且其凸起11分别被倒装连接到第二、第三布线图样32a、32b。之后,两个半导体芯片20通过分别形成于这些半导体芯片以及第二个、第三个夹层绝缘层34a、34b之中的通路孔36相互连接到一起。之后,叠加半导体芯片20a的凸起11被倒装连接到第四布线图样32c上面的镍/金层42,作为最上层。
半导体芯片20也按照同样的结构安装在底部基片20的另一个表面侧。这样,安装在底部基片30的两个表面侧的多个半导体芯片20通过通路孔36和底部基片30上面的通路孔30a相互连接到一起。
用这种方法,可以使用这样的模式:多个半导体芯片20以多层的方式被安装在底部基片30的两个表面侧,而这些芯片被分别埋入夹层绝缘层,并且多个半导体芯片20也通过通路孔36等相互连接到一起。
如上所述,在本实施例的电子部件封装结构1a、1b中,夹层绝缘层或者布线图样可选地形成于底部基片30的两个表面上,并且半导体芯片20在它们被埋入预定的绝缘层的情况下,被倒装连接到预定的布线图样上。之后,通路孔36被形成于半导体芯片20和覆盖半导体芯片的夹层绝缘层的预定部分之中,其中每个通路孔36的深度都到达位于半导体芯片20的元件形成表面侧上面的连接垫10a。
通过通路孔36连接到半导体芯片20的连接垫10a上面的布线图样也被形成于覆盖半导体芯片20的夹层绝缘层上。由于通路孔36通过一个蚀刻步骤被连续形成于夹层绝缘层和半导体芯片20之中,它们的侧表面作为在不同的深度处保持连续的相同表面而形成。此外,叠加半导体芯片20a的凸起11被连接到最上面的布线图样。
这样,可以获得这样的模式:通过用上述方法以多层方式在三维方向上安装多个半导体芯片20,被分别埋入夹层绝缘层的多个半导体芯片20通过通路孔36相互连接到一起。
第二个实施例的电子部件封装结构可以达到与第一实施例同样的优点。
并且,在生产第二个实施例的电子部件封装结构1a、1b的方法中,通路孔36通过以RIE或者激光方法连续蚀刻第二个夹层绝缘层34a和半导体芯片20而形成。通过这样做,通路孔36可以仅通过步骤很少的非常简单的方法来形成。此外,通过通路孔36而连接到半导体芯片20的连接垫10a的第三布线图样32b可以通过一个电镀步骤形成,以建立上述的第二个夹层绝缘层。
这样,比起在第一个实施例中那样,即在半导体芯片20中形成贯通电极16之后才安装半导体芯片20的情况下,使用昂贵生产仪器的RIE步骤和电镀步骤的工时可以被缩减。结果是,诸如生产成本高、延迟指定交付日期等缺点可以被克服。
由于连接垫10a从通路孔36的底部部分暴露出来,并且在通过电镀在通路孔36中形成第三布线图样32b的过程中,连接垫10a被用作电镀电源层,因而避免了在通路孔36中形成空隙。其结果是,由于在半导体芯片20的连接垫10a和第三布线图样32b之间的连接的可靠性可以被提高,生产该电子部件封装结构的产量也可以提高。
Claims (15)
1.电子部件封装结构,包括:
包含预定布线图样的布线基片;
电子部件,其元件形成表面上的连接终端被倒装连接到布线图样上;
用来覆盖电子部件的绝缘层;
在电子部件的预定部位和位于连接终端上的绝缘层中形成的通路孔;
在绝缘层上形成、并通过通路孔连接到连接终端的叠加布线图样。
2.如权利要求1所述的电子部件封装结构,其中在电子部件和绝缘层中形成的通路孔的侧表面由连续的相同表面构成。
3.电子部件封装结构,包括:
包含预定布线图样的布线基片;
电子部件,其元件形成表面上的连接终端被倒装连接到布线图样上,以及具有通过在电子部件中形成的第一通路孔连接到连接终端的贯通电极的电子部件;
用来覆盖电子部件的绝缘层;
在贯通电极上的绝缘层的预定部位中形成的第二通路孔;
在绝缘层上形成的、并通过第二通路孔连接到贯通电极的叠加布线图样。
4.如权利要求1所述的电子部件封装结构,其中在电子部件中形成的通路孔的侧表面除了底部部分之外都由无机绝缘层所覆盖。
5.如权利要求1所述的电子部件封装结构,其中电子部件是厚度大约为150μm或者更少的半导体芯片。
6.如权利要求1所述的电子部件封装结构,其中与电子部件同样的结构体、绝缘层、以及在布线基片的布线图样上形成的叠加布线图样可以以多层方式在叠加布线图样上被重复n次(n是为1或者更大的整数),并且多个电子部件可以通过通路孔相互连接到一起。
7.如权利要求1所述的电子部件封装结构,其中叠加电子部件的连接终端被倒装连接到叠加布线图样。
8.生产电子部件封装结构的方法,包括以下步骤:
将在元件形成表面上具有连接终端的电子部件的连接终端倒装连接到在底部基片的上面或者上方形成的布线图样;
形成用来覆盖电子部件的绝缘层;
通过在预定部位处从绝缘层的上表面蚀刻到电子部件的元件形成表面,形成深度到达连接终端的通路孔;
在绝缘层上形成叠加布线图样,它通过通路孔连接到连接终端。
9.生产电子部件封装结构的方法,包括以下步骤:
将电子部件的连接终端倒装连接到在布线基片的上面或者上方形成的布线图样,该电子部件在元件形成表面上具有连接终端,并具有通过位于后表面上的第一通路孔连接到连接终端的贯通电极;
形成用来覆盖电子部件的绝缘层;
通过蚀刻位于贯通电极上的绝缘层的预定部位,形成深度到达贯通电极的第二通路孔;
在绝缘层上形成叠加布线图样,它通过第二通路孔连接到贯通电极。
10.如权利要求8所述的生产电子部件封装结构的方法,其中在形成通路孔的步骤中,绝缘层和电子部件通过RIE或者激光来进行蚀刻。
11.如权利要求8所述的生产电子部件封装结构的方法,其中形成叠加布线图样的步骤包括以下步骤:
在绝缘层上形成在包括通路孔的预定部位中具有开口部分的保护层;
通过使用布线图样和作为电镀电源层而连接到布线图样的电子部件的连接终端的电镀方法,应用从通路孔的底部部分暴露出来的连接终端向上的电镀,在通路孔和保护层的开口中形成导电层图样;
除去保护层,以获得叠加布线图样。
12.如权利要求8所述的生产电子部件封装结构的方法,在形成通路孔的步骤之后,但是在形成叠加布线图样的步骤之前,还包括以下步骤:
在通路孔的内表面和绝缘层上形成无机绝缘层;
从通路孔的底部部分去除无机绝缘层,以暴露通路孔的底部部分上面的连接终端。
13.如权利要求8所述的生产电子部件封装结构的方法,其中通过将从将电子部件倒装连接到布线图样的步骤到形成叠加布线图样的步骤,之间的各个步骤重复n次(n是为1或者更大的整数),形成了一种结构,在这种结构中,多个电子部件以一种多层方式在三维方向上被堆叠在一起,并通过通路孔相互连接到一起。
14.如权利要求8所述的生产电子部件封装结构的方法,在形成叠加布线图样的步骤之后,还包括下面的步骤:
将具有连接终端的叠加电子部件的连接终端倒装连接到叠加布线图样。
15.如权利要求8所述的生产电子部件封装结构的方法,其中电子部件是厚度大约为150μm或者更少的半导体芯片。
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Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104008980A (zh) * | 2013-02-22 | 2014-08-27 | 英飞凌科技股份有限公司 | 半导体器件 |
CN104124229A (zh) * | 2013-04-25 | 2014-10-29 | 英特尔公司 | 具有在嵌入式管芯上捕获导电部件的高密度互连设计的封装衬底 |
TWI460844B (zh) * | 2009-04-06 | 2014-11-11 | King Dragon Internat Inc | 具有內嵌式晶片及矽導通孔晶粒之堆疊封裝結構及其製造方法 |
CN104321866A (zh) * | 2012-09-14 | 2015-01-28 | 瑞萨电子株式会社 | 半导体器件的制造方法 |
Families Citing this family (46)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2005109187A (ja) * | 2003-09-30 | 2005-04-21 | Tdk Corp | フリップチップ実装回路基板およびその製造方法ならびに集積回路装置 |
JP4850392B2 (ja) * | 2004-02-17 | 2012-01-11 | 三洋電機株式会社 | 半導体装置の製造方法 |
JP2005277114A (ja) * | 2004-03-25 | 2005-10-06 | Sanyo Electric Co Ltd | 半導体装置 |
TWI309456B (en) * | 2004-04-27 | 2009-05-01 | Advanced Semiconductor Eng | Chip package structure and process for fabricating the same |
US20050258533A1 (en) * | 2004-05-21 | 2005-11-24 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device mounting structure |
JP4383257B2 (ja) * | 2004-05-31 | 2009-12-16 | 三洋電機株式会社 | 回路装置およびその製造方法 |
JP3961537B2 (ja) * | 2004-07-07 | 2007-08-22 | 日本電気株式会社 | 半導体搭載用配線基板の製造方法、及び半導体パッケージの製造方法 |
US7420282B2 (en) * | 2004-10-18 | 2008-09-02 | Sharp Kabushiki Kaisha | Connection structure for connecting semiconductor element and wiring board, and semiconductor device |
JP4443379B2 (ja) * | 2004-10-26 | 2010-03-31 | 三洋電機株式会社 | 半導体装置の製造方法 |
TWI303864B (en) | 2004-10-26 | 2008-12-01 | Sanyo Electric Co | Semiconductor device and method for making the same |
JP4873517B2 (ja) * | 2004-10-28 | 2012-02-08 | オンセミコンダクター・トレーディング・リミテッド | 半導体装置及びその製造方法 |
TWI256694B (en) * | 2004-11-19 | 2006-06-11 | Ind Tech Res Inst | Structure with embedded active components and manufacturing method thereof |
US20090008792A1 (en) * | 2004-11-19 | 2009-01-08 | Industrial Technology Research Institute | Three-dimensional chip-stack package and active component on a substrate |
US7208843B2 (en) * | 2005-02-01 | 2007-04-24 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Routing design to minimize electromigration damage to solder bumps |
US7253528B2 (en) | 2005-02-01 | 2007-08-07 | Avago Technologies General Ip Pte. Ltd. | Trace design to minimize electromigration damage to solder bumps |
JP2006253631A (ja) * | 2005-02-14 | 2006-09-21 | Fujitsu Ltd | 半導体装置及びその製造方法、キャパシタ構造体及びその製造方法 |
US7485967B2 (en) * | 2005-03-10 | 2009-02-03 | Sanyo Electric Co., Ltd. | Semiconductor device with via hole for electric connection |
TWI269419B (en) * | 2005-06-09 | 2006-12-21 | Advanced Semiconductor Eng | Method for forming wafer-level heat spreader structure and packaging structure thereof |
JP4507101B2 (ja) * | 2005-06-30 | 2010-07-21 | エルピーダメモリ株式会社 | 半導体記憶装置及びその製造方法 |
JP4841234B2 (ja) * | 2005-11-24 | 2011-12-21 | 日本特殊陶業株式会社 | ビアアレイキャパシタ内蔵配線基板の製造方法 |
US20070126085A1 (en) * | 2005-12-02 | 2007-06-07 | Nec Electronics Corporation | Semiconductor device and method of manufacturing the same |
US7906850B2 (en) * | 2005-12-20 | 2011-03-15 | Unimicron Technology Corp. | Structure of circuit board and method for fabricating same |
US7638867B2 (en) * | 2006-06-02 | 2009-12-29 | Intel Corporation | Microelectronic package having solder-filled through-vias |
KR100818088B1 (ko) * | 2006-06-29 | 2008-03-31 | 주식회사 하이닉스반도체 | 반도체 패키지 및 그 제조 방법 |
JP4773307B2 (ja) * | 2006-09-15 | 2011-09-14 | Okiセミコンダクタ株式会社 | 半導体装置の製造方法 |
US7781311B2 (en) * | 2006-12-20 | 2010-08-24 | Texas Instruments Incorporated | System and method for filling vias |
US7662665B2 (en) * | 2007-01-22 | 2010-02-16 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for fabricating a semiconductor package including stress relieving layer for flip chip packaging |
US20080246152A1 (en) * | 2007-04-04 | 2008-10-09 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device with bonding pad |
JP2008294367A (ja) * | 2007-05-28 | 2008-12-04 | Nec Electronics Corp | 半導体装置およびその製造方法 |
WO2009031285A1 (ja) | 2007-09-03 | 2009-03-12 | Panasonic Corporation | 慣性力センサ |
US8441804B2 (en) | 2008-07-25 | 2013-05-14 | Infineon Technologies Ag | Semiconductor device and method of manufacturing a semiconductor device |
US20100155931A1 (en) * | 2008-12-22 | 2010-06-24 | Qualcomm Incorporated | Embedded Through Silicon Stack 3-D Die In A Package Substrate |
US8274139B2 (en) | 2009-07-21 | 2012-09-25 | Stmicroelectronics (Crolles 2) Sas | Scalloped tubular electric via |
EP2278613B1 (fr) * | 2009-07-21 | 2013-06-05 | STMicroelectronics (Crolles 2) SAS | Via de connexion électrique tubulaire constitué de plusieurs vias conducteurs élémentaires |
JP2011061004A (ja) * | 2009-09-10 | 2011-03-24 | Elpida Memory Inc | 半導体装置及びその製造方法 |
US8618629B2 (en) * | 2009-10-08 | 2013-12-31 | Qualcomm Incorporated | Apparatus and method for through silicon via impedance matching |
JP5715334B2 (ja) * | 2009-10-15 | 2015-05-07 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US8618654B2 (en) | 2010-07-20 | 2013-12-31 | Marvell World Trade Ltd. | Structures embedded within core material and methods of manufacturing thereof |
JP2012231096A (ja) * | 2011-04-27 | 2012-11-22 | Elpida Memory Inc | 半導体装置及びその製造方法 |
US20120292777A1 (en) * | 2011-05-18 | 2012-11-22 | Lotz Jonathan P | Backside Power Delivery Using Die Stacking |
US8872349B2 (en) * | 2012-09-11 | 2014-10-28 | Intel Corporation | Bridge interconnect with air gap in package assembly |
DE102012108522A1 (de) * | 2012-09-12 | 2014-03-13 | Ams Ag | Verfahren zur Herstellung eines Halbleiterstapels und Halbleiterstapel mit rückseitigem Durchkontakt |
US9721920B2 (en) * | 2012-10-19 | 2017-08-01 | Infineon Technologies Ag | Embedded chip packages and methods for manufacturing an embedded chip package |
US9397071B2 (en) * | 2013-12-11 | 2016-07-19 | Intel Corporation | High density interconnection of microelectronic devices |
US9741649B2 (en) * | 2014-06-04 | 2017-08-22 | Invensas Corporation | Integrated interposer solutions for 2D and 3D IC packaging |
US10325855B2 (en) * | 2016-03-18 | 2019-06-18 | Qualcomm Incorporated | Backside drill embedded die substrate |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61150250A (ja) * | 1984-12-24 | 1986-07-08 | Hitachi Ltd | 半導体装置 |
JP2658661B2 (ja) * | 1991-09-18 | 1997-09-30 | 日本電気株式会社 | 多層印刷配線板の製造方法 |
JPH09321175A (ja) * | 1996-05-30 | 1997-12-12 | Oki Electric Ind Co Ltd | マイクロ波回路及びチップ |
JP3184493B2 (ja) * | 1997-10-01 | 2001-07-09 | 松下電子工業株式会社 | 電子装置の製造方法 |
JP2000323645A (ja) | 1999-05-11 | 2000-11-24 | Shinko Electric Ind Co Ltd | 半導体装置及びその製造方法 |
JP3670917B2 (ja) * | 1999-12-16 | 2005-07-13 | 新光電気工業株式会社 | 半導体装置及びその製造方法 |
JP4251421B2 (ja) | 2000-01-13 | 2009-04-08 | 新光電気工業株式会社 | 半導体装置の製造方法 |
US6444576B1 (en) * | 2000-06-16 | 2002-09-03 | Chartered Semiconductor Manufacturing, Ltd. | Three dimensional IC package module |
JP3951091B2 (ja) * | 2000-08-04 | 2007-08-01 | セイコーエプソン株式会社 | 半導体装置の製造方法 |
JP4570809B2 (ja) * | 2000-09-04 | 2010-10-27 | 富士通セミコンダクター株式会社 | 積層型半導体装置及びその製造方法 |
JP2002270718A (ja) * | 2001-03-07 | 2002-09-20 | Seiko Epson Corp | 配線基板及びその製造方法、半導体装置及びその製造方法、回路基板並びに電子機器 |
JP2002305282A (ja) | 2001-04-06 | 2002-10-18 | Shinko Electric Ind Co Ltd | 半導体素子とその接続構造及び半導体素子を積層した半導体装置 |
-
2002
- 2002-12-03 JP JP2002351526A patent/JP2004186422A/ja active Pending
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2003
- 2003-11-25 KR KR1020030084008A patent/KR20040048816A/ko not_active Application Discontinuation
- 2003-11-25 US US10/720,514 patent/US6943442B2/en not_active Expired - Lifetime
- 2003-11-27 TW TW092133375A patent/TW200415776A/zh unknown
- 2003-12-02 CN CNA200310118745A patent/CN1505147A/zh active Pending
- 2003-12-03 EP EP03257626A patent/EP1427006B1/en not_active Expired - Fee Related
- 2003-12-03 DE DE60324755T patent/DE60324755D1/de not_active Expired - Lifetime
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2004
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Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI460844B (zh) * | 2009-04-06 | 2014-11-11 | King Dragon Internat Inc | 具有內嵌式晶片及矽導通孔晶粒之堆疊封裝結構及其製造方法 |
CN104321866A (zh) * | 2012-09-14 | 2015-01-28 | 瑞萨电子株式会社 | 半导体器件的制造方法 |
CN104321866B (zh) * | 2012-09-14 | 2018-03-02 | 瑞萨电子株式会社 | 半导体器件的制造方法 |
CN104008980A (zh) * | 2013-02-22 | 2014-08-27 | 英飞凌科技股份有限公司 | 半导体器件 |
CN104124229A (zh) * | 2013-04-25 | 2014-10-29 | 英特尔公司 | 具有在嵌入式管芯上捕获导电部件的高密度互连设计的封装衬底 |
CN104124229B (zh) * | 2013-04-25 | 2017-07-28 | 英特尔公司 | 具有在嵌入式管芯上捕获导电部件的高密度互连设计的封装衬底 |
Also Published As
Publication number | Publication date |
---|---|
EP1427006B1 (en) | 2008-11-19 |
KR20040048816A (ko) | 2004-06-10 |
EP1427006A1 (en) | 2004-06-09 |
US6943442B2 (en) | 2005-09-13 |
US20040209399A1 (en) | 2004-10-21 |
DE60324755D1 (de) | 2009-01-02 |
US7084009B2 (en) | 2006-08-01 |
TW200415776A (en) | 2004-08-16 |
JP2004186422A (ja) | 2004-07-02 |
US20040113261A1 (en) | 2004-06-17 |
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