TW200415776A - Electronic parts packaging structure and method of manufacturing the same - Google Patents

Electronic parts packaging structure and method of manufacturing the same Download PDF

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Publication number
TW200415776A
TW200415776A TW092133375A TW92133375A TW200415776A TW 200415776 A TW200415776 A TW 200415776A TW 092133375 A TW092133375 A TW 092133375A TW 92133375 A TW92133375 A TW 92133375A TW 200415776 A TW200415776 A TW 200415776A
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TW
Taiwan
Prior art keywords
wiring pattern
insulating film
electronic component
hole
holes
Prior art date
Application number
TW092133375A
Other languages
English (en)
Inventor
Masahiro Sunohara
Kei Murayama
Naohiro Mashino
Mitsutoshi Higashi
Original Assignee
Shinko Electric Ind Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Ind Co filed Critical Shinko Electric Ind Co
Publication of TW200415776A publication Critical patent/TW200415776A/zh

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H05K1/186—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or connecting to patterned circuits before or during embedding
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
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    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
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Description

玖、發明說明: 【鸯^明所屬老L術^領域^ 發明領域 本發明係有關於一種電子部件封裝結構與其製造方法 且，特別地’本發明係有關於一種電子部件封裝結構，其 結構係可使多數電子部件在它們被埋在一絕緣膜中之情形 下互相連接及其製造方法。 先前技術之說明 成為實現多媒體裝置之關鍵技術之LSI技術的發展穩 定地進展為更高速與更大量之資料傳輸，因此，一作為在 該LSI與電子裝置間之介面之更高密度之封裝技術亦正在 發展中。 為了達成更高密度之要求，目前已發展出其中多數半 V體晶片係被立體地積層在該基板上並被封裝的多晶片封 裝（半導體裝置）。舉例而言，該半導體裝置之結構係多數半 V體晶片立體地安裝在該配線基板上且它們分別地被埋在 該絕緣膜中，並且多數半導體晶片透過形成在該絕緣膜與 該等配線圖案中之通孔來互相連接。例如，這種半導體裝 置係揭露在日本專利申請案（kokai)2〇〇M96525(專利文 獻U，曰本專利申請案(KOKAI)2001-177045(專利文獻2)及 曰本專利申請案(K〇KAI)2〇〇〇-323645(專利文獻3)。 近年來，為了對應較高密度之封裝，在目前所研究之 結構中係封裝有多數半導體晶片，且它們係被埋入絕緣膜 盘2仔該料導體晶片透過多數形成在該等半導體晶片 =緣财之魏叫目賴。前述财糊文獻1至 3均與夕數半導體晶片透過形成在該絕緣財之通孔而互 相連接的結構有關，但目前並未對前述封震結構加以考慮。 【^明内】 發明概要 本發明之目的是提供一種電子部件封裝結構其具有 多數電子部倾人-絕_且多數電子部件係透過多數形 成在該等電子部件與該等絕緣财之通孔而互相連接，且 使該結構可轉由-簡單之綠來製造，及純造方法。 本發明係有關於-種電子部件封震結構，其包含一配 線基板，包括-配線圖案；—電子部件連接端子，係在_ 70件形成表面上且以條晶片接合法與該配線圖案連接； ς絕緣膜’用以覆蓋多數電子部件；―通孔，係形成在該 電子部件之—預定部份中與在該連接端子上之絕緣膜 中；及-重疊配線圖案，係形成在該絕緣膜上且透過該通 孔與該連接端子連接。 在本發明之電子部件封袭結構中，首先，該等電子部 件(半導體晶片等）之連接端子係以倒裝晶片接合法連接在 該配線基板上之崎_案，接著形姻⑽蓋鱗電子部 件之絕緣膜。然後，暴露出該連接端子之各通孔係藉由利 用赃或f射來連續_該等電子部件與在該等連接端子 上之’、G緣膜的駄部份㈣成。再將透過形成在該等電子 部件與該絕緣膜上之與該等連接端子連接的重 疊配線圖案 200415776 形成在該絕緣膜上。 依此方式，在本發明之電子部件封裝結構中，例如該 等通孔係以一次蝕刻步驟連續地形成在該絕緣膜與該等電 子部件中，此外，透過該等通孔連接至該等連接端子並延 5伸至该絕緣膜上的重疊配線圖案係藉由一次電鍍步驟來形 成。即，由於本發明之電子部件封裝結構係由非常簡單之 製造方法製成，故其製造成本可降低且亦可避免延遲預定 之交貨時間。 10 15 20 在本發明之-較佳實施例中，係使用其厚度減少至大 =等於或小於150叫之半導體晶片作為該等電子部件，同 時，形成在該S&絲板之配線圖案±的與該料子部件相 同'、構本體、該纟ε緣膜與該重疊配線圖案可以—多層之 方式在該重疊配線圖案上重覆歧仏是大於或等於i之整 數）’且多數電子部件可以透過該等通孔互相連接。
Ml❿卜…W計部件之總厚度可ΰ 少’故這種封裝結構可因應一較高密度。此外，由於」 下電子部件係透過在垂直方向上之配線來互相連接1 導體晶片通過電線連接或藉由在橫向上配置配詞 達成配線目的之情形，該s始+ — 配線之長度可以縮短。因此， 命頻應用中之半導财置可以因應較高之訊號速度。 =發明係有關於—種製造1子部件封裝結福 =件步驟:，晶片接合法連接- 與-形成在-基底基板上或二電子部件的連翻 飞上方的配線圖案；形成一用 7 200415776 該=寺電子部件之絕緣膜’·利用由該絕緣膜之上表面至 且子卩件之元件形成表祕刻-預定部份，以形成一 達該連接端子之深度之通孔，·及在制緣膜上形成 端子=線圖案’該重疊配線圖案係透過該通孔與該連接 如上所述，本發明之電子部件封裝結構可以藉由使用 發月之電子部件封裳結構之製造方法而非常簡單地製 造° 在本發明之一較佳實施例中，形成該重疊配線圖案之 乂騾包括·在包含在該絕緣膜上之通孔之預定部份中形成 一具有一開口部份之抗蝕膜；以由該通孔之底部暴露出來 之連接端子向上利用電鍍法鍍上一電鍍層之方式在該通孔 與该抗蝕膜之開口部份中形成一導電膜圖案，且該電鍍法 係利用該配線圖案及與該配線圖案連接之電子部件之連接 I5端子作為一電鍍電源層；及去除該抗蝕膜以得到該重疊配 線圖案。 依此方式，在於該專通孔與該抗钱膜之開口部份中形 成導電膜圖案的步驟中，該等導電膜圖案係利用從由該等 通孔之底部暴露出來之連接端子向上依序電鑛一鐘層來形 2〇成，因此，該等導電膜圖案可被填滿且成形並且不會在該 專通孔中產生空洞。因此’由於可增加在該等電子部件之 連接端子與該等重疊配線圖案之間透過該等通孔連接之可 靠性，所以可提高該電子部件封裝結構之產率。 圖式簡單說明 第1A至1K圖是顯示本發明之第一實施例之電子部 封裝結構之製造方法的截面圖； 第2A至2L圖是顯示本發明之第二實施例之電子 封裝結構之製造方法的截面圖，其中第糊是顯示由第扭 圖之頂側看透之透視平面圖；及 第3圖是顯示本發明之第二實施例之電子部件封裝結 構之另一型態的截面圖。 【實施方式】 較隹實施例之詳細說明 以下將配合附圖說明本發明之實施例。 (第一實施例） 第1A至1K圖係依序顯示本發明之第一實施例之電子 部件封裝結構之製造方法的截面圖，在本發明之第一實施 例之電子部件封裝結構之製造方法中，如第1A圖所示，首 先製備多數預定元件、多層配線等（圖未示)形成於其上之半 導體晶圓10,由A1等製成之連接墊10a係形成在該半導體晶 圓10之元件形成表面上並暴露出來。接著，如第四圖所示， 藉由研磨該半導體晶圓10之元件非形成表面(背面），將該半 導體晶圓10之厚度減少至大約等於或小於l5Qpm。 其次，如第1C圖所示，將一在對應連接墊1〇a之預定部 份處具有多數開口部份12a的抗蝕膜12形成在該半導體晶 圓10之背面上。然後，利用RIE(反應性離子蝕刻）且使用該 抗蝕膜12作為一遮罩，由該背面側蝕刻出該半導體晶圓 10。如此可形成多數通孔l〇b，各通孔1〇b具有一通達在該 半導體晶圓10之元件形成表面側之連接墊1〇a。 接著，如第1D圖所示，移除該抗蝕膜12。然後，藉由 CVD等，將一由氧化矽膜等製成之無機絕緣膜抖形成在該 等通孔10b之内表面上與該半導體晶圓1〇之背面上。再藉由 雷射等由該等通孔10b之底部去除該無機絕緣膜14，如1， 該連接墊10a(第1D圖中之A所示之部份)係由該等通孔1〇b 之底部暴露出來。該無機絕緣膜14係形成為可使填充在該 等通孔10b中之導體與該半導體晶圓10隔離。 又，如第1E圖所示，藉由無電極電鍍或濺鍍法，將一 晶種Cxi膜（圖未示）形成在該等通孔1〇b之内表面與該半導 體晶圓10之背面上。接著，將在含有該等通孔1〇b之預定部 份處具有該等開口部份12 a之抗蝕膜12形在該晶種以膜 上，然後’猎由使用該晶種Cu膜作為該電鍍電源層之電鍍 法，將晶種Cu膜16a形成在該通孔lob與該抗钮膜12之開口 部份12a中。 接著，如第1F圖所示，將該抗蝕膜12移除。再藉由蝕 刻該晶種Cu膜並使用該晶種Cu膜作為一遮罩，形成多數透 過通孔10b與該等連接墊l〇a連接之穿過電極16。如第1(}圖 所示，一被分割成一單獨構件之半導體晶片2〇係藉由切割 該半導體晶圓10而獲得，然後，在切割該半導體晶圓1〇之 前或之後形成多數與該半導體晶片20之連接墊1〇a連接的 凸塊11。該連接墊10a與該凸塊11係該等連接端子之一例， 在這種情形下，除了該半導體晶片2〇以外，亦可使用如電 容器部件等各種電子部件。 接著，如第m圖所示，製備-可供該半導體晶片2〇安 裝於其上之配線基板40，在這配線基板4〇中，多數穿孔3如 係設置在由樹脂製成之基底基板3〇中，然後，將與該基底 基板3〇之第-配關案32賴之穿孔電鍍層分獅成二該 等穿孔30a之内表面上，並且再以一樹脂本體3〇c填充該等 穿孔。 同時，-其中具有多數通孔34χ之第_層間絕緣膜％ 係形成在該等第-赠圖案32上，_，各透過該等通孔 34χ與該第-配線圖案32連接之第二配線圖案仏係形成在 該第一脣間絕緣膜34上。 接著，如第il圖所示，該半導體晶片2〇之凸塊U係以 倒裝晶片接合法接合至該喊基板做第二配線圖案32a 上’再將底層填充樹脂18填入該半導體晶片2〇、該第二配 線圖案32a與該第一層間絕緣膜34之間的間隙之間。 然後，形成-用以覆蓋該半導體晶片2()之第二層間絕 緣膜34a，接著以雷射等兹刻第二層間絕緣膜*在該半導 體晶片2G之穿過電極16上之預定部份上，藉此形成各具有 -通該穿過電極16之上表面之深度的第二通孔外。 接著，如第1J圖所示，藉由與用以形成在該半導體晶 圓10中之穿過電極16之方法(半添加法等)相同的方法，形成 透過該㈣二軌3々與料f過電極16連接的第三配線 圖案32b。 一 在這種情形下晶片接合法將前述半導體晶 片20接合在該等第二配線圖案似上之步驟至形成該第彡 200415776 配線圖案32b之步驟之各步驟可以重覆預定次數。在此情形 下，多數半導體晶片20分別被埋設在層間絕緣膜中且以立 體之方式被封裝，且多數半導體晶片20係透過形成在該等 半導體晶片20與該等層間絕緣膜中之通孔互相連接。 5 然後，如第1K圖所示，形成一在該第三配線圖案32b 之連接部份處具有多數開口部份的焊料抗蝕膜21，接著， 藉由電鍍程序將一见/入11膜42形成在該第三配線圖案32b之 連接部份中。 接著’具有該等凸塊11之疊置半導體晶片20a之凸塊η ίο係以倒裝晶片接合法接合至在該第三配線圖案32b上之
Ni/Au膜42 ’藉此結構，可得到此實施例之電子部件封裝結 構卜 在第一實施例之電子部件封裝結構丨中，其厚度減少至 大約15〇μιη(以大約刈卜㈤較佳)之半導體晶片2〇係以倒裝晶 15 1接合法連接至該等第二配線圖案32a且這晶片被埋入該 第1間絕緣膜34a中。接著，將該等通孔勘形成在該半 導體曰曰片20中’且在該元件形成表面上之連接墊收透過該 等通孔i〇b連接在该背面上之穿過電極16。同時，該等第二 通孔34y係形成在覆蓋該半導體晶片之第二層間絕緣膜 4a中並且形成與該等穿過電極16連接之第三配線圖案 32b 〇 田此外，各具有類似結構之多數半導體晶片可立體地層 且f夕層結構’且這些半導體晶片2〇可再透過形成在這 -曰曰片中之牙過電極16_成在該層間絕緣膜中之通孔互 12 200415776 相連接。 又’該豐置半導體晶片20a之凸塊11係以倒裝晶片接合 法接合至在該第三配線圖案32b上之Ni/Au膜42。 §該封裝結構如此構成時，不僅該電子部件封裝結構 5之總厚度可以減少，而且該等上與下半導體晶片20透過在 垂直方向没置之配線互相連接。因此，該配線之長度可以 縮短而不是該等半導體晶片透過電線連接或者設置有連接 在橫向方向上配置之配線連接之配線。因此，在高頻應用 中之半導體裝置可以因應較高速之訊號速度。 10 (第二實施例) 苐2A至2L圖係依序顯示本發明之第二實施例之電子 部件封裝結構之製造方法的截面圖，在前述實施例中，首 先，將具有該等穿過電極16之半導體晶片2〇以倒裝晶片接 合法安裝在該配線基板40上，再形成該第二層間絕緣膜3如 15並且形成該等通孔34丫以暴露該等穿過電極16。然後，將透 過在該第二層間絕緣膜34a中之通孔34y與在該半導體晶片 20連接之背©上之穿過電極16之第三配線圖案奶形成在 該第二層間絕緣膜34a上。 依此方式’在第-實施例中，為了形成透過該等通孔 20與該半導體晶片20之連接塾1Ga連接以便在該第二層間絕 緣膜34a上升起之第三配線圖案细，該等通孔勘、叫必 須先分別藉由不同之步驟(形成該等通孔之步驟必須有兩 個步驟(該步驟與該雷射步驟))形成在該半導體晶片加 與該第二層間絕緣膜34a中。此外，在猶後之步驛中（該電 13 鍍步驟必财兩個步驟），該等穿過電祕必紗成在該半 導體晶片20之通孔10b中並且該第三配線圖案你必須形成 在該第二層間絕緣膜34a中。 在前述RIE步驟（或雷射步驟）中使用之製造設備與電 鑛步驟是昂貴的，因此，如果該RIE或該電鑛之工時如第_ 實施例般增加，财要大量的設備資本並且因此會增加製 造成本。此外，在某些情形下，由於製造工時增加，會產 生預定交貨曰期延期的缺點。 第二實施例之電子部件縣結構之製造方法可克服這 種缺點。 在本發明之第二實施例之電子部件封裝結構之製造方 法中，首先，如第2A圖所示，製備用來製造一内建配線基 板的基底基板30 ’該基底基板3〇係由如樹脂等絕緣材料製 成。接著，將該等穿孔3〇a設置在該基底基板30中，且將與 设置於該基底基板30之兩表面上之第一配線圖案32連接之 該穿孔電鍍層30b形成在該等穿孔3如中，並將該樹脂本體 30c填充在該等穿孔30a之孔中。 然後，將用以覆蓋該第一配線圖案32之第一層間絕緣 膜34分別形成在該基底基板30之兩表面上。該第一層間絕 緣膜34可使用，例如，環氧樹脂、聚醯亞胺樹脂、聚苯醚 等。換言之，該樹脂層係藉由分別積層一在該第一配線圖 案32上之抗姓膜於該基底基板30之兩表面上而形成並且再 進行退火處理使它硬化。 在這種情形下，除了前述積層該樹脂膜之方法以外’ 200415776 作為该第一層間絕緣膜34之抗蝕膜亦可以藉由旋塗法或印 刷法形成，同時，亦可使用由CVD法形成之如氧化矽膜等 及樹脂膜之無機絕緣膜。 接著，藉由分別以雷射蝕刻在該等第一配線圖案32上 5之第-層間絕緣膜Μ之預定部份而在該基底基板3〇之兩表 面上形成該第一通孔34x，然後，各透過通孔34\與該第一 配線圖案32連接之第二配線圖案仏係分別藉由，例如，半 、加法形成在该基底基板3〇之兩表面側之第一層間絕緣膜 34上。 1〇 詳而言之，該晶種Cu膜（圖未示）係先藉由電錢或濺鍍 法形成在該㈣-通孔34x^_面上與該第—層間絕緣 膜34上，接著，具有對應於該第二配線圖案之開口部份的 抗餘膜（圖未示)形成在.該晶種Cu膜上，而&膜圖案（圖未示） 則稭由使⑽晶齡順作為魏電源層之賊法形成在該 15 抗蝕膜之開口部份中。 然後，移除該抗朗，且再藉由_該晶種Cu膜且使 用”亥等Cu膜圖案作為_遮罩來形成該第二配線圖案仏。在 這種情形下，該第二配線圖案32a可以藉由削除法或全添加 法取代該半添加法來形成。換言之，與在前述第—實施例 2G中之第1A圖與第1B圖類似地研磨元件非形成表面（背面）， 且該元件非形成表面（背面）具有預定元件與該等連接墊l〇a 之半$體曰曰圓10並且具有大约4〇〇叫之厚度，如此，該半 導體晶圓10之可減少至大約等於或小於，m(以等於或小 於50μιη為佳）。接著’藉由蝴該半導體晶圓…可獲得被分 15 200415776 割成一單獨構件之半導體晶片20，且在切割該半導體晶圓 10之前或之後，該半導體晶片20之凸塊11。 在這種情形下，該連接墊l〇a與該凸塊11係該等連接端 子之一例，同時’該半導體晶圓10亦係該等電子部件封装 5 結構之一例。但除此以外’亦可使用各種如電容器部件之 電子部件。 在該第二實施例中，此時該等通孔已形成在該半導體 晶片20中，如前所述，該等通孔係在安裝該半導體晶片2〇 之後形成。 10 接著，類似於如第2B圖所示，該半導體晶片20之凸塊 11係以倒裝晶片接合法接合至該第二配線圖案32a，然後， 將底層填充樹脂18填入该半導體晶片2〇、該第二配線圖案 32a與該第一層間絕緣膜34之間的間隙。或者，可在接合該 半導體晶片20之前，將一絕緣膜(NCF或ncp)預先塗布在該 15半導體晶片20上，再藉插入這樹脂以倒裝晶片接合法接合 它們。 然後，如第2C圖所示，該第二層間絕緣膜34a係形成在 該半導體晶片20與該第二配線圖案32&上，如此，可將該半 導體晶片20埋入該第二層間絕緣膜3如中，且藉由與前述第 20 一層間絕緣膜34之相同材料與方法可形成該第二層間絕緣 膜 34a。 接著，如第2D圖所示，藉由微影成像法在該半導體晶 片20之連接塾l〇a上形成-抗钱膜13，且該抗钱膜13具有多 數可暴露該第二層間絕緣膜34a之預定部份。然後，以 16 200415776 RIE(反應性離子蝕刻）蝕刻該第二層間絕緣膜3如與該半導 體晶片20並且使用該抗蝕膜13作為一遮罩。如此，可形成 多數通孔36，且各通孔36具有一通達該半導體晶片2〇之連 接墊10a之深度。 5 以下將詳細說明這步驟之一較佳型態。首先，該第二 層間絕緣膜(抗蝕膜)34a係在使用氧(〇2)作為蝕刻氣體、壓 力為10至lOOPa且階段溫度為室溫至削艺之幻^條件下進 行蝕刻。接著，該半導體晶片（矽晶片)2〇係在使甩六氟化硫 (SF6)作為一蝕刻氣體、壓力為1〇至1〇〇Pa且階段溫度為室溫 10至lOOt之RIE條件下進行蝕刻。此時，該蝕刻程序係由以 A1等製成之連接墊l〇a來停止。接著移除該抗蚀膜13。 在這RIE步驟中，該第二層間絕緣膜34a與該半導體晶 片20可以在具有相同RIE設備之不同室中分別進行鍅刻，或 者它們可以在更換蝕刻氣體後在相同之室中蝕刻。 I5 在這步驟中，如第2E圖所示，該等通孔36可由雷射而 不疋别述化见來形成’在這種情形之一較佳型態中，該第二 層間絕緣膜(抗蝕膜)34a與該半導體晶片（石夕晶片）2〇可以在 相同之條件下以振盪波長為355nm且頻率為1〇〇〇至5000Hz 之YAG雷射連續地蝕刻。此時，由該雷射進行之蝕刻亦藉 20 由該連接墊l〇a來停止。 依此方式，在此實施例之電子部件封裝結構之製造方 法中’係在該弟一層間絕緣膜34a形成在該半導體晶片2〇後 使用該RIE或使用該雷射，使得該等通孔36可藉由連續地餘 刻該第二層間絕緣膜34a與該半導體晶片20而形成。即，該 17 200415776 等通孔36係利用非常簡單之方法而同時形成在該第二層間 絕緣膜34a與該半導體晶片2〇中。 此時’在雨述第-實施例中，由於該等通孔觸必須藉 由敍刻變薄且具有小剛性之半導體晶圓1〇來形成，因此^ 5 1職備等姓刻該變薄之半導體晶圓1〇考慮到處理程序 等’則厚度之減少有一極限M旦是，在第二實施例中，由 於該等通孔36係在該變薄之半導體晶片20安裝在具有大剛 性之配線基板4〇的情形下形成，因此由該半導體晶圓10之 厚度可以與該第-實施例不同地減少的觀點來看，該第二 10 實施例較為方便。 15 20 接著，如第2F圖所示，—由氧化石夕膜等製成之無機絕 緣膜38储由CVD#形成㈣等軌批絲面上與該第 -層間緣膜34a之上表面上。這無機絕_38係形成為可 使該半導體晶片20與-在稍後之步驟中填充於該等通孔36 中之導體絕緣。此時’由於該無機絕緣膜％亦留下作為層 門、巴緣膜有時含有無機絕緣膜38之第二層間絕緣膜地亦 被稱為第二層間絕緣膜34a(絕緣膜）。 、然後’如S2G1I所;^，藉由雷射等蝴並移除在該等 、 之底α卩上之無機絕緣膜％。如此，該半導體晶片2〇 之連接墊IGa之-部份(在第2G圖中以β表示之部份)可由該 等通孔36之底部暴露出來。 /下將說明如電娜成料第三配顧案之方法， 且該第三配線_係透過該等通孔36與該半導體晶片20之 連接墊IGa連接。在此實施例中，如第所示，該等第二 18 200415776 配線圖_a係在形成該等第三配_案之前，與設置在該 外周緣部份上之外框配線部份33連接，並且用以供應電鑛 電流之電鑛電源部份33x係形成在該外框配線部份财。該 等開孔部份34x係藉由在該等電觀源部份33χ絲刻該第 5二層間絕緣膜34a與該無機絕緣膜38而形成，如此，該電鍍 電源部份33x可由該等開口部份34χ之内侧暴露出來。 接著，該電鍍設備之陰極15係在進行電鍍時與該外框 配線部份33之電鍍電源部份33χ連接，且與該外框配線部份 33連接之第二配線圖案32a係作為該電鍍電源層。即，一電 1 〇 鑛電係經由5亥弟一配線圖案32a及該半導體晶片2〇之凸 塊11供應至該半導體晶片20之連接墊i〇a，且該半導體晶片 20之凸塊11與該第二配線圖案32a連接。 由第2H圖之頂側看穿這結構之透視圖係顯示在第21圖 中’此時’第2H圖對應於一沿著第21圖之線14所截取之截 15面圖與一沿著第21圖之線IMI所截取之截面圖的合成圖。同 時，在第21圖中，省略了抗蝕膜19。 如第21圖所示，該半導體晶片20之凸塊11係接合至類 似梳齒般形成之第二配線圖案32a，該第二配線圖案32a係 與設置於該半導體晶片20之封裝區域之外周緣部份之外框 20 配線部份33連接。此外，該等開口部份34x係形成在於該外 框配線部份33中形成之電鍍電源部份33x上，且該電鍍設備 之陰極15係與該電鍍電源部份33x連接。又，如前所述，該 電鍍電流係由談電鍍電源部份33x經由該等第二配線圖案 32a與該等凸塊11，供應至由該等通孔36之底部暴露出來之 19 200415776 連接墊10a。 雖然未在第21圖中顯示，但是多數半導體晶片加可分 別安裝在多數安裝區域中以具有類似之結構，且在多數安 裝區域中之第二配線圖案32a係分別與前述外框配線部份 5 33連接。依此方丨’可同時將電鍍電流供應至形成在多數 安裝區域中之第二配線圖案32a。 為了使在該外框配線部份33中之電鍍電源部份33χ暴 露出來，在前述形成該等通孔36之步驟與由該等通孔妬之 底部移除該無機絕緣膜38之步驟中，該第二層間絕緣膜“a 1〇與在該電鍍電源部份33x上之無機絕緣膜38可以在各個步 驟中同時蝕刻。 接著，如第2H圖所示，使作為在該無機絕緣膜38上之 電鍍遮罩之抗蝕膜19形成圖案，這抗蝕膜19形成圖案之方 式疋使在該外框配線部份33中之電鍍電源部份33χ暴露出 15來且多數開口部份19a形成在含有該等通孔36之預定部份 中。 然後’该等陰極15係利用該Cii膜用之電鐘設備來連接 在該外框配線部份33中之電鍍電源部份33χ，且該Cxi膜之電 鍍係使用該抗蝕膜19作為一遮罩開始進行。 10 此時，如前所述，由於作為該電鍍電源層之第二配線 圖案32a係透過該半導體晶片20之凸塊η電氣連接該等連 接墊10a，所以該電鍍電流可供應至該半導體晶片2〇之連接 墊 10a。 因此，該Cu膜（導電膜）係由從該等通孔36之底部暴露 20 200415776 出來之連接墊10a朝上侧依序形成(倒置系統），即，在該 膜（導電膜）填入該等通孔36後，該Cu膜圖案（導電膜圖案） 係形成在抗細19之開口部份19a中，料，移除該抗钱膜 19。 、 5 因此，如第2J圖所示，可形成以插頭31與第三配線圖 案32b，且該半導體晶片2〇之連接塾他與該第三配線圖案 32b係經由該等通孔36互相電氣連接。 依此方式，利用由該等通孔36之底部暴露出來之連接 墊l〇a，該Cu膜由該等通孔36之底部依序向上形成，所以可 10防止在該等通孔36中產生空洞且因此該〇11膜穩定地填充在 該等通孔36中。因此，即使該等通孔36具有一高長寬比， 如直徑約等於或小於20μπι且深度約等於或大於4〇μιη，亦可 防止在該等通孔36中產生空洞且因此可增加在該等連接墊 10a與該第三配線圖案32b之間之電氣連接的可靠性。 15 在這種情形下，在形成該第三配線圖案32b之步驟中， 可使用在形成該第二配線圖案32a之步驟中的半添加法、或 削除法、或全添加法。 又’該等第二通孔34y係形成在未安裝該半導體晶片2〇 之該基底基板30之表面側之第二層間絕緣膜34a上，且形成 20该等第二配線圖案32b，而各第三配線圖案32b係透過該等 第二通孔34y連接該第二配線圖案32a。 接著’如第2K圖所示，在該等第三配線圖案32b之連接 部份32x處具有多數開口部份2ia之焊料抗蝕膜21係分別形 成在該基底基板3〇之兩表面側。然後，藉由利用該焊料抗 21 200415776 姓膜21作為遮罩之無電極電鍍，將該Ni/Au膜42形成在該第 二配線圖案32b之連接部份32x中且在該基底基板30之兩表 面側上。 然後，具有該等凸塊11之疊置半導體晶片20a之凸塊11 5係以倒裴晶片接合法接合於在該等第三配線圖案32b上之 Ni/Au膜 42 〇 接著，在第2K圖中之結構本體被分割成多數預定區 域，各預定區域含有預定數目之半導體晶片2〇。此時，與 該第二配線圖案32a連接之外框配線部份33被刮除，在此情 10形下，在第2J圖中形成有該焊料抗蝕膜21之結構本體被分 割後，可安裝該疊置半導體晶片2〇a。 因此，如第2L圖所示，可得到本發明之第二實施例之 電子部件封裝結構la。在此實施例之電子部件封裝結構^ 中’係以LGA(焊接區夾持陣列)型結構為例。此時，該等焊 b料球係安裝在該安裝基板（主機板)之配線墊上，且該等焊料 球係與《子料結構狀第三配線圖案 3以電氣連接。或者，該等凸塊可相反地安裝在該電子部件 封裝結構la之第二配線圖案32b之連接部份”乂上。 其次，以下將以該第二實施例之另—型態為例來說 20明。第3圖是-顯示本發明之第二實施例之另一型態之截面 圖，在第3圖中，相同之標號係表示與第儿圖相同之元件， 且在此將省略其說明。 換言之，由第2B圖中之前述安裝半導體晶片2〇之步驟 至第2琐中之形成第三配線圖案32b之步驟的各步驟可在 22 200415776 第2J圖中之前述步驟後(在形成該第三配線圖案32b後）重覆 Π一人(η為大於或等於1之整數）。此外，-或多個半導體晶片 可安裝在組目巾未絲該半導體⑸默該基底基板 30之表面側上，以具有相同之結構。 5 刖述另一型態之例子的電子部件封裝結構lb係顯示於 第3圖中，兩半導體晶片20係設置在該基底基板30之一表面 側，使得這些晶片可以分別埋入第二、第三層間絕緣膜 34a、34b，且它們的凸塊11係以倒裝晶片接合法分別連接 至第一、第二配線圖案32a、32b。又，兩半導體晶片2〇係 ίο透過分別形成在這些晶片與第二、第三層間絕緣膜34a、34b 中之通孔36互相地連接。該疊置半導體晶片2〇a之凸塊^係 以倒裝晶片接合法連接作為最上層之第四配線圖案上 之Ni/Au膜 42 〇 同時，在相同結構中，該半導體晶片2〇係安裝在該基 I5底基板30之另-表面側上。如此，安裝在該基底基板川之 兩表面側上之多數半導體晶片20係透過該等通孔36與該基 底基板30之穿孔30a互相連接。 ㈣方式’可使料翻態，使得多數半導體晶片2〇 可以一多層方式安裝在該基底基板30之兩表面侧上，且這 20些晶片可分別埋入該層間絕緣膜中，並且多數半導體晶片 20亦透過該等通孔36等互相連接。 如前所述，在本發明之電子部件封裝結構以、比中， 該層間絕緣膜與該等配線圖案係交替地形成在該基底基板 30之兩表面上，且該半導體晶片20係以倒裝晶片接合法連 23 接於預定配線圖案，使得它們被埋入預定絕緣膜中。接著， 各具有一通達在該半導體晶片20之元件形成表面側之連接 塾10a之深度的通孔36係形成在該等半導體晶片2〇斑覆蓋 該等半導體晶片20之層間絕緣膜的預定部份中。 S 此外，透過該等通孔36與該等半導體晶片2〇之連接墊 l〇a連接的配線圖案係形成在覆蓋該等半導體晶片2Q之層 間絕緣膜上。由於該等通孔36係藉由一次钱刻步驟連續地 形成在該層間絕緣膜與該半導體晶片2〇中，所以它們的側 表面形成為一接續該洙度之相同表面。此外，該疊置半導 10體晶片20a之凸塊11係與最上方之配線圖案連接。 如此’這種型態可藉由以前述方法並以多層方式立體 地安裝多數半導體晶片20，使分別埋入該層間絕緣膜中之 多數半導體晶片20係透過該等通孔36互相連接。 該第二實施例之電子部件封裝結構可達到與第一實施 15 例相同之優點。 又，在第二實施例之電子部件封裝結構la、lb之製造 方法中，該等通孔36係藉由利用RIE或雷射而連續地蝕刻該 第二層間絕緣膜34a與該等半導體晶片2〇來形成。藉此，該 等通孔36可以利用具有少數步驟之非常簡單之方法來形 2〇成。此外，透過該等通孔36與該半導體晶片2〇之連接墊10a 連接的第三配線圖案32b可以藉由一次電鍍步驟形成以向 上升起於該第二層間絕緣膜上方。 因此，相較於類似於第一實施例一般，該半導體晶片 20在該等牙過電極16形成在該半導體晶片汕中後，可以減 24 200415776 少該RIE步驟與使甩昂責製造設備之電鍍步驟的工時。故， 可克服如增加製造成本、預定交貨曰期延遲等缺點。 又，由於在利用電鍍於該等通孔36中形成該等第三配 線圖案32b時’由該等通孔36之底部暴露出來之連接端子係 5被用來作為電鍍電源層，所以可避免在該等通孔36中產生 空洞。因此’由於可增加在該半導體晶片2〇之連接墊1〇a與 該等第三配線圖案32b之間之連接的可靠性，故可增加該電 子部件封裝結構之產率。
【圖式簡單^說^明】 0 々 第1A至1K圖是顯示本發明之第一實施例之電子部件 封裳結構之製造方法的截面圖； 第2A至2L圖是顯示本發明之第二實施例之電子部件 封裝結構之製造方法的截面圖，其中第21圖是顯示由第2H 圖之頂側看透之透視平面圖；及
第3圖是顯示本發明之第二實施例之電子部件封裝結 構之另一型態的截面圖。 25 200415776 【圖式之主要元件代表符號表】 Uajb···電子部件封裝結構 32a···第二配線圖案 10…半導體晶圓 l〇a...連接墊 10b···通孔 11…凸塊 12…抗舰 12a…開口部份 13…抗健 14…無機絕緣膜 16.. .穿過電極 16a…晶種Cu膜 18.. .底層填充樹脂 19···抗娜 19a...開口部份 20…半導體晶片 20a...疊置半導體晶片 21…焊料抗娜 21a…開口部份 30…基底基板 30a···穿孔 30b…穿孔電鑛層 30c…樹脂本體 32.. .第一配線圖案 32b···第三配線圖案 32c···第四配線圖案 32χ·"連接部份 33…外框配線部份 33χ...電鍍電源部份 34…第一層間絕緣膜 34a··.第二層間絕緣膜 34b…第三層間絕緣膜 34χ·"通孔 34y…第二通孔 36···通孔 38…無機絕緣膜 40…配線基板
42...Ni/Au 膜 26

Claims (1)

  1. 200415776 拾、申請專利範圍·· 1· -種電子部件封裳結構，包含有·· —配線基板，包括—預定配麵案； 一電子部件連接端子，係在_元侔^、 倒裝晶片接合法與該配線圖案連接；&表面上且以 一絕緣膜，㈣覆好數電子部件; 一通孔，係形成在該等電子部件 在該連接端子上之絕緣膜中；及 ίο 之 預定部份中與 .過談通 —重疊配線圖案’係形成在該絕緣膜上且透： 孔與該連接端子連接。 I ==範圍第1項之電子部件封裝結構，其中形成 ^該專電子部件中之通孔之職面構成—連續之相同 表面。 3· —種電子部件封裝結構，包含有： 一配線基板，包括一預定配線圖案； 電子^件連接端子，係在一元件形成表面上且以 倒裝晶片接合法細配線圖案連接，且在_背面上，多 數電子部件具有穿過電極，並且該穿過電極係透過形成 在該等電子部件巾之第-通孔與該連接端子連接； 一絕緣膜，用以覆蓋該等電子部件； 一第二通孔，係形成在該穿過電極之絕緣膜之一預 定部份中；及 一重疊配線圖案，係形成在該絕緣膜上且透過該第 一通孔與該穿過電極連接。 27 200415776 4.如申請專利範圍第1項之電子部件社結構，1中b ^該等電子部件中之通孔之侧面係被—無機絕緣膜覆 5.如申請糊制第1項之電子料料結構，复中判 6如申嘖專财門笛旧 4於或小於150_。 .如申响專心㈣丨項之電子部件封裝結構， 在該配線基板之配_案上之—與料電子部件相同 之結構本體、該絕緣膜與該重疊配線圖案係以_多 10 式在該重疊配線圖案上重覆n次_或大於k整數曰 且多數電子部件係透過該料孔互相連接。 7.如申請專利範圍第i項之電子部件封裝結構，其中一重 疊配線圖案之連接端子係以倒裝晶片接合法與該重最 配線圖案連接。 8. 15 一種製造—電子部件«結構之方法，該方法包含下列 步驟： 以倒裝晶片接合法連接一在一元件形成表面上具 有-連接端子之電子部件的連接端子與一形成在一基 底基板上或上方的配線圖案； 形成一用以覆蓋該等電子部件之絕緣膜； 利用由該絕緣膜之上表面至該等電子部件之元件 形成表面蝕刻一預定部份，以形成一具有通達該連接端 子之深度之通孔·，及 在該絕緣膜上形成一重疊配線圖案，且該重疊配線 圖案係透過該通孔與該連接端子連接。 28 種IL造一電子部件封裝結構之方法，該方法包含下 步驟： /以甸裝晶片接合法連接一電子部件的連接端子與 7成在一基底基板上或上方的配線圖案，且該電子部 件在一 一 丨 元件形成表面上具有該連接端子並且在背面具 有透過一第一通孔與該連接端子連接之穿過電極； 形成一用以覆蓋該等電子部件之絕緣膜； 用鍅刻在該牙過電極上之該絕緣膜之一預定部 伤’以形成一具有通達該穿過電極之深度之第二通孔； 及 在忒緣膜上形成一重疊配線圖案，且該重疊配線 圖案係透過該第二魏與該穿過電極連接。 10·如申請專利範圍第8項之電子部件封裝結構之製造方 法’其中在形成該通孔之步驟中，該絕緣膜與該等電子 部件係藉由RIE或雷射來蝕刻。 1L如申請專雜圍第8項之電子料封裝結構之製造方 法，其中形成該重叠配線圖案之步驟包括以下步驟： 在顏賴上軸—抗麵，且該抗雜在一含有 該通孔之預定部份上具有一開口部份； 以由該通孔之底部暴露出來之連接端子向上利用 電錢法鍵上-電鍍層之方式在該通孔與該抗⑽之開 口部份中形成-導電膜目案，且該電鍍法制用該配線 圖案及與該配線圖案連接之電子部件之連接端子作為 一電鍍電源層；及 29 200415776 移除該抗蝕膜以得到該重疊配線圖案。 12 ·如申請專利範圍第8項之電子部件封裝結構之製造方 法，其中在形成該通孔之步驟之後，但在形成該重疊配 線圖案之前，更包含以下步驟： 5 在該通孔之一内表面與在該絕緣膜上形成一無機 絕緣膜；及 由該通孔之底部移除該無機絕緣膜以暴露出該通 孔之底部上之連接端子。 13. 如申請專利範圍第8項之電子部件封裝結構之製造方 10 法，其中多數電子部件以一多層方式立體地層疊且透過 該通孔互相連接之結構係藉由重覆η次(η係1或大於1之 整數）由連接該等電子部件與該配線圖案之步驟至形成 該重疊配線圖案之步驟之各個步驟來形成。 14. 如申請專利範圍第8項之電子部件封裝結構之製造方 15 法，其中形成該重疊配線圖案之步驟包括以下步驟·· 以倒裝晶片接合法連接具有該連接端子之重疊配 線圖案之連接端子與該重疊配線圖案。 15·如申請專利範圍第8項之電子部件封裝結構之製造方 法，其中該等電子部件是一半導體晶片，其厚度為等於 20 或小於150μπι 〇 30
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