KR100818088B1 - 반도체 패키지 및 그 제조 방법 - Google Patents
반도체 패키지 및 그 제조 방법 Download PDFInfo
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- KR100818088B1 KR100818088B1 KR1020060059827A KR20060059827A KR100818088B1 KR 100818088 B1 KR100818088 B1 KR 100818088B1 KR 1020060059827 A KR1020060059827 A KR 1020060059827A KR 20060059827 A KR20060059827 A KR 20060059827A KR 100818088 B1 KR100818088 B1 KR 100818088B1
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- semiconductor package
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 151
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 238000000034 method Methods 0.000 claims description 19
- 239000000758 substrate Substances 0.000 claims description 18
- 238000002161 passivation Methods 0.000 claims description 16
- 230000001681 protective effect Effects 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 5
- 230000000149 penetrating effect Effects 0.000 claims description 5
- 239000011810 insulating material Substances 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 2
- 239000004020 conductor Substances 0.000 description 8
- 239000010408 film Substances 0.000 description 8
- 239000002184 metal Substances 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 230000035939 shock Effects 0.000 description 1
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Abstract
Description
Claims (14)
- 제 1면에 회로부가 형성된 반도체 칩;상기 반도체 칩의 상기 제 1면과 대향하는 제 2면 상에 배치된 제1 절연층;상기 제1 절연층 상에 형성된 제1 전기 소자들;상기 제1 절연층을 관통하며 상기 제1 절연층의 표면으로부터 상기 제1 전기 소자들과 동일한 높이로 돌출되고 상기 제1 전기소자들과 전기적으로 연결된 제1 비아;상기 제1 전기 소자들을 덮고 유전체 역할을 하는 제2 절연층;상기 제2 절연층 상에 배치된 제2 전기 소자들;상기 제2 절연층을 관통하며 상기 제2 절연층의 표면으로부터 상기 제2 전기 소자들과 동일한 높이로 돌출되고, 상기 제2 전기 소자들과 전기적으로 연결된 제2 비아; 및상기 회로부와 전기적으로 연결되며 상기 제 1 및 제2 비아들과 직접 연결되도록 상기 반도체 칩을 관통하여 형성된 제 3비아들을 포함하는 반도체 패키지 유닛을 포함하는 것을 특징으로 하는 반도체 패키지.
- 삭제
- 제 1 항에 있어서,상기 제1 및 제2 전기 소자들은 저항(R), 인덕턴스(L) 및 커패시턴스(C) 등을 포함하는 수동소자인 것을 특징으로 하는 반도체 패키지.
- 제 1 항에 있어서,상기 반도체 패키지 유닛은 적어도 2개 이상이 적층된 것을 특징으로 하는 반도체 패키지.
- 제 1 항에 있어서,상기 반도체 패키지 유닛이 실장되는 베이스 기판 및 상기 제 3비아들 통해 상기 회로부와 전기적으로 연결되는 외부 접속 단자를 포함하는 것을 특징으로 하는 반도체 패키지.
- 웨이퍼에 회로부를 포함하는 반도체 칩들을 형성하는 단계;상기 회로부가 형성된 상기 반도체 칩의 제 1면과 대향하는 상기 반도체 칩의 제 2면에 제1 비아홀을 갖는 절연 패턴을 형성하는 단계;상기 절연 패턴 상에 전기 소자들 및 상기 1비아홀에 형성된 제1 비아들을 형성하는 단계;상기 제 1면에 상기 제 1비아들을 노출시키는 제 2비아홀들을 형성하는 단계; 및상기 회로부 및 상기 제 1비아들과 연결된 제 2비아들을 상기 제 2비아홀들에 형성하여 반도체 패키지 유닛을 제조하는 단계를 포함하는 것을 특징으로 하는 반도체 패키지의 제조 방법.
- 제 6 항에 있어서,상기 제 1면에 상기 회로부를 형성한 후 상기 절연 패턴을 형성하기 전에 상기 제 1면에 감광물질을 포함하는 제 1보호막을 형성하고, 상기 제 2비아홀을 형성하기 전에 상기 제 1보호막을 제거하는 것을 특징으로 하는 반도체 패키지의 제조 방법.
- 제 6 항에 있어서,상기 전기 소자들을 형성하는 단계에서, 상기 전기 소자는 저항(R), 인덕턴스(L) 및 커패시턴스(C) 등을 포함하는 수동소자인 것을 특징으로 하는 반도체 패키지의 제조 방법.
- 제 6 항에 있어서,상기 전기 소자들 및 상기 제 1비아들을 형성하는 단계는 적어도 2 번 이상 반복하는 것을 특징으로 하는 반도체 패키지의 제조 방법.
- 제 6 항에 있어서,상기 전기 소자들 및 상기 제 1비아들을 형성한 후 상기 제2 비아홀들을 형성하기 전에 상기 전기 소자들 및 상기 제 1비아들 상에 절연물질로 제 2보호막을 형성하는 것을 특징으로 하는 반도체 패키지의 제조 방법.
- 제 6 항에 있어서,상기 제 2비아홀들은 식각에 의하여 형성되는 것을 특징으로 하는 반도체 패키지의 제조 방법.
- 제 6 항에 있어서,상기 제 2비아홀들은 레이저에 의하여 형성되는 것을 특징으로 하는 반도체 패키지의 제조 방법.
- 제 6 항에 있어서,상기 반도체 패키지 유닛은 적어도 2 개 이상이 적층되며, 제 1 및 제 2비아들에 의해 서로 이웃한 반도체 패키지 유닛과 전기적으로 연결되는 것을 특징으로 하는 반도체 패키지의 제조 방법.
- 제 6 항에 있어서,상기 제 2비아들은 상기 반도체 패키지 유닛이 실장되는 베이스 기판과 전기적으로 연결되는 것을 특징으로 하는 반도체 패키지의 제조 방법.
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KR1020060059827A KR100818088B1 (ko) | 2006-06-29 | 2006-06-29 | 반도체 패키지 및 그 제조 방법 |
US11/647,702 US7652347B2 (en) | 2006-06-29 | 2006-12-29 | Semiconductor package having embedded passive elements and method for manufacturing the same |
TW096100985A TWI339882B (en) | 2006-06-29 | 2007-01-10 | Semiconductor package having embedded passive elements and method for manufacturing the same |
JP2007031207A JP5090749B2 (ja) | 2006-06-29 | 2007-02-09 | 半導体パッケージ及びその製造方法 |
CNB2007100053780A CN100541771C (zh) | 2006-06-29 | 2007-02-14 | 具有嵌入式无源元件的半导体封装及其制造方法 |
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KR100869832B1 (ko) * | 2007-09-18 | 2008-11-21 | 삼성전기주식회사 | 반도체칩 패키지 및 이를 이용한 인쇄회로기판 |
US7648911B2 (en) * | 2008-05-27 | 2010-01-19 | Stats Chippac, Ltd. | Semiconductor device and method of forming embedded passive circuit elements interconnected to through hole vias |
US8263437B2 (en) * | 2008-09-05 | 2012-09-11 | STATS ChiPAC, Ltd. | Semiconductor device and method of forming an IPD over a high-resistivity encapsulant separated from other IPDS and baseband circuit |
US7858441B2 (en) * | 2008-12-08 | 2010-12-28 | Stats Chippac, Ltd. | Semiconductor package with semiconductor core structure and method of forming same |
TWI581384B (zh) * | 2009-12-07 | 2017-05-01 | 英特希爾美國公司 | 堆疊式電子電感封裝組件及其製造技術 |
US8987830B2 (en) | 2010-01-12 | 2015-03-24 | Marvell World Trade Ltd. | Attaching passive components to a semiconductor package |
FR2961345A1 (fr) * | 2010-06-10 | 2011-12-16 | St Microelectronics Tours Sas | Circuit integre passif |
CN103247614A (zh) * | 2013-04-28 | 2013-08-14 | 上海宏力半导体制造有限公司 | 电感器件 |
US9123735B2 (en) * | 2013-07-31 | 2015-09-01 | Infineon Technologies Austria Ag | Semiconductor device with combined passive device on chip back side |
US20190043255A1 (en) * | 2016-02-11 | 2019-02-07 | 3M Innovative Properties Company | Population-based surface mesh reconstruction |
US10559213B2 (en) * | 2017-03-06 | 2020-02-11 | Rosemount Aerospace Inc. | Method and system for aircraft taxi strike alerting |
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