CN111725146A - 电子封装件及其制法 - Google Patents

电子封装件及其制法 Download PDF

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Publication number
CN111725146A
CN111725146A CN201910249759.6A CN201910249759A CN111725146A CN 111725146 A CN111725146 A CN 111725146A CN 201910249759 A CN201910249759 A CN 201910249759A CN 111725146 A CN111725146 A CN 111725146A
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China
Prior art keywords
conductive
electronic
pillar
package
layer
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CN201910249759.6A
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English (en)
Inventor
邱志贤
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Siliconware Precision Industries Co Ltd
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Siliconware Precision Industries Co Ltd
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Publication of CN111725146A publication Critical patent/CN111725146A/zh
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Abstract

一种电子封装件及其制法，包括将电子元件与多个电性连接该电子元件的导电柱嵌埋于封装层中，其中，该导电柱的周面的宽度小于该导电柱的两端面的宽度，从而经由该封装层包覆该电子元件，以有效保护该电子元件，且提升产品的可靠度。

Description

电子封装件及其制法
技术领域
本发明有关一种半导体封装制程，尤指一种电子封装件及其制法。
背景技术
随着电子产业的发达，现今的电子产品已趋向轻薄短小与功能多样化的方向设计，半导体封装技术也随之开发出不同的封装型态。为满足半导体封装结构的高集成度(Integration)以及微型化(Miniaturization)需求，除传统打线式(Wire bonding)的半导体封装技术外，也可经由覆晶(Flip chip)方式，以提升布线密度。
图1为悉知覆晶式封装结构1的剖视示意图。如图1所示，主要将一半导体芯片13经由多个焊锡凸块130结合至一封装基板10的线路层11的电性接触垫110上并电性连接该线路层11的导电迹线111，再形成如封装胶体或底胶的绝缘材14于该半导体芯片13与该封装基板10之间，以包覆该些焊锡凸块130。
然而，在封装制程中，由于该半导体芯片13以裸晶状态(如晶背13b外露)于制程机台间进行运送，因而该半导体芯片13无任何保护，容易造成该半导体芯片13发生缺角(chipping)与损毁问题，严重导致产品发生可靠度问题与庞大的财务损失。
此外，该封装基板10的绝缘保护层12形成有多个对应外露各该电性接触垫110的开孔，故于该绝缘材14流入该半导体芯片13与该封装基板10间时，容易导致该绝缘材14中具较大尺寸的填充料(filler)无法通过而产生气室(void)，以致于后续制程中容易发生爆米花现象(Popcorn)，造成产品良率下降问题。
因此，如何克服上述悉知技术的种种问题，实已成为目前业界亟待克服的难题。
发明内容
鉴于上述悉知技术的缺失，本发明提供一种电子封装件及其制法，以有效保护该电子元件，且提升产品的可靠度。
本发明的电子封装件，包括：至少一电子元件；多个导电结构，其设于该电子元件上且包含有导电柱，其中，该导电柱具有相对的两端面及邻接该两端面的周面，且该周面的宽度小于该两端面的宽度；以及一封装层，其包覆该电子元件与该多个导电结构，且令该导电柱的一端面外露出该封装层的外表面。
本发明还提供一种电子封装件的制法，包括：提供一导电架，其中，该导电架包含有一板体与多个连接该板体的导电柱，且该导电柱具有相对的两端面及邻接该两端面的周面，且该周面的宽度小于该两端面的宽度；设置至少一电子元件于该导电架上，且令该多个导电柱的至少一部分与该电子元件结合；形成封装层于该板体上，以令该封装层包覆该电子元件与该多个导电柱；以及移除该板体，以令该导电柱的一端面外露出该封装层的外表面。
前述的电子封装件及其制法中，该导电柱经由导电体结合该电子元件，例如，该导电体包含焊锡材料。进一步，该电子元件经由金属部结合该导电体，例如，该金属部为铜柱。
前述的电子封装件及其制法中，该导电柱的外露端面低于或齐平该封装层的外表面。
前述的电子封装件及其制法中，该电子元件的部分表面外露于该封装层的外表面。
前述的电子封装件及其制法中，还包括于移除该板体后，形成导电元件于该导电柱上，且该导电元件位于该封装层的外表面上。
前述的电子封装件及其制法中，该多个导电柱的其中一部分未与该电子元件结合，以作为虚柱结构。例如，该虚柱结构外露出该封装层的外表面。
由上可知，本发明的电子封装件及其制法，主要经由该导电柱与该封装层的设计，以令该封装层包覆该电子元件的表面，使该电子元件能有效受到保护，故相较于悉知技术，本发明的电子封装件能提升产品的可靠度。
此外，本发明以导电架取代悉知封装基板，因而无需形成绝缘保护层及用以对应外露各该电性接触垫的开孔，故相较于悉知技术，该封装层能顺利布设而不会产生气室，因而能避免于后续制程中发生爆米花现象。
附图说明
图1为悉知覆晶式封装结构的剖视示意图。
图2A至2G为本发明的电子封装件的制法的剖视示意图。
图2A’为图2A的局部上视图。
图2B’为图2B的另一实施例的剖视示意图。
图2C’及图2C”为图2C的其它不同实施例的局部剖视示意图。
图2G’为图2G的另一实施例的剖视示意图。
图2H为图2G的后续应用的剖视示意图。
图3A至图3C为图2G的其它不同实施例的剖视示意图。
图4A及图4B为图2G的其它不同实施例的剖视示意图。
符号说明
1 覆晶式封装结构 10 封装基板
11 线路层 110 电性接触垫
111 导电迹线 13 半导体芯片
13b 晶背 130 焊锡凸块
14 绝缘材 2,2’,3a,3b,3c,4a,4b 电子封装件
2a 导电架 20 金属板
21 电子元件 21a 作用面
21b 非作用面 21c 侧面
210 电极垫 22 导电体
22a,22a’ 导电凸块 220 金属部
221 焊锡部 23,33 导电柱
23a,23b,33a 端面 23c 周面
24 板体 240 凹部
25,35 封装层 25a 第一表面
25b,35b 第二表面 25c 侧面
26,26’,36 导电结构 27 导电元件
28 导电材料 3 电路板
43 虚柱结构 A 垂直投影区域
d 宽度 S 切割路径。
具体实施方式
以下经由特定的具体实施例说明本发明的实施方式，本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其他优点及功效。
须知，本说明书所附图式所绘示的结构、比例、大小等，均仅用以配合说明书所揭示的内容，以供本领域技术人员的了解与阅读，并非用以限定本发明可实施的限定条件，故不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的如“上”、“第一”、“第二”及“一”等的用语，也仅为便于叙述的明了，而非用以限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当视为本发明可实施的范畴。
图2A至图2G为本发明的电子封装件2的制法的剖视示意图。
如图2A所示，提供一导电架2a，其包含一板体24及多个形成于该板体24上的导电柱23，其中，该导电柱23具有相对的两端面23a,23b及邻接该两端面23a,23b的周面23c，且该周面23c的宽度小于该两端面23a,23b的宽度d。
在本实施例中，该导电柱23的周面23c相对两端面23a,23b呈凹状，使该导电柱23呈苹果核状，且该板体24与导电柱23为一体成形。例如，利用蚀刻、雷射或其它适当方式移除一金属板的部分材质，以形成该导电架2a。具体地，可经由蚀刻方式于该金属板上形成底切型凹部240，借以形成多个间隔相邻的导电柱23，且令该导电柱23的周面23c呈内凹弧形。
此外，该导电柱23并未延伸有导电迹线，如图2A’所示，即没有走线(routing)设计。
如图2B所示，形成导电材料28于该导电架2a的导电柱23的端面23b上。
在本实施例中，该导电材料28如焊锡材料、锡膏、铜膏、银胶或其它适当材料。
此外，该导电架2a与该导电材料28的制程顺序可依需求调整。如图2B’所示，若该导电材料28不同于该导电架2a的材质，则可利用该导电材料28作为阻层，而形成于一金属板20上，再利用蚀刻、雷射或其它适当方式移除该金属板20的部分材质，以令该金属板20成为该导电架2a。
如图2C所示，设置至少一电子元件21于该导电柱23上的导电材料28上。
在本实施例中，该电子元件21为主动元件、被动元件或其二者组合等，其中，该主动元件为例如半导体芯片，且该被动元件为例如电阻、电容及电感。例如，该电子元件21具有相对的作用面21a与非作用面21b，该作用面21a具有多个电极垫210，并以覆晶方式将其作用面21a结合于该导电材料28上以电性连接该导电柱23。
此外，该电子元件21的作用面21a的电极垫210上可先形成多个导电凸块22a，如图2C’所示，且该导电凸块22a包含一结合该电极垫210的金属部220与一结合该金属部220的焊锡部221(如锡膏)；或者，如图2C”所示，该导电凸块22a’也可为焊锡凸块(如锡膏)，而未具有如铜块的金属部。具体地，该电子元件21可于晶圆状态时布设该些导电凸块22a,22a’，再依规格需求切单成所需尺寸的电子元件21。
又，该电子元件21与该导电柱23相结合后，将回焊所用的焊锡材料(如锡膏)，以令所用的焊锡材料融合成导电体22。例如，该导电材料28与图2C’的焊锡部221形成该导电体22；或者，该导电材料28与图2C”的导电凸块22a’形成该导电体22。亦或，该电子元件21仅设有该金属部220，以令该导电材料28作为该导电体22。
因此，于设置该电子元件21于该导电柱23上之前，所用的焊锡材料(或该导电体22于回焊前的状态)可依需求形成于该电子元件21的电极垫210(或该金属部220)上及/或该导电架2a的导电柱23上。
如图2D所示，接续图2C所示的制程，形成一封装层25于该导电架2a的板体24上，以包覆该电子元件21、导电体22、导电柱23及金属部220，使该封装层25覆盖该电子元件21的作用面21a、非作用面21b及侧面21c，且令该导电架2a的板体24外露出该封装层25。
在本实施例中，该封装层25具有相对的第一表面25a与第二表面25b，且其以第一表面25a结合于该板体24上，并使该板体24外露出该封装层25的第一表面25a。
此外，形成该封装层25的材质为绝缘材，如聚酰亚胺(polyimide，简称PI)、干膜(dry film)、环氧树脂(expoxy)环氧树脂的封装胶体或封装材(molding compound)，其可用压合(lamination)或模压(molding)的方式形成于该板体24上，但不限于上述。
如图2E所示，移除该导电架2a的板体24，以令该导电柱23的端面23a外露出该封装层25的第一表面25a。又，由于该封装层25包覆该导电柱23，故该导电柱23可视为封装穿孔(Through Mold Via，简称TMV)结构。
在本实施例中，为采用研磨、蚀刻、烧灼、切除或其它适合方式移除该板体24(依需求可一并移除该封装层25的部分材质)，使该导电柱23的端面23a与该封装层25的第一表面25a共平面(即该导电柱23的端面23a齐平该封装层25的第一表面25a)，以令该导电柱23的端面23a外露出该封装层25的第一表面25a。因此，经由移除该板体24以分开该些导电柱23，可使该些导电柱23的高度一致，故该些导电柱23所排列成的栅状阵列的共面性良好，因而能避免于后续制程中产生接点偏移的问题。
此外，该导电体22、导电柱23及金属部220作为导电结构26，以作为接点。
如图2F所示，结合多个如焊球的导电元件27于该导电结构26的导电柱23的外露端面23a上。
如图2G所示，沿如图2F所示的切割路径S进行切单制程，以获取多个电子封装件2，且该电子封装件2可于后续应用中经由该些导电元件27接置如电路板3的电子装置，如图2H所示。
在本实施例中，若接续图2C”所示的制程，可获取如图2G’所示的电子封装件2’，其导电结构26’未包含有金属部。
此外，在其它实施例中，如图3A所示，于切单制程时，可依需求令该电子封装件3a包括多个电子元件21；或者，如图3B所示的电子封装件3b，可进行整平制程，如采用研磨、蚀刻、烧灼、切除或其它适合方式移除该封装层25的部分材质(依需求可一并移除该电子元件21的部分材质)，使该电子元件21的非作用面21b齐平该封装层35的第二表面35b，以令该电子元件21的非作用面21b外露出该封装层35；亦或，如图3C所示的电子封装件3c，于移除该板体24时，可一并移除该导电柱23的部分材质，使该导电结构36(或该导电柱33的端面33a)低于该封装层25的第一表面25a。
又，部分该导电柱23也可未连结该电子元件21，如图4A或图4B所示，以作为虚柱结构43(其未电性连接该电子元件21)，供该电子封装件4a,4b分散应力之用。具体地，该虚柱结构43可对应位于该电子元件21的垂直投影区域A之内(如图4A所示)或之外(如图4B所示)，且该虚柱结构43更可外露于该封装层25的侧面25c(如图4B所示)。
因此，本发明的制法主要经由该导电柱23,33与该封装层25,35的设计，以包覆该电子元件21的表面，使该电子元件21于制程机台间进行运送时(如于后续应用中接合该电路板3)能有效受到保护，以避免该电子元件21的缺角问题，因而能避免整个电子元件21损毁，故相较于悉知技术，本发明的电子封装件2,2’,3a,3b,3c,4a,4b能提升产品的可靠度。
此外，本发明的制法以导电架2a取代悉知封装基板，因而无需形成绝缘保护层及用以对应外露各该电性接触垫的开孔，故于该封装层25,35流入该电子元件21与该板体24间时，该封装层25,35能顺利通过而不会产生气室(void)，因而能避免于后续制程中发生爆米花现象。
又，该导电柱23,33的周面23c的宽度小于该两端面23a,23b的宽度d，使该导电柱23,33的周面23c内凹，故于回焊该些导电元件27而使该导电体22变成流体(处于回焊温度的条件状态)时，能避免该导电体22沿该周面23c溢流至该封装层25,35的第一表面25a而桥接相邻两导电元件27的问题。换言之，若该导电柱23,33的周面呈平面状，于回焊该些导电元件27而使该导电体22变成流体时，该导电体22容易沿平面状周面溢流至该封装层25,35的第一表面25a而桥接相邻两导电元件27，进而发生短路问题。
另外，该导电柱23,33的内凹周面23c也能容纳该封装层25,35，以提供该封装层25,35与该导电柱23,33之间较佳的固定效果，故本发明的制法能避免因该封装层25,35与该导电柱23,33的结合性不佳而于后续制程发生脱层的问题。
本发明还提供一种电子封装件2,2’,3a,3b,3c,4a,4b，包括：至少一电子元件21、多个导电结构26,26’,36以及一封装层25,35。
所述的电子元件21具有相对的作用面21a与非作用面21b，该作用面21a具有多个电极垫210。
所述的导电结构26,26’,36设于该电子元件21的作用面21a上且包含有导电柱23,33，其中，各该导电柱23具有相对的两端面23a,23b及邻接该两端面23a,23b的周面23c，且该周面23c的宽度小于该两端面23a,23b的宽度d。
所述的封装层25,35包覆该电子元件21与该多个导电结构26,26’,36，且该封装层25,35具有相对的第一表面25a与第二表面25b,35b，以令该导电柱23,33的一端面外露出该封装层25,35的第一表面25a。
在一实施例中，该导电结构26,26’,36还具有导电体22，如包含焊锡材料，其设于该导电柱23,33与该电子元件21之间。进一步，该导电结构26还具有金属部220，如铜柱，其设于该导电体22与该电子元件21之间。
在一实施例中，该导电柱23的外露端面23a齐平该封装层25的第一表面25a。
在一实施例中，该导电柱33的外露端面33a低于该封装层25的第一表面25a。
在一实施例中，该电子元件21的非作用面21b外露于该封装层35的第二表面35b。
在一实施例中，所述的电子封装件2,2’,3a,3b,4a,4b还包括多个结合该些导电柱23,33的导电元件27，其位于该封装层25,35的第一表面25a外。
在一实施例中，所述的电子封装件4a,4b还包括至少一嵌埋于该封装层25中的虚柱结构43，其未连结该电子元件21。例如，该虚柱结构43外露于该封装层25的第一表面25a及/或侧面25c。
综上所述，本发明的电子封装件及其制法，经由该导电柱与该封装层的设计，以令该封装层包覆该电子元件的表面，使该电子元件能有效受到保护，故本发明的电子封装件能提升产品的可靠度。
此外，本发明以导电架取代悉知封装基板，因而无需形成绝缘保护层及用以对应外露各该电性接触垫的开孔，故该封装层能顺利布设而不会产生气室，因而能避免于后续制程中发生爆米花现象。
又，经由该导电柱的内凹周面的设计，故于回焊该些导电元件而使该导电体变成流体时，能避免该导电体沿该周面溢流至该封装层的第一表面而桥接相邻两导电元件的问题。
另外，该导电柱的内凹周面也能容纳该封装层，以提供该封装层与该导电柱之间较佳的固定效果，故能避免该封装层与该导电柱发生脱层的问题。
上述实施例仅用以例示性说明本发明的原理及其功效，而非用于限制本发明。任何本领域技术人员均可在不违背本发明的精神及范畴下，对上述实施例进行修改。因此本发明的权利保护范围，应如权利要求书所列。

Claims (20)

1.一种电子封装件，其特征在于，包括：
至少一电子元件；
多个导电结构，其设于该电子元件上且包含有导电柱，其中，该导电柱具有相对的两端面及邻接该两端面的周面，且该周面的宽度小于该两端面的宽度；以及
一封装层，其包覆该电子元件与该多个导电结构，且令该导电柱的一端面外露出该封装层的外表面。
2.根据权利要求1所述的电子封装件，其特征在于，该导电结构还包含有设于该导电柱与该电子元件之间的导电体。
3.根据权利要求2所述的电子封装件，其特征在于，该导电体包含焊锡材料。
4.根据权利要求2所述的电子封装件，其特征在于，该导电结构还包含有设于该导电体与该电子元件之间的金属部。
5.根据权利要求4所述的电子封装件，其特征在于，该金属部为铜柱。
6.根据权利要求1所述的电子封装件，其特征在于，该导电柱的外露端面低于或齐平该封装层的外表面。
7.根据权利要求1所述的电子封装件，其特征在于，该电子元件的部分表面外露于该封装层的外表面。
8.根据权利要求1所述的电子封装件，其特征在于，该电子封装件还包括多个位于该封装层的外表面上且结合至该导电柱的导电元件。
9.根据权利要求1所述的电子封装件，其特征在于，该电子封装件还包括至少一嵌埋于该封装层中且未连结该电子元件的虚柱结构。
10.根据权利要求9所述的电子封装件，其特征在于，该虚柱结构外露出该封装层的外表面。
11.一种电子封装件的制法，其特征在于，包括：
提供一导电架，其中，该导电架包含有一板体与多个连接该板体的导电柱，且该导电柱具有相对的两端面及邻接该两端面的周面，且该周面的宽度小于该两端面的宽度；
设置至少一电子元件于该导电架上，且令该多个导电柱的至少一部分与该电子元件结合；
形成封装层于该板体上，以令该封装层包覆该电子元件与该多个导电柱；以及
移除该板体，以令该导电柱的一端面外露出该封装层的外表面。
12.根据权利要求11所述的电子封装件的制法，其特征在于，该导电柱经由导电体结合该电子元件。
13.根据权利要求12所述的电子封装件的制法，其特征在于，该导电体包含焊锡材料。
14.根据权利要求12所述的电子封装件的制法，其特征在于，该电子元件经由金属部结合该导电体。
15.根据权利要求14所述的电子封装件的制法，其特征在于，该金属部为铜柱。
16.根据权利要求11所述的电子封装件的制法，其特征在于，该导电柱的外露端面低于或齐平该封装层的外表面。
17.根据权利要求11所述的电子封装件的制法，其特征在于，该电子元件的部分表面外露于该封装层的外表面。
18.根据权利要求11所述的电子封装件的制法，其特征在于，该制法还包括于移除该板体后，形成导电元件于该导电柱上，且该导电元件位于该封装层的外表面上。
19.根据权利要求11所述的电子封装件的制法，其特征在于，该多个导电柱的其中一部分未与该电子元件结合，以作为虚柱结构。
20.根据权利要求19所述的电子封装件的制法，其特征在于，该虚柱结构外露出该封装层的外表面。
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Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI778654B (zh) * 2021-06-09 2022-09-21 矽品精密工業股份有限公司 電子封裝件及其製法
US11876065B2 (en) * 2021-09-30 2024-01-16 Texas Instruments Incorporated Flip chip package assembly
TWI807665B (zh) * 2022-03-03 2023-07-01 復盛精密工業股份有限公司 預成型導電柱結構及其製作方法

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1326225A (zh) * 2000-05-26 2001-12-12 日本电气株式会社 芯片倒装型半导体器件及其制造方法
US6683368B1 (en) * 2000-06-09 2004-01-27 National Semiconductor Corporation Lead frame design for chip scale package
US6689640B1 (en) * 2000-10-26 2004-02-10 National Semiconductor Corporation Chip scale pin array
CN101313402A (zh) * 2005-11-16 2008-11-26 冲电气工业株式会社 双面电极插件及其制造方法
CN102842515A (zh) * 2011-06-23 2012-12-26 飞思卡尔半导体公司 组装半导体器件的方法
CN103531560A (zh) * 2013-10-31 2014-01-22 矽力杰半导体技术(杭州)有限公司 芯片的封装结构及其制造方法
CN103839913A (zh) * 2012-11-27 2014-06-04 英飞凌科技股份有限公司 半导体封装及其形成方法
CN107293499A (zh) * 2016-03-30 2017-10-24 意法半导体股份有限公司 用于倒装芯片封装件的热超声接合的连接
US10008437B2 (en) * 2016-08-31 2018-06-26 Shinko Electric Industries Co., Ltd. Lead frame and electronic component device

Family Cites Families (42)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4545610A (en) * 1983-11-25 1985-10-08 International Business Machines Corporation Method for forming elongated solder connections between a semiconductor device and a supporting substrate
US4878611A (en) * 1986-05-30 1989-11-07 American Telephone And Telegraph Company, At&T Bell Laboratories Process for controlling solder joint geometry when surface mounting a leadless integrated circuit package on a substrate
US5014111A (en) * 1987-12-08 1991-05-07 Matsushita Electric Industrial Co., Ltd. Electrical contact bump and a package provided with the same
US5233504A (en) * 1990-12-06 1993-08-03 Motorola, Inc. Noncollapsing multisolder interconnection
US5466635A (en) * 1994-06-02 1995-11-14 Lsi Logic Corporation Process for making an interconnect bump for flip-chip integrated circuit including integral standoff and hourglass shaped solder coating
US5578527A (en) * 1995-06-23 1996-11-26 Industrial Technology Research Institute Connection construction and method of manufacturing the same
US6225205B1 (en) * 1998-01-22 2001-05-01 Ricoh Microelectronics Company, Ltd. Method of forming bump electrodes
US6657124B2 (en) * 1999-12-03 2003-12-02 Tony H. Ho Advanced electronic package
JP3548082B2 (ja) * 2000-03-30 2004-07-28 三洋電機株式会社 半導体装置及びその製造方法
JP2001326250A (ja) * 2000-05-17 2001-11-22 Nec Corp フリップチップ型半導体装置及び製造方法
TW507348B (en) * 2001-01-17 2002-10-21 Nec Corp Semiconductor device and method of manufacturing the same
US6965160B2 (en) * 2002-08-15 2005-11-15 Micron Technology, Inc. Semiconductor dice packages employing at least one redistribution layer
US7042088B2 (en) * 2004-03-10 2006-05-09 Ho Tony H Package structure with two solder arrays
US7875988B2 (en) * 2007-07-31 2011-01-25 Seiko Epson Corporation Substrate and manufacturing method of the same, and semiconductor device and manufacturing method of the same
US20090091025A1 (en) * 2007-10-04 2009-04-09 Agency For Science, Technology And Research Method for forming and releasing interconnects
US20100109169A1 (en) * 2008-04-29 2010-05-06 United Test And Assembly Center Ltd Semiconductor package and method of making the same
JP5147677B2 (ja) * 2008-12-24 2013-02-20 新光電気工業株式会社 樹脂封止パッケージの製造方法
US9018758B2 (en) * 2010-06-02 2015-04-28 Taiwan Semiconductor Manufacturing Company, Ltd. Cu pillar bump with non-metal sidewall spacer and metal top cap
US8258055B2 (en) * 2010-07-08 2012-09-04 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming semiconductor die
US8580607B2 (en) * 2010-07-27 2013-11-12 Tessera, Inc. Microelectronic packages with nanoparticle joining
US8076184B1 (en) * 2010-08-16 2011-12-13 Stats Chippac, Ltd. Semiconductor device and method of forming wafer-level multi-row etched leadframe with base leads and embedded semiconductor die
KR101932665B1 (ko) * 2011-10-10 2018-12-27 삼성전자 주식회사 반도체 패키지
US8653658B2 (en) * 2011-11-30 2014-02-18 Taiwan Semiconductor Manufacturing Company, Ltd. Planarized bumps for underfill control
US9646923B2 (en) * 2012-04-17 2017-05-09 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices, methods of manufacture thereof, and packaged semiconductor devices
KR101932727B1 (ko) * 2012-05-07 2018-12-27 삼성전자주식회사 범프 구조물, 이를 갖는 반도체 패키지 및 이의 제조 방법
US9111817B2 (en) * 2012-09-18 2015-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Bump structure and method of forming same
US8975726B2 (en) * 2012-10-11 2015-03-10 Taiwan Semiconductor Manufacturing Company, Ltd. POP structures and methods of forming the same
DE112014001274T5 (de) * 2013-03-13 2015-12-17 Ps4 Luxco S.A.R.L. Halbleitervorrichtung
US9484291B1 (en) * 2013-05-28 2016-11-01 Amkor Technology Inc. Robust pillar structure for semicondcutor device contacts
JP2015162660A (ja) * 2014-02-28 2015-09-07 イビデン株式会社 プリント配線板、プリント配線板の製造方法、パッケージ−オン−パッケージ
US9636675B2 (en) * 2014-11-26 2017-05-02 International Business Machines Corporation Pillar array structure with uniform and high aspect ratio nanometer gaps
US10331161B2 (en) * 2014-12-24 2019-06-25 Fujitsu Limited Power supply board
US10115647B2 (en) * 2015-03-16 2018-10-30 Taiwan Semiconductor Manufacturing Company, Ltd. Non-vertical through-via in package
US10340241B2 (en) * 2015-06-11 2019-07-02 International Business Machines Corporation Chip-on-chip structure and methods of manufacture
US10886250B2 (en) * 2015-07-10 2021-01-05 Invensas Corporation Structures and methods for low temperature bonding using nanoparticles
US9633971B2 (en) * 2015-07-10 2017-04-25 Invensas Corporation Structures and methods for low temperature bonding using nanoparticles
US9984960B2 (en) * 2016-07-21 2018-05-29 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package and method of fabricating the same
US9922896B1 (en) * 2016-09-16 2018-03-20 Taiwan Semiconductor Manufacturing Company, Ltd. Info structure with copper pillar having reversed profile
US11322449B2 (en) * 2017-10-31 2022-05-03 Taiwan Semiconductor Manufacturing Co., Ltd. Package with fan-out structures
US10608642B2 (en) * 2018-02-01 2020-03-31 iCometrue Company Ltd. Logic drive using standard commodity programmable logic IC chips comprising non-volatile radom access memory cells
US10825774B2 (en) * 2018-08-01 2020-11-03 Samsung Electronics Co., Ltd. Semiconductor package
KR20200036981A (ko) * 2018-09-28 2020-04-08 삼성전자주식회사 범프 구조체 및 범프 제조방법

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1326225A (zh) * 2000-05-26 2001-12-12 日本电气株式会社 芯片倒装型半导体器件及其制造方法
US6683368B1 (en) * 2000-06-09 2004-01-27 National Semiconductor Corporation Lead frame design for chip scale package
US6689640B1 (en) * 2000-10-26 2004-02-10 National Semiconductor Corporation Chip scale pin array
CN101313402A (zh) * 2005-11-16 2008-11-26 冲电气工业株式会社 双面电极插件及其制造方法
CN102842515A (zh) * 2011-06-23 2012-12-26 飞思卡尔半导体公司 组装半导体器件的方法
CN103839913A (zh) * 2012-11-27 2014-06-04 英飞凌科技股份有限公司 半导体封装及其形成方法
CN103531560A (zh) * 2013-10-31 2014-01-22 矽力杰半导体技术(杭州)有限公司 芯片的封装结构及其制造方法
CN107293499A (zh) * 2016-03-30 2017-10-24 意法半导体股份有限公司 用于倒装芯片封装件的热超声接合的连接
US10008437B2 (en) * 2016-08-31 2018-06-26 Shinko Electric Industries Co., Ltd. Lead frame and electronic component device

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
田民波著: "《电子封装工程》", 31 October 2005 *

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