CN107293499A - 用于倒装芯片封装件的热超声接合的连接 - Google Patents

用于倒装芯片封装件的热超声接合的连接 Download PDF

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Publication number
CN107293499A
CN107293499A CN201610851698.7A CN201610851698A CN107293499A CN 107293499 A CN107293499 A CN 107293499A CN 201610851698 A CN201610851698 A CN 201610851698A CN 107293499 A CN107293499 A CN 107293499A
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Prior art keywords
lead
nude film
plating layer
surface plating
part according
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CN201610851698.7A
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M·马佐拉
B·维塔利
M·德桑塔
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STMicroelectronics SRL
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STMicroelectronics SRL
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Publication of CN107293499A publication Critical patent/CN107293499A/zh
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Abstract

本公开涉及用于倒装芯片封装件的热超声接合的连接，具体公开了制造封装件的方法。该方法可以包括：在衬底的第一表面上形成接合焊盘；通过在衬底的第二表面中蚀刻凹部在衬底中形成引线，第二表面与第一表面相对；以及使引线的顶面的至少一部分镀敷有表面镀敷层。该方法还可以包括：通过将表面镀敷层热超声地接合至裸片来将引线热超声地接合至裸片，以及在密封剂中密封裸片和引线。

Description

用于倒装芯片封装件的热超声接合的连接
技术领域
本公开总体上涉及倒装芯片封装件，并且更具体地，涉及热超声接合的倒装芯片封装件。
背景技术
无铅(或不含铅)的封装件通常被用于期望小型封装的应用。通常，平坦的无铅封装件提供近似芯片规模的密封封装件，其由附接至半导体裸片的平坦引线框来形成。位于封装件底面上的引线在半导体裸片与衬底(诸如印刷电路板(PCB))之间提供电连接。
典型地，无铅封装件包括半导体裸片或安装至裸片焊盘的芯片，并且电耦合至引线(诸如通过导线)。使封装件更薄的改进消除了裸片焊盘的需要。具体地，引线上芯片(COL)封装件使得半导体裸片直接安装在引线上而不需要裸片焊盘。裸片和引线被密封在封装中以形成封装件。
用于半导体封装的当前应用期望封装件具有减小的厚度以及裸片和引线框架的引线之间的简化连接，以减小体积并增加封装件的信号承载能力。
发明内容
公开了一种制造封装件的方法。该方法可包括：在衬底的第一表面上形成接合焊盘；通过在衬底的第二表面中蚀刻凹部而在衬底中形成引线，第二表面与第一表面相对；以及用表面镀敷(finish plating)层镀敷引线的顶面的至少一部分。该方法还可以包括：通过将表面镀敷层热超声地接合至裸片并且在密封剂中密封裸片和引线来将引线热超声地接合至裸片。
公开了一种半导体封装件。该半导体封装件可以包括：半导体裸片，具有有源表面；引线，具有第一和第二相对端；以及表面镀敷层，位于引线的第一端上。引线可以经由表面镀敷层热超声地耦合至半导体裸片。封装件还可以包括密封剂，其密封裸片和引线并且露出引线的第二端。
公开了一种形成芯片级封装件的方法。该方法可以包括：在衬底的第一表面上形成接合焊盘；以及通过在衬底的第二表面中蚀刻凹部来在衬底中形成引线，其中衬底的第二表面与第一表面相对。该方法还包括：将引线热超声地接合至裸片；以及在密封剂中密封裸片和引线。
附图说明
图1A是根据本公开一个或多个实施例的倒装芯片封装件结构的截面的示意图。
图1B示出了图1A的倒装芯片封装件结构的截面的示意图的细节图。
图2A和图2B是根据本公开一个或多个实施例的处于制造处理的各个阶段的形成在引线框架带中的导电衬底的示意性截面图。
图3A至图3E是倒装芯片封装件(诸如图1A的倒装芯片封装件)的组装的各个阶段的示意性截面图。
图4A是根据本公开一个或多个实施例的引线框架的示意性截面图。
图4B是根据本公开一个或多个实施例的引线框架的示意性截面图。
图5A是根据本公开一个或多个实施例的引线框架的顶侧和裸片的底侧的示意图。
图5B是根据本公开一个或多个实施例的引线框架的顶侧和裸片的底侧的示意图。
具体实施方式
图1A和图1B示出了四方扁平无铅(QFN)半导体封装件100的实施例。封装件100包括环绕引线224和裸片110的密封剂140。图1A示出了封装件100的总体结构，而图1B示出了引线224与裸片110之间的连接的特写图。
裸片110可根据标准半导体制造工艺来制造，并且可以由硅或其他半导体材料制成。裸片110包括其中形成集成电路的有源表面116。集成电路可以是实施为形成在裸片内且根据裸片的电设计和功能而互连的有源器件、无源器件、导电层和介电层的模拟或数字电路。例如，电路可以包括一个或多个形成在有源表面116内的一个或多个晶体管、二极管以及其他电路元件，以实施模拟电路或数字电路，诸如数字信号处理器(DSP)、ASIC、MEMS、存储器或其他信号处理电路。裸片110还可以包含用于RF信号处理的集成无源器件(IPD)，诸如电感器、电容器和电阻器。
在一些实施例中，裸片110包括帮助保护有源表面116和裸片110免受电和物理损伤和污染的钝化层120。钝化层是绝缘材料，诸如金属氧化物，并且通常非常薄，为1至3微米的级别。在一些实施例中，钝化层可以是光敏绝缘体永久层。裸片焊盘上的光敏绝缘体材料可以是聚苯并二恶唑(PBO)或聚酰亚胺材料，并且具有多达10um以上的厚度。
钝化层120包括开口112，其露出裸片110的有源表面116上的接合焊盘113。裸片110的接合焊盘113耦合至引线224。
每条引线224都提供裸片110与封装件100外的环境之间的电和物理耦合。每条引线224均包括接合焊盘226，用于将封装件连接至另一器件或衬底(诸如印刷电路板)，用于与封装件100外的器件通信。
每条引线224均包括表面镀敷层222。表面镀敷层222提供裸片与引线224之间的界面。表面镀敷层222可以包括镍、银或金的一层或多层，其经由电镀敷工艺来沉积。电镀敷工艺使得表面镀敷层222铺设为非常薄的层；例如，镀敷层可以具有基本对应于钝化层120的厚度的厚度或者可以厚于钝化层。尽管未示出，但图案化的掩模可在形成表面镀敷层222之前沉积在第二表面232上，以控制表面镀敷层222的施加，这在本领域是公知的。在形成表面镀敷层222之后，从衬底220的第二侧232去除图案化的掩模层。
表面镀敷层222的厚度可以在5微米和25微米之间。在一些实施例中，表面镀敷层可以具有少至1微米的厚度。在又一些实施例中，表面镀敷层的厚度可多至60微米。在又一些实施例中，表面镀敷层的厚度可小于1微米。
镀敷处理还使得表面镀敷层222形成为各种形状，如以下参照图5A和图5B所描述的；例如，表面镀敷层222的形状可以基本对应于钝化层120中的开口112的形状。具体地，镀敷处理允许形成具有紧公差的表面镀敷层222，诸如1微米的级别。这些公差小于通过例如可以用于形成引线224的其他沉积和蚀刻工艺可用的公差。在一些实施例中，表面镀敷层222的大小对应于引线224的大小，其小于钝化层中的开口的大小。关于这点，在引线224的端部与接合焊盘113之间没有产生间隙。
表面镀敷层222还帮助减小封装件100的整体高度和引线224的长度，尤其与典型的凸起连接处理(其通常涉及在倒装芯片结构中将裸片耦合至引线的导电凸块)相比。经由线缆接合工艺形成在引线顶部处的凸块具有至少25至30微米的厚度，而经由镀敷工艺施加的表面镀敷层具有小至2.5微米的厚度。通过减小引线的长度以及它们与裸片的连接，可以增加封装件100的性能；例如，较短的引线长度可使得裸片110在较高的频率下与电子器件的其他部件通信，这具有更高的数据传送速率。
封装件100还包括密封剂140，其密封裸片110、表面镀敷层222和引线224的部分。裸片110和引线224通过密封剂140保持在封装件100内的其相应位置。密封剂140是绝缘材料，其保护电部件和材料免受损伤，诸如腐蚀、物理损伤、湿气损伤或者对电器件和材料的其他原因的损伤。在一个实施例中，密封剂140可以是任何适当的模塑料，诸如但不限于环氧树脂、酚醛树脂、聚合物或聚酯树脂。终端引线224的基础部分和接触焊盘226保持从密封剂140中露出。
引线224经由热超声接合工艺(其将表面镀敷层222接合至裸片110的有源表面116)而电且机械地耦合至裸片110。热超声接合工艺使用热、摩擦和声音振动以软化表面镀敷层222并将其接合至裸片110的有源表面116。热超声工艺还使得表面镀敷层222的上表面基本平坦并且比例如凸块接合工艺更加均匀。通过电镀敷工艺形成的表面镀敷层222的上表面基本平坦且均匀的形状增加了引线224与裸片110之间的机械连接的强度，尤其与凸块连接工艺相比。
使用热超声接合至裸片110的表面镀敷层222还允许使用不同类型的密封剂，诸如与例如包括引线224与裸片110之间的凸块连接的封装件相比更加容易使用且更便宜的模塑料。典型地，凸块连接在引线的顶部和裸片的有源表面之间留下窄间隙。通常，由于凸块远小于引线224的上表面的尺寸而形成该间隙。在组装期间，使用树脂或模塑料，其可以充分地流动以填充引线的顶部与裸片之间以及凸块周围的间隙，使得裸片能够充分被密封剂支持。从而，本公开的表面镀敷层222与引线224的尺寸和形状更加对准，并且允许紧公差和精确的镀敷形状，使得可以减小或消除间隙。因此，可以使用不同类型的树脂，诸如更容易使用和普通的树脂和模塑料。
图2A和图2B示出了形成具有引线的引线框架的方法的一个实施例，其中引线包括表面镀敷层。如图2A所示，导电衬底220设置有用于引线框架的基础材料。在一些实施例中，衬底220可以是金属材料，诸如铜或铜合金。如图2A所示，接触焊盘226可形成在衬底220的第一表面230上。利用可接合金属材料(诸如Ni、Ag、Ni/Pd、Ni/Pd/Ag、Ni/Pa/Au-Ag合金或Ni/Pd/Au/Ag、或者任何可接合导电材料)，在铜衬底220的底侧230上执行诸如镀敷的沉积工艺，从而形成接触焊盘226。尽管未示出，但如本领域公知的，在形成接触焊盘226之前，可以在第一表面230上沉积光敏材料的图案化掩模层。在形成接触焊盘226之后，从衬底220的第一侧230去除图案化掩模层。
如图2A所示，引线224的顶面被电镀敷有表面镀敷层222。表面镀敷层222是镀敷金属的薄层，其帮助经由热超声接合工艺将衬底220的铜接合至裸片110。表面镀敷层222可以是电和热导体，诸如银、金或镍。在一些实施例中，表面镀敷层222可以包括多个电镀敷层。例如，第一层为镍，接下来为金或银的第二顶层。
表面镀敷层222的厚度可以对应于将附接最终的引线框架的裸片110的钝化层120的厚度。通过将表面镀敷层222形成为具有与钝化层120的厚度相应的厚度，引线224的长度被最小化，从而增加了引线的电特性；例如，与较长引线224所能接受的相比，以更高的质量和更高的频率传输信号。
此外，使用诸如银和金的珍贵金属对制造诸如封装件110的封装件的总体成本具有显著的影响。表面镀敷层222的精确施加使得制造商最小化用于将引线224连接至裸片110的银和金的量。例如，尽管引线224的上表面232可具有相对较大的表面积，但表面镀敷层222可以被施加为小于引线224的整个上表面。例如，表面镀敷层222可形成在引线224上，其尺寸和形状基本对应于引线223将附接至的裸片110的钝化层120中的开口112的尺寸和形状。然而，应该理解，表面镀敷层222稍小于钝化层120中的开口112的尺寸，使得表面镀敷层222适合处于开口112内。此外，通过使表面镀敷层222的厚度充分对应于钝化层120的厚度，使得引线224的上表面不与钝化层120相互干扰，用于表面镀敷层222的材料(诸如金或银)的量可以被最小化。
如图2B所示，执行蚀刻工艺以从第二侧232蚀刻衬底220的露出部分。蚀刻可以是半蚀刻，或者可以蚀刻穿过衬底220的一半以上。在蚀刻工艺期间，在衬底220的第二表面中形成凹部227以形成引线224和引线224之间的边带(webbing)202。在蚀刻工艺期间，图案化掩模(诸如光刻胶膜)可以被施加至衬底220的第二侧232以露出衬底220的表面的用于蚀刻的部分以及覆盖衬底220不被蚀刻的部分。可选地，表面镀敷层222可用作用于形成凹部227的蚀刻掩模。在蚀刻衬底220之后，如果使用的话，则从衬底220的第二侧232去除光刻胶膜，并且第二侧232的剩余部分现在形成每条引线224的顶面。
尽管未示出，但在另一实施例中，表面镀敷层222可以毯式沉积在衬底220的整个第二侧232上，然后进行图案化。在一个或多个蚀刻步骤中，表面镀敷层222被蚀刻并且衬底220被蚀刻，以在表面镀敷层和衬底220中形成通道227，从而形成各个引线224，引线顶部覆有表面镀敷层222。
如图3A所示，多个裸片110耦合至引线224。具体地，裸片110经由热超声接合工艺而附接至引线224，其中通过钝化层120中的开口，表面镀敷层222被压向裸片110的有源表面116，并且经受热和声振动来软化和接合表面镀敷层222至裸片110的接合焊盘。
图3B示出了密封工艺，其中裸片110和终端引线224在其相应的位置中被密封剂140环绕并保持。如上所述，密封剂140是模塑料。衬底220和裸片110的组件被放置在模型中，并且树脂在各个裸片110及其相应的引线224周围和之间流动以填充开放空间，从而为裸片和引线提供不受外部环境影响的结构支持。如上所述，表面镀敷层222的尺寸和形状基本对应于引线224的端部的尺寸和形状。因此，模塑料和树脂不需要在引线的端部与接合焊盘之间的间隙之间流动。
如图3B所示，通过模塑料保持露出衬底220的第一侧230。然后，密封剂140硬化，这可能涉及加热或固化步骤。
一直到制造工艺的该点，衬底220及其与裸片110的接合(尤其是衬底220的被蚀刻引线224之间的边带202)保持部件的相对位置和结构稳定性。在密封剂140硬化之后，密封剂140提供附加的结构支持以保持各个部件(包括裸片110和引线224)的相对位置和结构稳定性。
如图3C所示，去除引线之间的边带202和衬底220的任何其他外来部分。可以经由蚀刻去除边带202和衬底220的其他外来部分，例如上文参照蚀刻衬底220的顶部所描述的。在一些实施例中，接触焊盘226用作用于蚀刻边带202的蚀刻掩模。在完成蚀刻步骤之后，引线相互之间电隔离。
在引线224相互电隔离之后，可以对引线和裸片执行电测试以检查缺陷，如图3D示意性所示出的。如本领域已知的，通过向每个接触焊盘226施加探针180来执行该处理，并且进行各种诊断检查。
在图3E中，执行切割步骤。切割步骤可以包括任何适当的切割工艺来分离各个封装件，诸如机械锯切(切割锯用于沿着线切割封装件100)，或者可以包括激光切割(激光器用于沿着线来分离封装件100进而形成多个单独的封装件100)。
图4A和图4B示出了引线框架结构的两个实施例。在图4A中，表面镀敷层222包括第一镀敷层225(其可以是镍)和第二镀敷层228(其可以是银或金)。引线224和镀敷层222之间的电和机械接合可以通过形成具有导电材料的两层的表面镀敷层222来提高。例如，与金直接与铜接合的能力相比，镍可具有更好的与金和铜接合的能力。因此，与在铜引线上直接镀敷金或银相比，位于第二镀敷层228与引线之间的镍的第一镀敷层225可以提供例如引线224的铜与金或银的第二镀敷层226之间增强的接合。
在图4B中，衬底220包括集成引线227而不具有施加至集成引线227的上表面236的表面镀敷层。在这种实施例中，可以从封装件100的制造工艺中省略表面镀敷工艺，并且衬底材料可以热超声地直接接合至裸片110。例如，如果衬底220由铜片制成，则由铜片形成的铜引线可直接热超声地接合至裸片。
图5A和图5B示出了表面镀敷层的两个实施例，其形成有与钝化层内的开口的尺寸和形状相对应的尺寸和形状，并且还可以是裸片的接合焊盘的形状。在图5A中，裸片110a的钝化层120a中的开口112a具有矩形形状，诸如正方形。位于衬底220a的每条引线224a上方的对应表面镀敷层222具有与钝化层120a中的开口112a的尺寸和形状相对应的尺寸和形状。在一些实施例中，对应开口112a和表面镀敷层222a的尺寸彼此可以基本相似，并且在一些实施例中，对应开口112a的尺寸可大于表面镀敷层222a的尺寸。
图5B示出了裸片110b的钝化层120b的开口112b，其具有圆化形状，诸如圆形、椭圆形或环形。位于衬底220b的每条引线224b上方的对应表面镀敷层222a具有与钝化层120b中的开口112b的尺寸和形状相对应的尺寸和形状。在一些实施例中，对应开口112b和表面镀敷层222b的尺寸彼此可以基本相似，并且在一些实施例中，对应开口112b的尺寸可大于表面镀敷层222b的尺寸。
上述各个实施例可以组合以提供又一些实施例。如果需要使用各个专利、申请和公开的概念，则可以修改实施例的方面以提供又一些实施例。
可以考虑到上面的详细描述对实施例进行这些和其他变化。通常，在以下权利要求中，所使用的术语不应将权利要求限于说明书和权利要求中公开的具体实施例，而是应该包括所有可能的实施例。因此，不通过公开限制权利要求。

Claims (21)

1.一种制造封装件的方法，包括：
在引线框架的第一表面上形成多个表面镀敷层；
蚀刻所述引线框架的所述第一表面以形成引线，其中所述引线的端部包括所述表面镀敷层；
通过热超声接合工艺，将所述表面镀敷层热超声地接合至裸片的接合焊盘；以及
在密封剂中密封所述裸片和所述引线。
2.根据权利要求1所述的制造封装件的方法，还包括：
在所述裸片的有源表面上形成钝化层；
在所述裸片的所述有源表面上的所述钝化层中形成开口；以及
将所述引线的顶面上的所述表面镀敷层插入到所述钝化层的开口中。
3.根据权利要求2所述的制造封装件的方法，其中所述钝化层中的开口形成有第一尺寸和形状，并且所述表面镀敷层形成有对应于所述第一尺寸和形状的第二尺寸和形状。
4.根据权利要求3所述的制造封装件的方法，其中所述第二尺寸小于所述第一尺寸。
5.根据权利要求2所述的制造封装件的方法，其中所述钝化层中的开口形成有第一厚度，并且所述表面镀敷层形成有对应于所述第一厚度的第二厚度。
6.根据权利要求5所述的制造封装件的方法，其中所述第一厚度小于所述第二厚度。
7.根据权利要求1所述的制造封装件的方法，在所述引线框架的第一表面上形成多个表面镀敷层包括：
在所述引线的顶面的至少一部分上镀敷第一表面镀敷子层；以及
至少在所述第一表面镀敷子层的顶面上镀敷第二表面镀敷子层。
8.根据权利要求7所述的制造封装件的方法，其中所述第一表面镀敷子层是镍或镍合金。
9.根据权利要求7所述的制造封装件的方法，其中所述第二表面镀敷子层是银或金。
10.一种形成芯片级封装件的方法，包括：
在引线框架的第一表面上形成接触焊盘；
通过在所述引线框架的第二表面中蚀刻凹部而在所述引线框架中形成引线，所述第二表面与所述第一表面相对；
将所述引线热超声地接合至裸片；以及
在密封剂中密封所述裸片和所述引线。
11.根据权利要求10所述的形成芯片级封装件的方法，还包括：
在形成所述引线之前，使所述引线框架的顶面的至少一部分镀敷有表面镀敷层。
12.根据权利要求10所述的形成芯片级封装件的方法，还包括：
在形成所述引线之后，使所述引线的顶面的至少一部分镀敷有表面镀敷层。
13.根据权利要求11所述的形成芯片级封装件的方法，其中将所述引线热超声地接合至所述裸片包括：将所述表面镀敷层热超声地接合至所述裸片。
14.根据权利要求10所述的形成芯片级封装件的方法，其中所述引线框架是铜引线框架，并且将所述引线热超声地接合至所述裸片包括：将所述铜引线框架的铜热超声地接合至所述裸片。
15.一种半导体封装件，包括：
半导体裸片，具有有源表面；
引线，具有相对的第一端部和第二端部；
表面镀敷层，位于所述引线的第一端部上，所述引线经由所述表面镀敷层直接耦合至所述半导体裸片；
密封剂，密封所述裸片和所述引线并露出所述引线的第二端部。
16.根据权利要求15所述的半导体封装件，还包括：
钝化层，形成在所述裸片的所述有源表面之上；以及
开口，形成在所述钝化层中，露出所述裸片的所述有源表面的部分。
17.根据权利要求16所述的半导体封装件，其中所述钝化层中的开口具有第一形状，并且所述表面镀敷层具有对应于所述第一形状的第二形状。
18.根据权利要求17所述的半导体封装件，其中所述表面镀敷层的尺寸小于所述钝化层中的开口的尺寸。
19.根据权利要求15所述的半导体封装件，其中所述钝化层中的开口具有第一厚度，并且所述表面镀敷层具有对应于所述第一厚度的第二厚度。
20.根据权利要求19所述的半导体封装件，其中所述第一厚度小于所述第二厚度。
21.根据权利要求15所述的半导体封装件，其中所述引线的所述第一端部上的所述表面镀敷层覆盖所述引线的整个所述第一端部。
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