JP7161904B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP7161904B2 JP7161904B2 JP2018192981A JP2018192981A JP7161904B2 JP 7161904 B2 JP7161904 B2 JP 7161904B2 JP 2018192981 A JP2018192981 A JP 2018192981A JP 2018192981 A JP2018192981 A JP 2018192981A JP 7161904 B2 JP7161904 B2 JP 7161904B2
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- metal plate
- sealing resin
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- semiconductor device
- electrode
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
- H01L24/92—Specific sequence of method steps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3512—Cracking
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Ceramic Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
[半導体装置の構成]
図1は、実施例に係る半導体装置1の構成の一例を示す図である。以下では、図1の上側の面を適宜「表面」と呼び、図1の下側の面を適宜「裏面」と呼ぶ。
次に、実施例に係る半導体装置1の製造方法について、図3A~3Iを参照して説明する。図3A~図3Iは、実施例に係る半導体装置1の製造方法の流れの一例を示す説明図である。
図4A~図4Cは、金属板80を形成する工程の一例を示す説明図である。金属板80を形成する工程は、例えば、突起部82と基板10の端子用電極13とを接合する工程(つまり、図3Bに示す工程)の前に、実行される。
上記実施例では、放熱板60と、複数の電極端子50とが独立している例を示したが、開示技術はこれに限られない。例えば、放熱板60は、図5に示すように、複数の電極端子50のうち半導体素子40と隣り合う電極端子50に連結されてもよい。図5は、変形例における放熱板60の構成の一例を示す図である。変形例における放熱板60は、半導体素子40と隣り合う電極端子50を介して基板10と電気的に接続されている。これにより、放熱板60をグランド端子や電源用端子として利用することが可能となる。
12 素子用電極
13 端子用電極
40 半導体素子
41 熱伝導性シート
41a 背面
50 電極端子
51 基端部
511 裾引き部
511a 斜面
52 先端部
522 裾引き部
522a 斜面
60 放熱板
70、75 封止樹脂
80 金属板
81 本体部
82 突起部
821 裾引き部
83 外縁部
85 金型
Claims (4)
- 基板の第1の面に配置された第1の電極に半導体素子を搭載する工程と、
本体部と前記本体部から立ち上がる突起部とを有する金属板を用意する工程と、
前記基板の第1の面に配置された第2の電極に前記突起部を接合することで、前記金属板を前記基板の第1の面側に搭載する工程と、
前記基板の第1の面と前記金属板の前記本体部との間に封止樹脂を充填し、前記半導体素子及び前記突起部を前記封止樹脂により封止する工程と、
前記本体部のうち平面視で前記突起部と重なる部分を残すように前記本体部をエッチングすることで、前記第2の電極に接続され且つ前記封止樹脂に側面が覆われた基端部と、前記基端部と一体的に形成され且つ前記封止樹脂の表面から突出する先端部とからなる電極端子を形成する工程と、
を含み、
前記金属板は、前記本体部において前記突起部を囲む領域から立ち上がる外縁部をさらに有し、
前記封止する工程は、前記金属板の前記外縁部に金型を組み合わせることで、前記金型と前記金属板との間に空間を形成し、前記金型と前記金属板との間の空間に前記封止樹脂を充填することを特徴とする半導体装置の製造方法。 - 前記金属板を用意する工程は、金属平板の一方の面側から前記突起部となる部分以外にハーフエッチングを施すことで前記金属板を形成する工程を含むことを特徴とする請求項1に記載の半導体装置の製造方法。
- 前記金属板を形成する工程において、前記突起部の前記本体部側に、前記本体部側に向かって径が広くなり、且つ斜面が凹曲面である裾引き部を形成し、
前記封止樹脂により封止する工程において、前記封止樹脂で前記裾引き部を覆うことを特徴とする請求項2に記載の半導体装置の製造方法。 - 前記電極端子を形成する工程は、前記本体部のうち平面視で前記半導体素子と重なる部分を残すように前記本体部をエッチングすることで、前記半導体素子の背面を覆う放熱板を前記電極端子と共に形成することを特徴とする請求項1~3のいずれか一つに記載の半導体装置の製造方法。
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JP2014049476A (ja) | 2012-08-29 | 2014-03-17 | Shinko Electric Ind Co Ltd | 電子部品内蔵基板及び電子部品内蔵基板の製造方法 |
JP2018037504A (ja) | 2016-08-31 | 2018-03-08 | 新光電気工業株式会社 | リードフレーム及び電子部品装置とそれらの製造方法 |
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US20090170241A1 (en) | 2007-12-26 | 2009-07-02 | Stats Chippac, Ltd. | Semiconductor Device and Method of Forming the Device Using Sacrificial Carrier |
US9202715B2 (en) * | 2010-11-16 | 2015-12-01 | Stats Chippac Ltd. | Integrated circuit packaging system with connection structure and method of manufacture thereof |
US10141197B2 (en) * | 2016-03-30 | 2018-11-27 | Stmicroelectronics S.R.L. | Thermosonically bonded connection for flip chip packages |
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Patent Citations (5)
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US20100224970A1 (en) | 2009-03-09 | 2010-09-09 | Asat Ltd. | Leadless integrated circuit package having standoff contacts and die attach pad |
US20120061814A1 (en) | 2010-09-14 | 2012-03-15 | Stats Chippac, Ltd. | Semiconductor Device and Method of Forming Leadframe Interposer Over Semiconductor Die and TSV Substrate for Vertical Electrical Interconnect |
JP2014049476A (ja) | 2012-08-29 | 2014-03-17 | Shinko Electric Ind Co Ltd | 電子部品内蔵基板及び電子部品内蔵基板の製造方法 |
JP2018037504A (ja) | 2016-08-31 | 2018-03-08 | 新光電気工業株式会社 | リードフレーム及び電子部品装置とそれらの製造方法 |
CN107799475A (zh) | 2016-08-31 | 2018-03-13 | 新光电气工业株式会社 | 引线框架和电子部件装置 |
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US20200118837A1 (en) | 2020-04-16 |
JP2020061503A (ja) | 2020-04-16 |
US10964553B2 (en) | 2021-03-30 |
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