TWI479580B - 四方平面無導腳半導體封裝件及其製法 - Google Patents

四方平面無導腳半導體封裝件及其製法 Download PDF

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TWI479580B
TWI479580B TW099107207A TW99107207A TWI479580B TW I479580 B TWI479580 B TW I479580B TW 099107207 A TW099107207 A TW 099107207A TW 99107207 A TW99107207 A TW 99107207A TW I479580 B TWI479580 B TW I479580B
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electrical connection
wafer holder
surface layer
wafer
connection pad
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TW201131672A (en
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湯富地
魏慶全
林勇志
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矽品精密工業股份有限公司
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Priority to US12/843,440 priority patent/US8624368B2/en
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Priority to US14/096,272 priority patent/US8835225B2/en
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Description

四方平面無導腳半導體封裝件及其製法
本發明係有關於一種四方平面無導腳半導體封裝件，尤指一種能防止銲料突出(solder extrusion)之四方平面無導腳半導體封裝件及其製法。
四方平面無導腳半導體封裝件為一種使晶片座和接腳底面外露於封裝膠體底部表面的封裝單元，一般係採用表面耦接技術將封裝單元耦接至印刷電路板上，藉此形成一特定功能之電路模組。在表面耦接程序中，四方平面無導腳半導體封裝件的晶片座和接腳係直接銲結至印刷電路板上。
舉例而言，第6,238,952、6,261,864和6,306,685號美國專利揭露一種習知四方平面無導腳半導體封裝件，以下配合第8圖，說明習知四方平面無導腳半導體封裝件及其製法。
習知四方平面無導腳半導體封裝件8，包括以下構件：導線架81，具有晶片座811和複數個接腳813；晶片83，接置於該晶片座811上；複數個銲線84，分別電性連接該晶片83和該些接腳813；以及封裝膠體85，包覆該晶片83、該些銲線84和該導線架81，但該導線架81的晶片座811和複數個接腳813係凸伸於該封裝膠體85外，其原因在於此類四方平面無導腳半導體封裝件8之晶片座811和接腳813係由金屬載體直接蝕刻形成得到，雖然可以增加I/O數量，但該製法僅能提供較多的接腳數目，而無法形成複雜的導電跡線。
如第9A至9C’圖所示，第5830800和6635957號美國專利則揭露另一種四方平面無導腳半導體封裝件9及其製法，首先係於金屬載體90上電鍍形成複數接腳913，接腳913係具有金/鈀/鎳/鈀或鈀/鎳/金之金屬層。接著，依序在接腳913上接置晶片93；以銲線94電性連接晶片93與接腳913及形成封裝膠體95，之後在移除載體90後，於封裝膠體95底面形成介電層96且該介電層96具有複數開口961，最後於該開口961中的接腳913上佈植銲球97。然而，因銲球97在金層或鈀層上的濕潤能力(wetting ability)較佳，但介電層96與金層或鈀層的接合度較差，銲料容易滲入金層和介電層96之界面，產生銲料突出(solder extrusion)962之缺陷現象，使得銲球無法形成，甚至造成相鄰銲球連接之電性短路問題。不但影響後續的表面耦接(SMT)製程，增加製程時間及成本亦降低產品良率。
是以，如何解決上述銲料突出問題，提升I/O數目，兼顧導電跡線之形成、產品良率及製程時間，並開發新穎的四方平面無導腳半導體封裝件及其製法，實為目前亟欲解決的課題。
鑒於以上所述先前技術之缺點，本發明提供一種四方平面無導腳半導體封裝件之製法，係包括：提供一銅載體，該銅載體上形成晶片座及複數個設於該晶片座周圍之電性 連接墊(I/O connection)；對該銅載體、晶片座及電性連接墊施加能量，俾使銅原子遷移及擴散至該晶片座及電性連接墊之底部，以形成表面層；於該晶片座頂面上接置晶片；再以銲線電性連接該晶片與各該電性連接墊；接著於該銅載體上形成封裝膠體，以包覆該晶片座、電性連接墊、晶片及銲線；之後移除該銅載體，以露出該表面層；以及於該封裝膠體、晶片座及電性連接墊底面形成介電層(dielectric layer)，且該介電層具有複數開口，係外露出該表面層。
另一方面，根據前述製法，本發明復提供一種四方平面無導腳半導體封裝件，係包括：晶片座；複數設於該晶片座周圍之電性連接墊；接置於該晶片座頂面上之晶片；複數銲線，分別電性連接該晶片與和該些電性連接墊；封裝膠體，包覆該晶片座、電性連接墊、晶片及該些銲線，但外露出該晶片座和電性連接墊的底部；表面層，形成於該晶片座和電性連接墊的底部上；介電層，係形成於該封裝膠體及表面層底面，且該介電層具有複數外露出該表面層的開口。
由上可知，本發明係於載體上形成晶片座和電性連接墊之方式，亦可滿足設置導電跡線及提升I/O數目的需求。又本發明之四方平面無導腳半導體封裝件及其製法，係藉由施加能量使載體上之金屬原子遷移及擴散至晶片座和電性連接墊底部，以形成表面層，由於該表面層與介電層的接合度較佳，可防止銲料於回銲時滲入晶片座及電性連接墊與介電層之界面的銲料突出缺陷，進而提升產品良率。此外，本發明係於製作封裝件過程透過施加能量之方式形成具有銅原子的表面層，無須使用程序繁複且耗費成本之電鍍或濺鍍，具有縮短製程時間及降低成本之優點。
以下係藉由特定的具體實施例說明本創作之實施方式，所屬技術領域中具有通常知識者可由本說明書所揭示之內容輕易地瞭解本創作之其他優點與功效。
請參閱第1至6圖，係為本發明之四方平面無導腳半導體封裝件及其製法之示意圖。
如第1A及1B圖所示，係提供一銅載體10，以在該銅載體10上形成晶片座111及複數個設於該晶片座111周圍之電性連接墊113或輸入/輸出連接點(I/O connection)，且較佳地，如第1B圖所示，至少部份該電性連接墊113延伸有導電跡線1131。該晶片座111及電性連接墊113可藉由電鍍方式形成，且該晶片座111及電性連接墊113可為金/鈀/鎳/鈀、金/鎳/銅/鎳/銀、金/鎳/銅/銀、鈀/鎳/鈀、金/鎳/金或鈀/鎳/金等之多層金屬其中一者所構成，且較佳地，該金層或鈀層係位於晶片座111及電性連接墊113之底部(指晶片座111以及電性連接墊113接觸該銅載體10之部位)。
復參閱第2A圖，對該銅載體10、晶片座111及電性連接墊113施加如熱能之能量，俾使銅原子遷移及擴散至該晶片座111及電性連接墊113之底部，以在該晶片座111及電性連接墊113之底部的金層或鈀層中形成具有銅原子之表面層12。在此須說明者係部份晶片座111及電性連接墊113底部之金層或鈀層之原子亦可能向銅載體10遷移。如第2B圖所示，以金/鈀/鎳/鈀之多層金屬所構成的晶片座111及電性連接墊113為例，因銅原子的遷移及擴散，故會在部份金層的底部形成表面層12，且該晶片座111及電性連接墊113底部之金或鈀原子亦可能遷移及擴散至銅載體10，故與晶片座111和電性連接墊113底部接觸之載體10部份亦可形成表面層12。其他適合施加之能量還包括電能、光能、磁能或離子束。
此外，該表面層12係可遮覆住該晶片座111及電性連接墊113之全部或部份底部。例如，如第2C圖所示之晶片座及電性連接墊仰視圖，係顯示晶片座111和電性連接墊113底部為金層的態樣，該表面層12係遮覆住該晶片座111及電性連接墊113之金層之部份表面。
如第2D圖所示載體俯視圖，為得到此態樣，可於形成晶片座111和電性連接墊113之前，在該銅載體10上預定之晶片座111和電性連接墊113處及對應後續形成之介電層開口位置設有遮蔽圖案101，以遮覆住該銅載體10之部份銅表面，俾於施加能量時避免銅原子遷移至遮蔽區域。
參閱第3圖，於該晶片座111頂面上接置晶片13，接著以銲線14電性連接該晶片13與各該電性連接墊113，之後再於該銅載體10上形成封裝膠體15，以包覆該晶片座111、電性連接墊113、晶片13及銲線14。
復參閱第4圖，可採用蝕刻之方式移除該銅載體10，以露出該表面層12，由於表面層12與銅載體10之被蝕刻速率不同，因此，該表面層12係可露出於該封裝膠體15底面。
如第5圖所示，於該封裝膠體15及晶片座111、電性連接墊113及導電跡線1131底面形成介電層16，且該介電層16具有複數開口161，係外露出該表面層12，其中，表面層12係使該晶片座111及電性連接墊113之底部不與介電層16接觸。
如第6圖所示，可復包括於該開口161中形成銲球17，並切割該封裝膠體以得到個別的四方平面無導腳半導體封裝件6。
本發明復提供一種四方平面無導腳半導體封裝件6，係包括晶片座111、複數電性連接墊113、晶片13、複數銲線14、封裝膠體15、表面層12及介電層16。
在一態樣中，本發明之四方平面無導腳半導體封裝件復可包括複數銲球17，形成於該開口161中。
所述複數電性連接墊113係設於該晶片座111周圍，且較佳地，至少部份該電性連接墊113延伸有導電跡線1131，而該晶片座111和複數電性連接墊113係可包括選自金、鈀、銀、銅及鎳所組成群組的一種或多種材質，例如，金/鈀/鎳/鈀層依序組成或金/鎳/銅/鎳/銀、金/鎳/銅/銀、鈀/鎳/鈀、金/鎳/金或鈀/鎳/金之多層金屬其中一者所構成。且較佳地，金層或鈀層係該晶片座111及電性連接墊113之底部。
該晶片13係接置於該晶片座111頂面上；複數銲線14係分別電性連接該晶片13與和該些電性連接墊113；該封裝膠體15係包覆該晶片座111、電性連接墊113、晶片13及該些銲線14，但外露出該晶片座111和電性連接墊113的底部。
該表面層12係形成於該晶片座111和電性連接墊113的底部上，該表面層12係因金屬原子的遷移及擴散而形成，使得晶片座111和電性連接墊113部份底部形成表面層12，且因製作封裝件時，與晶片座111和電性連接墊113底部接觸之銅載體10部份亦可形成表面層12，因此，該表面層12係外露出於該封裝膠體15底面。而介電層16係形成於該封裝膠體15及表面層12底面，且該介電層16具有複數外露出該表面層12的開口161。
於另一態樣中，該表面層12係可遮覆住該晶片座111及電性連接墊113之全部或部份底部。例如，如第2C圖所示之仰視圖，係顯示晶片座111和電性連接墊113底部為金層的態樣，該表面層12係遮覆住該晶片座111及電性連接墊113之金層之部份表面。而較佳的態樣則為，該表面層12係形成於介電層16覆蓋晶片座111和電性連接墊113之區域，而未被表面層12遮蔽的部份則可對應介電層16之開口。換言之，所形成之表面層12係使該晶片座111及電性連接墊113之底面不與該介電層16接觸。
請參閱第7圖，係顯示本發明另一四方平面無導腳半導體封裝件7，此態樣之半導體封裝件與前述者大致相同，其差異主要在於該表面層12係遮覆住該晶片座111及電性連接墊113之部分底面，且該晶片座111及電性連接墊113底部、表面層12及介電層16形成階梯狀結構。在此態樣中，該階梯狀結構提供較強韌的銲球接合強度，且同時避免銲料滲入晶片座及電性連接墊與介電層之界面，產生銲料突出之缺陷。
綜上所述，本發明提供一種新穎的四方平面無導腳半導體封裝件及其製法，透過金屬原子的遷移及擴散以於晶片座及電性連接墊底部形成表面層，該表面層與介電層的接合度較佳，可防止銲料於回銲時滲入晶片座及電性連接墊與介電層之界面的銲料突出缺陷，進而提升產品良率。此外，本發明係於製作封裝件過程透過施加能量之方式形成表面層，無須使用程序繁複且耗費成本之電鍍或濺鍍，具有縮短製程時間及降低成本之優點。
以上所述之具體實施例，僅係用以例釋本發明之特點及功效，而非用以限定本發明之可實施範疇，在未脫離本發明上揭之精神與技術範疇下，任何運用本發明所揭示內容而完成之等效改變及修飾，均仍應為下述之申請專利範圍所涵蓋。
10．．．銅載體
90．．．載體
101．．．遮蔽圖案
111、811．．．晶片座
113．．．電性連接墊
1131．．．導電跡線
12．．．表面層
13、83、93．．．晶片
14、84、94．．．銲線
15、85、95．．．封裝膠體
16、96．．．介電層
161、961．．．開口
17、97．．．銲球
6、7、8、9．．．四方平面無導腳半導體封裝件
81．．．導線架
813、913．．．接腳
962．．．銲料突出
第1至6圖係本發明之四方平面無導腳半導體封裝件之製法示意圖，其中，第1A圖為第1B圖虛線1A-1A之剖視圖，第2B圖為第2A圖之局部放大圖，第2C圖為本發明形成有金屬間化合物層之晶片座及電性連接墊仰視圖，第2D圖為具有遮蔽圖案之載體俯視圖；
第7圖係為本發明另一之四方平面無導腳封裝件之剖面示意圖；
第8圖係顯示習知四方平面無導腳半導體封裝件之示意圖；以及
第9A至9C’圖係顯示另一習知四方平面無導腳半導體封裝件及其製法之示意圖，其中，第9C’圖係第9C圖之局部放大圖。
111．．．晶片座
113．．．電性連接墊
12．．．表面層
13．．．晶片
14．．．銲線
15．．．封裝膠體
16．．．介電層
161．．．開口
17．．．銲球
6．．．四方平面無導腳半導體封裝件

Claims (15)

  1. 一種四方平面無導腳半導體封裝件之製法，係包括：提供一銅載體，該銅載體上形成晶片座及複數個設於該晶片座周圍之電性連接墊(I/O connection)；對該銅載體、晶片座及電性連接墊施加能量，該能量為熱能、電能、光能、磁能或離子束，俾使銅原子遷移及擴散至該晶片座及電性連接墊之底部，以令該晶片座及電性連接墊之底部之底區域形成一表面層，且該表面層係包含複數種類金屬之原子，而其中一種原子係為銅原子；於該晶片座頂面上接置晶片；以銲線電性連接該晶片與各該電性連接墊；於該銅載體上形成封裝膠體，以包覆該晶片座、電性連接墊、晶片及銲線；移除該銅載體，以露出該表面層；以及於該封裝膠體、晶片座及電性連接墊底面形成介電層，且該介電層具有複數開口，係外露出該表面層。
  2. 如申請專利範圍第1項之製法，復包括複數經由各該開口與該外露之表面層電性連接之銲球。
  3. 如申請專利範圍第1項之製法，其中，該晶片座及該電性連結墊之底面係金層或鈀層所構成者。
  4. 如申請專利範圍第1項之製法，其中，至少部份該電性連接墊延伸有導電跡線。
  5. 如申請專利範圍第1項之製法，其中，該表面層係遮覆 住該晶片座及電性連接墊之全部或部份底部。
  6. 如申請專利範圍第1項之製法，其中，所形成之表面層係使該晶片座及電性連接墊之底部不與該介電層接觸。
  7. 如申請專利範圍第1項之製法，其中，該銅載體上對應該開口位置具有遮蔽圖案，以遮覆住該銅載體之部份銅表面。
  8. 一種四方平面無導腳半導體封裝件，係包括：晶片座；複數設於該晶片座周圍之電性連接墊；晶片，接置於該晶片座頂面上；複數銲線，分別電性連接該晶片與和該些電性連接墊；封裝膠體，包覆該晶片座、電性連接墊、晶片及該些銲線，但外露出該晶片座和電性連接墊的底部；一表面層，形成於該晶片座和電性連接墊的底部之底區域，且該表面層係包含複數種類金屬之原子，而其中一種原子係為銅原子；以及介電層，係形成於該封裝膠體及表面層底面，且該介電層具有複數外露出該表面層的開口。
  9. 如申請專利範圍第8項之四方平面無導腳半導體封裝件，復包括複數經由各該開口與該外露之表面層電性連接之銲球。
  10. 如申請專利範圍第8項之四方平面無導腳半導體封裝件，其中，該晶片座及該電性連結墊之底面係金層或鈀 層所構成者。
  11. 如申請專利範圍第8項之四方平面無導腳半導體封裝件，其中，且至少部份該電性連接墊延伸有導電跡線。
  12. 如申請專利範圍第8項之四方平面無導腳半導體封裝件，其中，該表面層係具有金及銅或鈀及銅。
  13. 如申請專利範圍第8項之四方平面無導腳半導體封裝件，其中，該晶片座及電性連接墊底部、表面層及介電層形成階梯狀結構。
  14. 如申請專利範圍第8項之四方平面無導腳半導體封裝件，其中，所形成之表面層係使該晶片座及電性連接墊之底部不與該介電層接觸。
  15. 如申請專利範圍第8項之四方平面無導腳半導體封裝件，其中，該表面層係凸出於該封裝膠體底面。
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