TWI404175B - 具電性連接結構之半導體封裝件及其製法 - Google Patents

具電性連接結構之半導體封裝件及其製法 Download PDF

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Publication number
TWI404175B
TWI404175B TW098144920A TW98144920A TWI404175B TW I404175 B TWI404175 B TW I404175B TW 098144920 A TW098144920 A TW 098144920A TW 98144920 A TW98144920 A TW 98144920A TW I404175 B TWI404175 B TW I404175B
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Taiwan
Prior art keywords
wire
layer
semiconductor package
electrical connection
connection structure
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TW098144920A
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English (en)
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TW201123366A (en
Inventor
林邦群
李春源
湯富地
黃建屏
柯俊吉
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矽品精密工業股份有限公司
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Priority to TW098144920A priority Critical patent/TWI404175B/zh
Priority to US12/859,635 priority patent/US8390118B2/en
Publication of TW201123366A publication Critical patent/TW201123366A/zh
Priority to US13/779,077 priority patent/US8716861B2/en
Application granted granted Critical
Publication of TWI404175B publication Critical patent/TWI404175B/zh
Priority to US14/221,667 priority patent/US9177837B2/en

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Description

具電性連接結構之半導體封裝件及其製法
本發明係有關於一種封裝結構及其製法，尤指一種具電性連接結構之半導體封裝件(Quad Flat Non Leaded Package,QFN)及其製法。
傳統晶片係以導線架(Lead Frame)作為晶片承載件以形成一半導體封裝件，而該導線架主要包括一晶片座及形成於該晶片座周圍之複數導腳，於該晶片座上黏接晶片，並以銲線電性連接該晶片與導腳後，再將封裝樹脂包覆該晶片、晶片座、銲線以及導腳之內段而形成該具導線架之半導體封裝件。
就積體電路技術發展而言，在半導體製程上不斷朝向積集度更高的製程演進，且高密度的構裝結構係為業者追求的目標。而晶片尺寸構裝所採用之承載器(carrier)包括：導線架(lead frame)、軟質基板(flexible substrate)或硬質基板(rigid substrate)等，由於導線架具有成本低，加工容易等特性，為電子產品常用之晶片尺寸構裝類型；其中之四方扁平無接腳構裝(QFN)為以導線架為構裝基材之晶片尺寸構裝(lead frame based CSP)，其特徵在於未設置有外導腳，即未形成有用以與外界電性連接之外導腳，而能縮小整體尺寸。
請參閱第1A圖，係美國專利第6,143,981、6,130,115、及6,198,171號所揭示之以導線架作為晶片承載件之四方 扁平無接腳構裝(QFN)之剖視圖；如圖所示，係於具有引腳11之導線架10上固設晶片12，且該晶片12並藉由銲線13電性連接至該引腳11，形成封裝材14以包覆該導線架10、晶片12、及銲線13，並使該導線架10及引腳11之底面外露於該封裝材14表面，使該QFN半導體封裝結構得藉由該外露之引腳11外露表面以直接透過銲錫材料(未以圖式表示)而與外界裝置如印刷電路板(printed circuit board)之外部裝置電性連接。
惟，上述之習知結構，由於該外露之引腳11與封裝材14表面齊平，當該外露之引腳11上形成銲球16以與外部裝置之印刷電路板電性連接時，如第1B圖所示，該銲球16容易產生橋接(solder bridge)，而導致該引腳11之間產生橋接或短路，而造成電性連接不良的情況。
請參閱第2A至2D圖，係美國專利第5,830,800、6,498,099號所揭示之無承載結構之四方扁平無接腳構裝之製法。
如第2A圖所示，係於銅板(copper sheet)20上電鍍形成複數凸出銲墊(electroplated projections)21。
如第2B圖所示，接著，於該凸出銲墊21上接置晶片(chips)22，且該晶片22以金線(gold wires)23電性連接至該凸出銲墊21；然後於該銅板20、凸出銲墊21、晶片22、及金線23上形成封裝膠體24。
如第2C及2D圖所示，移除該銅板20，以露出該凸出銲墊21及封裝膠體24之底部，然後於該外露之封裝膠 體24之底部上形成外露部分凸出銲墊21之抗氧化層(antioxidation coating)25，且於該凸出銲墊21上形成銲球26。
雖然，該抗氧化層25覆蓋住各該凸出銲墊21之部分面積，惟，該抗氧化層25形成於該封裝膠體24之底部，而該抗氧化層25與封裝膠體24之間的熱膨脹係數(CET)並不相同，導致該抗氧化層25與封裝膠體24之間容易產生脫層(delamination)的現象。如第2E圖所示，若該抗氧化層25與封裝膠體24之間產生脫層，則容易因水氣滲入，導致該凸出銲墊21因水氣而產生漏電(leakage)現象，進而導致該電性運作功能不正常，因此影響整體之電性功能。再者，如第2C圖所示，凸出銲墊21與封裝膠體24表面齊平，導致該凸出銲墊21在製程中容易被刮傷；此外，相鄰兩凸出銲墊21亦可能於回銲過程中或因產品實際使用時之熱循環效應而使銲球26滲漏(solder protrusion)入該抗氧化層25與封裝膠體24之界面而造成漏電，甚至短路問題。
另外，晶片22以金線23電性連接至凸出銲墊21，若凸出銲墊21距離晶片22位置較遠時，需使用較長的金線23，使得製造成本提高。
因此，鑒於上述之問題，如何避免習知之半導體封裝件易因熱膨脹係數不相同導致脫層及水氣滲入而產生漏電、避免銲墊刮傷、避免銲球橋接、避免銲錫材料滲漏造成電性短路及避免金線過長造成成本過高等問題，實已成 為目前亟欲解決之課題。
鑒於上述習知技術之種種缺失，本發明揭露一種具電性連接結構之半導體封裝件，係包括：導線層，係具有晶片座及複數環設於該晶片座周圍之導線，其中，各該導線包括線本體、靠近晶片座端之銲指墊及相對之導線終端；晶片，係接置於該晶片座上；銲線，用以電性連接該晶片及各該銲指墊；封裝膠體，係包覆該晶片及銲線，該封裝膠體具有複數供嵌設該晶片座及導線且深度大於該晶片座及導線厚度之凹穴，俾外露出該些導線及該晶片座之表面；防銲層，係形成於該導線層及封裝膠體底面上，且該防銲層具有複數供對應露出各該導線終端的防銲層開孔；以及銲球，係形成於各該防銲層開孔中，以電性連接對應之該導線終端。
前述之半導體封裝件中，該凹穴之深度與該導線層之厚度差介於2至30微米。又，銲指墊係向晶片座延伸，可減少銲線長度，進而降低成本。
本發明復提供一種具電性連接結構之半導體封裝件之製法，係包括：準備具有複數基板單元之金屬板；於各該基板單元上形成圖案化之金屬層；於該金屬層上對應形成導線層，而該導線層係具有晶片座及複數環設於該晶片座周圍之導線，其中，各該導線包括線本體、靠近晶片座端之銲指墊及相對之導線終端；於該晶片座上接置晶片，並以銲線電性連接各該銲指墊；於該晶片、銲線及導線層 上覆蓋封裝膠體；移除該金屬板及金屬層，以露出該導線層，俾令該封裝膠體形成複數嵌設該晶片座及導線且深度大於該晶片座及導線厚度之凹穴；於外露該導線底面側上形成防銲層，以覆蓋該封裝膠體及導線層，且該防銲層中形成有複數防銲層開孔，以令各該防銲層開孔對應露出各該導線終端；於各該防銲層開孔中形成銲球；以及依各該基板單元之邊界切割該封裝膠體，以形成複數半導體封裝件。
依上述之具電性連接結構之半導體封裝件之製法，形成該金屬板之材料可為銅；而形成該金屬層之材料可為銅或選自鎳、錫及鉛所組成群組之一種或多種；又該金屬層之厚度介於2至30微米。
實施上，金屬層及導線層之製法係可包括：於該金屬板上形成阻層，且令該阻層形成有複數阻層開孔；於該阻層開孔中之金屬板上形成該金屬層；於該阻層開孔中之金屬層上形成該導線層；以及移除該阻層，以露出該金屬板及其上之金屬層與導線層。
在本發明之具電性連接結構之半導體封裝件及其製法中，該導線終端之尺寸係大於防銲層開孔，又該導線終端係可為橢圓狀、圓盤狀或十字狀者，但不以此為限。再者，形成該導線層之材料係可包括選自金、鈀及鎳所組成群組的一種或多種。另外，該導線層復具有電源墊及接地墊，且該銲線電性連接該電源墊及接地墊。
在本發明之具電性連接結構之半導體封裝件及其製 法中，該導線終端係部分外露於該防銲層開孔中，各該防銲層開孔復外露部分封裝膠體；各該防銲層開孔復外露部分晶片座底面。
本發明再提供一種具電性連接結構之半導體封裝件，係包括：導線層，係具有複數導線，各該導線包括線本體、靠近端處之接觸墊及導線終端；晶片，係以覆晶方式電性連接於該接觸墊上；封裝膠體，係包覆該晶片及導線層，該封裝膠體具有複數供嵌設該導線層且深度大於該導線層厚度之凹穴，俾外露出該些導線層之表面；防銲層，係形成於該導線層及封裝膠體底面上，且該防銲層具有複數供對應露出各該導線終端的防銲層開孔；以及銲球，係形成於各該防銲層開孔中，以電性連接對應之該導線終端。
前述之半導體封裝件中，該凹穴之深度與該導線層之厚度差介於2至30微米。
本發明另提供一種具電性連接結構之半導體封裝件之製法，係包括：準備具有複數基板單元之金屬板；於各該基板單元上形成圖案化之金屬層；於該金屬層上對應形成導線層，而該導線層係具有複數導線，各該導線包括線本體、靠近端處之接觸墊及導線終端；於該接觸墊上以覆晶方式電性連接晶片；於該晶片及導線層上覆蓋封裝膠體；移除該金屬板及金屬層，以露出該導線層，俾令該封裝膠體形成複數嵌設該導線且深度大於該導線厚度之凹穴；於外露該導線底面側上形成防銲層，以覆蓋該封裝膠體及導線層，且該防銲層中形成有複數防銲層開孔，以令 各該防銲層開孔對應露出各該導線終端；於各該防銲層開孔中形成銲球；以及依各該基板單元之邊界切割該封裝膠體，以形成複數半導體封裝件。
前述之半導體封裝件之製法中，形成該金屬板之材料係為銅，且形成該金屬層之材料係為銅或選自鎳、錫及鉛所組成群組之一種或多種；又該金屬層之厚度介於2至30微米。
前述之半導體封裝件之製法中，該金屬層及導線層之製法係包括：於該金屬板上形成阻層，且令該阻層形成有複數阻層開孔；於該阻層開孔中之金屬板上形成該金屬層；於該阻層開孔中之金屬層上形成該導線層；以及移除該阻層，以露出該金屬板及其上之金屬層與導線層。
前述之半導體封裝件及其製法中，形成該導線層之材料係包括選自金、鈀及鎳所組成群組的一種或多種；該導線終端之尺寸大於該防銲層開孔；該導線終端為橢圓狀、圓盤狀或十字狀；該導線終端係部分外露於該防銲層開孔中；各該防銲層開孔復外露部分封裝膠體。
由上可知，本發明具電性連接結構之半導體封裝件及其製法，令導線向晶片座延伸之，可減少銲線長度，封裝膠體凹穴深度大於該晶片座及導線厚度，是以，防銲層得與該封裝膠體相互嵌卡以提升防銲層附著強度，再者，該防銲層之防銲層開孔令各該導線終端之底面及部分晶片座底面對應露出，而能藉由該防銲層以避免該銲球於熱製程之電性連接過程中發生橋接，此外，由於本發明之製法步 驟中包含金屬層之形成，使得在移除該金屬層後，封裝膠體凹穴深度大於該晶片座及導線厚度，可避免導線層刮傷，又，嵌入凹穴中之防銲層，可藉由防銲層與封裝膠體及導線層的接合，例如，水平及垂直方向上的接合，使得銲錫材料或濕氣侵入封裝件之路徑變長，而能避免因防銲層脫層造成漏電及避免銲錫材料之滲漏所造成之電性短路。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
並須說明的是，本說明書中所敘述之“頂面”與“底面”並非絕對之空間概念，而係隨構成要件之空間關係而變化，亦即，倒置本案圖式中所示之半導體封裝件時，“頂面”即成“底面”而“底面”即成“頂面”。故該等“頂面”、“底面”名詞之使用，係用以說明本發明所揭示之半導體封裝件中構成要件間之連結關係，使本發明所揭示之半導體封裝件在等效之範圍內具有合理之變化與替換，而非用以限定本發明之可實施範圍於一特定之態樣(Embodiment)。
請參閱第3A至3H圖，係說明本發明具電性連接結構之半導體封裝件之製法。
如第3A圖所示，準備具有複數基板單元31之金屬板30，且在本實施例中，該金屬板30之材料係為銅；接著，於該金屬板30上形成阻層32，且於該阻層32中形成複數 阻層開孔320，以露出部分之金屬板30表面。
如第3B圖所示，於該阻層開孔320中之金屬板30上利用如電鍍的方式形成金屬層33，且形成該金屬層33之材料係為銅，或者可選自鎳、錫及鉛所組成群組之一種或多種材料。在此，使用多種材料來形成金屬層亦包括合金的態樣，例如二元合金或三元合金。在此步驟中，該金屬層33的形成係用以提供後續封裝膠體有較大的凹穴深度。較佳地，所形成之金屬層33厚度係介於2至30微米。
如第3C圖所示，接著，於該阻層開孔320中之金屬層33上形成導線層34，而形成該導線層34之材料可包括選自金、鈀及鎳所組成群組的一種或多種，例如，金/鈀/鎳/鈀層依序組成或可倒置形成等。
如第3D及3D’圖所示，其中該第3D’圖係為本實施例之上視圖，第3D圖係為第3D’圖沿3D-3D之剖視圖；如圖所示，移除該阻層32，以於觀察時可見到露出之金屬板30及其上之金屬層33與導線層34；其中，該導線層34係具有晶片座341及複數環設於該晶片座341周圍之導線342，且具體而言，各該導線342包括線本體3421、靠近晶片座341端之銲指墊3422及相對之導線終端3423，該導線層34係具有相對應之頂面34a及底面34b，是以該導線342同樣具有相對應之頂面34a及底面34b。
如第3E圖所示，於該晶片座341上接置晶片35，該晶片35具有相對應之作用面35a與非作用面35b，而該非作用面35b係接置於該晶片座341上，且於該作用面35a 上具有複數信號銲墊、電源銲墊及接地銲墊，而各該信號銲墊、電源銲墊及接地銲墊係以銲線36電性連接至各該銲指墊3422之頂面34a；之後，於該晶片35、銲線36及導線層34上覆蓋封裝膠體37。此外，銲指墊3422係向晶片座341延伸，可減少銲線36長度，進而降低成本。
如第3F圖所示，以例如蝕刻的方式移除該金屬板30及金屬層33，以露出該導線層34，俾令該封裝膠體37形成複數嵌設該晶片座341及導線342且深度大於該晶片座341及導線342厚度之凹穴40。此時，該導線層34係嵌設於該封裝膠體37中，且部分封裝膠體37自導線層34凸出。此外，因製法包含金屬層33之形成，使得在移除該金屬層33後，該封裝膠體之嵌設有導線層34位置處具有凹穴40結構。再者，於金屬層33為非銅質材料之實施例中，可因不同的材質，使得蝕刻之控制更加容易。
如第3G圖所示，於外露該導線342底面側之封裝膠體37及導線層34之表面上形成防銲層38，且於該防銲層38中形成複數防銲層開孔380，以令各該防銲層開孔380對應露出各該導線終端3423及部分晶片座341。
如第3G’圖所示之局部放大圖，該封裝膠體凹穴40之深度H大於導線層之厚度h，具體而言，該凹穴40之深度H與該晶片座341及導線342之厚度h差介於2至30微米。又，嵌入凹穴40中之防銲層38，可藉由防銲層38與封裝膠體37及導線層34的接合，例如，與導線層34接合部位及與封裝膠體37接合部位，使得銲錫材料或濕氣 侵入封裝件之路徑變長，而能避免因防銲層脫層造成漏電及避免銲錫材料之滲漏所造成之電性短路。
如第3H圖所示，於各該防銲層開孔380中形成銲球39；以及依各該基板單元31之邊界切割該封裝膠體37，以形成複數半導體封裝件3。如圖所示，該防銲層38之防銲層開孔380令各該導線終端3423之底面及部分晶片座341對應露出，而能藉由該防銲層開孔380容置銲球39以避免該銲球39於熱製程之電性連接過程中發生橋接。
此外，如第3H’及3H”圖所示，因部分封裝膠體37’(如第3H’圖之斜線部位所示者)自導線層34凸出，故即便銲錫材料欲滲漏入封裝件，亦會受到該凸出之封裝膠體37’阻擋，而銲錫材料不易滲漏入連接相鄰導線層34亦避免濕氣延滲入方向侵入封裝件內，有效避免漏電短路的問題。再者，該防銲層38與導線層34接合部位亦延長濕氣及/或銲錫材料滲入之路徑。
又因導線層34內凹於封裝膠體37內，可避免製造過程中刮傷導線層34，而造成對銲球39銲接不良的現象。
另請參閱第4-1至4-2圖，係為上述之導線342與防銲層開孔380各種非限制性實施態樣。
在本發明中，較佳地，該導線終端3423之尺寸大於該防銲層開孔380，該「尺寸」主要係指在平面上形成的導線終端3423面積大於防銲層開孔380者。此外，該導線終端3423係可為橢圓狀、圓盤狀或十字狀，該不同外觀之導線終端3423可於形成導線層34之步驟中進行變化，故 不在此贅述。
如第4-1至4-2圖所示，該防銲層開孔380係僅令導線終端3423部分外露於該防銲層開孔380中。因此，在封裝件接置到電路板之製程時，有需要重製的時候，由於部分導線終端3423被防銲層38所覆蓋，該導線終端3423與封裝膠體37的接合強度相形提升，可避免導線終端3423之脫離。
本發明復提供一種具電性連接結構之半導體封裝件，係包括：導線層34、晶片35、銲線36、封裝膠體37、防銲層38及銲球39。
所述之導線層34具有相對應之頂面34a及底面34b，且該導線層34具有晶片座341及複數環設於該晶片座341周圍之導線342，而形成該導線層34之材料係可包括選自金、鈀及鎳所組成群組的一種或多種，例如，金/鈀/鎳/鈀層依序組成或可倒置形成。
所述之晶片35係接置於該晶片座341之頂面34a上，該晶片35具有相對應之作用面35a與非作用面35b，而該非作用面35b係接置於該晶片座341上，且於該作用面35a上具有複數信號銲墊、電源銲墊及接地銲墊，而各該信號銲墊、電源銲墊及接地銲墊係以銲線36電性連接至各該銲指墊3422之頂面34a。
所述之封裝膠體37，係係包覆該晶片35及銲線36，該封裝膠體37具有複數供嵌設該晶片座341及導線342且深度大於該晶片座341及導線342厚度之凹穴40，俾外 露出該些導線342及該晶片座341之表面。
所述之防銲層38係形成於該導線層34及封裝膠體37底面上，且該防銲層38具有複數供對應露出各該導線終端3423及部分晶片座341底面的防銲層開孔380。
所述之銲球39係形成於各該防銲層開孔380中，以連接於各該導線終端3423之底面34b及部分晶片座341。
依如本發明製法所得到者，較佳地，該導線終端3423之尺寸大於該防銲層開孔380。此外，該導線終端3423係可為橢圓狀、圓盤狀或十字狀。
如第4-1至4-2圖，該防銲層開孔380係僅令導線終端3423部分外露於該防銲層開孔380中。因此，在封裝件接置到電路板之製程時，有需要重製的時候，由於部分導線終端3423被防銲層38所覆蓋，該導線終端3423與封裝膠體37的接合強度相形提升，可避免導線終端3423之脫離。
請參閱第5圖，本實施例與上述實施例之差異僅在於晶片35’係以覆晶方式電性連接導線層34’，其餘相關半導體封裝件之結構與製法均大致相同，因此不再重複說明相同部分，以下僅說明其相異處，特此敘明。
所述之半導體封裝件中，該導線層34’係僅具有複數導線342，且各該導線342包括線本體3421、靠近端處之接觸墊341’及導線終端3423，以令該晶片35’接置於該接觸墊341’上。
請參閱第6圖，本實施例與第3H圖之實施例之差異 僅在於該導線層34”復具有電源墊3424及接地墊3425，且該銲線36亦電性連接該電源墊3424及接地墊3425。又該電源墊3424及接地墊3425係可為環狀。
本發明具電性連接結構之半導體封裝件及其製法，係於該金屬板上形成金屬層及與其相對應之導線層，且於該金屬板之各基板單元的晶片座上接置晶片，並且以封裝膠體進行封裝，之後移除該金屬板及金屬層，以露出該導線層，且於該封裝膠體及導線層上形成防銲層，接著於該防銲層中形成複數防銲層開孔，以令各該防銲層開孔對應露出各該導線終端之底面及部分晶片座，俾使該導線層嵌設於該封裝膠體中且為該防銲層所覆蓋，最後，於各該防銲層開孔中形成銲球，令各該銲球電性連接於各該導線之底面及部分晶片座，而能藉由該防銲層以避免該銲球於熱製程之電性連接過程中發生橋接的情況。此外，由於本發明之製法步驟中包含金屬層之形成，使得在移除該金屬層後，該嵌設有導線層位置處具有凹穴結構，而於形成防銲層後，令部分防銲層亦嵌入凹穴結構中，提升防銲層之附著力，並使濕氣侵入封裝件之途徑較習知更長，而能避免因防銲層脫層造成漏電及避免銲錫材料之滲漏所造成之電性短路。
另外，本發明之半導體封裝件中，因導線層內凹於封裝膠體內，可避免製造過程中刮傷導線層，而造成對銲球銲接不良的現象。又，向晶片座延伸之銲指墊，可減少銲線長度，進而降低成本。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
10‧‧‧導線架
11‧‧‧引腳
12‧‧‧晶片
13‧‧‧銲線
14‧‧‧封裝材
16‧‧‧銲球
20‧‧‧銅板
21‧‧‧凸出銲墊
22‧‧‧晶片
23‧‧‧金線
24‧‧‧封裝膠體
25‧‧‧抗氧化層
26‧‧‧銲球
3‧‧‧半導體封裝件
30‧‧‧金屬板
31‧‧‧基板單元
32‧‧‧阻層
320‧‧‧阻層開孔
33‧‧‧金屬層
34、34’、34”‧‧‧導線層
341‧‧‧晶片座
341’‧‧‧接觸墊
342‧‧‧導線
34a‧‧‧頂面
34b‧‧‧底面
3421‧‧‧線本體
3422‧‧‧銲指墊
3423‧‧‧導線終端
3424‧‧‧電源墊
3425‧‧‧接地墊
35、35’‧‧‧晶片
35a‧‧‧作用面
35b‧‧‧非作用面
36‧‧‧銲線
37、37’‧‧‧封裝膠體
38‧‧‧防銲層
380‧‧‧防銲層開孔
39‧‧‧銲球
40‧‧‧凹穴
AA‧‧‧虛線
h‧‧‧厚度
H‧‧‧深度
第1A及1B圖係為習知以導線架作為晶片承載件之四方扁平無接腳構裝(QFN)之剖視圖；第2A至2E圖係為美國專利第5,830,800、6,498,099號之無承載結構之四方扁平無接腳構裝之製法示意圖；第3A至3H圖係為本發明具電性連接結構之半導體封裝件之製法的剖視示意圖；其中，該第3D’圖係為本實施例之上視圖，第3D圖係為第3D’圖之剖視圖，該第3G’圖係第3G圖之局部放大圖，該第3H’圖係第3H圖之局部放大下視圖，第3H”圖係第3H’圖AA虛線之剖面示意圖；第4-1至4-2圖係為本發明導線終端及防銲層開孔之各種實施態樣下視圖；第5圖係為本發明具電性連接結構之半導體封裝件之其中一實施例的剖視示意圖；以及第6圖係為本發明具電性連接結構之半導體封裝件之另一實施例的剖視示意圖。
3‧‧‧半導體封裝件
31‧‧‧基板單元
34‧‧‧導線層
341‧‧‧晶片座
342‧‧‧導線
34a‧‧‧頂面
3423‧‧‧導線終端
34b‧‧‧底面
35‧‧‧晶片
36‧‧‧銲線
37‧‧‧封裝膠體
38‧‧‧防銲層
380‧‧‧防銲層開孔
39‧‧‧銲球

Claims (29)

  1. 一種具電性連接結構之半導體封裝件，係包括：導線層，係具有晶片座及複數環設於該晶片座周圍之導線，其中，各該導線包括線本體、靠近晶片座端之銲指墊及相對之導線終端；晶片，係接置於該晶片座上；銲線，用以電性連接該晶片及各該銲指墊；封裝膠體，係包覆該晶片及銲線，該封裝膠體具有複數供嵌設該晶片座及導線且深度大於該晶片座及導線厚度之凹穴，俾外露出該些導線及該晶片座之表面；防銲層，係形成於該導線層及封裝膠體底面上，且該防銲層具有複數供對應露出各該導線終端的防銲層開孔；以及銲球，係形成於各該防銲層開孔中，以電性連接對應之該導線終端。
  2. 如申請專利範圍第1項所述之具電性連接結構之半導體封裝件，其中，形成該導線層之材料係包括選自金、鈀及鎳所組成群組的一種或多種。
  3. 如申請專利範圍第1項所述之具電性連接結構之半導體封裝件，其中，該導線終端之尺寸大於該防銲層開孔。
  4. 如申請專利範圍第1項所述之具電性連接結構之半導體封裝件，其中，該導線終端為橢圓狀、圓盤狀或十字狀。
  5. 如申請專利範圍第1項所述之具電性連接結構之半導體封裝件，其中，該導線終端係部分外露於該防銲層開 孔中。
  6. 如申請專利範圍第5項所述之具電性連接結構之半導體封裝件，其中，各該防銲層開孔復外露部分封裝膠體。
  7. 如申請專利範圍第1項所述之具電性連接結構之半導體封裝件，其中，該防銲層開孔復外露部分晶片座底面。
  8. 如申請專利範圍第1項所述之具電性連接結構之半導體封裝件，其中，該凹穴之深度與該晶片座及導線之厚度差介於2至30微米。
  9. 如申請專利範圍第1項所述之具電性連接結構之半導體封裝件，其中，該導線層復具有電源墊及接地墊，且該銲線電性連接該電源墊及接地墊。
  10. 一種具電性連接結構之半導體封裝件之製法，係包括：準備具有複數基板單元之金屬板；於各該基板單元上形成圖案化之金屬層；於該金屬層上對應形成導線層，而該導線層係具有晶片座及複數環設於該晶片座周圍之導線，其中，各該導線包括線本體、靠近晶片座端之銲指墊及相對之導線終端；於該晶片座上接置晶片，並以銲線電性連接各該銲指墊；於該晶片、銲線及導線層上覆蓋封裝膠體；移除該金屬板及金屬層，以露出該導線層；於外露該導線底面側上形成防銲層，以覆蓋該封裝膠體及導線層，且該防銲層中形成有複數防銲層開孔， 以令各該防銲層開孔對應露出各該導線終端；於各該防銲層開孔中形成銲球；以及依各該基板單元之邊界切割該封裝膠體，以形成複數半導體封裝件。
  11. 如申請專利範圍第10項所述之具電性連接結構之半導體封裝件之製法，其中，該金屬板之材料係為銅。
  12. 如申請專利範圍第10項所述之具電性連接結構之半導體封裝件之製法，其中，形成該金屬層之材料係為銅。
  13. 如申請專利範圍第10項所述之具電性連接結構之半導體封裝件之製法，其中，形成該金屬層之材料係選自鎳、錫及鉛所組成群組之一種或多種。
  14. 如申請專利範圍第10項所述之具電性連接結構之半導體封裝件之製法，其中，形成該導線層之材料係包括選自金、鈀及鎳所組成群組的一種或多種。
  15. 如申請專利範圍第10項所述之具電性連接結構之半導體封裝件之製法，其中，該金屬層及導線層之製法係包括：於該金屬板上形成阻層，且令該阻層形成有複數阻層開孔；於該阻層開孔中之金屬板上形成該金屬層；於該阻層開孔中之金屬層上形成該導線層；以及移除該阻層，以露出該金屬板及其上之金屬層與導線層。
  16. 如申請專利範圍第10項所述之具電性連接結構之半導 體封裝件之製法，其中，該導線終端之尺寸大於該防銲層開孔。
  17. 如申請專利範圍第10項所述之具電性連接結構之半導體封裝件之製法，其中，該導線終端係為橢圓狀、圓盤狀或十字狀。
  18. 如申請專利範圍第10項所述之具電性連接結構之半導體封裝件之製法，其中，該導線終端係部分外露於該防銲層開孔中。
  19. 如申請專利範圍第18項所述之具電性連接結構之半導體封裝件之製法，其中，各該防銲層開孔復外露部分封裝膠體。
  20. 如申請專利範圍第10項所述之具電性連接結構之半導體封裝件之製法，其中，各該防銲層開孔復外露部分晶片座底面。
  21. 如申請專利範圍第10項所述之具電性連接結構之半導體封裝件之製法，其中，該金屬層之厚度介於2至30微米。
  22. 如申請專利範圍第10項所述之具電性連接結構之半導體封裝件之製法，其中，該導線層復具有電源墊及接地墊，且該銲線電性連接該電源墊及接地墊。
  23. 一種具電性連接結構之半導體封裝件，係包括：導線層，係具有複數導線，各該導線包括線本體、靠近端處之接觸墊及導線終端；晶片，係覆晶方式電性連接於該接觸墊上； 封裝膠體，係包覆該晶片及導線層，該封裝膠體具有複數供嵌設該導線層且深度大於該導線層厚度之凹穴，俾外露出該些導線層之表面；防銲層，係形成於該導線層及封裝膠體底面上，且該防銲層具有複數供對應露出各該導線終端的防銲層開孔；以及銲球，係形成於各該防銲層開孔中，以電性連接對應之該導線終端。
  24. 如申請專利範圍第23項所述之具電性連接結構之半導體封裝件，其中，形成該導線層之材料係包括選自金、鈀及鎳所組成群組的一種或多種。
  25. 如申請專利範圍第23項所述之具電性連接結構之半導體封裝件，其中，該導線終端之尺寸大於該防銲層開孔。
  26. 如申請專利範圍第23項所述之具電性連接結構之半導體封裝件，其中，該導線終端為橢圓狀、圓盤狀或十字狀。
  27. 如申請專利範圍第23項所述之具電性連接結構之半導體封裝件，其中，該導線終端係部分外露於該防銲層開孔中。
  28. 如申請專利範圍第27項所述之具電性連接結構之半導體封裝件，其中，各該防銲層開孔復外露部分封裝膠體。
  29. 如申請專利範圍第23項所述之具電性連接結構之半導體封裝件，其中，該凹穴之深度與該導線層之厚度差介於2至30微米。
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