TWI419278B - 封裝基板及其製法 - Google Patents

封裝基板及其製法 Download PDF

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TWI419278B
TWI419278B TW099136401A TW99136401A TWI419278B TW I419278 B TWI419278 B TW I419278B TW 099136401 A TW099136401 A TW 099136401A TW 99136401 A TW99136401 A TW 99136401A TW I419278 B TWI419278 B TW I419278B
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layer
circuit
package substrate
pad
dielectric layer
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TW099136401A
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TW201218332A (en
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Paohung Chou
Hsien Min Chang
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Unimicron Technology Corp
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Priority to TW099136401A priority Critical patent/TWI419278B/zh
Priority to CN2011101124154A priority patent/CN102456649A/zh
Priority to US13/191,807 priority patent/US9230895B2/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0097—Processing two or more printed circuits simultaneously, e.g. made from a common substrate, or temporarily stacked circuit boards
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/107—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by filling grooves in the support with conductive material
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/02—Electroplating of selected surface areas
    • H—ELECTRICITY
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48105—Connecting bonding areas at different heights
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H—ELECTRICITY
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0364—Conductor shape
    • H05K2201/0376—Flush conductors, i.e. flush with the surface of the printed circuit
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/15—Position of the PCB during processing
    • H05K2203/1536—Temporarily stacked PCBs
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    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
    • H05K3/282—Applying non-metallic protective coatings for inhibiting the corrosion of the circuit, e.g. for preserving the solderability

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Description

封裝基板及其製法
　　本發明係有關一種封裝基板及其製法，尤指一種具單層線路層的封裝基板及其製法。
　　於半導體晶片的封裝歷史中，導線架式(lead frame)封裝基板已經長期被使用，其主要原因係其具有較低製造成本與較高可靠度之優點；此外，對於輸入/輸出(I/O)數目較低之半導體晶片而言，導線架式封裝基板在成本上仍極具有競爭力。
　　在某些情況下，例如：較為單純或簡單的電子產品的情形中，其所需的封裝基板僅需具有單層之線路層。
　　請參閱第1A至1G圖，係習知之具單層線路層之封裝基板及其製法之剖視圖。
　　如第1A圖所示，提供一承載板10，其兩表面均設有銅層11。
　　如第1B圖所示，於一該銅層11上形成阻層12，且該阻層12具有複數外露該銅層11的開孔120。
　　如第1C圖所示，移除未被該阻層12所覆蓋的銅層11，而於該承載板10上形成一線路層111。
　　如第1D圖所示，移除該阻層12。
　　如第1E圖所示，以雷射形成複數貫穿之通孔100，該通孔100之一端連通該線路層111。
　　如第1F圖所示，於該承載板10具有該線路層111之一側形成第一絕緣保護層13，該第一絕緣保護層13具有複數第一絕緣保護層開口130以外露部分該線路層111，並於該承載板10之另一側形成第二絕緣保護層14，該第二絕緣保護層14具有複數第二絕緣保護層開口140以對應外露各該通孔100。
　　如第1G圖所示，於該線路層111之外露表面上形成表面處理層15，以供接置焊料球(未圖示)之用。
　　惟，習知之具單層線路層之封裝基板最終仍具有用以支承該線路層的承載板，所以整體封裝基板的厚度約為130微米，其與一般具雙層線路層之封裝基板相近，故不利於電子產品的輕薄化。
　　因此，如何避免習知技術中之封裝基板的厚度過大而難以微小化等問題，實已成為目前亟欲解決的課題。
　　鑑於上述習知技術之種種缺失，本發明之主要目的係提供一種厚度較小的封裝基板及其製法。
　　為達上述及其他目的，本發明揭露一種封裝基板，係包括：介電層；線路層，係嵌設於該介電層中，且該線路層係外露於該介電層之相對兩表面，該線路層具有焊指墊、接觸墊、及電性連接該焊指墊與接觸墊的線路；以及第一絕緣保護層，係設於該介電層之一側表面，且覆蓋該介電層與線路層，並具有複數接觸墊用開孔，以對應外露各該接觸墊。
　　前述之封裝基板中，復可包括第二絕緣保護層，係設於該介電層與線路層之另一側表面，且具有複數焊指墊用開孔，以對應外露各該焊指墊，又復可包括表面處理層，係設於該焊指墊與接觸墊之外露表面上。
　　依上述之封裝基板，復可包括表面處理層，係設於該線路層之外露表面上。
　　本發明提供另一種封裝基板，係包括：介電層；以及 線路層，係嵌設於該介電層中，且該線路層具有焊指墊、接觸墊、及電性連接該焊指墊與接觸墊的線路，該線路層係外露於該介電層之一表面，於該介電層之另一表面具有複數接觸墊用開孔，以對應外露各該接觸墊。
　　前述之封裝基板中，復可包括絕緣保護層，係設於外露該線路層之介電層與線路層之表面，且具有複數焊指墊用開孔，以對應外露各該焊指墊，又復可包括表面處理層，係設於該焊指墊與接觸墊之外露表面上。
　　依上述之封裝基板，復可包括表面處理層，係設於該線路層之外露表面上。
　　於本發明之封裝基板中，該介電層之材質可為防焊材料或環氧樹脂。
　　本發明復提供一種封裝基板之製法，係包括：提供一承載板，其兩表面均設有第一金屬層，各該第一金屬層上設有第二金屬層； 於各該第二金屬層上以電鍍方式形成圖案化之線路層，各該線路層具有焊指墊、接觸墊、及電性連接該焊指墊與接觸墊的線路；於該第二金屬層與線路層上形成介電層；移除該線路層上的介電層之部分厚度，以外露該線路層之一側；移除該承載板與第一金屬層；移除該第二金屬層，以外露該線路層之另一側；以及於該介電層之一側表面形成覆蓋該介電層與線路層的第一絕緣保護層，並於該第一絕緣保護層中形成複數接觸墊用開孔，以對應外露各該接觸墊。
　　依上所述之封裝基板之製法，移除該線路層上方的部分介電層之方式可為研磨該介電層表面使其與該線路層同高。
　　前述之封裝基板之製法中，復可包括於外露該焊指墊之介電層表面形成覆蓋該介電層與線路層的第二絕緣保護層，且於該第二絕緣保護層中形成複數焊指墊用開孔，以對應外露各該焊指墊，又復可包括於外露之該焊指墊與接觸墊表面上形成表面處理層。
　　於所述之封裝基板之製法中，復可包括於外露之該線路層表面上形成表面處理層。
　　本發明又提供另一種封裝基板之製法，係包括：提供一承載板，其兩表面均設有第一金屬層，各該第一金屬層上設有第二金屬層；於各該第二金屬層上以電鍍方式形成圖案化之線路層，各該線路層具有焊指墊、接觸墊、及電性連接該焊指墊與接觸墊的線路；於該第二金屬層與線路層上形成介電層；於該介電層中形成複數接觸墊用開孔，以對應外露各該接觸墊；移除該承載板與第一金屬層；以及移除該第二金屬層，以外露該線路層。
　　依上所述之封裝基板之製法，形成該接觸墊用開孔之方式可為雷射燒灼或曝光顯影，且該介電層之材質可為防焊材料或環氧樹脂。
　　前述之封裝基板之製法中，復可包括於外露該焊指墊之介電層表面形成覆蓋該介電層與線路層的絕緣保護層，且於該絕緣保護層中形成複數焊指墊用開孔，以對應外露各該焊指墊，又復可包括於該外露之焊指墊與接觸墊表面上形成表面處理層。
　　於上述之封裝基板之製法中，復可包括於該外露之線路層表面上形成表面處理層。
　　由上可知，本發明之封裝基板係以介電層作為基底的具單層線路層的封裝基板，使該介電層直接與線路層結合在同一層中，而最終可大幅降低封裝基板的整體厚度，進而有利於電子產品的輕薄化；此外，本發明可在單次製程中製作兩個封裝基板，且置於中間的承載板可重複再利用，所以能降低生產成本。
　　以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
第一實施例
　　請參閱第2A至2J圖，係本發明之封裝基板及其製法的第一實施例的剖視圖，其中，第2H'與2H''圖係第2H圖之俯視圖的不同實施態樣，第2I'與2J'圖分別係第2I與2J圖之另一實施態樣。
　　如第2A圖所示，提供一承載板20，其兩表面均設有第一金屬層21，各該第一金屬層21上設有第二金屬層22。
　　如第2B圖所示，於各該第二金屬層22上形成阻層23，且令該阻層23具有複數外露該第二金屬層22表面的圖案化開口區230。
　　如第2C圖所示，於該圖案化開口區230中形成線路層24。
　　如第2D圖所示，移除該阻層23，各該線路層24具有焊指墊(finger)241、接觸墊(contact pad)242及電性連接該焊指墊241與接觸墊242的線路243。
　　如第2E圖所示，於該第二金屬層22與線路層24上形成介電層25。
　　如第2F圖所示，移除該線路層24上的介電層25之部分厚度，以外露該線路層24之一側，移除該線路層24上方的部分介電層25之方式可為研磨該介電層25表面使其與該線路層24同高。
　　如第2G圖所示，移除該承載板20與第一金屬層21。
　　如第2H圖所示，移除該第二金屬層22，以外露該線路層24之另一側。
　　第2H'與2H''圖係第2H圖之俯視圖的不同實施態樣，第2H'圖係一實施態樣，其中該接觸墊242係應用於四方平面無引腳(Quad Flat No leads，簡稱QFN)封裝之焊腳墊；而第2H''圖係另一實施態樣，其中該接觸墊242係可應用於球柵陣列(Ball Grid Array，簡稱BGA)封裝之焊球墊。
　　如第2I圖所示，於該介電層25之一側表面形成覆蓋該介電層25與線路層24的第一絕緣保護層26，並於該第一絕緣保護層26中形成複數接觸墊用開孔260，以對應外露各該接觸墊242；且於外露之該線路層24表面上形成表面處理層29。或者，如第2I'圖所示，復於外露該焊指墊241之介電層25表面形成覆蓋該介電層25與線路層24的第二絕緣保護層27，且於該第二絕緣保護層27中形成複數焊指墊用開孔270，以對應外露各該焊指墊241；再於外露之該焊指墊241與接觸墊242表面上形成表面處理層29，前述之表面處理層29之材質可為鎳/金(Ni/Au)或化鎳鈀浸金(Electroless Nickel / Electroless Palladium / Immersion Gold，簡稱ENEPIG)；又於第2I'圖之實施態樣中，該表面處理層29之材質亦可為有機保焊層(Organic Solderability Preservative，簡稱OSP)。
　　如第2J與2J'圖所示，分別係第2I與2I'圖之封裝基板之應用例，於該封裝基板之置晶區上接置半導體晶片30，該半導體晶片30具有一作用面30a，該作用面30a上具有複數電極墊301，並藉由焊線31以對應電性連接各該電極墊301與焊指墊241，且形成包覆該半導體晶片30與焊線31的封裝材料32，而完成一封裝結構。
　　要注意的是，於完成如第2J或2J'圖之封裝結構後，亦可依據後續的應用情況而於該表面處理層29上形成焊料球(未圖示)，以電性連接至例如電路板的外部電子裝置。
　　本發明復提供一種封裝基板，係包括：介電層25，該介電層25之材質可為環氧樹脂(epoxy)；線路層24，係嵌設於該介電層25中，且該線路層24係外露於該介電層25之相對兩表面，該線路層24具有焊指墊241、接觸墊242及電性連接該焊指墊241與接觸墊242的線路243；以及第一絕緣保護層26，係設於該介電層25之一側表面，且覆蓋該介電層25與線路層24，並具有複數接觸墊用開孔260，以對應外露各該接觸墊242。
　　所述之封裝基板中，復包括第二絕緣保護層27，係設於該介電層25與線路層24之另一側表面，且具有複數焊指墊用開孔270，以對應外露各該焊指墊241。
　　於上述之封裝基板中，復包括表面處理層29，係設於該線路層24之外露表面上。
　　於本發明之封裝基板中，復包括表面處理層29，係設於該焊指墊241與接觸墊242之外露表面上。
第二實施例
　　請參閱第3A至3D圖，係本發明之封裝基板及其製法的第二實施例的剖視圖，其中，第3C-2、3D-2與3D'-2圖分別係第3C-1、3D-1與3D'-1圖之另一實施態樣，第3D'-1與3D'-2圖分別係第3D-1與3D-2圖之另一實施態樣。
　　如第3A圖所示，其係延續自第2E圖，於該介電層25中形成複數接觸墊用開孔250，以對應外露各該接觸墊242，形成該接觸墊用開孔250之方式可為雷射燒灼或曝光顯影。
　　如第3B圖所示，移除該承載板20與第一金屬層21。
　　如第3C-1或3C-2圖所示，移除該第二金屬層22，以外露該線路層24。
　　如第3D-1或3D-2圖所示，於外露該焊指墊241之介電層25表面形成覆蓋該介電層25與線路層24的絕緣保護層28，且於該絕緣保護層28中形成複數焊指墊用開孔280，以對應外露各該焊指墊241，並於該外露之焊指墊241與接觸墊242表面上形成表面處理層29。
　　或者，如第3D'-1或3D'-2圖所示，於該外露之線路層24表面上形成表面處理層29，前述之表面處理層29之材質可為鎳/金(Ni/Au)或化鎳鈀浸金(Electroless Nickel / Electroless Palladium / Immersion Gold，簡稱ENEPIG)。
　　要說明的是，該介電層25之材質可為環氧樹脂(epoxy)或防焊材料，而分別對應至第3C-1、3D-1與3D'-1圖、以及第3C-2、3D-2與3D'-2圖之實施態樣。
　　本發明並提供另一種封裝基板，係包括：介電層25；以及線路層24，係嵌設於該介電層25中，且該線路層24具有焊指墊241、接觸墊242及電性連接該焊指墊241與接觸墊242的線路243，該線路層24係外露於該介電層25之一表面，於該介電層25之另一表面具有複數接觸墊用開孔250，以對應外露各該接觸墊242。
　　於所述之封裝基板中，復包括絕緣保護層28，係設於外露該線路層24之介電層25與線路層24之表面，且具有複數焊指墊用開孔280，以對應外露各該焊指墊241。
　　本發明之封裝基板中，復包括表面處理層29，係設於該線路層24之外露表面上。
　　依前所述之封裝基板中，復包括表面處理層29，係設於該焊指墊241與接觸墊242之外露表面上。
　　綜上所述，不同於習知技術，本發明之封裝基板係以介電層作為基底的具單層線路層的封裝基板，使該介電層直接與線路層結合在同一層中，而最終可大幅降低整體厚度，以達到輕薄化的目的；此外，本發明可在單次製程中製作兩個封裝基板，且置於中間的承載板可重複再利用，所以能降低生產成本。
　　上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
10、20‧‧‧承載板
100‧‧‧通孔
11‧‧‧銅層
111、24‧‧‧線路層
12、23‧‧‧阻層
120‧‧‧開孔
13、26‧‧‧第一絕緣保護層
130‧‧‧第一絕緣保護層開口
14、27‧‧‧第二絕緣保護層
140‧‧‧第二絕緣保護層開口
15、29‧‧‧表面處理層
21‧‧‧第一金屬層
22‧‧‧第二金屬層
230‧‧‧圖案化開口區
241‧‧‧焊指墊
242‧‧‧接觸墊
243‧‧‧線路
25‧‧‧介電層
250、260‧‧‧接觸墊用開孔
270、280‧‧‧焊指墊用開孔
28‧‧‧絕緣保護層
30‧‧‧半導體晶片
30a‧‧‧作用面
301‧‧‧電極墊
31‧‧‧焊線
32‧‧‧封裝材料
　　第1A至1G圖係習知之具單層線路層之封裝基板及其製法之剖視圖；
　　第2A至2J圖係本發明之封裝基板及其製法的第一實施例的剖視圖，其中，第2H'與2H''圖係第2H圖之俯視圖的不同實施態樣，第2I'與2J'圖分別係第2I與2J圖之另一實施態樣，第2J與2J'圖分別係第2I與2I'圖之應用例；以及
　　第3A至3D圖係本發明之封裝基板及其製法的第二實施例的剖視圖，其中，第3C-2、3D-2與3D'-2圖分別係第3C-1、3D-1與3D'-1圖之另一實施態樣，第3D'-1與3D'-2圖分別係第3D-1與3D-2圖之另一實施態樣。
241‧‧‧焊指墊
242‧‧‧接觸墊
25‧‧‧介電層
26‧‧‧第一絕緣保護層
260‧‧‧接觸墊用開孔
29‧‧‧表面處理層

Claims (8)

  1. 一種封裝基板之製法，係包括：提供一承載板，其兩表面均設有第一金屬層，各該第一金屬層上設有第二金屬層；於各該第二金屬層上以電鍍方式形成圖案化之線路層，各該線路層具有焊指墊、接觸墊、及電性連接該焊指墊與接觸墊的線路；於該第二金屬層與線路層上形成介電層；移除該線路層上的介電層之部分厚度，以外露該線路層之一側；移除該承載板與第一金屬層；移除該第二金屬層，以外露該線路層之另一側；以及於該介電層之一側表面形成覆蓋該介電層與線路層的第一絕緣保護層，並於該第一絕緣保護層中形成複數接觸墊用開孔，以對應外露各該接觸墊。
  2. 如申請專利範圍第1項所述之封裝基板之製法，其中，移除該線路層上方的部分介電層之方式係研磨該介電層表面使其與該線路層同高。
  3. 如申請專利範圍第1項所述之封裝基板之製法，復包括於外露該焊指墊之介電層表面形成覆蓋該介電層與線路層的第二絕緣保護層，且於該第二絕緣保護層中形成複數焊指墊用開孔，以對應外露各該焊指墊。
  4. 如申請專利範圍第1項所述之封裝基板之製法，復包括於外露之該線路層表面上形成表面處理層。
  5. 一種封裝基板之製法，係包括：提供一承載板，其兩表面均設有第一金屬層，各該第一金屬層上設有第二金屬層；於各該第二金屬層上以電鍍方式形成圖案化之線路層，各該線路層具有焊指墊、接觸墊、及電性連接該焊指墊與接觸墊的線路；於該第二金屬層與線路層上形成介電層；於該介電層中形成複數接觸墊用開孔，以對應外露各該接觸墊；移除該承載板與第一金屬層；以及移除該第二金屬層，以外露該線路層。
  6. 如申請專利範圍第5項所述之封裝基板之製法，其中，形成該接觸墊用開孔之方式係雷射燒灼或曝光顯影。
  7. 如申請專利範圍第5項所述之封裝基板之製法，其中，該介電層之材質係防焊材料或環氧樹脂。
  8. 如申請專利範圍第5項所述之封裝基板之製法，復包括於外露該焊指墊之介電層表面形成覆蓋該介電層與線路層的絕緣保護層，且於該絕緣保護層中形成複數焊指墊用開孔，以對應外露各該焊指墊。
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