TWI480989B - 半導體封裝件及其製法 - Google Patents

半導體封裝件及其製法 Download PDF

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Publication number
TWI480989B
TWI480989B TW101136309A TW101136309A TWI480989B TW I480989 B TWI480989 B TW I480989B TW 101136309 A TW101136309 A TW 101136309A TW 101136309 A TW101136309 A TW 101136309A TW I480989 B TWI480989 B TW I480989B
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Taiwan
Prior art keywords
layer
dielectric layer
semiconductor package
pads
pad
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TW101136309A
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English (en)
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TW201415589A (zh
Inventor
陳嘉成
何祈慶
唐紹祖
劉宇哲
蔡瀛洲
Original Assignee
矽品精密工業股份有限公司
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Application filed by 矽品精密工業股份有限公司 filed Critical 矽品精密工業股份有限公司
Priority to TW101136309A priority Critical patent/TWI480989B/zh
Priority to CN201210394739.6A priority patent/CN103715165B/zh
Priority to US13/729,963 priority patent/US20140091462A1/en
Publication of TW201415589A publication Critical patent/TW201415589A/zh
Application granted granted Critical
Publication of TWI480989B publication Critical patent/TWI480989B/zh
Priority to US15/632,669 priority patent/US9991197B2/en

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Description

半導體封裝件及其製法
本發明係有關一種半導體封裝件，尤指一種以無承載件之方式承載晶片的半導體封裝件及其製法。
傳統以導線架作為晶片承載件之半導體封件之型態及種類繁多，就四邊扁平無導腳(Quad Flat Non-leaded,QFN)半導體封裝件而言，其特徵在於未設置有外導腳，即未形成有如習知四邊形平面(Quad Flat package,QFP)半導體封裝件中用以與外界電性連接之外導腳，如此將得以縮小半導體封裝件之尺寸。然而伴隨半導體產品輕薄短小之發展趨勢，傳統導線架之QFN封裝件往往因其封裝膠體厚度之限制，而無法進一步縮小封裝件之整體高度。因此，業界便發展出一種無承載件(carrier)之半導體封裝件，冀藉由減低習用之導線架厚度，以令其整體厚度得以較傳統導線架式封裝件更為輕薄，如第1D圖所示。
第1A至1D圖係為習知半導體封裝件1之製法之剖面示意圖。
如第1A圖所示，蝕刻移除一金屬載板10之部分材質，以形成複數打線墊101與複數置晶墊102。
如第1B圖所示，形成一綠漆防銲層11於該金屬載板10上，並使該打線墊101與置晶墊102外露出該防銲層11，再覆蓋一抗氧化層15於該打線墊101與置晶墊102上。
如第1C圖所示，藉由黏著材料171置放一半導體晶片17於該置晶墊102上，並利用複數例如金線之銲線170電性連接該半導體晶片17與打線墊101，再形成封裝膠體18於該防銲層11上，以包覆該半導體晶片17與銲線170。
如第1D圖所示，蝕刻移除該金屬載板10，以露出該打線墊101與置晶墊102之下表面。
然而，習知半導體封裝件1之製法中，該些銲線170需相互跨接，如第1D’圖所示，故該些銲線170之間容易相接觸而造成短路。
再者，該銲線170具有弧高、弧長之限制，致使該些打線墊101之佈設靈活性受限於該銲線170之打線範圍。
又，如第1D’圖所示，部分外圈打線墊101與該半導體晶片17之電極墊17a間的距離較遠，因而打線距離較長，故需形成較長之銲線170，以致無法節省該銲線170之使用量，致使該半導體封裝件1之製作成本難以降低，且該半導體封裝件1之尺寸亦難以進一步微小化。
為了進一步改進前述習知半導體封裝件1之缺失而使封裝結構更微小化，遂發展出一種製法，如第2A至2E圖所示，係為習知半導體封裝件2之另一種製法的剖面示意圖。
如第2A圖所示，電鍍形成一線路層24於一銅載板20上，且該線路層24具有複數銲墊241、複數電性連接墊242與置晶墊243，又形成該線路層24之材質係為鈀、鎳、鈀及金材(Pd/Ni/Pd/Au)堆疊。
如第2B圖所示，藉由例如銀膠之黏著材料271置放至少一半導體晶片27於該置晶墊243上，且該半導體晶片27係以複數銲線270電性連接該些銲墊241。
接著，形成封裝膠體28於該銅載板20上，以包覆該半導體晶片27與該線路層24。
如第2C圖所示，藉由該線路層24底部之金材作為止蝕部，以蝕刻移除該銅載板20。
如第2D圖所示，於該銲墊241、電性連接墊242與置晶墊243上形成一極薄銅層25，再形成一如綠漆之防銲層21於該封裝膠體28上，並形成複數開孔210於該防銲層21上，以令該些電性連接墊242上之極薄銅層25與該置晶墊243上之部分極薄銅層25外露於該些開孔210。
如第2E圖所示，利用該極薄銅層25電鍍形成複數銲球29於該開孔210中之極薄銅層25上。
惟，習知半導體封裝件2之製法中，因需先形成該線路層24，再形成該防銲層21，故該防銲層21會覆蓋該線路層24之部分材質。當該些銲球29形成後，因該防銲層21與該線路層24之金材間(該銅層25極薄，可忽略其應力影響)的結合性不佳，導致該防銲層21易於該開孔210處周圍發生脫層現象，致使該半導體封裝件2具有落球(Ball drop fail)之信賴度問題。
又，習知半導體封裝件2之製法中，因使用金材形成該線路層24，故難以降低該半導體封裝件2之製作成本。
因此，如何克服上述習知技術的種種問題，實已成目 前亟欲解決的課題。
鑑於上述習知技術之種種缺失，本發明係提供一種半導體封裝件，係包括：介電層，係為製作增層線路用之介電層，且具有相對之第一表面與第二表面，且具有貫穿於該第一與第二表面之開孔；線路層，係形成於該介電層之第一表面上，該線路層具有複數線路及位於各該線路兩端之銲墊與電性連接墊，且令該些電性連接墊外露於該介電層之開孔；至少一半導體晶片，係置放於該介電層之第一表面上，且該半導體晶片具有複數電極墊；以及複數銲線，係電性連接該半導體晶片之電極墊與該些銲墊。
前述之半導體封裝件中，該線路層復具有置晶墊，以令該半導體晶片置放於該置晶墊上，且該半導體晶片係電性連接該置晶墊。
前述之半導體封裝件中，該些銲墊係佈設位於該半導體晶片之外緣處。
前述之半導體封裝件中，該銲墊係位於該電性連接墊與該半導體晶片之間。
本發明復提供一種半導體封裝件，係包括：介電層，係為製作增層線路用之介電層，且具有相對之第一表面與第二表面，且具有貫穿於該第一與第二表面之開孔；線路層，係形成於該介電層之第一表面上，該線路層具有複數線路及位於各該線路兩端之銲墊與電性連接墊，且令該些電性連接墊外露於該介電層之開孔；複數導電凸塊，形成 於該些銲墊上；以及至少一半導體元件，係接置於該導電凸塊上，且該半導體晶片具有複數電極墊，以藉由該些導電凸塊電性連接該些電極墊與該些銲墊。
本發明又提供一種半導體封裝件之製法，係包括：提供一承載件，該承載件表面具有介電層，且該介電層係為製作增層線路用之介電層；形成線路層於該介電層上，該線路層具有複數線路及位於各該線路兩端之銲墊與電性連接墊；置放至少一半導體晶片於該介電層上，且令該半導體晶片電性連接該些銲墊；形成封裝膠體於該介電層上，以包覆該半導體晶片與線路層；移除該承載件，且保留該介電層於該封裝膠體上；以及形成貫穿該介電層之開孔，以外露該電性連接墊。
前述之製法中，該承載件之材質係為金屬。
前述之製法中，該線路層係以電鍍方式形成之。
前述之製法中，該半導體晶片係以銲線或導電凸塊電性連接該些銲墊。
前述之製法中，該線路層復具有置晶墊，以令該半導體晶片置放於該置晶墊。
前述之製法中，係以蝕刻方式移除該承載件。
前述之半導體封裝件及其製法中，該介電層之材質係為聚醯亞胺、ABF(ajinomoto build-up film)、環氧樹脂複合玻璃材質、強化纖維複合玻璃材質或環氧樹脂複合玻璃陶瓷粉材質。
前述之半導體封裝件及其製法中，復包括形成表面處 理層於該銲墊上。
前述之半導體封裝件及其製法中，復包括形成膠材於該介電層與該半導體晶片之間。
前述之半導體封裝件及其製法中，復包括形成封裝膠體於該介電層之第一表面上，以包覆該半導體晶片與線路層。
另外，前述之半導體封裝件及其製法中，復包括形成銲球於該介電層之開孔上。
由上可知，本發明之半導體封裝件及其製法，係藉由製作增層線路用之介電層取代習知技術之防銲層，令該介電層作為止蝕層與防銲層，故能以銅材製作線路層，而無需以金材製作線路層與止蝕層，且無需製作防銲層與化鍍銅，故本發明有效降低製作成本。
再者，該製作增層線路用之介電層與銅材之結合性佳，故該介電層於該開孔處周圍不會發生脫層現象。因此，本發明之半導體封裝件可避免落球之信賴度問題。
又，該製作增層線路用之介電層亦提供較佳的支撐性以避免落球。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝 之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“上”、“下”、“第一”、“第二”、“第三”及“一”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
第3A至3F圖係為本發明之半導體封裝件3之製法的剖面示意圖。
如第3A圖所示，提供一承載結構3a具有一製增層線路用之介電層31、一導電層32與一承載件30，再形成第一圖案化阻層33a於該導電層32上以外露該導電層32之部分表面。
於本實施例中，形成該介電層31之材質係為製作增層線路用之材質，即聚醯亞胺(Polyimide,PI)、ABF(ajinomoto build-up film)、環氧樹脂複合玻璃材質、強化纖維複合玻璃材質或環氧樹脂複合玻璃陶瓷粉材質，並非一般預浸材(prepreg,PP)之介電材。因考量後續封裝模壓製程(Molding)中，封裝膠體與介電材之間的熱膨脹係數(thermal expansion coefficient,CTE)差異大小的問題及介電材是否易脆而受壓裂壞的問題，故選用上述該製增層線路用之介電層31，並非一般預浸材(prepreg, PP)之介電層。
接著，利用該導電層32電鍍形成一線路層34於該介電層31上，且該線路層34具有複數線路340(如第3F”圖所示)、置晶墊343以及位於各該線路340兩端之銲墊341與電性連接墊342。其中，該置晶墊343在本實施例係用以接置半導體晶片，故可不另連接至該線路340，而於其它實施例中，該置晶墊343除了用以接置半導體晶片外，亦可作為如接地用的電性連接墊而連接該線路340，以令該置晶墊343藉由該線路340電性連接該電性連接墊342,342’。
於本實施例中，形成該承載件30與該導電層32之主要材質係為如銅或鋁之金屬，且該導電層32係作為電鍍製程之電流路徑，而形成該線路層34之主要材質係為銅材或鋁材。
再者，該承載件30、介電層31及導電層32可視為一承載結構3a。
又，該些銲墊341係作為打線墊，且佈設位於該置晶墊343之外緣處，並位於該電性連接墊342,342’與該置晶墊343之間。
另外，該介電層31係具有相對之第一表面31a(此處表示圖式中之上表面)與第二表面31b(此處表示圖式中之下表面)，且其以該第一表面31a結合該導電層32，而以該第二表面31b結合該承載件30。
如第3B圖所示，形成一第二圖案化阻層33b於該第 一圖案化阻層33a上以外露該銲墊341，再形成一表面處理層35於該銲墊341上。
同時，形成一第三圖案化阻層33c於該承載件30之另一側(如圖所示之下側)，以形成一支撐層36a於該承載件30上。
於本實施例中，該支撐層36a與該表面處理層35係為相同材質組成，該材質如為從該銲墊341處由下而上之鎳/金層(Ni/Au)，例如，化鎳/金(Ni/Au)；或者，由化鎳鈀金(Electroless Nickel/Electroless Palladium/Immersion Gold,ENEPIG)、直接浸金(Direct Immersion Gold,DIG)、電鍍鎳/化鍍鈀/電鍍金形成。
如第3C圖所示，移除該第一至第三圖案化阻層33a,33b,33c，且一併移除該第一圖案化阻層33a下方之導電層32。
有關製作圖案化線路之方式繁多，並不限於上述，特此述明。
如第3D圖所示，進行置晶(Die Bonding)、打線(Wire Bonding)及封裝模壓(Molding)製程。藉由例如銀膠之黏著材料371置放至少一半導體晶片37於該置晶墊343上，且該半導體晶片37係以複數銲線370電性連接該些銲墊341。
接著，形成封裝膠體38於該介電層31上，以包覆該半導體晶片37與線路層34。
於本實施例中，該半導體晶片37具有複數電極墊 37a，如第3F”圖所示，以令該銲線370電性連接該些電極墊37a與該些銲墊341。
再者，該些銲墊341係佈設位於該半導體晶片37之外緣處，且該銲墊341係位於該電性連接墊342,342’與該半導體晶片37之間。
又，該些銲墊341亦可佈設於該些電性連接墊342,342’之間。
於其它實施例中，亦可不形成置晶墊343，以令該半導體晶片37直接置放於該介電層31之第一表面31a上。
本發明之製法，如第3F”圖所示，係於該介電層31上進行佈線，故不需將銲線370直接連接至該電性連接墊342,342’，因而可避免習知銲線跨接而造成短路之問題。
再者，藉由該線路340之設計，可提升該些銲墊341之佈設靈活性，使該電性連接墊342,342’之佈設不受該銲線370之打線範圍的限制。
又，藉由該線路340之設計，該些銲墊341與該半導體晶片37的電極墊37a(含I/O接點)之間的距離縮短，故無需使用較長之銲線370，不僅有效節省該銲線370之使用量以達到降低材料成本之目的，且利於微小化該半導體封裝件3之尺寸。
另外，該線路層34之電性連接墊342,342’之總數大於或等於該半導體晶片37的電極墊37a(含I/O接點)之總數，如第3F”圖所示。
如第3E圖所示，蝕刻移除該承載件30未具有該支撐 層36a之部份，且保留該介電層31於該封裝膠體38上，以形成支撐結構36於該介電層31之第二表面31b上。
如第3F圖所示，形成複數開孔310於該介電層31之第二表面31b上，以令該些電性連接墊342,342’與置晶墊343外露於該些開孔310中，俾供形成銲球39於該開孔310中之電性連接墊342,342’與置晶墊343上，以令該半導體封裝件3之底部具有陣列球柵(Ball Array)，並且部分該些置晶墊343可以視需求作接地之用。
於本實施例中，該支撐結構36係作為製程中之測試結構。
再者，該些最外側之電性連接墊342’亦可不外露於該開孔310中。
又藉由該介電層31作為保護線路之用，可免作習知如綠漆之防銲層。
另外，於第3F”圖中，為了清楚顯示本發明之技術，係簡化該半導體晶片37的電極墊37a及該線路340之實際佈設情況，故部分電極墊37a係以「．」表示，且僅顯示部分線路340，因而部分該電性連接墊342’,342’並未顯示連接該線路340，亦即實際上，該電性連接墊342’,342’應連接於該線路340之一端。
如第3F’圖所示，於另一實施例中，該半導體封裝件3’可不形成該支撐結構36，亦即於第3B圖之製程中不製作該支撐層36a，而於第3E圖之製程中移除全部該承載件30。
本發明之製法中，係以材質較軟之製作增層線路之介 電層31取代習知技術中材質較碎之防銲層，且將以銅材或鋁材為主之線路層34形成於該介電層31上，又該介電層31與銅材或鋁材之結合性佳，故該介電層31於該開孔310處周圍不會發生脫層現象。因此，本發明之半導體封裝件3可避免落球(Ball drop fail)，故能提升可靠度。
再者，該介電層31亦提供較佳的支撐性以避免落球，且該介電層31係用以作為止蝕層，因而該線路層34無需以金材製作，故本發明之製法能有效節省材料成本。
又，移除該承載件30之後，該介電層31即可作為防銲之用，故無需使用習知之綠漆製程，因而本發明之製法可降低製作成本。且使用銅材或鋁材製作該線路層34，故於形成該銲球39之前，無需進行化鍍銅製程，因而本發明之製法可大幅降低製作成本。
另外，使用銅材或鋁材製作該線路層34以取代習知技術之較長銲線，不僅可節省金材之使用量以降低材料成本，且利於微小化該半導體封裝件3之尺寸。
第4及5圖係為本發明之半導體封裝件4,5之另一實施例的剖面示意圖。如第4圖所示，該半導體晶片37’可藉由複數導電凸塊370’電性連接該些銲墊341’，亦即於第3A圖之製程中，可不需製作置晶墊。接著，形成底膠38’於該半導體晶片37’與該介電層31之第一表面31a之間，以包覆該些導電凸塊370’；亦可不形成底膠38’而直接以該封裝膠體38包覆該些導電凸塊370’。或者，如第5圖所示，僅形成底膠38’於該半導體晶片37’與該介電層31 之第一表面31a之間，而不形成該封裝膠體38。
於本實施例中，該些銲墊341’可選擇性地藉由該線路340連接內側之電性連接墊342或外圍之電性連接墊342’。
再者，該半導體晶片37’之電極墊(圖略)上係形成有凸塊底下金屬層(Under Bump Metallurgy,UBM，圖未示)，以結合該導電凸塊370’。其中，有關覆晶式半導體晶片之電極墊佈設情況係可依需求而定，並無特別限制，且有關UBM之結構種類繁多，亦無特別限制。
本發明之製法，不僅具有導線架(Lead Frame)之結構特徵，且可利用佈線形成覆晶式或打線式結構，並於底部形成陣列球柵，故能製作出多功能、多優點之封裝件結構。
本發明復提供一種半導體封裝件3,3’,4,5，係包括：一製作增層線路用之介電層31、一線路層34以及至少一半導體晶片37,37’。
所述之介電層31係具有相對之第一表面31a與第二表面31b，且於該第二表面31b上形成複數開孔310，又形成該介電層31之材質係為聚醯亞胺(Polyimide,PI)、ABF(ajinomoto build-up film)、環氧樹脂複合玻璃材質、強化纖維複合玻璃材質或環氧樹脂複合玻璃陶瓷粉材質。
所述之線路層34係形成於該介電層31之第一表面31a上，該線路層34具有複數線路340及位於各該線路340兩端之銲墊341,341’與電性連接墊342(或電性連接墊342’與置晶墊343)，以令該些電性連接墊342(或電性連 接墊342’與置晶墊343)外露於該介電層31之開孔310，又形成該線路層34之材質係為銅材或鋁材。
所述之半導體晶片37,37’係置放於該介電層31之第一表面31a上或該銲墊341’上，且該半導體晶片37,37’具有複數電極墊37a，並以複數銲線370或複數導電凸塊370’電性連接該些電極墊37a與該些銲墊341,341’。
所述之半導體封裝件3,3’,4復包括封裝膠體38，係形成於該介電層31之第一表面31a上，以包覆該半導體晶片37,37’與線路層34。
所述之半導體封裝件3,3’,4,5復包括表面處理層35，係形成於該銲墊341上。
所述之半導體封裝件3,3’,4,5復包括複數銲球39，係分別形成於各該開孔310中之電性連接墊342(或電性連接墊342’與置晶墊343)上。
所述之半導體封裝件3,3’,4,5復包括形成於該介電層31與該半導體晶片37,37’之間的膠材(即該黏著材料371或該底膠38’)。
於一實施例中，該線路層34復具有置晶墊343，以令該半導體晶片37置放於該置晶墊343上，且該置晶墊343可作為電性連接墊。
於一實施例中，該些銲墊341係佈設位於該半導體晶片37之外緣處。
於一實施例中，該銲墊341係位於該電性連接墊342,342’與該半導體晶片37之間。
綜上所述，本發明之半導體封裝件及其製法，主要藉由該製增層線路用之介電層可同時作為止蝕層與防銲層，故能以銅材或鋁材製作線路層，而無需以金材製作線路層與止蝕層，且無需製作防銲層與化鍍銅，故本發明有效降低製作成本。
再者，該製增層線路用之介電層與銅材或鋁材之結合性佳，故該製增層線路用之介電層於該開孔處周圍不會發生脫層現象，因而有效提升本發明之半導體封裝件之可靠度。
又，使用銅材製作該線路層，不僅可節省金材之使用量以降低材料成本，且利於微小化該半導體封裝件之尺寸。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
1,2,3,3’,4,5‧‧‧半導體封裝件
10‧‧‧金屬載板
101‧‧‧打線墊
102,243,343‧‧‧置晶墊
11,21‧‧‧防銲層
15‧‧‧抗氧化層
17,27,37,37’‧‧‧半導體晶片
17a,37a‧‧‧電極墊
170,270,370‧‧‧銲線
171,271,371‧‧‧黏著材料
18,28,38‧‧‧封裝膠體
20‧‧‧銅載板
210,310‧‧‧開孔
24,34‧‧‧線路層
241,341,341’‧‧‧銲墊
242,342,342’‧‧‧電性連接墊
25‧‧‧銅層
29,39‧‧‧銲球
3a‧‧‧承載結構
30‧‧‧承載件
31‧‧‧介電層
31a‧‧‧第一表面
31b‧‧‧第二表面
32‧‧‧導電層
33a‧‧‧第一圖案化阻層
33b‧‧‧第二圖案化阻層
33c‧‧‧第三圖案化阻層
340‧‧‧線路
35‧‧‧表面處理層
36‧‧‧支撐結構
36a‧‧‧支撐層
370’‧‧‧導電凸塊
38’‧‧‧底膠
第1A至1D圖係為習知半導體封裝件之製法之剖視示意圖；其中，第1D’圖係為第1D圖之局部打線的上視平面示意圖，第1D’圖之A-A剖面線係為第1D圖；第2A至2E圖係為習知半導體封裝件之製法的剖視示意圖；第3A至3F圖係為本發明之半導體封裝件之製法的剖視示意圖；其中，第3F’圖係為第3F圖之另一態樣；第3F” 圖係為第3F’圖(無封裝膠體)之上視平面示意圖；第4圖係為本發明之半導體封裝件之另一實施例之剖視示意圖；以及第5圖係為第4圖之另一態樣。
3’‧‧‧半導體封裝件
31‧‧‧介電層
31a‧‧‧第一表面
31b‧‧‧第二表面
34‧‧‧線路層
341‧‧‧銲墊
342,342’‧‧‧電性連接墊
343‧‧‧置晶墊
37‧‧‧半導體晶片
370‧‧‧銲線
371‧‧‧黏著材料
38‧‧‧封裝膠體
39‧‧‧銲球

Claims (20)

  1. 一種半導體封裝件，係包括：製作增層線路用之介電層，係具有相對之第一表面與第二表面，並具有貫穿於該第一與第二表面之開孔，其中，該介電層之材質係為聚醯亞胺、ABF(ajinomoto build-up film)、環氧樹脂複合玻璃材質、強化纖維複合玻璃材質或環氧樹脂複合玻璃陶瓷粉材質；線路層，係形成於該介電層之第一表面上，該線路層具有複數線路及位於各該線路兩端之銲墊與電性連接墊，且令該些電性連接墊外露於該介電層之開孔；至少一半導體晶片，係置放於該介電層之第一表面上，且該半導體晶片具有複數電極墊；以及複數銲線，係電性連接該半導體晶片之電極墊與該些銲墊。
  2. 一種半導體封裝件，係包括：製作增層線路用之介電層，係具有相對之第一表面與第二表面，且具有貫穿於該第一與第二表面之開孔，其中，該介電層之材質係為聚醯亞胺、ABF(ajinomoto build-up film)、環氧樹脂複合玻璃材質、強化纖維複合玻璃材質或環氧樹脂複合玻璃陶瓷粉材質；線路層，係形成於該介電層之第一表面上，該線路層具有複數線路及位於各該線路兩端之銲墊與電性 連接墊，且令該些電性連接墊外露於該介電層之開孔；複數導電凸塊，形成於該些銲墊上；以及至少一半導體元件，係接置於該導電凸塊上，且該半導體晶片具有複數電極墊，以藉由該些導電凸塊電性連接該些電極墊與該些銲墊。
  3. 如申請專利範圍第1或2項所述之半導體封裝件，復包括形成於該銲墊上之表面處理層。
  4. 如申請專利範圍第1或2項所述之半導體封裝件，復包括形成於該介電層之開孔中之銲球。
  5. 如申請專利範圍第1或2項所述之半導體封裝件，復包括形成於該介電層與該半導體晶片之間的膠材。
  6. 如申請專利範圍第1或2項所述之半導體封裝件，復包括封裝膠體，係形成於該介電層之第一表面上，以包覆該半導體晶片與線路層。
  7. 如申請專利範圍第1項所述之半導體封裝件，其中，該線路層復具有置晶墊，以令該半導體晶片置放於該置晶墊上。
  8. 如申請專利範圍第7項所述之半導體封裝件，其中，該半導體晶片係電性連接該置晶墊。
  9. 如申請專利範圍第1項所述之半導體封裝件，其中，該些銲墊係佈設位於該半導體晶片之外緣處。
  10. 如申請專利範圍第1項所述之半導體封裝件，其中，該銲墊係位於該電性連接墊與該半導體晶片之間。
  11. 一種半導體封裝件之製法，係包括： 提供一承載件，該承載件表面具有介電層，且該介電層係為製作增層線路用之介電層；形成線路層於該介電層上，該線路層具有複數線路及位於各該線路兩端之銲墊與電性連接墊，其中，形成該介電層之材質係為聚醯亞胺、ABF(ajinomoto build-up film)、環氧樹脂複合玻璃材質、強化纖維複合玻璃材質或環氧樹脂複合玻璃陶瓷粉材質；置放至少一半導體晶片於該介電層上，且令該半導體晶片電性連接該些銲墊；形成封裝膠體於該介電層上，以包覆該半導體晶片與線路層；移除該承載件，且保留該介電層於該封裝膠體上；以及形成貫穿該介電層之開孔，以外露該電性連接墊。
  12. 如申請專利範圍第11項所述之半導體封裝件之製法，其中，該承載件之材質係為金屬。
  13. 如申請專利範圍第11項所述之半導體封裝件之製法，其中，該線路層係以電鍍方式形成之。
  14. 如申請專利範圍第11項所述之半導體封裝件之製法，其中，該線路層復具有置晶墊，以令該半導體晶片置放於該置晶墊上。
  15. 如申請專利範圍第11項所述之半導體封裝件之製法，其中，該半導體晶片係以銲線或導電凸塊電性連接該些銲墊。
  16. 如申請專利範圍第11項所述之半導體封裝件之製法，其中，係以蝕刻方式移除該承載件。
  17. 如申請專利範圍第11項所述之半導體封裝件之製法，復包括形成表面處理層於該銲墊上。
  18. 如申請專利範圍第11項所述之半導體封裝件之製法，復包括形成銲球於該介電層之開孔中。
  19. 如申請專利範圍第11項所述之半導體封裝件之製法，復包括形成膠材於該介電層與該半導體晶片之間。
  20. 如申請專利範圍第11項所述之半導體封裝件之製法，復包括形成封裝膠體於該介電層之第一表面上，以包覆該半導體晶片與線路層。
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Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6100648B2 (ja) * 2013-08-28 2017-03-22 ルネサスエレクトロニクス株式会社 半導体装置及び半導体装置の製造方法
TWI563577B (en) * 2014-10-09 2016-12-21 Phoenix Pioneer Technology Co Ltd Package structure and method of manufacture
TWI558286B (zh) * 2014-10-28 2016-11-11 恆勁科技股份有限公司 封裝結構及其製法
TWI559470B (zh) * 2015-08-06 2016-11-21 力成科技股份有限公司 無基板的半導體封裝結構及其製造方法
US9741677B1 (en) * 2016-03-01 2017-08-22 Infineon Technologies Ag Semiconductor device including antistatic die attach material
TWI622151B (zh) * 2016-12-07 2018-04-21 矽品精密工業股份有限公司 用於半導體封裝的承載基板與其封裝結構，及半導體封裝元件的製作方法
CN108242403A (zh) * 2016-12-27 2018-07-03 冠宝科技股份有限公司 一种无基板半导体封装制造方法
TWI690039B (zh) * 2019-07-03 2020-04-01 矽品精密工業股份有限公司 電子封裝件及其製法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200408102A (en) * 2002-11-08 2004-05-16 Advanced Semiconductor Eng Stack package structure and electrically-connected board for stack package
TW201036138A (en) * 2009-03-17 2010-10-01 Powertech Technology Inc Flip-chip stacked package structure and its package methodfabrication method of a photonic crystal structure
TW201231860A (en) * 2011-01-18 2012-08-01 Gio Optoelectronics Corp Light emitting apparatus

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5541450A (en) * 1994-11-02 1996-07-30 Motorola, Inc. Low-profile ball-grid array semiconductor package
US5990545A (en) * 1996-12-02 1999-11-23 3M Innovative Properties Company Chip scale ball grid array for integrated circuit package
US20010052647A1 (en) * 1998-05-07 2001-12-20 3M Innovative Properties Company Laminated integrated circuit package
US6635957B2 (en) * 1998-06-10 2003-10-21 Asat Ltd. Leadless plastic chip carrier with etch back pad singulation and die attach pad array
EP1346411A2 (en) * 2000-12-01 2003-09-24 Broadcom Corporation Thermally and electrically enhanced ball grid array packaging
US7259448B2 (en) * 2001-05-07 2007-08-21 Broadcom Corporation Die-up ball grid array package with a heat spreader and method for making the same
US7196415B2 (en) * 2002-03-22 2007-03-27 Broadcom Corporation Low voltage drop and high thermal performance ball grid array package
US6906415B2 (en) * 2002-06-27 2005-06-14 Micron Technology, Inc. Semiconductor device assemblies and packages including multiple semiconductor devices and methods
US7148560B2 (en) * 2005-01-25 2006-12-12 Taiwan Semiconductor Manufacturing Co., Ltd. IC chip package structure and underfill process
US7279785B2 (en) * 2005-02-14 2007-10-09 Stats Chippac Ltd. Stacked die package system
TWI316749B (en) * 2006-11-17 2009-11-01 Siliconware Precision Industries Co Ltd Semiconductor package and fabrication method thereof
US7847399B2 (en) * 2007-12-07 2010-12-07 Texas Instruments Incorporated Semiconductor device having solder-free gold bump contacts for stability in repeated temperature cycles
JP5684122B2 (ja) 2008-07-15 2015-03-11 クルセル ホランド ベー ヴェー Ｐｅｒ．ｃ６細胞の培養およびそれからの生成物の生産のための拡張可能なプロセス
JP2010093109A (ja) * 2008-10-09 2010-04-22 Renesas Technology Corp 半導体装置、半導体装置の製造方法および半導体モジュールの製造方法
US20110140253A1 (en) * 2009-12-14 2011-06-16 National Semiconductor Corporation Dap ground bond enhancement
TWI469289B (zh) * 2009-12-31 2015-01-11 矽品精密工業股份有限公司 半導體封裝結構及其製法
TWI416682B (zh) * 2010-09-01 2013-11-21 Unimicron Technology Corp 封裝結構
KR101711499B1 (ko) * 2010-10-20 2017-03-13 삼성전자주식회사 반도체 패키지 및 그 제조 방법
US9275877B2 (en) * 2011-09-20 2016-03-01 Stats Chippac, Ltd. Semiconductor device and method of forming semiconductor package using panel form carrier
US9324641B2 (en) * 2012-03-20 2016-04-26 Stats Chippac Ltd. Integrated circuit packaging system with external interconnect and method of manufacture thereof

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200408102A (en) * 2002-11-08 2004-05-16 Advanced Semiconductor Eng Stack package structure and electrically-connected board for stack package
TW201036138A (en) * 2009-03-17 2010-10-01 Powertech Technology Inc Flip-chip stacked package structure and its package methodfabrication method of a photonic crystal structure
TW201231860A (en) * 2011-01-18 2012-08-01 Gio Optoelectronics Corp Light emitting apparatus

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