CN103715165A - 半导体封装件及其制法 - Google Patents

半导体封装件及其制法 Download PDF

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Publication number
CN103715165A
CN103715165A CN201210394739.6A CN201210394739A CN103715165A CN 103715165 A CN103715165 A CN 103715165A CN 201210394739 A CN201210394739 A CN 201210394739A CN 103715165 A CN103715165 A CN 103715165A
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dielectric layer
semiconductor package
semiconductor chip
layer
pad
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CN201210394739.6A
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CN103715165B (zh
Inventor
陈嘉成
何祈庆
唐绍祖
刘宇哲
蔡瀛洲
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Siliconware Precision Industries Co Ltd
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Siliconware Precision Industries Co Ltd
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Abstract

一种半导体封装件及其制法，该半导体封装件包括制作增层线路用的介电层、形成于该介电层上的线路层、结合并电性连接该线路层的半导体芯片、以及包覆该半导体芯片的封装胶体。因此种介电层与该线路层的结合性佳，所以两者之间不会发生脱层现象，遂能提高该半导体封装件的可靠度及能使封装体积更微小化。

Description

半导体封装件及其制法
技术领域
本发明涉及一种半导体封装件，尤指一种以无承载件的方式承载芯片的半导体封装件及其制法。
背景技术
传统以导线架作为芯片承载件的半导体封件的型态及种类繁多，就四边扁平无导脚(Quad Flat Non-leaded,QFN)半导体封装件而言，其特征在于未设置有外导脚，即未形成有如现有四边形平面(Quad Flatpackage,QFP)半导体封装件中用以与外界电性连接的外导脚，如此将得以缩小半导体封装件的尺寸。然而伴随半导体产品轻薄短小的发展趋势，传统导线架的QFN封装件往往因其封装胶体厚度的限制，而无法进一步缩小封装件的整体高度。因此，业界便发展出一种无承载件(carrier)的半导体封装件，冀借由减低习用的导线架厚度，以令其整体厚度得以较传统导线架式封装件更为轻薄，如图1D所示。
图1A至图1D为现有半导体封装件1的制法的剖面示意图。
如图1A所示，蚀刻移除一金属载板10的部分材质，以形成多个打线垫101与多个置晶垫102。
如图1B所示，形成一绿漆防焊层11于该金属载板10上，并使该打线垫101与置晶垫102外露出该防焊层11，再覆盖一抗氧化层15于该打线垫101与置晶垫102上。
如图1C所示，借由粘着材料171置放一半导体芯片17于该置晶垫102上，并利用多条例如金线的焊线170电性连接该半导体芯片17与打线垫101，再形成封装胶体18于该防焊层11上，以包覆该半导体芯片17与焊线170。
如图1D所示，蚀刻移除该金属载板10，以露出该打线垫101与置晶垫102的下表面。
然而，现有半导体封装件1的制法中，该些焊线170需相互跨接，如图1D’所示，所以该些焊线170之间容易相接触而造成短路。
此外，该焊线170具有弧高、弧长的限制，致使该些打线垫101的布设灵活性受限于该焊线170的打线范围。
再者，如图1D’所示，部分外圈打线垫101与该半导体芯片17的电极垫17a间的距离较远，因而打线距离较长，所以需形成较长的焊线170，以致无法节省该焊线170的使用量，致使该半导体封装件1的制作成本难以降低，且该半导体封装件1的尺寸亦难以进一步微小化。
为了进一步改进前述现有半导体封装件1的缺失而使封装结构更微小化，遂发展出一种制法，如图2A至图2E所示，其为现有半导体封装件2的另一种制法的剖面示意图。
如图2A所示，电镀形成一线路层24于一铜载板20上，且该线路层24具有多个焊垫241、多个电性连接垫242与置晶垫243，此外形成该线路层24的材质为钯、镍、钯及金材(Pd/Ni/Pd/Au)堆栈。
如图2B所示，借由例如银胶的粘着材料271置放至少一半导体芯片27于该置晶垫243上，且该半导体芯片27以多条焊线270电性连接该些焊垫241。
接着，形成封装胶体28于该铜载板20上，以包覆该半导体芯片27与该线路层24。
如图2C所示，借由该线路层24底部的金材作为止蚀部，以蚀刻移除该铜载板20。
如图2D所示，于该焊垫241、电性连接垫242与置晶垫243上形成一极薄铜层25，再形成一如绿漆的防焊层21于该封装胶体28上，并形成多个开孔210于该防焊层21上，以令该些电性连接垫242上的极薄铜层25与该置晶垫243上的部分极薄铜层25外露于该些开孔210。
如图2E所示，利用该极薄铜层25电镀形成多个焊球29于该开孔210中的极薄铜层25上。
然而，现有半导体封装件2的制法中，因需先形成该线路层24，再形成该防焊层21，所以该防焊层21会覆盖该线路层24的部分材质。当该些焊球29形成后，因该防焊层21与该线路层24的金材间（该铜层25极薄，可忽略其应力影响）的结合性不佳，导致该防焊层21易于该开孔210处周围发生脱层现象，致使该半导体封装件2具有落球（Ball drop fail）的信赖度问题。
此外，现有半导体封装件2的制法中，因使用金材形成该线路层24，所以难以降低该半导体封装件2的制作成本。
因此，如何克服上述现有技术的种种问题，实已成目前亟欲解决的课题。
发明内容
鉴于上述现有技术的种种缺陷，本发明的主要目的在于提供一种半导体封装件及其制法，能提高该半导体封装件的可靠度及能使封装体积更微小化。
本发明的半导体封装件，其包括：介电层，其为制作增层线路用的介电层，且具有相对的第一表面与第二表面，且具有贯穿于该第一与第二表面的开孔；线路层，其形成于该介电层的第一表面上，该线路层具有多条线路及位于各该线路两端的焊垫与电性连接垫，且令该些电性连接垫外露于该介电层的开孔；至少一半导体芯片，其置放于该介电层的第一表面上，且该半导体芯片具有多个电极垫；以及多条焊线，其电性连接该半导体芯片的电极垫与该些焊垫。
前述的半导体封装件中，该线路层还具有置晶垫，以令该半导体芯片置放于该置晶垫上，且该半导体芯片电性连接该置晶垫。
前述的半导体封装件中，该些焊垫布设位于该半导体芯片的外缘处。
前述的半导体封装件中，该焊垫位于该电性连接垫与该半导体芯片之间。
本发明还提供一种半导体封装件，其包括：介电层，其为制作增层线路用的介电层，且具有相对的第一表面与第二表面，且具有贯穿于该第一与第二表面的开孔；线路层，其形成于该介电层的第一表面上，该线路层具有多条线路及位于各该线路两端的焊垫与电性连接垫，且令该些电性连接垫外露于该介电层的开孔；多个导电凸块，形成于该些焊垫上；以及至少一半导体组件，其接置于该导电凸块上，且该半导体芯片具有多个电极垫，以借由该些导电凸块电性连接该些电极垫与该些焊垫。
本发明还提供一种半导体封装件的制法，其包括：提供一承载件，该承载件表面具有介电层，且该介电层为制作增层线路用的介电层；形成线路层于该介电层上，该线路层具有多条线路及位于各该线路两端的焊垫与电性连接垫；置放至少一半导体芯片于该介电层上，且令该半导体芯片电性连接该些焊垫；形成封装胶体于该介电层上，以包覆该半导体芯片与线路层；移除该承载件，且保留该介电层于该封装胶体上；以及形成贯穿该介电层的开孔，以外露该电性连接垫。
前述的制法中，该承载件的材质为金属。
前述的制法中，该线路层是以电镀方式形成。
前述的制法中，该半导体芯片是以焊线或导电凸块电性连接该些焊垫。
前述的制法中，该线路层还具有置晶垫，以令该半导体芯片置放于该置晶垫。
前述的制法中，是以蚀刻方式移除该承载件。
前述的半导体封装件及其制法中，该介电层的材质为聚酰亚胺、ABF(ajinomoto build-up film，阿基诺莫脱内建膜)、环氧树脂复合玻璃材质、强化纤维复合玻璃材质或环氧树脂复合玻璃陶瓷粉材质。
前述的半导体封装件及其制法中，还包括形成表面处理层于该焊垫上。
前述的半导体封装件及其制法中，还包括形成胶材于该介电层与该半导体芯片之间。
前述的半导体封装件及其制法中，还包括形成封装胶体于该介电层的第一表面上，以包覆该半导体芯片与线路层。
另外，前述的半导体封装件及其制法中，还包括形成焊球于该介电层的开孔上。
由上可知，本发明的半导体封装件及其制法，其借由制作增层线路用的介电层取代现有技术的防焊层，令该介电层作为止蚀层与防焊层，所以能以铜材制作线路层，而无需以金材制作线路层与止蚀层，且无需制作防焊层与化镀铜，所以本发明有效降低制作成本。
此外，该制作增层线路用的介电层与铜材的结合性佳，所以该介电层于该开孔处周围不会发生脱层现象。因此，本发明的半导体封装件可避免落球的信赖度问题。
另外，该制作增层线路用的介电层亦提供较佳的支撑性以避免落球。
附图说明
图1A至图1D为现有半导体封装件的制法的剖视示意图；其中，图1D’为图1D的局部打线的上视平面示意图，图1D’的A-A剖面线为图1D；
图2A至图2E为现有半导体封装件的制法的剖视示意图；
图3A至图3F为本发明的半导体封装件的制法的剖视示意图；其中，图3F’为图3F的另一实施例；图3F”为图3F’（无封装胶体）的上视平面示意图；
图4为本发明的半导体封装件的另一实施例的剖视示意图；以及
图5为图4的另一实施例。
主要组件符号说明
1,2,3,3’,4,5        半导体封装件
10                   金属载板
101                  打线垫
102,243,343          置晶垫
11,21                防焊层
15                   抗氧化层
17,27,37,37’        半导体芯片
17a,37a              电极垫
170,270,370          焊线
171,271,371          粘着材料
18,28,38             封装胶体
20                   铜载板
210,310              开孔
24,34            线路层
241,341,341’    焊垫
242,342,342’    电性连接垫
25               铜层
29,39            焊球
3a               承载结构
30               承载件
31               介电层
31a              第一表面
31b              第二表面
32               导电层
33a              第一图案化阻层
33b              第二图案化阻层
33c              第三图案化阻层
340              线路
35               表面处理层
36               支撑结构
36a              支撑层
370’            导电凸块
38’             底胶。
具体实施方式
以下借由特定的具体实施例说明本发明的实施方式，本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其它优点及功效。
须知，本说明书所附图式所绘示的结构、比例、大小等，均仅用以配合说明书所揭示的内容，以供本领域技术人员的了解与阅读，并非用以限定本发明可实施的限定条件，所以不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的如“上”、“下”、“第一”、“第二”、“第三”及“一”等用语，也仅为便于叙述的明了，而非用以限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当也视为本发明可实施的范畴。
图3A至图3F为本发明的半导体封装件3的制法的剖面示意图。
如图3A所示，提供一承载结构3a具有一制增层线路用的介电层31、一导电层32与一承载件30，再形成第一图案化阻层33a于该导电层32上以外露该导电层32的部分表面。
于本实施例中，形成该介电层31的材质为制作增层线路用的材质，即聚酰亚胺（Polyimide,PI）、ABF(ajinomoto build-up film，阿基诺莫脱内建膜)、环氧树脂复合玻璃材质、强化纤维复合玻璃材质或环氧树脂复合玻璃陶瓷粉材质，并非一般预浸材（prepreg,PP）的介电材。因考量后续封装模压工艺（Molding）中，封装胶体与介电材之间的热膨胀系数（thermal expansion coefficient,CTE）差异大小的问题及介电材是否易脆而受压裂坏的问题，所以选用上述该制增层线路用的介电层31，并非一般预浸材（prepreg,PP）的介电层。
接着，利用该导电层32电镀形成一线路层34于该介电层31上，且该线路层34具有多条线路340（如图3F”所示）、置晶垫343以及位于各该线路340两端的焊垫341与电性连接垫342。其中，该置晶垫343在本实施例仅用以接置半导体芯片，所以可不另连接至该线路340，而于其它实施例中，该置晶垫343除了用以接置半导体芯片外，也可作为如接地用的电性连接垫而连接该线路340，以令该置晶垫343借由该线路340电性连接该电性连接垫342,342’。
于本实施例中，形成该承载件30与该导电层32的主要材质为如铜或铝的金属，且该导电层32作为电镀工艺的电流路径，而形成该线路层34的主要材质为铜材或铝材。
此外，该承载件30、介电层31及导电层32可视为一承载结构3a。
再者，该些焊垫341作为打线垫，且布设位于该置晶垫343的外缘处，并位于该电性连接垫342,342’与该置晶垫343之间。
另外，该介电层31具有相对的第一表面31a（此处表示图式中的上表面）与第二表面31b（此处表示图式中的下表面），且其以该第一表面31a结合该导电层32，而以该第二表面31b结合该承载件30。
如图3B所示，形成一第二图案化阻层33b于该第一图案化阻层33a上以外露该焊垫341，再形成一表面处理层35于该焊垫341上。
同时，形成一第三图案化阻层33c于该承载件30的另一侧（如图所示的下侧），以形成一支撑层36a于该承载件30上。
于本实施例中，该支撑层36a与该表面处理层35为相同材质组成，该材质如为从该焊垫341处由下而上的镍/金层(Ni/Au)，例如，化镍/金(Ni/Au)；或者，由化镍钯金(Electroless Nickel/ElectrolessPalladium/Immersion Gold,ENEPIG)、直接浸金(Direct Immersion Gold,DIG)、电镀镍/化镀钯/电镀金形成。
如图3C所示，移除该第一至第三图案化阻层33a,33b,33c，且一并移除该第一图案化阻层33a下方的导电层32。
有关制作图案化线路的方式繁多，并不限于上述，特此述明。
如图3D所示，进行置晶（Die Bonding）、打线（Wire Bonding）及封装模压（Molding）工艺。借由例如银胶的粘着材料371置放至少一半导体芯片37于该置晶垫343上，且该半导体芯片37以多条焊线370电性连接该些焊垫341。
接着，形成封装胶体38于该介电层31上，以包覆该半导体芯片37与线路层34。
于本实施例中，该半导体芯片37具有多个电极垫37a，如图3F”所示，以令该焊线370电性连接该些电极垫37a与该些焊垫341。
此外，该些焊垫341布设位于该半导体芯片37的外缘处，且该焊垫341位于该电性连接垫342,342’与该半导体芯片37之间。
另外，该些焊垫341也可布设于该些电性连接垫342,342’之间。
于其它实施例中，也可不形成置晶垫343，以令该半导体芯片37直接置放于该介电层31的第一表面31a上。
本发明的制法，如图3F”所示，于该介电层31上进行布线，所以不需将焊线370直接连接至该电性连接垫342,342’，因而可避免现有焊线跨接而造成短路的问题。
此外，借由该线路340的设计，可提升该些焊垫341的布设灵活性，使该电性连接垫342,342’的布设不受该焊线370的打线范围的限制。
再者，借由该线路340的设计，该些焊垫341与该半导体芯片37的电极垫37a（含I/O接点）之间的距离缩短，所以无需使用较长的焊线370，不仅有效节省该焊线370的使用量以达到降低材料成本的目的，且利于微小化该半导体封装件3的尺寸。
另外，该线路层34的电性连接垫342,342’的总数大于或等于该半导体芯片37的电极垫37a（含I/O接点）的总数，如图3F”所示。
如图3E所示，蚀刻移除该承载件30未具有该支撑层36a的部份，且保留该介电层31于该封装胶体38上，以形成支撑结构36于该介电层31的第二表面31b上。
如图3F所示，形成多个开孔310于该介电层31的第二表面31b上，以令该些电性连接垫342,342’与置晶垫343外露于该些开孔310中，以供形成焊球39于该开孔310中的电性连接垫342,342’与置晶垫343上，以令该半导体封装件3的底部具有数组球栅（Ball Array），并且部分该些置晶垫343可以视需求作接地之用。
于本实施例中，该支撑结构36作为工艺中的测试结构。
此外，该些最外侧的电性连接垫342’也可不外露于该开孔310中。
再者，借由该介电层31作为保护线路之用，可免作现有如绿漆的防焊层。
另外，于图3F”中，为了清楚显示本发明的技术，所以简化该半导体芯片37的电极垫37a及该线路340的实际布设情况，因而部分电极垫37a以「．」表示，且仅显示部分线路340，因而部分该电性连接垫342’,342’并未显示连接该线路340，也就是实际上，该电性连接垫342’,342’应连接于该线路340的一端。
如图3F’所示，于另一实施例中，该半导体封装件3’可不形成该支撑结构36，也就是于图3B的工艺中不制作该支撑层36a，而于图3E的工艺中移除全部该承载件30。
本发明的制法中，是以材质较软的制作增层线路的介电层31取代现有技术中材质较碎的防焊层，且将以铜材或铝材为主的线路层34形成于该介电层31上，此外该介电层31与铜材或铝材的结合性佳，所以该介电层31于该开孔310处周围不会发生脱层现象。因此，本发明的半导体封装件3可避免落球（Ball drop fail），所以能提升可靠度。
此外，该介电层31还提供较佳的支撑性以避免落球，且该介电层31用以作为止蚀层，因而该线路层34无需以金材制作，所以本发明的制法能有效节省材料成本。
再者，移除该承载件30之后，该介电层31即可作为防焊之用，所以无需使用现有的绿漆工艺，因而本发明的制法可降低制作成本。且使用铜材或铝材制作该线路层34，所以于形成该焊球39之前，无需进行化镀铜工艺，因而本发明的制法可大幅降低制作成本。
另外，使用铜材或铝材制作该线路层34以取代现有技术的较长焊线，不仅可节省金材的使用量以降低材料成本，且利于微小化该半导体封装件3的尺寸。
图4及图5为本发明的半导体封装件4,5的另一实施例的剖面示意图。如图4所示，该半导体芯片37’可借由多个导电凸块370’电性连接该些焊垫341’，也就是于图3A的工艺中，可不需制作置晶垫。接着，形成底胶38’于该半导体芯片37’与该介电层31的第一表面31a之间，以包覆该些导电凸块370’；也可不形成底胶38’而直接以该封装胶体38包覆该些导电凸块370’。或者，如图5所示，仅形成底胶38’于该半导体芯片37’与该介电层31的第一表面31a之间，而不形成该封装胶体38。
于本实施例中，该些焊垫341’可选择性地借由该线路340连接内侧的电性连接垫342或外围的电性连接垫342’。
此外，该半导体芯片37’的电极垫（图略）上形成有凸块底下金属层（Under Bump Metallurgy,UBM，图未示），以结合该导电凸块370’。其中，有关覆晶式半导体芯片的电极垫布设情况可依需求而定，并无特别限制，且有关UBM的结构种类繁多，也无特别限制。
本发明的制法，不仅具有导线架（Lead Frame）的结构特征，且可利用布线形成覆晶式或打线式结构，并于底部形成数组球栅，所以能制作出多功能、多优点的封装件结构。
本发明还提供一种半导体封装件3,3’,4,5，包括：一制作增层线路用的介电层31、一线路层34以及至少一半导体芯片37,37’。
所述的介电层31具有相对的第一表面31a与第二表面31b，且于该第二表面31b上形成多个开孔310，此外形成该介电层31的材质为聚酰亚胺（Polyimide,PI）、ABF(ajinomoto build-up film，阿基诺莫脱内建膜)、环氧树脂复合玻璃材质、强化纤维复合玻璃材质或环氧树脂复合玻璃陶瓷粉材质。
所述的线路层34形成于该介电层31的第一表面31a上，该线路层34具有多条线路340及位于各该线路340两端的焊垫341,341’与电性连接垫342（或电性连接垫342’与置晶垫343），以令该些电性连接垫342（或电性连接垫342’与置晶垫343）外露于该介电层31的开孔310，此外形成该线路层34的材质为铜材或铝材。
所述的半导体芯片37,37’置放于该介电层31的第一表面31a上或该焊垫341’上，且该半导体芯片37,37’具有多个电极垫37a，并以多条焊线370或多个导电凸块370’电性连接该些电极垫37a与该些焊垫341,341’。
所述的半导体封装件3,3’,4还包括封装胶体38，形成于该介电层31的第一表面31a上，以包覆该半导体芯片37,37’与线路层34。
所述的半导体封装件3,3’,4,5还包括表面处理层35，形成于该焊垫341上。
所述的半导体封装件3,3’,4,5还包括多个焊球39，分别形成于各该开孔310中的电性连接垫342（或电性连接垫342’与置晶垫343）上。
所述的半导体封装件3,3’,4,5还包括形成于该介电层31与该半导体芯片37,37’之间的胶材（即该粘着材料371或该底胶38’）。
于一实施例中，该线路层34还具有置晶垫343，以令该半导体芯片37置放于该置晶垫343上，且该置晶垫343可作为电性连接垫。
于一实施例中，该些焊垫341布设位于该半导体芯片37的外缘处。
于一实施例中，该焊垫341位于该电性连接垫342,342’与该半导体芯片37之间。
综上所述，本发明的半导体封装件及其制法，主要借由该制增层线路用的介电层可同时作为止蚀层与防焊层，所以能以铜材或铝材制作线路层，而无需以金材制作线路层与止蚀层，且无需制作防焊层与化镀铜，所以本发明有效降低制作成本。
此外，该制增层线路用的介电层与铜材或铝材的结合性佳，所以该制增层线路用的介电层于该开孔处周围不会发生脱层现象，因而有效提升本发明的半导体封装件的可靠度。
另外，使用铜材制作该线路层，不仅可节省金材的使用量以降低材料成本，且利于微小化该半导体封装件的尺寸。
上述实施例仅用以例示性说明本发明的原理及其功效，而非用于限制本发明。任何本领域技术人员均可在不违背本发明的精神及范畴下，对上述实施例进行修改。因此本发明的权利保护范围，应如权利要求书所列。

Claims (20)

1.一种半导体封装件，其包括：
制作增层线路用的介电层，其具有相对的第一表面与第二表面，并具有贯穿于该第一与第二表面的开孔；
线路层，其形成于该介电层的第一表面上，该线路层具有多条线路及位于各该线路两端的焊垫与电性连接垫，且令该些电性连接垫外露于该介电层的开孔；
至少一半导体芯片，其置放于该介电层的第一表面上，且该半导体芯片具有多个电极垫；以及
多条焊线，其电性连接该半导体芯片的电极垫与该些焊垫。
2.一种半导体封装件，其包括：
制作增层线路用的介电层，其具有相对的第一表面与第二表面，且具有贯穿于该第一与第二表面的开孔；
线路层，其形成于该介电层的第一表面上，该线路层具有多条线路及位于各该线路两端的焊垫与电性连接垫，且令该些电性连接垫外露于该介电层的开孔；
多个导电凸块，形成于该些焊垫上；以及
至少一半导体组件，其接置于该导电凸块上，且该半导体芯片具有多个电极垫，以借由该些导电凸块电性连接该些电极垫与该些焊垫。
3.根据权利要求1或2所述的半导体封装件，其特征在于，该介电层的材质为聚酰亚胺、ABF、环氧树脂复合玻璃材质、强化纤维复合玻璃材质或环氧树脂复合玻璃陶瓷粉材质。
4.根据权利要求1或2所述的半导体封装件，其特征在于，该半导体封装件还包括形成于该焊垫上的表面处理层。
5.根据权利要求1或2所述的半导体封装件，其特征在于，该半导体封装件还包括形成于该介电层的开孔中的焊球。
6.根据权利要求1或2所述的半导体封装件，其特征在于，该半导体封装件还包括形成于该介电层与该半导体芯片之间的胶材。
7.根据权利要求1或2所述的半导体封装件，其特征在于，该半导体封装件还包括封装胶体，其形成于该介电层的第一表面上，以包覆该半导体芯片与线路层。
8.根据权利要求1所述的半导体封装件，其特征在于，该线路层还具有置晶垫，以令该半导体芯片置放于该置晶垫上。
9.根据权利要求8所述的半导体封装件，其特征在于，该半导体芯片电性连接该置晶垫。
10.根据权利要求1所述的半导体封装件，其特征在于，该些焊垫布设位于该半导体芯片的外缘处。
11.根据权利要求1所述的半导体封装件，其特征在于，该焊垫位于该电性连接垫与该半导体芯片之间。
12.一种半导体封装件的制法，其包括：
提供一承载件，该承载件表面具有介电层，且该介电层为制作增层线路用的介电层；
形成线路层于该介电层上，该线路层具有多条线路及位于各该线路两端的焊垫与电性连接垫；
置放至少一半导体芯片于该介电层上，且令该半导体芯片电性连接该些焊垫；
形成封装胶体于该介电层上，以包覆该半导体芯片与线路层；
移除该承载件，且保留该介电层于该封装胶体上；以及
形成贯穿该介电层的开孔，以外露该电性连接垫。
13.根据权利要求12所述的半导体封装件的制法，其特征在于，该承载件的材质为金属。
14.根据权利要求12所述的半导体封装件的制法，其特征在于，形成该介电层的材质为聚酰亚胺、ABF、环氧树脂复合玻璃材质、强化纤维复合玻璃材质或环氧树脂复合玻璃陶瓷粉材质。
15.根据权利要求12所述的半导体封装件的制法，其特征在于，该线路层以电镀方式形成。
16.根据权利要求12所述的半导体封装件的制法，其特征在于，该线路层还具有置晶垫，以令该半导体芯片置放于该置晶垫上。
17.根据权利要求12所述的半导体封装件的制法，其特征在于，该半导体芯片以焊线或导电凸块电性连接该些焊垫。
18.根据权利要求12所述的半导体封装件的制法，其特征在于，是以蚀刻方式移除该承载件。
19.根据权利要求12所述的半导体封装件的制法，其特征在于，该制法还包括形成焊球于该介电层的开孔中。
20.根据权利要求12所述的半导体封装件的制法，其特征在于，该制法还包括形成封装胶体于该介电层的第一表面上，以包覆该半导体芯片与线路层。
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