JP2010093109A - 半導体装置、半導体装置の製造方法および半導体モジュールの製造方法 - Google Patents
半導体装置、半導体装置の製造方法および半導体モジュールの製造方法 Download PDFInfo
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- JP2010093109A JP2010093109A JP2008262682A JP2008262682A JP2010093109A JP 2010093109 A JP2010093109 A JP 2010093109A JP 2008262682 A JP2008262682 A JP 2008262682A JP 2008262682 A JP2008262682 A JP 2008262682A JP 2010093109 A JP2010093109 A JP 2010093109A
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Abstract
【解決手段】配線基板3の上面上に半導体チップが搭載され、配線基板3の下面3bに形成された複数のランド上に複数の半田ボール6がそれぞれ配置されている。複数のランドは、配線基板3の下面3bの周縁部に沿って、かつ複数列に亘ってランド16aが配列された第1ランド群56と、配線基板3の下面3bにおいて第1ランド群56よりも内側にランド16bが配列された第2ランド群57とを有し、第1ランド群56は、第1ピッチでランド16aが配列され、第2ランド群57は、第1ピッチよりも大きい第2ピッチでランド16bが配列されている。
【選択図】図59
Description
本実施の形態の半導体装置を図面を参照して説明する。
まず、半導体チップ2の構成について説明する。
次に、配線基板3の構成について説明する。
次に、本実施の形態の半導体装置1の製造方法を、図面を参照して説明する。図10は、本実施の形態の半導体装置1の製造工程を示す工程フロー図である。図11〜図15および図22は、本実施の形態の半導体装置1の製造工程中の断面図であり、上記図4(上記図2のA1−A1線の断面)に対応する断面が示されている。図16〜図21は、ステップS5の半田ボール6の接続工程の説明図(説明用の断面図)であり、上記図2のB1−B1線に対応する断面が示されている。
次に、本実施の形態の半導体装置1を実装基板(マザーボード)に実装し、半導体モジュールを製造する方法について、図面を参照して説明する。図23は、半導体モジュールの製造工程の一部(半導体装置1の実装工程)を示す工程フロー図である。図24は、半導体装置1を実装するための実装基板である配線基板31の断面図(要部断面図)であり、図25は、配線基板31の平面図(要部平面図)であり、図26は、図25の部分拡大平面図であり、図27は配線基板31の部分拡大断面図である。なお、図25のA2−A2線の断面図が図24にほぼ対応し、図25の二点鎖線で囲まれた領域27の拡大図が図26にほぼ対応し、図26のC1−C1線の断面が図27にほぼ対応する。また、理解を簡単にするために、図26では、配線基板31の半田レジスト層36を透視し、基板側端子32および引出し配線35のパターンを示してある。また、配線基板31上に半導体装置1を実装した際に、図25のA2−A2線と、上記図1および図2のA1−A1線とは、平面的に一致する。また、配線基板31上に半導体装置1を実装した際に、半導体装置1が平面的に重なる領域(半導体装置1搭載領域)28を点線で図25に示してある。図28〜図30は、本実施の形態の半導体モジュールの製造工程(半導体装置の実装工程)中の断面図(要部断面図)であり、上記図24に対応する断面、すなわち上記図4にも対応する断面が示されている。図31は、図30の部分拡大断面図であり、図30および図31には、半導体装置1を配線基板31に実装した状態が示されている。また、図32および図33は、製造された半導体モジュールMJ1の一例を模式的に示す平面図および断面図であり、図32のD1−D1線の断面が図33にほぼ相当する。
次に、本実施の形態の半導体装置1の下面、すなわち配線基板3の下面3bにおける、複数の半田ボール6(又はランド16)の配列の仕方について、詳細に説明する。
上述のように、配線基板31への半導体装置1の実装時の半田リフロー工程において、第1半田ボール群51の半田ボール6aに比べて中央部(配線基板3の下面3bの中央部)側に位置する第2半田ボール群52の半田ボール6bは、半導体装置1の反りによって押しつぶされやすい。特に、この反り(配線基板3の下面3bの中央部が、実装基板(上記配線基板31に対応)側に突出する反り)は、半導体チップ2の熱膨張係数が配線基板3の熱膨張係数よりも低く、さらに、半導体チップ2のサイズ(外形寸法)が配線基板3のサイズ(外形寸法)とほぼ同じ大きさの場合に発生しやすい。
尚、本実施の形態では、図2に配線基板3の下面3bに形成された第2ランド群57が、第1ランド群56の第1ピッチよりも大きい第2ピッチでランド16が配列することについて説明したが、これに限定されるものではない。
本実施の形態2の半導体装置を図面を参照して説明する。
本実施の形態3の半導体装置を図面を参照して説明する。
本実施の形態の半導体装置を図面を参照して説明する。
本実施の形態では、上記実施の形態1の半導体装置1の他の製造方法について、図面を参照して説明する。本実施の形態では、印刷法によって、上記半田ボール6を形成する。
本実施の形態の半導体装置を、図面を参照して説明する。
本実施の形態の半導体装置を、図面を参照して説明する。
本実施の形態の半導体装置を、図面を参照して説明する。
2 半導体チップ
2a,2aSGN1,2aSGN2,2aSGN3,2aSGN4,2aVDD,2aGND 電極(電極パッド、ボンディングパッド)
3 配線基板(インターポーザ)
3a 上面(第1面、表面、主面、チップ支持面)
3b 下面(第2面、裏面、上面3aとは反対側の主面)
4 導電性部材(ボンディングワイヤ)
5,5a 封止樹脂(封止樹脂部、封止部、封止体)
6,6a,6a1,6a2,6a3,6a4,6b,6b1,6b2,6b3,6c,6d,6e,6e1,6e2,6e3,6e4,6e5 外部端子(半田ボール、ボール電極、半田バンプ、バンプ電極、突起電極)
8 接着材
9 貫通孔(スリット)
11 基材層
14 ボンディングリード(電極、ボンディングパッド、パッド電極)
15 配線
16,16a,16b ランド(電極、パッド、端子)
17 端子(ランド)
18,18a ビア配線
19 導体層
21 配線基板
21a 上面
21b 下面
22 半導体装置領域
22a 領域
24 マスク
24a 孔部
25 フラックス
27,27a,27b,28 領域
31 配線基板(実装基板、マザーボード)
31a 上面(表面)
31b 下面
32,32a,32b 基板側端子
33 絶縁体層
34 配線層
35 引出し配線
36 半田レジスト層
37 ビアホール
38 導体膜
40 基板側端子
41 半田ペースト
46 半田ボール
51 第1半田ボール群
51a,51b 半田ボール群
51e 第1基板側端子群
52 第2半田ボール群
52a 半田ボール群
52e 第2基板側端子群
56 第1ランド群
56a,56b ランド群
57 第2ランド群
57a ランド群
58 第1開口部群
59 第2開口部群
61a,61b,62a,62b,67a、67b、67c、68a,68b,68c,69a,69b,69c 列
71,72,73 半導体チップ
71a,72a,73a 電極
74 アンダーフィル樹脂
75,76 接着材
81 マスク
82,82a,82b 開口部
83 半田ペースト
84 半田バンプ
101 半導体装置
103 配線基板
106 半田ボール
128 領域
131 実装基板
132 基板側端子
135 引出し配線
140 基板側端子
201 BGA
206 半田バンプ
231 実装基板
BP1 バンプ電極
CP1 コンデンサ
G1,G2,G3,G11,G12,G13,G14,G15 間隔
L1,L2,L3,L4,L5 距離(隣接する半田ボール間の距離)
LSI1,LSI2 外部LSI
MJ1 半導体モジュール
P1,P2,P3,P4,P5 ピッチ
R1 領域
RS1 抵抗
SC1 半導体集積回路
SR1,SR2 ソルダレジスト層
SR1a,SR2a 開口部
X 第1ランド群(又は第1半田バンプ群)の配置領域
Y 第2ランド群(又は第2半田バンプ群)の配置領域
Z テスト用のランドの配置領域
Claims (20)
- 第1面、前記第1面に形成された複数のボンディングリード、前記第1面とは反対側の第2面、及び前記第2面に形成された複数のランドを有する配線基板と、
第3面、前記第3面に形成された複数の電極パッド、及び前記第3面とは反対側の第4面を有し、前記配線基板の前記第1面上に搭載された半導体チップと、
前記半導体チップの前記複数の電極パッドと前記配線基板の前記複数のボンディングリードとをそれぞれ電気的に接続する複数の導電性部材と、
前記配線基板の前記複数のランドのそれぞれに配置された複数の外部端子と、
を含み、
前記複数のランドは、前記配線基板の前記第2面の周縁部に沿って、かつ複数列に亘って前記ランドが配列された第1ランド群と、前記配線基板の前記第2面において前記第1ランド群よりも内側に前記ランドが配列された第2ランド群とを有し、
前記第1ランド群は、第1ピッチで前記ランドが配列され、
前記第2ランド群は、前記第1ピッチよりも大きい第2ピッチで前記ランドが配列されていることを特徴とする半導体装置。 - 請求項1において、
前記第1ランド群と前記第2ランド群との距離は、前記第1ランド群における列の間隔よりも大きいことを特徴とする半導体装置。 - 請求項2において、
前記配線基板の熱膨張係数は、前記半導体チップの熱膨張係数よりも大きいことを特徴とする半導体装置。 - 請求項3において、
前記半導体チップには、回路素子が形成されており、
前記複数の電極パッドは、前記回路素子と電気的に接続された複数の信号用電極パッドを有し、
前記第1ランド群及び前記第2ランド群のそれぞれは、前記複数の信号用電極パッドと電気的に接続されていることを特徴とする半導体装置。 - 請求項4において、
前記第2ランド群は、複数列に亘って前記ランドが配列されており、
前記第1ランド群では、隣り合う列同士の配列が一致し、
前記第2ランド群では、隣り合う列同士の配列がずれていることを特徴とする半導体装置。 - 請求項5において、
前記第1ランド群では、隣り合う列に属する前記ランド同士が、列の進行方向と直交する方向に見て重なっており、
前記第2ランド群では、列の進行方向と直交する方向に見て、各列に属する前記ランドの間に、その列の隣の列に属する前記ランドが位置していることを特徴とする半導体装置。 - (a)第1面、前記第1面に形成された複数のボンディングリード、前記第1面とは反対側の第2面、及び前記第2面に形成された複数のランドを有する配線基板と、第3面、前記第3面に形成された複数の電極パッド、及び前記第3面とは反対側の第4面を有し、前記配線基板の前記第1面上に搭載された半導体チップと、前記半導体チップの前記複数の電極パッドと前記配線基板の前記複数のボンディングリードとをそれぞれ電気的に接続する複数の導電性部材と、前記配線基板の前記複数のランドのそれぞれに配置された複数の外部端子とを有する半導体装置を準備する工程、
(b)表面、及び前記表面に形成された複数の接続端子を有する実装基板を準備する工程、
(c)前記第2面が前記表面と対向するように、前記実装基板の前記表面上に前記半導体装置を配置する工程、
(d)前記(c)工程後、熱処理を行い、前記半導体装置の前記複数の外部端子を前記実装基板の前記複数の接続端子にそれぞれ電気的に接続する工程、
を含み、
前記(a)工程で準備された前記半導体装置では、
前記複数のランドは、前記配線基板の前記第2面の周縁部に沿って、かつ複数列に亘って前記ランドが配列された第1ランド群と、前記配線基板の前記第2面において前記第1ランド群よりも内側に前記ランドが配列された第2ランド群とを有し、
前記第1ランド群は、第1ピッチで前記ランドが配列され、
前記第2ランド群は、前記第1ピッチよりも大きい第2ピッチで前記ランドが配列されていることを特徴とする半導体モジュールの製造方法。 - 請求項7において、
前記(b)工程で準備された前記実装基板の前記表面の前記複数の接続端子は、前記半導体装置の前記複数の外部端子の配列に対応した配列を有していることを特徴とする半導体モジュールの製造方法。 - 請求項8において、
前記第1ランド群と前記第2ランド群との距離は、前記第1ランド群における列の間隔よりも大きいことを特徴とする半導体モジュールの製造方法。 - 請求項9において、
前記配線基板の熱膨張係数は、前記半導体チップの熱膨張係数よりも大きいことを特徴とする半導体モジュールの製造方法。 - 請求項10において、
前記半導体チップには、回路素子が形成されており、
前記複数の電極パッドは、前記回路素子と電気的に接続された複数の信号用電極パッドを有し、
前記第1ランド群及び前記第2ランド群のそれぞれは、前記複数の信号用電極パッドと電気的に接続されていることを特徴とする半導体モジュールの製造方法。 - 請求項11において、
前記(a)工程で準備された前記半導体装置では、
前記第2ランド群は、複数列に亘って前記ランドが配列されており、
前記第1ランド群は、隣り合う列同士の配列が一致し、
前記第2ランド群は、隣り合う列同士の配列がずれていることを特徴とする半導体モジュールの製造方法。 - 請求項12において、
前記(a)工程で準備された前記半導体装置では、
前記第1ランド群では、隣り合う列に属する前記ランド同士が、列の進行方向と直交する方向に見て重なっており、
前記第2ランド群では、列の進行方向と直交する方向に見て、各列に属する前記ランドの間に、その列の隣の列に属する前記ランドが位置していることを特徴とする半導体モジュールの製造方法。 - 第1面、前記第1面に形成された複数のボンディングリード、前記第1面とは反対側の第2面、及び前記第2面に形成された複数のランドを有する配線基板と、
第3面、前記第3面に形成された複数の電極パッド、及び前記第3面とは反対側の第4面を有し、前記配線基板の前記第1面上に搭載された半導体チップと、
前記半導体チップの前記複数の電極パッドと前記配線基板の前記複数のボンディングリードとをそれぞれ電気的に接続する複数の導電性部材と、
前記配線基板の前記複数のランドのそれぞれに配置された複数の外部端子と、
を含み、
前記複数の外部端子は、前記配線基板の前記第2面の周縁部に沿って、かつ複数列に亘って前記外部端子が配列された第1外部端子群と、前記配線基板の前記第2面において前記第1外部端子群よりも内側に前記外部端子が配列された第2外部端子群とを有し、
前記第1外部端子群は、第1ピッチで前記外部端子が配列され、
前記第2外部端子群は、前記第1ピッチよりも大きい第2ピッチで前記外部端子が配列されていることを特徴とする半導体装置。 - 請求項14において、
前記第1外部端子群と前記第2外部端子群との距離は、前記第1外部端子群における列の間隔よりも大きいことを特徴とする半導体装置。 - 請求項15において、
前記配線基板の熱膨張係数は、前記半導体チップの熱膨張係数よりも大きいことを特徴とする半導体装置。 - 請求項16において、
前記半導体チップには、回路素子が形成されており、
前記複数の電極パッドは、前記回路素子と電気的に接続された複数の信号用電極パッドを有し、
前記第1外部端子群及び前記第2外部端子群のそれぞれは、前記複数の信号用電極パッドと電気的に接続されていることを特徴とする半導体装置。 - 請求項17において、
前記第2外部端子群は、複数列に亘って前記外部端子が配列されており、
前記第1外部端子群では、隣り合う列同士の配列が一致し、
前記第2外部端子群では、隣り合う列同士の配列がずれていることを特徴とする半導体装置。 - 請求項18において、
前記第1外部端子群では、隣り合う列に属する前記外部端子同士が、列の進行方向と直交する方向に見て重なっており、
前記第2外部端子群では、列の進行方向と直交する方向に見て、各列に属する前記外部端子の間に、その列の隣の列に属する前記外部端子が位置していることを特徴とする半導体装置。 - 以下の工程を含むことを特徴とする半導体装置の製造方法:
(a)第1面、前記第1面に形成された複数のボンディングリード、前記第1面とは反対側の第2面、及び前記第2面に形成された複数のランドを有する配線基板を準備する工程;
(b)第3面、前記第3面に形成された複数の電極パッド、及び前記第3面とは反対側の第4面を有する半導体チップを、前記配線基板の前記第1面上に搭載する工程;
(c)前記半導体チップの前記複数の電極パッドと前記配線基板の前記複数のボンディングリードとを、複数の導電性部材を介してそれぞれ電気的に接続する工程;
(d)前記配線基板の前記複数のランドに、複数の外部端子をそれぞれに配置する工程;
ここで、
前記複数の外部端子は、前記配線基板の前記第2面の周縁部に沿って、かつ複数列に亘って前記外部端子が配列された第1外部端子群と、前記配線基板の前記第2面において前記第1外部端子群よりも内側に前記外部端子が配列された第2外部端子群とを有し、
前記第1外部端子群は、第1ピッチで前記外部端子が配列され、
前記第2外部端子群は、前記第1ピッチよりも大きい第2ピッチで前記外部端子が配列されている。
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US8405231B2 (en) | 2013-03-26 |
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US20100090333A1 (en) | 2010-04-15 |
US20120043656A1 (en) | 2012-02-23 |
CN101719486A (zh) | 2010-06-02 |
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