TWI445155B - 堆疊式封裝結構及其製造方法 - Google Patents

堆疊式封裝結構及其製造方法 Download PDF

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Publication number
TWI445155B
TWI445155B TW100100425A TW100100425A TWI445155B TW I445155 B TWI445155 B TW I445155B TW 100100425 A TW100100425 A TW 100100425A TW 100100425 A TW100100425 A TW 100100425A TW I445155 B TWI445155 B TW I445155B
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Taiwan
Prior art keywords
die
substrate
wafer
protective layer
crystal grains
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TW100100425A
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English (en)
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TW201230288A (en
Inventor
Chia Lin Hung
Jen Chuan Chen
Hui Shan Chang
Kuo Pin Yang
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Advanced Semiconductor Eng
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Priority to TW100100425A priority Critical patent/TWI445155B/zh
Priority to US13/311,364 priority patent/US8643167B2/en
Publication of TW201230288A publication Critical patent/TW201230288A/zh
Application granted granted Critical
Publication of TWI445155B publication Critical patent/TWI445155B/zh

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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Description

堆疊式封裝結構及其製造方法
本發明係關於一種封裝結構及其製造方法，詳言之，係關於一種堆疊式封裝結構及其製造方法。
堆疊式封裝結構係將二顆晶粒(下晶粒及上晶粒)堆疊在一基板上以形成之三維封裝結構，其中位於下方之下晶粒會具有複數個連通柱(Through Silicon Via,TSV)結構，該等連通柱會突出於該下晶粒之一表面，而且該下晶粒另一表面會具有複數個凸塊結構。習知製造方法係先將薄化過後的下晶粒直接以熱壓製程與基板接著，接著再將上晶粒以相同方法堆疊於該下晶粒上。因此，該製造方法會遭遇以下問題。
首先，薄化過後的下晶粒在搬運及運送是一項挑戰。其次，該基板的翹曲在該下晶粒堆疊過程中，會造成電性量測上的良率降低、凸塊結構接著失敗等問題。接著，以熱壓作為晶粒接著的技術而言，產出的速度較低。
因此，有必要提供一種堆疊式封裝結構及其製造方法，以解決上述問題。
本發明提供一種堆疊式封裝結構之製造方法，其包括以下步驟：(a)提供一晶圓，該晶圓具有一第一表面及一第二表面；(b)提供複數個第一晶粒，每一該第一晶粒包括一第一晶粒本體、複數個連通柱(Conductive Vias)及複數個凸塊，該第一晶粒本體包括一第一表面及一第二表面，該等連通柱係突出於該第二表面，該等凸塊係鄰接於該第一表面且電性連接該等連通柱；(c)覆晶接合該等第一晶粒至該晶圓之第一表面，其中該等連通柱係電性連接至該晶圓之第一表面；(d)將該等第一晶粒及該晶圓進行迴焊(Reflow)；(e)形成一第一保護層於該等第一晶粒及該晶圓之第一表面之間以保護該等連通柱；(f)於步驟(d)之後，從該晶圓之第二表面薄化該晶圓；(g)切割該晶圓以形成複數個複合晶粒(Combo Die)；(h)提供一基板，該基板具有一第一表面及一第二表面；(i)形成一第二保護層於該基板之第一表面；(j)將該等複合晶粒接合至該基板之第一表面上，其中該等凸塊係位於該第二保護層內；及(k)切割該基板，以形成複數個堆疊式封裝結構。
在本發明中，在步驟(d)中該晶圓及其上之該等第一晶粒係同時進行迴焊，因此可節省時間，而且該晶圓及該等第一晶粒之材質相同，而不會有翹曲之情況發生。此外，該晶圓係在迴焊後才薄化，因此其在搬運及運送過程中容易夾持。
本發明另提供由上述方法所製得之堆疊式封裝結構，其包括一基板、一第一晶粒、一第二保護層、一第二晶粒及一第一保護層。該基板具有一第一表面及一第二表面。該第一晶粒接合於該基板，該第一晶粒包括一第一晶粒本體、複數個連通柱及複數個凸塊，該第一晶粒本體包括一第一表面及一第二表面，該等連通柱係突出於該第二表面，該等凸塊係鄰接於該第一表面且電性連接該等連通柱，且該等凸塊係電性連接該基板之第一表面。該第二保護層位於該基板之第一表面及該第一晶粒本體之第一表面之間，以保護該等凸塊。該第二晶粒具有一第一表面及一第二表面，該第二晶粒係利用迴焊製程而與該第一晶粒之該等連通柱接合。該第一保護層位於該第一晶粒本體之第二表面及該第二晶粒之第一表面之間，以保護該等連通柱。
參考圖1至11，顯示本發明堆疊式封裝結構之製造方法之一實施例之示意圖。參考圖1，提供一晶圓1，該晶圓1具有一第一表面101及一第二表面102。在本實施例中，該晶圓1係為一整片材質相同之矽晶圓，其具有複數條切割線103，該等切割線103定義出複數個第二晶粒10。亦即，該晶圓1沿著該等切割線103被切割後即直接形成該等第二晶粒10。較佳地，該晶圓1更具有複數個第二銲墊104及複數個預銲料(Presolder)105，該等第二銲墊104係位於該晶圓1之第一表面101，且該等預銲料105係位於該等第二銲墊104上。在本實施例中，該等第二晶粒10係為記憶體晶粒(Memory Dice)。
參考圖2，提供複數個第一晶粒12。每一該第一晶粒12包括一第一晶粒本體14、複數個連通柱(Conductive Vias)16及複數個凸塊18。該第一晶粒本體14包括一第一表面141及一第二表面142。該等連通柱16係突出於該第二表面142，且其數目及位置係對應該等第二銲墊104。該等凸塊18係鄰接於該第一表面141且電性連接該等連通柱16。在本實施例中，該等凸塊18係為銅柱(Copper Pillar)及焊料(Solder)之堆疊結構。在其他實施例中，該等凸塊18可僅為銅柱亦或是焊料。
較佳地，該等第一晶粒12係為處理器晶粒(Processor Die)。每一該第一晶粒12更包括一鈍化層(Passivation Layer)22、一重佈層(Redistribution,RDL)24、一表面處理層(Surface Finish Layer)(圖中未示)及複數個第一銲墊20。該鈍化層22係位於該第二表面142，其材質例如苯環丁烯(Benzocyclobutene,BCB)、聚醯亞胺(polyimide，PI)等高分子材料；亦或是無機絕緣層，如：二氧化矽(SiO2 )。該重佈層24係位於該第一表面141。該等第一銲墊20係位於該重佈層24上，且該等凸塊18係位於該等第一銲墊20上。該表面處理層係位於該等連通柱16突出之一端161。
接著，以覆晶接合方式將該等第一晶粒12接合至該晶圓1之第一表面101，其中該等連通柱16係電性連接至該晶圓1之第一表面101。在本實施例中，該等連通柱16突出之一端161係接觸該等預銲料105而電性連接至該晶圓1之該等第二銲墊104。
接著，將該晶圓1及其上之該等第一晶粒12一起放進一迴焊爐中，使該等第一晶粒12及該晶圓1進行迴焊(Reflow)。在本實施例中，由於未進行熱壓，因此該等連通柱16突出之一端161係未接觸到該等第二銲墊104。而且該等預銲料105之外型變形量比習知熱壓製程來得小。
參考圖3，形成一第一保護層26於該等第一晶粒12及該晶圓1之第一表面101之間以保護該等連通柱16。在本實施例中，該第一保護層26係為一底膠(Underfill)，較佳為毛細底膠(Capillary Underfill,CUF)，其黏度約為100Pa.s，係以毛細現象充滿該等連通柱16之間。
參考圖4，將該晶圓1之第一表面101及其上之該等第一晶粒12黏附至一背磨膠帶(BSG Tape)28，且顯露該晶圓1之第二表面102。參考圖5，利用一研磨機31研磨該晶圓1之第二表面102以薄化該晶圓1，使得該晶圓1之厚度從圖1之約760μm降至約50μm。之後，移除該背磨膠帶28。
參考圖6，將該晶圓1之第二表面102黏附至一切割膠帶(DC Tape)29，且顯露該晶圓1之第一表面101及其上之該等第一晶粒12。參考圖7，沿著該等切割線103切割該晶圓1以形成複數個複合晶粒(Combo Die)30。每一複合晶粒30包括一第一晶粒12及一第二晶粒10，其中該第一晶粒12之寬度係小於該第二晶粒10之寬度。
參考圖8，提供一基板32，例如一有機基板(Organic Substrate)。該基板32具有一第一表面321及一第二表面322。較佳地，該基板32更包含複數個基板焊墊323，位於該基板32之第一表面321。接著，形成一第二保護層34於該基板32之第一表面321。在本實施例中，該第一保護層26與該第二保護層34不同。該第二保護層34係為一非導電膠(Non Conductive Paste,NCP)，且其黏度約為200Pa.s。亦即，該第二保護層34之黏度係大於該第一保護層26之黏度，且該第二保護層34固化時間比該第一保護層26短。在本實施例中，該第二保護層34可為一高分子膠材，例如是環氧樹脂膠(Epoxy Paste)或是壓克力膠(Acrylic Paste)；在其他實施例中，該第二保護層34亦可為一非導電高分子膜(Non Conductive Film,NCF)。
參考圖9，將該等複合晶粒30接合至該基板32之第一表面321上。在本實施例中，係以熱壓合(Thermal Compression Bonding,TCB)方式將複合晶粒30接合至基板32。接合後，該等凸塊18係電性連接至該基板32之第一表面321，且位於該第二保護層34內。在本實施例中，該等凸塊18係接觸且電性連接至該基板焊墊323上。
參考圖10，形成複數個外銲球36於該基板32之第二表面322。參考圖11，切割該基板32，以形成複數個堆疊式封裝結構4。
在本發明中，該晶圓1及其上之該等第一晶粒12係同時進行迴焊，因此可節省時間，而且該晶圓1及該等第一晶粒12之材質相同，而不會有翹曲之情況發生。此外，該晶圓1係在迴焊後才薄化，因此其在搬運及運送過程中容易夾持。
參考圖11，顯示本發明堆疊式封裝結構之一實施例之示意圖。該堆疊式封裝結構4包括一基板32、一第一晶粒12、一第二保護層34、一第二晶粒10及一第一保護層26。
該基板32具有一第一表面321及一第二表面322。該第一晶粒12接合於該基板32。該第一晶粒12包括一第一晶粒本體14、複數個連通柱16及複數個凸塊18。該第一晶粒本體14包括一第一表面141及一第二表面142，該等連通柱16係貫穿該第一晶粒本體14，且突出於該第二表面142。該等凸塊18係鄰接於該第一表面141且電性連接該等連通柱16。該等凸塊18係接觸且電性連接該基板32之第一表面321。在本實施例中，該等凸塊18係為銅柱及焊料之堆疊結構。在其他實施例中，該等凸塊18可僅為銅柱亦或是焊料。較佳地，該基板32更包含複數個基板焊墊323，位於該第一表面321上，其中，該等凸塊18係接觸且電性連接至該基板焊墊323上。
較佳地，該第一晶粒12更包括一鈍化層22、一重佈層24、一表面處理層(圖中未示)及複數個第一銲墊20。該鈍化層22係位於該第二表面142，其材質例如苯環丁烯、聚醯亞胺等高分子材料；亦或是無機絕緣層，如：二氧化矽。該重佈層24係位於該第一表面141。該等第一銲墊20係位於該重佈層24上，且該等凸塊18係位於該等第一銲墊20上。該表面處理層係位於該等連通柱16突出之一端161。
該第二保護層34係位於該基板32之第一表面321及該第一晶粒本體14之第一表面141之間，以保護該等凸塊18。
第二晶粒10具有一第一表面101及一第二表面102。該第二晶粒10係利用迴焊製程而與該第一晶粒12之該等連通柱16接合。在本實施例中，該第二晶粒10更包括複數個第二銲墊104，該等第二銲墊104係鄰接於該第二晶粒10之第一表面101，且該等第二銲墊104係電性連接該等連通柱16。該第一晶粒12之寬度係小於該第二晶粒10之寬度。
該第一保護層26係位於該第一晶粒本體14之第二表面142及該第二晶粒10之第一表面101之間，以保護該等連通柱16。在本實施例中，該第一保護層26與該第二保護層34不同。該第一保護層26係為一底膠。該第二保護層34係為一非導電膠。該第二保護層34之黏度係大於該第一保護層26之黏度。
較佳地，該堆疊式封裝結構4更包括複數個外銲球36，位於該基板32之第二表面322。
參考圖12至22，顯示本發明堆疊式封裝結構之製造方法之另一實施例之示意圖。參考圖12，提供一晶圓5，該晶圓5具有一第一表面501、一第二表面502及複數條切割線503。在本實施例中，該晶圓5包括複數個第二晶粒50及一絕緣層51，該等第二晶粒50係為切割後之晶粒，且重新排列後之該等第二晶粒50係彼此間隔而未接觸。該絕緣層51係位於該等第二晶粒50間之間隔內，且該等切割線503係經過該絕緣層51。較佳地，該晶圓5更具有複數個第二銲墊504及複數個預銲料505，該等第二銲墊504係位於該晶圓5之第二晶粒50之第一表面501，且該等預銲料505係位於該等第二銲墊504上。
參考圖13，提供複數個第一晶粒52。本實施例之該等第一晶粒52係與圖2之第一晶粒12大致相同，其不同處僅在於該等連通柱16之數目及位置。
接著，以覆晶接合方式將該等第一晶粒52接合至該晶圓5之第一表面501，其中該等連通柱16係電性連接至該晶圓5之第一表面501。在本實施例中，該等連通柱16突出之一端161係接觸該等預銲料505而電性連接至該晶圓5之該等第二銲墊504。
接著，將該晶圓5及其上之該等第一晶粒52一起放進一迴焊爐中，使該等第一晶粒52及該晶圓5進行迴焊。在本實施例中，由於未進行熱壓，因此該等連通柱16突出之一端161係未接觸到該等第二銲墊504。而且該等預銲料505之外型變形量比習知熱壓製程來得小。
參考圖14，形成一第一保護層26於該等第一晶粒52及該晶圓5之第一表面501之間以保護該等連通柱16。本實施例之該第一保護層26係與圖3之第一保護層26相同。參考圖15，將該晶圓5之第一表面501及其上之該等第一晶粒52黏附至一背磨膠帶28，且顯露該晶圓5之第二表面502。
參考圖16，利用研磨機31研磨該晶圓5之第二表面502以薄化該晶圓5。參考圖17，將該晶圓5之第二表面502黏附至一切割膠帶29，且顯露該晶圓5之第一表面501及其上之該等第一晶粒52。
參考圖18，沿著該等切割線503切割該晶圓5以形成複數個複合晶粒70。每一複合晶粒70包括一第一晶粒52、一第二晶粒50及一絕緣層51。該第一晶粒52之寬度係大於該第二晶粒50之寬度。該絕緣層51係位於該第二晶粒50之外圍。
參考圖19，提供一基板32。該基板32具有一第一表面321及一第二表面322。較佳地，該基板32更包含複數個基板焊墊323，位於該基板32之第一表面321。接著，形成一第二保護層34於該基板32之第一表面321。本實施例之該基板32及該第二保護層34係與圖8之基板32及該第二保護層34相同。
參考圖20，將該等複合晶粒70接合至該基板32之第一表面321上。參考圖21，形成複數個外銲球36於該基板32之第二表面322。參考圖22，切割該基板32，以形成複數個堆疊式封裝結構8。
參考圖22，顯示本發明堆疊式封裝結構之另一實施例之示意圖。本實施例之堆疊式封裝結構8與圖11之堆疊式封裝結構4大致相同，其中相同之元件賦予相同之編號。
該堆疊式封裝結構8包括一基板32、一第一晶粒52、一第二保護層34、一第二晶粒50、一絕緣層51及一第一保護層26。
該基板32具有一第一表面321及一第二表面322。該第一晶粒52接合於該基板32。該第一晶粒52包括一第一晶粒本體14、複數個連通柱16、複數個凸塊18、一鈍化層22、一重佈層24、一表面處理層(圖中未示)及複數個第一銲墊20。較佳地，該基板32更包含複數個基板焊墊323，位於該第一表面321上，其中，該等凸塊18係接觸且電性連接至該基板焊墊323上。
該第二保護層34係位於該基板32之第一表面321及該第一晶粒本體14之第一表面141之間，以保護該等凸塊18。
第二晶粒50具有一第一表面501及一第二表面502。該第二晶粒50係利用迴焊製程而與該第一晶粒52之該等連通柱16接合。在本實施例中，該第二晶粒50更包括複數個第二銲墊504，該等第二銲墊504係鄰接於該第二晶粒50之第一表面501，且該等第二銲墊504係電性連接該等連通柱16。該第一晶粒52之寬度係大於該第二晶粒50之寬度。
該第一保護層26係位於該第一晶粒本體14之第二表面142及該第二晶粒50之第一表面501之間，以保護該等連通柱16。
較佳地，該堆疊式封裝結構8更包括複數個外銲球36，位於該基板32之第二表面322。
參考圖23至29，顯示本發明堆疊式封裝結構之製造方法之另一實施例之示意圖。本實施例之製造方法之前半段(即該複合晶粒30之製造方法)與圖1至圖7之製造方法相同，因此不再贅述。
參考圖23，提供一基板32。該基板32具有一第一表面321、一第二表面322及複數個基板焊墊323。接著，形成複數個內銲球33於該基板32之第一表面321。參考圖24，形成一第二保護層34於該基板32之第一表面321，其中該第二保護層34係形成於該等內銲球33之間。
參考圖25，將該等複合晶粒30接合至該基板32之第一表面321上。接合後，該等凸塊18係接電性連接至該些基板焊墊323，且位於該第二保護層34內。而且該第二晶粒50係未延伸至該等內銲球33正上方。參考圖26，形成一封膠材料35於該基板32之第一表面321以包覆該等複合晶粒30及該等內銲球33。
參考圖27，利用雷射形成複數個開口351於該封膠材料35以顯露該等內銲球33。參考圖28，形成複數個外銲球36於該基板32之第二表面322。參考圖29，切割該基板32，以形成複數個堆疊式封裝結構9。
參考圖29，顯示本發明堆疊式封裝結構之另一實施例之示意圖。本實施例之堆疊式封裝結構9與圖11之堆疊式封裝結構4大致相同，其中相同之元件賦予相同之編號。本實施例之堆疊式封裝結構9與圖11之堆疊式封裝結構4之不同處在於，該堆疊式封裝結構9更包括複數個內銲球33及一封膠材料35。該等內銲球33係位於該基板32之第一表面321且位於該第二保護層34之外。該封膠材料35係位於該基板32之第一表面321以包覆該第一晶粒12及該第二晶粒10，且該封膠材料35具有複數個開口351以顯露該等內銲球33。
惟上述實施例僅為說明本發明之原理及其功效，而非用以限制本發明。因此，習於此技術之人士對上述實施例進行修改及變化仍不脫本發明之精神。本發明之權利範圍應如後述之申請專利範圍所列。
1．．．晶圓
4．．．堆疊式封裝結構
5．．．晶圓
8．．．堆疊式封裝結構
9．．．堆疊式封裝結構
10．．．第二晶粒
12．．．第一晶粒
14．．．第一晶粒本體
16．．．連通柱
18．．．凸塊
20．．．第一銲墊
22．．．鈍化層
24．．．重佈層
26．．．第一保護層
28．．．背磨膠帶
29．．．切割膠帶
30．．．複合晶粒
31．．．研磨機
32．．．基板
33．．．內銲球
34．．．第二保護層
35．．．封膠材料
36．．．外銲球
50．．．第二晶粒
51．．．絕緣層
52．．．第一晶粒
70．．．複合晶粒
101．．．第一表面
102．．．第二表面
103．．．切割線
104．．．第二銲墊
141．．．第一表面
142．．．第二表面
161．．．連通柱突出之一端
321．．．第一表面
322．．．第二表面
323．．．基板焊墊
351．．．開口
501．．．第一表面
502．．．第二表面
503．．．切割線
504．．．第二銲墊
圖1至11顯示本發明堆疊式封裝結構之製造方法之一實施例之示意圖；
圖12至22顯示本發明堆疊式封裝結構之製造方法之另一實施例之示意圖；及
圖23至29顯示本發明堆疊式封裝結構之製造方法之另一實施例之示意圖。
4．．．堆疊式封裝結構
10．．．第二晶粒
12．．．第一晶粒
14．．．第一晶粒本體
16．．．連通柱
18．．．凸塊
20．．．第一銲墊
22．．．鈍化層
24．．．重佈層
26．．．第一保護層
30．．．複合晶粒
32．．．基板
34．．．第二保護層
36．．．外銲球
101．．．第一表面
102．．．第二表面
104．．．第二銲墊
141．．．第一表面
142．．．第二表面
161．．．連通柱突出之一端
321．．．第一表面
322．．．第二表面
323．．．基板焊墊

Claims (12)

  1. 一種堆疊式封裝結構之製造方法，包括：(a)提供一晶圓，該晶圓具有一第一表面及一第二表面；(b)提供複數個第一晶粒，每一該第一晶粒包括一第一晶粒本體、複數個連通柱(Conductive Vias)及複數個凸塊，該第一晶粒本體包括一第一表面及一第二表面，該等連通柱係突出於該第二表面，該等凸塊係鄰接於該第一表面且電性連接該等連通柱；(c)覆晶接合該等第一晶粒至該晶圓之第一表面，其中該等連通柱係電性連接至該晶圓之第一表面；(d)將該等第一晶粒及該晶圓進行迴焊(Reflow)；(e)形成一第一保護層於該等第一晶粒及該晶圓之第一表面之間以保護該等連通柱；(f)於步驟(d)之後，從該晶圓之第二表面薄化該晶圓；(g)切割該晶圓以形成複數個複合晶粒(Combo Die)；(h)提供一基板，該基板具有一第一表面及一第二表面；(i)形成一第二保護層於該基板之第一表面；(j)將該等複合晶粒接合至該基板之第一表面上，其中該等凸塊係位於該第二保護層內；及(k)切割該基板，以形成複數個堆疊式封裝結構。
  2. 如請求項1之方法，其中該步驟(a)中，該晶圓係為一整片材質相同之晶圓，其具有複數條切割線，該等切割線 定義出複數個第二晶粒，步驟(b)中，該等第一晶粒之寬度係小於該等第二晶粒之寬度，且該步驟(g)中，每一複合晶粒包括一第一晶粒及一第二晶粒。
  3. 如請求項1之方法，其中該步驟(a)中，該晶圓包括複數個第二晶粒及一絕緣層，該等第二晶粒係彼此間隔，該絕緣層係位於該等第二晶粒間之間隔內，步驟(b)中，該等第一晶粒之寬度係大於該等第二晶粒之寬度，且該步驟(g)中，每一複合晶粒包括一第一晶粒、一第二晶粒及部份絕緣層。
  4. 如請求項1之方法，其中該步驟(e)之第一保護層與該步驟(i)之第二保護層不同。
  5. 如請求項1之方法，其中該步驟(h)之後更包括一形成複數個內銲球於該基板之第一表面之步驟，且該步驟(i)之第二保護層係形成於該等內銲球之間。
  6. 如請求項5之方法，其中該步驟(j)之後更包括：(j1)形成一封膠材料於該基板之第一表面以包覆該等複合晶粒；及(j2)形成複數個開口於該封膠材料以顯露該等內銲球。
  7. 一種堆疊式封裝結構，包括：一基板，具有一第一表面及一第二表面；一第一晶粒，接合於該基板，該第一晶粒包括一第一晶粒本體、複數個連通柱及複數個凸塊，該第一晶粒本體包括一第一表面及一第二表面，該等連通柱係突出於該第二表面，該等凸塊係鄰接於該第一表面且電性連接 該等連通柱，且該等凸塊係電性連接該基板之第一表面；一第二保護層，位於該基板之第一表面及該第一晶粒本體之第一表面之間，以保護該等凸塊；一第二晶粒，具有一第一表面及一第二表面，該第二晶粒係利用迴焊製程而與該第一晶粒之該等連通柱接合；及一第一保護層，位於該第一晶粒本體之第二表面及該第二晶粒之第一表面之間，以保護該等連通柱。
  8. 如請求項7之堆疊式封裝結構，其中該等連通柱突出之一端具有一表面處理層。
  9. 如請求項7之堆疊式封裝結構，其中該第一晶粒更包括一鈍化層及一重佈層，該鈍化層係位於該第一晶粒本體之第二表面，且該重佈層係位於該第一晶粒本體之第一表面。
  10. 如請求項7之堆疊式封裝結構，其中該第一晶粒之寬度係小於該第二晶粒之寬度。
  11. 如請求項7之堆疊式封裝結構，其中該第一晶粒之寬度係大於該第二晶粒之寬度。
  12. 如請求項7之堆疊式封裝結構，其中該第一保護層係為一底膠，該第二保護層係為一非導電膠，該第二保護層之黏度係大於該第一保護層之黏度。
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