JP3798620B2 - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法 Download PDF

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JP3798620B2
JP3798620B2 JP2000368910A JP2000368910A JP3798620B2 JP 3798620 B2 JP3798620 B2 JP 3798620B2 JP 2000368910 A JP2000368910 A JP 2000368910A JP 2000368910 A JP2000368910 A JP 2000368910A JP 3798620 B2 JP3798620 B2 JP 3798620B2
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semiconductor device
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semiconductor
wiring
formed
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JP2002170906A (ja
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文彦 谷口
晃 高島
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富士通株式会社
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Description

【0001】
【発明の属する技術分野】
本発明は半導体装置の製造方法に係り、特に複数の半導体装置を積層して三次元構造として実装密度の向上を図るのに最適な半導体装置の製造方法に関する。
【0002】
電子機器の小型化、軽量化、薄型化に伴い、電子機器に使用される半導体装置にも小型化、薄型化が要求されている。このような要求に対処すべく、半導体装置のパッケージは、4方向に端子がガルウィング状に延出した表面実装用のQFPから、パッケージの底面に外部接続端子をエリアアレイ状に配置したBGA(ボールグリッドアレイ)型パッケージあるいはCSP(チップサイズパッケージ)へと移行してきている。
【0003】
このような半導体パッケージにおいて、半導体チップを配線基板(インターポーザ)に実装し、インターポーザにより半導体チップの周囲に外部接続用端子を配置したいわゆるファンアウト型のパッケージが多く使用されている。
【0004】
【従来の技術】
図18は従来のファンアウト型の半導体装置の断面図である。図18において、半導体装置1は大略すると基板2、半導体チップ4、半田ボール6、及び封止樹脂8等により構成されている。ここで、インターポーザは、基板2、電極パターン10、ボンディングパッド12により構成され、外部の電極と半導体チップとを電気的に導通させるために用いられる。
【0005】
基板2は、例えばポリイミド樹脂、セラミック樹脂、ガラスエポキシ樹脂等により形成されており、その表面2aには半導体チップ4が搭載されると共に、電極パターン10が形成される。半導体チップ4は、フェイスアップの状態でDB材(ボンディング材)5により基板2に固定されている。電極パターン10は、基板2に銅膜を形成した後、エッチング等により所定のパターンに形成したものである。また、電極パターン10は、図示しない配線パターンにより電気的に接続されている。
【0006】
電極パターン10は、一部をボンディングパッド12と一体化されている。このボンディングパッド12と半導体チップ4の電極とは、ワイヤ14により接続されている。これにより、半導体チップ4と電極パターン10、ボンディングパッド12はワイヤ14及び配線パターンを介して電気的に接続された構成となっている。また、基板2の半導体チップ4が接続された面2aは、半導体チップ4、ワイヤ14、ボンディングパッド5等を保護するためにエポキシ系樹脂等よりなる封止樹脂8により封止されている。
【0007】
更に、また、基板2の電極パターン10と対向する位置には、基板2を貫通する孔部16が形成されている。この孔部16は、基板2に対してレーザ加工、ドリル加工、もしくは金型加工等を実施することにより形成されていた。
【0008】
一方、基板2の裏面2bには、半田ボール6が配設されている。この半田ボール6は、前記した孔部16の形成位置に配設されており、この孔部16を介して電極パターン10に接合された構成とされている。即ち、半田ボール6は電極パターンに接合することにより、基板2に固定された構成とされている。
【0009】
上記のように、半導体装置1にインターポーザを用いたパッケージ構造が主流となってきているが、更に半導体装置の高密度化が進み、半導体チップを含めたパッケージの実装面積が縮小されつつある。よって、半導体装置のパッケージサイズが縮小され、パッケージ構造の二次元的な縮小はほぼ限界に達しているものと考えられる。従って、半導体装置の小型化を実現するためには、三次元的(スタック)に実装することが必要とされる。三次元的な実装方法において、樹脂パッケージの上面に接続用の電極を設けた半導体装置等が提供されている。
【0010】
【発明が解決しようとする課題】
しかしながら、上記のように樹脂パッケージの上面に接続用の電極を設けるためには、樹脂パッケージを回避して配線しなければならず、樹脂パッケージの上面に接続用の電極を引き出すのは困難である。例えば、樹脂パッケージを形成後に、インターポーザに設けられた外部端子と接続した配線を、樹脂パッケージを回避するように半導体装置の外周表面を迂回して上面に配設すると、配線が露出すると共に、配線が切れ易くなり、半導体装置の信頼性に欠ける。また、このような電極の配設では、配線が長くなることによりインピーダンスが大きくなり、半導体装置の高速化を妨げてしまう。
【0011】
本発明は上述の課題に鑑みてなされたものであり、半導体装置のパッケージを簡単な構造で形成し、積層して一体化することにより三次元構造の実装密度の向上を図ることのできる半導体装置の製造方法を提供することを目的とする。
【0012】
【課題を解決するための手段】
上述の目的を達成するために、請求項1記載の発明に係る半導体装置の製造方法は、
電極パターンを有する基板に半導体素子を配設する素子配設工程と、
前記半導体素子と前記電極パターンとを電気的に接続する接続工程と、
前記電極パターン上に配線孔を有するマスクを形成し、前記配線孔に導電材を導入して配線を形成する配線形成工程と、
前記マスクを除去した後、前記基板の前記半導体素子と前記配線の形成された面に前記配線の一部が外部に露出するように樹脂形成を行う樹脂形成工程を実施することを特徴とする。
【0022】
上記の各手段は、次のように作用する。
【0031】
請求項1記載の発明によれば、電極パターン上に配線孔を有するマスクを形成し、この配線孔に導電材を導入して配線を形成した後に基板の半導体素子と配線の形成された面に樹脂で封止することにより、複数の同型の半導体装置における積層が可能となる。
【0033】
【発明の実施の形態】
以下、図面を参照して本発明における実施の形態を詳細に説明する。
【0034】
図1は本発明の第1実施例による半導体装置の断面図である。図1に示した半導体装置20は、ワイヤボンディング接続されたファンアウト型の半導体装置である。以下に示す図1〜17において、図18に示した構成部品と同じ部品には同じ符号を付し、その説明は省略する。
【0035】
図1において、半導体装置20は大略すると基板2、半導体チップ4、半田ボール6、及び封止樹脂8、ポスト18等により構成されている。
【0036】
ポスト18は、封止樹脂8内に配設され、一端を電極パターン10に接続され、他端を封止樹脂8の外周表面8aから露出するように配設されている。ポスト18の一端は、電極パターン10に接続されることにより、半田ボール6と電気的に接続される。ポスト18の他端は、封止樹脂8の外周表面8aから露出するように配設されることにより、他の同型の半導体装置の外部端子と接続することが可能となる。即ち、ポスト18により効率的に半導体装置を積層して一体化することができ、三次元構造の実装密度の向上を図ることができる。また、配線を樹脂内に設けることにより、最短の配線を配設することができ、簡単なパッケージ構造の半導体装置を提供することができる。
【0037】
一方、ポスト18は、マスク等で形成されたポスト孔部22に、例えば高速Cuメッキ法を用いて形成される。ポスト18が形成された後、封止樹脂8が形成される。上記半導体装置の製造工程について以下に詳述する。
【0038】
図2、図3は、本発明の第1実施例による半導体装置の第1製造工程を説明するための図である。図2に示す半導体装置の基板2において、ポスト孔部22を電極パターン10に接し、封止樹脂8を形成した時と同じ厚さとなるようにマスク23により形成する。ポスト孔部22には、図3に示すように、高速Cuメッキ法等によりポスト18が形成される。ポスト18が形成された後、半導体装置に金型24、25を配設し、封止樹脂8を金型24の上部から充填することにより、図1に示すような半導体装置20が製造される。
【0039】
図4、図5は、本発明の第1実施例による半導体装置の第2製造工程を説明するための図である。図4に示す半導体装置において、基板2の半導体チップ4が設けられた面に金型26及び金型27を配設し、封止樹脂8を金型26の上部から充填する。金型26に設けられたポスト形成部29により、図5に示すように封止樹脂8にポスト孔部22が形成される。ポスト孔部22には、高速Cuメッキ法等によりポスト18が形成され、図1に示すような半導体装置20を製造することができる。
【0040】
尚、ポスト18の形成は、高速Cuメッキ法に限らず、CVD(Chemical Vapor Deposition)法、スパッタリング法等でも可能である。また、ポスト18は、封止樹脂8でポスト孔部22を形成した後、ポスト孔部22に半田ボール及び半田ペーストを埋めることにより形成することも可能である。
【0041】
図6は、本発明の第2実施例による半導体装置の断面図である。図6に示す半導体装置20aは、上記図2、3及び図4、5で示した製造工程により形成され、形成されたポスト18の封止樹脂8の外周表面に露出する一端に、外部端子として半田ボール6aを配設する。このように、ポスト18に半田ボール6aを設けることにより、半導体装置の実装の信頼性を向上させることができる。
【0042】
図7は、本発明の第3実施例による半導体装置の断面図である。図7に示す半導体装置20bは、ポスト18a、18bが配設されている。ポスト18aは、図2、3に示す第1製造工程で形成され、封止樹脂8の表面8aより低い高さに形成される。ポスト18aが形成された後、図4に示すポスト形成部を有する金型を配設し、封止樹脂8を充填すると、図7のポスト孔部30が形成される。このポスト孔部30へ高速Cuメッキ等を行うことにより、ポスト18bを形成することができる。ポスト18a、18bは、ポスト18a、18bの断面積がそれぞれ異なるように形成される。これにより、両方のポストのインピーダンスが小さくなるように形成することができるため、半導体装置の高速化を図ることができる。また、図7に示すようにポスト18bがポスト18aの断面積より小さく、ポスト18aの形成された後にポスト18bが半田ペースト埋め等で形成される場合、ポスト18bの形成時間を大幅に短縮できる。また、ポスト18aと電極パッド10に接続する断面積を大きくできるため、半導体装置の信頼性を向上させることができる。
【0043】
図8は、本発明の第3実施例の変形例による半導体装置の断面図である。図8に示す半導体装置20cは、図7に示す半導体装置20bのポスト18bに、半田ボール6bを配設したものである。このように、ポスト18bの封止樹脂8の外周表面に露出する一端に、外部端子として半田ボール6bを設けることにより、半導体装置の実装の信頼性を向上させることができる。また、ポスト18aをあらかじめCuメッキ等で形成し、高さを確保しておくことにより、半田ペーストの穴埋めを実施することなくボール搭載工程が半田ボール搭載のみで可能となる。
【0044】
図9は、本発明の第4実施例による半導体装置の断面図である。図9に示す半導体装置20dは、ポスト18cの一端を半導体チップ4の表面の所定位置と接続させ、他端を封止樹脂8の外周表面に露出するように配設する。ポスト18cは、高速Cuメッキ法等により形成する。このように、半導体チップ4の表面にポスト18cを配設することにより、ポスト18cの配設位置の自由度を向上させることができる。尚、ポスト18cと半導体チップ4との接続は、図示しない半導体チップ4に形成された配線により行われる。
【0045】
図10は、本発明の第4実施例の変形例による半導体装置の断面図である。図10に示す半導体装置20eは、図9に示す半導体装置20dのポスト18c上に半田ボール6cを配設したものである。このように、ポスト18cに半田ボール6cを設けることにより、半導体装置の実装の信頼性を向上させることができる。なお、図9、図10に示すようなポストの配設方法はファンアウト構造及びファンイン構造のいずれに対しても対応が可能である。
【0046】
図11は、本発明の第5実施例による半導体装置ユニットの断面図である。図11に示す半導体装置ユニット20fでは、図1に示す複数の半導体装置20を積層し、ユニット化した構造としている。半導体装置20の半田ボール6とポスト18の接続面32との接続により、複数の半導体装置20を重ねて実装することができる。例えば、DRAM、フラッシュメモリ等のメモリICの半導体素子を小さな実装面積で大容量化する場合に有効な方法である。
【0047】
図12は、本発明の第6実施例による半導体装置ユニットの断面図である。図12に示す半導体装置ユニット20gでは、接合部35により積層型のパッケージとシールド材34とを接続している。このシールド材34は半導体装置のバンプ18cと接続されている。また、バンプ18cと電気的に接続される半田ボール6dは接地されているため、シールド材34は外部からのノイズ及び内部から発生するノイズをシールドする。従って、半導体装置ユニット20gに影響するノイズを減らすことができ、信頼性を向上させることができる。また、積層型パッケージの半導体装置ではなく、単一パッケージの半導体装置にシールド材を設けることも可能である。
【0048】
図13は、本発明の第7実施例による半導体装置の断面図である。図13に示す半導体装置20hでは、接合部38によりポスト18とアンテナ36とを接続している。図14に示すようにアンテナ36では、2つの接合部38が配線で接続されている。このように、半導体装置20hのポスト18にアンテナ36を接続することにより、ICカードや道路交通システム(ITS:Intelligent Transport System)等における無線信号の送受信を行うことができる。
【0049】
図15は、本発明の第8実施例による半導体装置の断面図である。図15の半導体装置20iは、図1に示す半導体装置20にチップ部品40を配設している。チップ部品40は、半導体装置20iの封止樹脂8から露出するポスト18に接続される。このように、チップ部品をポスト18に接続することにより、半導体装置の機能性、汎用性を向上させることができる。
【0050】
図16は、本発明の第9実施例による半導体装置の断面図である。図16に示す半導体装置20jは、半田ボール6と電気的に接続されるポスト18と半導体チップ4上にポスト18cが形成されている。また、この半導体装置では、接合部44によりポスト18、18cとヒートシンク42とを接続している。このように、ヒートシンク42を設けることで、半導体装置20jで発生した熱を放出することができ、半導体装置の温度上昇を押えることができる。
【0051】
図17は、本発明の第10実施例による半導体装置の断面図である。図17に示す半導体装置20kは、半導体チップ4上に半田ボール6eが形成され、半田ボール6eを挟んで半導体チップ4aが配設されている。半導体チップ4aの背面を封止樹脂8から露出するように配設し、この半導体チップ4aの背面とヒートシンク42を接続させる。これにより、半導体装置で発生した熱を効率的に放出することができる。尚、半導体チップ4aは必ずしも電気的に機能させる必要はなく、半導体装置の熱抵抗を低減させるためのダミー素子を搭載してもよい。
【0052】
(付記1) 半導体素子と、
外部と接続する外部端子と、
前記半導体素子を第1の面に搭載し、前記第1の面と反対側の面に外部端子を設け、前記半導体素子と前記外部端子とを電気的に接続するインターポーザと、
該インターポーザの第1の面を封止する樹脂とを有する半導体装置であって、
前記外部端子と電気的に接続する第1の接続部と、前記樹脂の外周表面に露出する第2の接続部とを有し、前記樹脂に内設されている配線を有することを特徴とする半導体装置。
【0053】
(付記2) 半導体素子と、
外部と接続する外部端子と、
前記半導体素子を第1の面に搭載し、前記第1の面と反対側の面に外部端子を設け、前記半導体素子と前記外部端子とを電気的に接続するインターポーザと、
該インターポーザの第1の面を封止する樹脂とを有する半導体装置であって、
前記半導体素子と電気的に接続する第1の接続部と、前記樹脂の外周表面に露出する第2の接続部とを有し、前記樹脂に内設されると共に前記半導体素子の表面上に配設された配線を有することを特徴とする半導体装置。
【0054】
(付記3) 付記1又は2記載の半導体装置であって、
前記第1の接続部と第2の接続部との断面積が異なることを特徴とする半導体装置。
【0055】
(付記4) 付記1乃至3いずれか一項記載の半導体装置であって、
前記第2の接続部にバンプを形成することを特徴とする半導体装置。
【0056】
(付記5) 付記1乃至4いずれか一項記載の半導体装置であって、
複数の前記半導体装置のそれぞれを積層固定することを特徴とする半導体装置。
【0057】
(付記6)付記1乃至5いずれか一項記載の半導体装置であって、
前記第2の接続部にシールド材を載置することを特徴とする半導体装置。
【0058】
(付記7) 付記1乃至5いずれか一項記載の半導体装置であって、
前記第2の接続部にアンテナを載置することを特徴とする半導体装置。
【0059】
(付記8) 付記1乃至5いずれか一項記載の半導体装置であって、
前記第2の接続部に電子部品を載置することを特徴とする半導体装置。
【0060】
(付記9) 付記1乃至5いずれか一項記載の半導体装置であって、
前記第2の接続部にヒートシンクを載置することを特徴とする半導体装置。
【0061】
(付記10) 付記1乃至3いずれか一項記載の半導体装置であって、
前記半導体素子に他の半導体素子の第1の面を接続させ、前記他の半導体素子の第2の面及び第2の接続部にヒートシンクを載置することを特徴とする半導体装置。
【0062】
(付記11) 電極パターンを有する基板に半導体素子を配設する素子配設工程と、
前記半導体素子と前記電極パターンとを電気的に接続する接続工程と、
前記電極パターン上に配線孔を有するマスクを形成し、前記配線孔に導電材を導入して配線を形成する配線形成工程と、
前記マスクを除去した後、前記基板の前記半導体素子と前記配線の形成された面に前記配線の一部が外部に露出するように樹脂形成を行う樹脂形成工程を実施することを特徴とする半導体装置の製造方法。
【0063】
(付記12) 電極パターンを有する基板に半導体素子を配設する素子配設工程と、
前記半導体素子と前記電極パターンとを電気的に接続する接続工程と、
前記電極パターン上に配線がを形成されるよう前記基板の前記半導体素子の配設面に樹脂を形成する樹脂形成工程と、
前記配線孔に導電材を導入することにより、前記樹脂内に配線を形成する配線形成工程を実施することを特徴とする半導体装置の製造方法。
【0064】
【発明の効果】
以上説明したように、請求項1記載の発明によれば、電極パターン上に配線孔を有するマスクを形成し、この配線孔に導電材を導入して配線を形成した後に基板の半導体素子と配線の形成された面に樹脂で封止することにより、複数の同型の半導体装置における積層が可能となる。
【図面の簡単な説明】
【図1】本発明の第1実施例による半導体装置の断面図である。
【図2】本発明の第1実施例による半導体装置の第1製造工程を説明するための図である。
【図3】本発明の第1実施例による半導体装置の第1製造工程を説明するための図である。
【図4】本発明の第1実施例による半導体装置の第2製造工程を説明するための図である。
【図5】本発明の第1実施例による半導体装置の第2製造工程を説明するための図である。
【図6】本発明の第2実施例による半導体装置の断面図である。
【図7】本発明の第3実施例による半導体装置の断面図である。
【図8】本発明の第3実施例の変形例による半導体装置の断面図である。
【図9】本発明の第4実施例による半導体装置の断面図である。
【図10】本発明の第4実施例の変形例による半導体装置の断面図である。
【図11】本発明の第5実施例による半導体装置ユニットの断面図である。
【図12】本発明の第6実施例による半導体装置ユニットの断面図である。
【図13】本発明の第7実施例による半導体装置の断面図である。
【図14】本発明の第7実施例による半導体装置に配設されたアンテナの断面図である。
【図15】本発明の第8実施例による半導体装置の断面図である。
【図16】本発明の第9実施例による半導体装置の断面図である。
【図17】本発明の第10実施例による半導体装置の断面図である。
【図18】従来のファンアウト型の半導体装置の断面図である。
【符号の説明】
1、20、20a〜20e、20h〜20k 半導体装置
2 基板
4、4a 半導体チップ
5 DB材
6、6a〜6e 半田ボール
8 封止樹脂
10 電極パターン
12 ボンディングパッド
14 ワイヤ
16 孔部
18、18a〜18c ポスト
20f、20g 半導体装置ユニット
22、30 ポスト孔部
23 マスク
24、25、26、27 金型
29 ポスト形成部
32 接続面
34 シールド材
35、38、44 接続部
36 アンテナ
40 チップ部品
42 ヒートシンク

Claims (1)

  1. 電極パターンを有する基板に半導体素子を配設する素子配設工程と、
    前記半導体素子と前記電極パターンとを電気的に接続する接続工程と、
    前記電極パターン上に配線孔を有するマスクを形成し、前記配線孔に導電材を導入して配線を形成する配線形成工程と、
    前記マスクを除去した後、前記基板の前記半導体素子と前記配線の形成された面に前記配線の一部が外部に露出するように樹脂形成を行う樹脂形成工程を実施することを特徴とする半導体装置の製造方法。
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US09/843,912 US6489676B2 (en) 2000-12-04 2001-04-30 Semiconductor device having an interconnecting post formed on an interposer within a sealing resin
TW090110479A TW529155B (en) 2000-12-04 2001-05-02 Semiconductor device, semiconductor device package and a method of manufacturing a semiconductor device
KR1020010024525A KR100692441B1 (ko) 2000-12-04 2001-05-07 반도체 장치 및 반도체 장치의 제조 방법
US10/278,940 US6812066B2 (en) 2000-12-04 2002-10-24 Semiconductor device having an interconnecting post formed on an interposer within a sealing resin

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US20030042564A1 (en) 2003-03-06
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US6812066B2 (en) 2004-11-02
US6489676B2 (en) 2002-12-03
KR100692441B1 (ko) 2007-03-09
US20020066952A1 (en) 2002-06-06

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