FR2893764B1 - Boitier semi-conducteur empilable et procede pour sa fabrication - Google Patents

Boitier semi-conducteur empilable et procede pour sa fabrication

Info

Publication number
FR2893764B1
FR2893764B1 FR0511766A FR0511766A FR2893764B1 FR 2893764 B1 FR2893764 B1 FR 2893764B1 FR 0511766 A FR0511766 A FR 0511766A FR 0511766 A FR0511766 A FR 0511766A FR 2893764 B1 FR2893764 B1 FR 2893764B1
Authority
FR
France
Prior art keywords
board
electrical connections
chip
front face
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR0511766A
Other languages
English (en)
Other versions
FR2893764A1 (fr
Inventor
Romain Coffy
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SA
Original Assignee
STMicroelectronics SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SA filed Critical STMicroelectronics SA
Priority to FR0511766A priority Critical patent/FR2893764B1/fr
Priority to US11/601,569 priority patent/US7737565B2/en
Publication of FR2893764A1 publication Critical patent/FR2893764A1/fr
Application granted granted Critical
Publication of FR2893764B1 publication Critical patent/FR2893764B1/fr
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
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    • H01L23/00—Details of semiconductor or other solid state devices
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    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01L2224/732—Location after the connecting process
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    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
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    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
FR0511766A 2005-11-21 2005-11-21 Boitier semi-conducteur empilable et procede pour sa fabrication Expired - Fee Related FR2893764B1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
FR0511766A FR2893764B1 (fr) 2005-11-21 2005-11-21 Boitier semi-conducteur empilable et procede pour sa fabrication
US11/601,569 US7737565B2 (en) 2005-11-21 2006-11-17 Stackable semiconductor package and method for its fabrication

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0511766A FR2893764B1 (fr) 2005-11-21 2005-11-21 Boitier semi-conducteur empilable et procede pour sa fabrication

Publications (2)

Publication Number Publication Date
FR2893764A1 FR2893764A1 (fr) 2007-05-25
FR2893764B1 true FR2893764B1 (fr) 2008-06-13

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
FR0511766A Expired - Fee Related FR2893764B1 (fr) 2005-11-21 2005-11-21 Boitier semi-conducteur empilable et procede pour sa fabrication

Country Status (2)

Country Link
US (1) US7737565B2 (fr)
FR (1) FR2893764B1 (fr)

Families Citing this family (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI335070B (en) 2007-03-23 2010-12-21 Advanced Semiconductor Eng Semiconductor package and the method of making the same
JP5081578B2 (ja) * 2007-10-25 2012-11-28 ローム株式会社 樹脂封止型半導体装置
JP2009302505A (ja) * 2008-05-15 2009-12-24 Panasonic Corp 半導体装置、および半導体装置の製造方法
TWI473553B (zh) * 2008-07-03 2015-02-11 Advanced Semiconductor Eng 晶片封裝結構
US20100072600A1 (en) * 2008-09-22 2010-03-25 Texas Instrument Incorporated Fine-pitch oblong solder connections for stacking multi-chip packages
US8183677B2 (en) * 2008-11-26 2012-05-22 Infineon Technologies Ag Device including a semiconductor chip
US8354304B2 (en) * 2008-12-05 2013-01-15 Stats Chippac, Ltd. Semiconductor device and method of forming conductive posts embedded in photosensitive encapsulant
US7642128B1 (en) 2008-12-12 2010-01-05 Stats Chippac, Ltd. Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP
US9293401B2 (en) 2008-12-12 2016-03-22 Stats Chippac, Ltd. Semiconductor device and method for forming a low profile embedded wafer level ball grid array molded laser package (EWLP-MLP)
US9082806B2 (en) 2008-12-12 2015-07-14 Stats Chippac, Ltd. Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP
US9064936B2 (en) 2008-12-12 2015-06-23 Stats Chippac, Ltd. Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP
US8592992B2 (en) 2011-12-14 2013-11-26 Stats Chippac, Ltd. Semiconductor device and method of forming vertical interconnect structure with conductive micro via array for 3-D Fo-WLCSP
TWI469283B (zh) * 2009-08-31 2015-01-11 Advanced Semiconductor Eng 封裝結構以及封裝製程
US8198131B2 (en) * 2009-11-18 2012-06-12 Advanced Semiconductor Engineering, Inc. Stackable semiconductor device packages
TWI408785B (zh) * 2009-12-31 2013-09-11 Advanced Semiconductor Eng 半導體封裝結構
US8569894B2 (en) 2010-01-13 2013-10-29 Advanced Semiconductor Engineering, Inc. Semiconductor package with single sided substrate design and manufacturing methods thereof
TWI419283B (zh) 2010-02-10 2013-12-11 Advanced Semiconductor Eng 封裝結構
TWI411075B (zh) 2010-03-22 2013-10-01 Advanced Semiconductor Eng 半導體封裝件及其製造方法
US8624374B2 (en) 2010-04-02 2014-01-07 Advanced Semiconductor Engineering, Inc. Semiconductor device packages with fan-out and with connecting elements for stacking and manufacturing methods thereof
US8278746B2 (en) 2010-04-02 2012-10-02 Advanced Semiconductor Engineering, Inc. Semiconductor device packages including connecting elements
US8742603B2 (en) * 2010-05-20 2014-06-03 Qualcomm Incorporated Process for improving package warpage and connection reliability through use of a backside mold configuration (BSMC)
KR101071928B1 (ko) 2010-06-21 2011-10-11 삼성전기주식회사 패키지 온 패키지 제조방법
TWI451546B (zh) 2010-10-29 2014-09-01 Advanced Semiconductor Eng 堆疊式封裝結構、其封裝結構及封裝結構之製造方法
US9171792B2 (en) 2011-02-28 2015-10-27 Advanced Semiconductor Engineering, Inc. Semiconductor device packages having a side-by-side device arrangement and stacking functionality
US8461676B2 (en) 2011-09-09 2013-06-11 Qualcomm Incorporated Soldering relief method and semiconductor device employing same
CN102509722A (zh) * 2012-01-06 2012-06-20 日月光半导体制造股份有限公司 半导体封装件及其制造方法
JP6115505B2 (ja) * 2013-06-21 2017-04-19 株式会社デンソー 電子装置
WO2015165068A1 (fr) * 2014-04-30 2015-11-05 Intel Corporation Ensembles circuits intégrés à composé de moulage
US9806066B2 (en) 2015-01-23 2017-10-31 Samsung Electronics Co., Ltd. Semiconductor package including exposed connecting stubs
JP2017112325A (ja) * 2015-12-18 2017-06-22 Ｔｏｗａ株式会社 半導体装置及びその製造方法

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06268101A (ja) * 1993-03-17 1994-09-22 Hitachi Ltd 半導体装置及びその製造方法、電子装置、リ−ドフレ−ム並びに実装基板
JP3233507B2 (ja) * 1993-08-13 2001-11-26 株式会社東芝 半導体装置
US5973393A (en) * 1996-12-20 1999-10-26 Lsi Logic Corporation Apparatus and method for stackable molded lead frame ball grid array packaging of integrated circuits
JP3996315B2 (ja) * 2000-02-21 2007-10-24 松下電器産業株式会社 半導体装置およびその製造方法
US7273769B1 (en) * 2000-08-16 2007-09-25 Micron Technology, Inc. Method and apparatus for removing encapsulating material from a packaged microelectronic device
US7009297B1 (en) * 2000-10-13 2006-03-07 Bridge Semiconductor Corporation Semiconductor chip assembly with embedded metal particle
JP3798620B2 (ja) * 2000-12-04 2006-07-19 富士通株式会社 半導体装置の製造方法
JP4023159B2 (ja) * 2001-07-31 2007-12-19 ソニー株式会社 半導体装置の製造方法及び積層半導体装置の製造方法
US6872599B1 (en) * 2002-12-10 2005-03-29 National Semiconductor Corporation Enhanced solder joint strength and ease of inspection of leadless leadframe package (LLP)
US7208825B2 (en) * 2003-01-22 2007-04-24 Siliconware Precision Industries Co., Ltd. Stacked semiconductor packages
US20040262728A1 (en) * 2003-06-30 2004-12-30 Sterrett Terry L. Modular device assemblies
US7345361B2 (en) * 2003-12-04 2008-03-18 Intel Corporation Stackable integrated circuit packaging
US7242081B1 (en) * 2006-04-24 2007-07-10 Advanced Semiconductor Engineering Inc. Stacked package structure

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