TWI469283B - 封裝結構以及封裝製程 - Google Patents

封裝結構以及封裝製程 Download PDF

Info

Publication number
TWI469283B
TWI469283B TW98129294A TW98129294A TWI469283B TW I469283 B TWI469283 B TW I469283B TW 98129294 A TW98129294 A TW 98129294A TW 98129294 A TW98129294 A TW 98129294A TW I469283 B TWI469283 B TW I469283B
Authority
TW
Taiwan
Prior art keywords
encapsulant
pads
heat sink
package structure
wafer
Prior art date
Application number
TW98129294A
Other languages
English (en)
Other versions
TW201108360A (en
Inventor
Yu Ching Sun
Fa Hao Wu
Kuang Hsiung Chen
Original Assignee
Advanced Semiconductor Eng
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Semiconductor Eng filed Critical Advanced Semiconductor Eng
Priority to TW98129294A priority Critical patent/TWI469283B/zh
Priority to US12/770,627 priority patent/US20110049704A1/en
Publication of TW201108360A publication Critical patent/TW201108360A/zh
Application granted granted Critical
Publication of TWI469283B publication Critical patent/TWI469283B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3675—Cooling facilitated by shape of device characterised by the shape of the housing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/40—Mountings or securing means for detachable cooling or heating arrangements ; fixed by friction, plugs or springs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Wire Bonding (AREA)

Description

封裝結構以及封裝製程
本發明是有關於一種封裝結構以及封裝製程，且特別是有關於一種整合了散熱片的封裝結構以及封裝製程。
在半導體產業中，積體電路(Integrated Circuits,IC)的生產，主要分為三個階段：晶圓(wafer)的製造、積體電路(IC)的製作以及積體電路(IC)的封裝(Package)等。其中，裸晶片係經由晶圓(Wafer)製作、電路設計、光罩製作以及切割晶圓等步驟而完成，而每一顆由晶圓切割所形成的裸晶片，在經由裸晶片上之接點與外部訊號電性連接後，可再以封膠材料將裸晶片包覆著，其封裝之目的在於防止裸晶片受到濕氣、熱量、雜訊的影響，並提供裸晶片與外部電路之間電性連接的媒介，如此即完成積體電路的封裝(Package)步驟。
隨著積體電路之積集度的增加，晶片的封裝結構越來越複雜而多樣。另一方面，為了提高封裝結構的散熱效果，通常會在封裝結構上設置散熱片。
習知通常是藉由黏膠(adhesive)或是銲料(solder)將散熱片貼附在封裝結構表面，然而此種接合方式無法牢固地將散熱片貼合在封裝結構上，以至於散熱片可能從封裝結構上剝離或脫落，而影響產品的生產良率以及使用上的可靠度。
本發明提供一種封裝結構，其具有散熱片，且散熱片可與封裝結構的本體之間牢固地結合，使得封裝結構具有高可靠度。
本發明更提供前述封裝結構的製程，可整合散熱片於封裝結構中，以提高封裝結構的散熱效果，並且可以牢固地將散熱片固定在封裝結構的本體上。
為具體描述本發明之內容，在此提出一種封裝結構，包括一線路基板、一晶片、多個第一銲球、一封裝膠體以及一散熱片。線路基板具有一承載表面以及位於承載表面上的多個第一銲墊。晶片配置於承載表面上，並且電性連接至線路基板。第一銲墊位於晶片外圍。第一銲球分別配置於第一銲墊上。封裝膠體配置於承載表面上並且覆蓋晶片。封裝膠體具有多個開孔，以分別暴露出第一銲球。散熱片配置於封裝膠體上，並且接合至第一銲球，其中散熱片面對封裝膠體的一接合面上具有對應於第一銲球的多個凸起，且凸起分別埋入其所對應的第一銲球內。
本發明更提出一種封裝製程。首先，提供一線路基板。線路基板具有一承載表面以及位於承載表面上的多個第一銲墊。接著，形成一第一銲球於每一第一銲墊上；並且，配置一晶片於承載表面上，其中第一銲球位於晶片外圍。然後，形成一封裝膠體於承載表面上，以覆蓋晶片。之後，形成多個開孔於封裝膠體內，且該些開孔分別暴露出第一銲球。之後，配置一散熱片於封裝膠體上，並且接合散熱片至第一銲球。所述散熱片面對封裝膠體的一接合面上具有對應於第一銲球的多個凸起，且凸起分別埋入其所對應的第一銲球內。
在一實施例中，散熱片接觸封裝膠體。
在一實施例中，第一銲墊為接地銲墊。
在一實施例中，每一開孔內的第一銲球與開孔的側壁保持一間隙。
在一實施例中，封裝膠體的邊緣與線路基板的邊緣切齊。
在一實施例中，所述之封裝結構更包括多條導線，其連接於晶片與線路基板之間。
在一實施例中，線路基板更具有相對於承載表面的一底面以及位於底面上的多個第二銲墊。此外，所述多個第二銲墊上更例如可分別配置有多個第二銲球。
在一實施例中，形成開孔於封裝膠體內的方法包括雷射燒孔(laser ablation)。
基於上述，本發明將銲球埋置於封裝膠體中，散熱片配置於封裝膠體上並且與銲球接合。由於散熱片底部的凸起是埋入銲球內，因此散熱片可被牢固地固定在線路基板與封裝膠體上，如此，不僅可提高封裝結構的散熱效果，並可確保封裝結構的可靠度。
為讓本發明之上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
圖1A-1C繪示依照本發明之一實施例的一種封裝結構，其中圖1A為立體圖，圖1B為剖面圖，而圖1C為上視圖。
如圖1A-1C所示，封裝結構100包括一線路基板110，其具有一承載表面112以及位於承載表面112上的多個第一銲墊114。一晶片120配置於線路基板110的承載表面112上，並且電性連接至線路基板110。第一銲墊114位於晶片120外圍。在本實施例中，晶片120是採用打線接合方式藉由多條導線190電性連接到線路基板110，再藉由線路基板110的內部線路(未繪示)電性連接到第一銲墊114。當然，在其他實施例中，晶片120也可以採用覆晶接合或是其他可能的方式電性連接到線路基板110。
此外，多個第一銲球130分別配置於第一銲墊114上，而一封裝膠體140配置於承載表面112上，並且覆蓋晶片120。封裝膠體140具有多個開孔142，以分別暴露出第一銲球130。另外，一散熱片150配置於封裝膠體140上，並且接合至第一銲球130。散熱片150面對封裝膠體140的一接合面152上具有對應於第一銲球114的多個凸起154，且所述凸起154分別埋入其所對應的第一銲球130內。
在本實施例中，線路基板110更具有相對於承載表面112的一底面116以及位於底面116上的多個第二銲墊118，而每一第二銲墊118上可配置有一第二銲球160，以供封裝結構100連接至外部電路，例如印刷電路板等。
本實施例在線路基板110的承載表面112上設置多個第一銲球130，並且在形成封裝膠體140之後，再於封裝膠體140上形成開孔142來暴露出第一銲球130，以藉由第一銲球130與散熱片150接合。藉由此種配置方式可以達到將散熱片150牢固地配置在線路基板110與封裝膠體140上的效果。另外，本實施利的散熱片150在面對封裝膠體140的接合面152上更具有凸起154，因此在散熱片150與第一銲球130接合時，凸起154會埋入第一銲球130內，進而提高散熱片150與第一銲球130的接合效果。
以下更進一步詳述本實施例之封裝結構的製作流程與可能的結構變化。圖2繪示前述實施例之封裝結構的製作流程，請同時參照圖1A-1C與圖2。
首先，如步驟210所示，提供線路基板110。在實際製程中，本實施例可以選擇以具有多個線路基板的基板條型態來進行大部份的製作流程，之後再對基板條進行切割，以得到相互分離的封裝結構單元。或者，先將基板條進行切割得到獨立的線路基板110之後，再於每個獨立的線路基板110上分別進行所述的製作流程。
需注意的是，若以基板條的型態來進行製作流程，則部份步驟可以對基板條上的所有線路基板同時實施，有助於減少製程步驟與製程時間。
接著，如步驟220所示，形成第一銲球130於每一第一銲墊114上，並且接合晶片120至線路基板110的承載表面112，其中第一銲球130位於晶片120外圍。在此步驟中，可以選擇先在第一銲墊114上形成第一銲球130之後，再將晶片120接合至線路基板110的承載表面112°或是，也可以選擇先將晶片120接合至線路基板110的承載表面112，再於第一銲墊114上形成第一銲球130。換言之，本實施例並不限定形成第一銲球130以及接合晶片120的先後順序。此外，如同前述，此步驟220的晶片120可以採用打線接合、覆晶接合或是其他可能的方式電性連接到線路基板110。
然後，如步驟230所示，形成封裝膠體140於線路基板110的承載表面112上，以覆蓋晶片120。若以基板條的型態來進行前述製作流程，則此步驟230可以在基板條上全面塗佈封裝膠體140，使封裝膠體140覆蓋所有線路基板110的承載表面112。
接著，如步驟240所示，形成多個開孔142於封裝膠體140內，且開孔142分別暴露出第一銲球130。本實施例用以形成開孔142的方法例如是雷射燒孔或是其他如化學蝕刻或是電漿蝕刻等可能的方法。此外，為了確保開孔142能夠確實暴露出第一銲球130，可以讓開孔142的尺寸略大於第一銲球130的尺寸，即第一銲球130與開孔142的側壁會保持一間隙195。
另外，若以基板條的型態來進行前述製作流程，則可以選擇在步驟240之前或是之後對基板條進行切割，以分離各線路基板110及其上的封裝膠體140。由於是對線路基板110以及封裝膠體140同時進行切割，因此所得到的封裝膠體140的邊緣會與線路基板110的邊緣切齊。
然後，如步驟250所示，配置散熱片150於封裝膠體140上，並且接合散熱片150至第一銲球130。散熱片150面對封裝膠體140的接合面152上具有對應於第一銲球130的多個凸起154，而接合散熱片150至第一銲球130的方法例如是對第一銲球130進行回焊，使其成為熔融或是半熔融狀態，並且將散熱片150的凸起154對應埋入到第一銲球130內。第一銲球130冷卻後便可與散熱片150的凸起154牢固地結合在一起。
本實施例可以選擇讓散熱片150接觸或是不接觸封裝膠體140，此係取決於散熱片150的凸起154與第一銲球130結合後的高度。一般而言，若散熱片150接觸封裝膠體140，可以提供較佳的散熱效果。
此外，散熱片150除了可以散熱之外，亦可以提供電磁屏蔽效果。更具體而言，本實施例可以將第一銲墊114設計為接地銲墊，使散熱片150與第一銲球130接合之後作為接地面，以屏蔽外界訊號對於晶片120或是其他線路上的訊號干擾。當然，在其他實施例中，散熱片150也可以連接到電源面或是其他訊號源，以提供類似的電磁屏蔽效果或是滿足其他電路設計的需求。
另一方面，本實施例也可以選擇在前述製作流程中維持基板條的型態，直到散熱片150與第一銲球130接合之後，才對基板條進行切割。如此一來，切割後所得到的散熱片150的邊緣、封裝膠體140的邊緣以及線路基板110的邊緣會切齊。
之後，如步驟260所示，形成多個第二銲球160於線路基板110之底面116的第二銲墊118上，以供封裝結構100藉由第二銲球160連接至外部電路，例如印刷電路板等。
綜上所述，本發明之封裝結構以及封裝製程藉由線路基板上的銲球來連接散熱片，以將散熱片固定在線路基板與封裝膠體上。此外，散熱片底部具有凸起可以埋入銲球內，有助於強化散熱片與銲球的結合效果。如此一來，不僅可提高封裝結構的散熱效果，並可確保封裝結構的可靠度。此外，散熱片可以連接到接地面、電源面或是其他訊號源，以提供電磁屏蔽效果或是滿足其他電路設計的需求。另外，本發明可以採用基板條型態來進行大部份的製作流程，之後再對基板條進行切割，以得到相互分離的封裝結構單元，因此可以減少製程步驟與製程時間，降低製作成本。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，故本發明之保護範圍當視後附之申請專利範圍所界定者為準。
100．．．封裝結構
110．．．線路基板
112．．．承載表面
114．．．第一銲墊
116．．．底面
118．．．第二銲墊
120．．．晶片
130．．．第一銲球130
140．．．封裝膠體
142．．．開孔
150．．．散熱片
152．．．接合面
154．．．凸起
160．．．第二銲球
190．．．導線
195．．．間隙
圖1A-1C繪示依照本發明之一實施例的一種封裝結構。
圖2繪示圖1A-1C之封裝結構的製作流程。
100．．．封裝結構
110．．．線路基板
112．．．承載表面
114．．．第一銲墊
116．．．底面
118．．．第二銲墊
120．．．晶片
130．．．第一銲球
140．．．封裝膠體
150．．．散熱片
152．．．接合面
154．．．凸起
160．．．第二銲球
190．．．導線
195．．．間隙

Claims (12)

  1. 一種封裝結構，包括：一線路基板，具有一承載表面以及位於該承載表面上的多個第一銲墊；一晶片，配置於該承載表面上，並且電性連接至該線路基板，該些第一銲墊位於該晶片外圍；多個第一銲球，分別配置於該些第一銲墊上；一封裝膠體，配置於該承載表面上，該封裝膠體覆蓋該晶片，且該封裝膠體具有多個開孔，以分別暴露出該些第一銲球，其中每一開孔內的該第一銲球與該開孔的側壁保持一間隙；以及一散熱片，配置於該封裝膠體上，並且接合至該些第一銲球，其中該散熱片面對該封裝膠體的一接合面上具有對應於該些第一銲球的多個凸起，且該些凸起分別埋入其所對應的該些第一銲球內。
  2. 如申請專利範圍第1項所述之封裝結構，其中該散熱片接觸該封裝膠體。
  3. 如申請專利範圍第1項所述之封裝結構，其中該些第一銲墊為接地銲墊。
  4. 如申請專利範圍第1項所述之封裝結構，其中該封裝膠體的邊緣與該線路基板的邊緣切齊。
  5. 如申請專利範圍第1項所述之封裝結構，更包括多條導線，連接於該晶片與該線路基板之間。
  6. 如申請專利範圍第1項所述之封裝結構，其中該線 路基板更具有相對於該承載表面的一底面以及位於該底面上的多個第二銲墊。
  7. 如申請專利範圍第6項所述之封裝結構，更包括多個第二銲球，分別配置於該些第二銲墊上。
  8. 一種封裝製程，包括：提供一線路基板，該線路基板具有一承載表面以及位於該承載表面上的多個第一銲墊；形成一第一銲球於每一第一銲墊上；配置一晶片於該承載表面上，該些第一銲球位於該晶片外圍；形成一封裝膠體於該承載表面上，以覆蓋該晶片；形成多個開孔於該封裝膠體內，該些開孔分別暴露出該些第一銲球，其中每一開孔內的該第一銲球與該開孔的側壁保持一間隙；以及配置一散熱片於該封裝膠體上，並且接合該散熱片至該些第一銲球，其中該散熱片面對該封裝膠體的一接合面上具有對應於該些第一銲球的多個凸起，且該些凸起分別埋入其所對應的該些第一銲球內。
  9. 如申請專利範圍第8項所述之封裝製程，其中該散熱片接觸該封裝膠體。
  10. 如申請專利範圍第8項所述之封裝製程，其中該些第一銲墊為接地銲墊。
  11. 如申請專利範圍第8項所述之封裝製程，其中該線路基板更具有相對於該承載表面的一底面以及位於該底 面上的多個第二銲墊，而該封裝製程更包括形成多個第二銲球於該些第二銲墊上。
  12. 如申請專利範圍第8項所述之封裝製程，其中形成該些開孔於該封裝膠體內的方法包括雷射燒孔。
TW98129294A 2009-08-31 2009-08-31 封裝結構以及封裝製程 TWI469283B (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
TW98129294A TWI469283B (zh) 2009-08-31 2009-08-31 封裝結構以及封裝製程
US12/770,627 US20110049704A1 (en) 2009-08-31 2010-04-29 Semiconductor device packages with integrated heatsinks

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW98129294A TWI469283B (zh) 2009-08-31 2009-08-31 封裝結構以及封裝製程

Publications (2)

Publication Number Publication Date
TW201108360A TW201108360A (en) 2011-03-01
TWI469283B true TWI469283B (zh) 2015-01-11

Family

ID=43623619

Family Applications (1)

Application Number Title Priority Date Filing Date
TW98129294A TWI469283B (zh) 2009-08-31 2009-08-31 封裝結構以及封裝製程

Country Status (2)

Country Link
US (1) US20110049704A1 (zh)
TW (1) TWI469283B (zh)

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI335070B (en) * 2007-03-23 2010-12-21 Advanced Semiconductor Eng Semiconductor package and the method of making the same
TWI473553B (zh) * 2008-07-03 2015-02-11 Advanced Semiconductor Eng 晶片封裝結構
US8183677B2 (en) * 2008-11-26 2012-05-22 Infineon Technologies Ag Device including a semiconductor chip
US20100171206A1 (en) * 2009-01-07 2010-07-08 Chi-Chih Chu Package-on-Package Device, Semiconductor Package, and Method for Manufacturing The Same
TWI499024B (zh) * 2009-01-07 2015-09-01 Advanced Semiconductor Eng 堆疊式多封裝構造裝置、半導體封裝構造及其製造方法
US8012797B2 (en) * 2009-01-07 2011-09-06 Advanced Semiconductor Engineering, Inc. Method for forming stackable semiconductor device packages including openings with conductive bumps of specified geometries
US8198131B2 (en) * 2009-11-18 2012-06-12 Advanced Semiconductor Engineering, Inc. Stackable semiconductor device packages
TWI408785B (zh) * 2009-12-31 2013-09-11 Advanced Semiconductor Eng 半導體封裝結構
US8569894B2 (en) 2010-01-13 2013-10-29 Advanced Semiconductor Engineering, Inc. Semiconductor package with single sided substrate design and manufacturing methods thereof
TWI419283B (zh) * 2010-02-10 2013-12-11 Advanced Semiconductor Eng 封裝結構
TWI411075B (zh) 2010-03-22 2013-10-01 Advanced Semiconductor Eng 半導體封裝件及其製造方法
US8278746B2 (en) 2010-04-02 2012-10-02 Advanced Semiconductor Engineering, Inc. Semiconductor device packages including connecting elements
US8624374B2 (en) 2010-04-02 2014-01-07 Advanced Semiconductor Engineering, Inc. Semiconductor device packages with fan-out and with connecting elements for stacking and manufacturing methods thereof
TWI451546B (zh) 2010-10-29 2014-09-01 Advanced Semiconductor Eng 堆疊式封裝結構、其封裝結構及封裝結構之製造方法
US9171792B2 (en) 2011-02-28 2015-10-27 Advanced Semiconductor Engineering, Inc. Semiconductor device packages having a side-by-side device arrangement and stacking functionality
US20130082407A1 (en) * 2011-10-04 2013-04-04 Texas Instruments Incorporated Integrated Circuit Package And Method
KR20140057982A (ko) * 2012-11-05 2014-05-14 삼성전자주식회사 반도체 패키지 및 반도체 패키지의 제조 방법
DE102013220880B4 (de) * 2013-10-15 2016-08-18 Infineon Technologies Ag Elektronisches Halbleitergehäuse mit einer elektrisch isolierenden, thermischen Schnittstellenstruktur auf einer Diskontinuität einer Verkapselungsstruktur sowie ein Herstellungsverfahren dafür und eine elektronische Anordung dies aufweisend
US20150116944A1 (en) * 2013-10-29 2015-04-30 Delphi Technologies, Inc. Electrical assembly with a solder sphere attached heat spreader
WO2017051951A1 (ko) * 2015-09-25 2017-03-30 재단법인 다차원 스마트 아이티 융합시스템 연구단 방열을 위하여 히트 싱크를 갖는 임베디드 기판 및 그 제조 방법
US10475750B2 (en) * 2016-04-02 2019-11-12 Intel Corporation Systems, methods, and apparatuses for implementing an organic stiffener with an EMI shield for RF integration
US10910233B2 (en) * 2018-04-11 2021-02-02 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method of manufacturing the same
US11127689B2 (en) 2018-06-01 2021-09-21 Qorvo Us, Inc. Segmented shielding using wirebonds
US11219144B2 (en) 2018-06-28 2022-01-04 Qorvo Us, Inc. Electromagnetic shields for sub-modules
US11114363B2 (en) 2018-12-20 2021-09-07 Qorvo Us, Inc. Electronic package arrangements and related methods
US11515282B2 (en) 2019-05-21 2022-11-29 Qorvo Us, Inc. Electromagnetic shields with bonding wires for sub-modules
US11527480B2 (en) * 2020-04-30 2022-12-13 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method of manufacturing the same
US11935777B2 (en) * 2021-12-01 2024-03-19 STATS ChipPAC Pte Ltd. Semiconductor manufacturing equipment and method of providing support base with filling material disposed into openings in semiconductor wafer for support

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08181268A (ja) * 1994-12-26 1996-07-12 Matsushita Electric Works Ltd 半導体装置
US5990554A (en) * 1990-12-03 1999-11-23 Motorola, Inc. Semiconductor package having isolated heatsink bonding pads
JP2006073699A (ja) * 2004-09-01 2006-03-16 Sumitomo Metal Electronics Devices Inc 発光素子収納用パッケージ
JP2008235492A (ja) * 2007-03-20 2008-10-02 Matsushita Electric Ind Co Ltd 半導体装置および半導体装置の製造方法

Family Cites Families (91)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5128831A (en) * 1991-10-31 1992-07-07 Micron Technology, Inc. High-density electronic package comprising stacked sub-modules which are electrically interconnected by solder-filled vias
JPH06103707B2 (ja) * 1991-12-26 1994-12-14 インターナショナル・ビジネス・マシーンズ・コーポレイション 半導体チップの交換方法
US5222014A (en) * 1992-03-02 1993-06-22 Motorola, Inc. Three-dimensional multi-chip pad array carrier
US5313021A (en) * 1992-09-18 1994-05-17 Aptix Corporation Circuit board for high pin count surface mount pin grid arrays
JPH06268101A (ja) * 1993-03-17 1994-09-22 Hitachi Ltd 半導体装置及びその製造方法、電子装置、リ−ドフレ−ム並びに実装基板
KR970000214B1 (ko) * 1993-11-18 1997-01-06 삼성전자 주식회사 반도체 장치 및 그 제조방법
JPH07335783A (ja) * 1994-06-13 1995-12-22 Fujitsu Ltd 半導体装置及び半導体装置ユニット
JP2780649B2 (ja) * 1994-09-30 1998-07-30 日本電気株式会社 半導体装置
US5579207A (en) * 1994-10-20 1996-11-26 Hughes Electronics Three-dimensional integrated circuit stacking
US5861666A (en) * 1995-08-30 1999-01-19 Tessera, Inc. Stacked chip assembly
US5892290A (en) * 1995-10-28 1999-04-06 Institute Of Microelectronics Highly reliable and planar ball grid array package
US5714800A (en) * 1996-03-21 1998-02-03 Motorola, Inc. Integrated circuit assembly having a stepped interposer and method
JP2806357B2 (ja) * 1996-04-18 1998-09-30 日本電気株式会社 スタックモジュール
US5859475A (en) * 1996-04-24 1999-01-12 Amkor Technology, Inc. Carrier strip and molded flex circuit ball grid array
US5748452A (en) * 1996-07-23 1998-05-05 International Business Machines Corporation Multi-electronic device package
US5973393A (en) * 1996-12-20 1999-10-26 Lsi Logic Corporation Apparatus and method for stackable molded lead frame ball grid array packaging of integrated circuits
US6195268B1 (en) * 1997-06-09 2001-02-27 Floyd K. Eide Stacking layers containing enclosed IC chips
US5889655A (en) * 1997-11-26 1999-03-30 Intel Corporation Integrated circuit package substrate with stepped solder mask openings
KR100260997B1 (ko) * 1998-04-08 2000-07-01 마이클 디. 오브라이언 반도체패키지
US6451624B1 (en) * 1998-06-05 2002-09-17 Micron Technology, Inc. Stackable semiconductor package having conductive layer and insulating layers and method of fabrication
US6194250B1 (en) * 1998-09-14 2001-02-27 Motorola, Inc. Low-profile microelectronic package
JP2000323623A (ja) * 1999-05-13 2000-11-24 Mitsubishi Electric Corp 半導体装置
US6642613B1 (en) * 2000-05-09 2003-11-04 National Semiconductor Corporation Techniques for joining an opto-electronic module to a semiconductor package
JP2002158312A (ja) * 2000-11-17 2002-05-31 Oki Electric Ind Co Ltd ３次元実装用半導体パッケージ、その製造方法、および半導体装置
US7242099B2 (en) * 2001-03-05 2007-07-10 Megica Corporation Chip package with multiple chips connected by bumps
US7034386B2 (en) * 2001-03-26 2006-04-25 Nec Corporation Thin planar semiconductor device having electrodes on both surfaces and method of fabricating same
US6930256B1 (en) * 2002-05-01 2005-08-16 Amkor Technology, Inc. Integrated circuit substrate having laser-embedded conductive patterns and method therefor
JP4023159B2 (ja) * 2001-07-31 2007-12-19 ソニー株式会社 半導体装置の製造方法及び積層半導体装置の製造方法
JP3866591B2 (ja) * 2001-10-29 2007-01-10 富士通株式会社 電極間接続構造体の形成方法および電極間接続構造体
TW533560B (en) * 2002-01-07 2003-05-21 Advanced Semiconductor Eng Semiconductor package mold
SG121707A1 (en) * 2002-03-04 2006-05-26 Micron Technology Inc Method and apparatus for flip-chip packaging providing testing capability
US6740546B2 (en) * 2002-08-21 2004-05-25 Micron Technology, Inc. Packaged microelectronic devices and methods for assembling microelectronic devices
US6787392B2 (en) * 2002-09-09 2004-09-07 Semiconductor Components Industries, L.L.C. Structure and method of direct chip attach
KR20040026530A (ko) * 2002-09-25 2004-03-31 삼성전자주식회사 반도체 패키지 및 그를 이용한 적층 패키지
US6798057B2 (en) * 2002-11-05 2004-09-28 Micron Technology, Inc. Thin stacked ball-grid array package
US20040191955A1 (en) * 2002-11-15 2004-09-30 Rajeev Joshi Wafer-level chip scale package and method for fabricating and using the same
TWI290757B (en) * 2002-12-30 2007-12-01 Advanced Semiconductor Eng Thermal enhance MCM package and the manufacturing method thereof
TWI284395B (en) * 2002-12-30 2007-07-21 Advanced Semiconductor Eng Thermal enhance MCM package
US6861288B2 (en) * 2003-01-23 2005-03-01 St Assembly Test Services, Ltd. Stacked semiconductor packages and method for the fabrication thereof
JP3917946B2 (ja) * 2003-03-11 2007-05-23 富士通株式会社 積層型半導体装置
TWI311353B (en) * 2003-04-18 2009-06-21 Advanced Semiconductor Eng Stacked chip package structure
US6888255B2 (en) * 2003-05-30 2005-05-03 Texas Instruments Incorporated Built-up bump pad structure and method for same
TWI297938B (en) * 2003-07-15 2008-06-11 Advanced Semiconductor Eng Semiconductor package
KR100493063B1 (ko) * 2003-07-18 2005-06-02 삼성전자주식회사 스택 반도체 칩 비지에이 패키지 및 그 제조방법
TWI286372B (en) * 2003-08-13 2007-09-01 Phoenix Prec Technology Corp Semiconductor package substrate with protective metal layer on pads formed thereon and method for fabricating the same
TWI239620B (en) * 2003-09-05 2005-09-11 Advanced Semiconductor Eng Method for forming ball pads of ball grid array package substrate
US7372151B1 (en) * 2003-09-12 2008-05-13 Asat Ltd. Ball grid array package and process for manufacturing same
US7015571B2 (en) * 2003-11-12 2006-03-21 Advanced Semiconductor Engineering, Inc. Multi-chips module assembly package
TWI227555B (en) * 2003-11-17 2005-02-01 Advanced Semiconductor Eng Structure of chip package and the process thereof
US7345361B2 (en) * 2003-12-04 2008-03-18 Intel Corporation Stackable integrated circuit packaging
US7187068B2 (en) * 2004-08-11 2007-03-06 Intel Corporation Methods and apparatuses for providing stacked-die devices
TWI256092B (en) * 2004-12-02 2006-06-01 Siliconware Precision Industries Co Ltd Semiconductor package and fabrication method thereof
JP4409455B2 (ja) * 2005-01-31 2010-02-03 株式会社ルネサステクノロジ 半導体装置の製造方法
US7408244B2 (en) * 2005-03-16 2008-08-05 Advanced Semiconductor Engineering, Inc. Semiconductor package and stack arrangement thereof
TWI257135B (en) * 2005-03-29 2006-06-21 Advanced Semiconductor Eng Thermally enhanced three dimension package and method for manufacturing the same
US7364945B2 (en) * 2005-03-31 2008-04-29 Stats Chippac Ltd. Method of mounting an integrated circuit package in an encapsulant cavity
JP2008535273A (ja) * 2005-03-31 2008-08-28 スタッツ・チップパック・リミテッド 上面および下面に露出した基板表面を有する半導体積層型パッケージアセンブリ
TWI442520B (zh) * 2005-03-31 2014-06-21 Stats Chippac Ltd 具有晶片尺寸型封裝及第二基底及在上側與下側包含暴露基底表面之半導體組件
US7429786B2 (en) * 2005-04-29 2008-09-30 Stats Chippac Ltd. Semiconductor package including second substrate and having exposed substrate surfaces on upper and lower sides
US7354800B2 (en) * 2005-04-29 2008-04-08 Stats Chippac Ltd. Method of fabricating a stacked integrated circuit package system
JP4322844B2 (ja) * 2005-06-10 2009-09-02 シャープ株式会社 半導体装置および積層型半導体装置
TWI267967B (en) * 2005-07-14 2006-12-01 Chipmos Technologies Inc Chip package without a core and stacked chip package structure using the same
TWI268628B (en) * 2005-08-04 2006-12-11 Advanced Semiconductor Eng Package structure having a stacking platform
US20070108583A1 (en) * 2005-08-08 2007-05-17 Stats Chippac Ltd. Integrated circuit package-on-package stacking system
TWI305410B (en) * 2005-10-26 2009-01-11 Advanced Semiconductor Eng Multi-chip package structure
FR2893764B1 (fr) * 2005-11-21 2008-06-13 St Microelectronics Sa Boitier semi-conducteur empilable et procede pour sa fabrication
TWI285423B (en) * 2005-12-14 2007-08-11 Advanced Semiconductor Eng System-in-package structure
TWI281236B (en) * 2005-12-16 2007-05-11 Advanced Semiconductor Eng A package structure with a plurality of chips stacked each other
US7737539B2 (en) * 2006-01-12 2010-06-15 Stats Chippac Ltd. Integrated circuit package system including honeycomb molding
US7288835B2 (en) * 2006-03-17 2007-10-30 Stats Chippac Ltd. Integrated circuit package-in-package system
TWI301315B (en) * 2006-04-13 2008-09-21 Advanced Semiconductor Eng Substrate structure having solder mask layer and process for making the same
US7498667B2 (en) * 2006-04-18 2009-03-03 Stats Chippac Ltd. Stacked integrated circuit package-in-package system
TWI309079B (en) * 2006-04-21 2009-04-21 Advanced Semiconductor Eng Stackable semiconductor package
US7242081B1 (en) * 2006-04-24 2007-07-10 Advanced Semiconductor Engineering Inc. Stacked package structure
TWI298198B (en) * 2006-05-30 2008-06-21 Advanced Semiconductor Eng Stackable semiconductor package
KR100800478B1 (ko) * 2006-07-18 2008-02-04 삼성전자주식회사 적층형 반도체 패키지 및 그의 제조방법
TWI317993B (en) * 2006-08-18 2009-12-01 Advanced Semiconductor Eng Stackable semiconductor package
TWI335658B (en) * 2006-08-22 2011-01-01 Advanced Semiconductor Eng Stacked structure of chips and wafer structure for making same
TWI336502B (en) * 2006-09-27 2011-01-21 Advanced Semiconductor Eng Semiconductor package and semiconductor device and the method of making the same
TWI312561B (en) * 2006-10-27 2009-07-21 Advanced Semiconductor Eng Structure of package on package and method for fabricating the same
TW200828528A (en) * 2006-12-19 2008-07-01 Advanced Semiconductor Eng Structure for packaging electronic components
TWI335070B (en) * 2007-03-23 2010-12-21 Advanced Semiconductor Eng Semiconductor package and the method of making the same
TWI356482B (en) * 2007-09-20 2012-01-11 Advanced Semiconductor Eng Semiconductor package and manufacturing method the
US7777351B1 (en) * 2007-10-01 2010-08-17 Amkor Technology, Inc. Thin stacked interposer package
TWI473553B (zh) * 2008-07-03 2015-02-11 Advanced Semiconductor Eng 晶片封裝結構
US7750455B2 (en) * 2008-08-08 2010-07-06 Stats Chippac Ltd. Triple tier package on package system
US8012797B2 (en) * 2009-01-07 2011-09-06 Advanced Semiconductor Engineering, Inc. Method for forming stackable semiconductor device packages including openings with conductive bumps of specified geometries
TWI499024B (zh) * 2009-01-07 2015-09-01 Advanced Semiconductor Eng 堆疊式多封裝構造裝置、半導體封裝構造及其製造方法
US20100171206A1 (en) * 2009-01-07 2010-07-08 Chi-Chih Chu Package-on-Package Device, Semiconductor Package, and Method for Manufacturing The Same
US8198131B2 (en) * 2009-11-18 2012-06-12 Advanced Semiconductor Engineering, Inc. Stackable semiconductor device packages
TWI408785B (zh) * 2009-12-31 2013-09-11 Advanced Semiconductor Eng 半導體封裝結構

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5990554A (en) * 1990-12-03 1999-11-23 Motorola, Inc. Semiconductor package having isolated heatsink bonding pads
JPH08181268A (ja) * 1994-12-26 1996-07-12 Matsushita Electric Works Ltd 半導体装置
JP2006073699A (ja) * 2004-09-01 2006-03-16 Sumitomo Metal Electronics Devices Inc 発光素子収納用パッケージ
JP2008235492A (ja) * 2007-03-20 2008-10-02 Matsushita Electric Ind Co Ltd 半導体装置および半導体装置の製造方法

Also Published As

Publication number Publication date
TW201108360A (en) 2011-03-01
US20110049704A1 (en) 2011-03-03

Similar Documents

Publication Publication Date Title
TWI469283B (zh) 封裝結構以及封裝製程
US8420437B1 (en) Method for forming an EMI shielding layer on all surfaces of a semiconductor package
TWI646642B (zh) 晶片封裝結構及其製造方法
TWI474462B (zh) 半導體封裝件及其製法
TWI551198B (zh) 具散熱功能之印刷電路板結構
TW201338108A (zh) 半導體封裝件及其製法
US20050287701A1 (en) Leadframe for a multi-chip package and method for manufacturing the same
TW201628145A (zh) 電子封裝結構及其製法
US7592694B2 (en) Chip package and method of manufacturing the same
TW201806042A (zh) 電子封裝件及其製法
US9502377B2 (en) Semiconductor package and fabrication method thereof
JP4919689B2 (ja) モジュール基板
TWI546931B (zh) 半導體器件的製作方法
TW201327769A (zh) 半導體封裝件及其製造方法
TWI405308B (zh) 封裝件及其製造方法
TWI416694B (zh) 全罩式屏蔽至接地銲球之晶片封裝構造
TW201508877A (zh) 半導體封裝件及其製法
TWI508197B (zh) 半導體封裝件及其製法
US9318354B2 (en) Semiconductor package and fabrication method thereof
TWI488272B (zh) 線路板及晶片封裝結構
TWI423405B (zh) 具載板之封裝結構
TWI559470B (zh) 無基板的半導體封裝結構及其製造方法
TW452950B (en) Packaging structure of bonding pad with increased space height
US20120168929A1 (en) Low cost thermally enhanced hybrid bga and method of manufacturing the same
TWI492358B (zh) 半導體封裝件及其製法