TWI416694B - 全罩式屏蔽至接地銲球之晶片封裝構造 - Google Patents

全罩式屏蔽至接地銲球之晶片封裝構造 Download PDF

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TWI416694B
TWI416694B TW099131707A TW99131707A TWI416694B TW I416694 B TWI416694 B TW I416694B TW 099131707 A TW099131707 A TW 099131707A TW 99131707 A TW99131707 A TW 99131707A TW I416694 B TWI416694 B TW I416694B
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substrate
ground
ball
shield
chip package
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TW201214650A (en
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Wen Jeng Fan
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Powertech Technology Inc
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
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    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
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    • H01L2224/73265—Layer and wire connectors
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    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
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    • H01L2924/151—Die mounting substrate
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Description

全罩式屏蔽至接地銲球之晶片封裝構造
本發明係有關於經封裝之半導體裝置，特別係有關於一種全罩式屏蔽至接地銲球之晶片封裝構造。
隨著電子元件的運算速度越來越高、或是資訊傳遞的訊號頻率越來越高，對於電磁干擾(electromagnetic interference,EMI)之防護的要求也必須不斷的提升。其是由於積體電路容易與其他內部或外部電子元件(electronic device)相互產生電磁干擾之現象，例如串擾(cross talk)、傳輸損耗(transmission loss)與訊號反射等等，使得積體電路的運作效能受到削減，故如何保護晶片封裝構造中的積體電路晶片不受電磁干擾以達到品質要求相對顯得重要。
習知係將電磁屏蔽層連接至接地之結構設置於基板內，例如我國專利證書號數I287433號所揭示者。在基板內部係預先形成有接地層，並使接地線路延伸於至基板上表面之側邊，透過導通孔(via)或可稱為鍍通孔(PTH)使接地線路電性連接至基板下表面。在封裝之後，另以一電磁干擾屏蔽層形成在封膠體表面並連接至該接地線路，以將電磁波或靜電導引至接地迴路予以釋放、排散，藉以保護晶片不受電磁干擾的影響。然此基板需要額外增設對應之接地線路至該基板之側邊，而相對提高製作成本。此外，利用電磁干擾屏蔽層去連接基板側面之接地線路，然基板側面之接地線路顯露端面是有限的、窄小的(narrow)，故與電磁干擾屏蔽層之接觸面積為點狀之接合，容易造成接地線路接觸不良而造成電磁屏蔽失敗。
另有人在屏蔽接地之晶片封裝構造中提出一種基板改善結構，例如我國專利公開公報編號201005911所揭示者。必須在封裝過程中，先在基板單元定義出一鄰近於基板單元之周邊設置的切除部，在封裝之前，將接地元件設置於原切除部的凹槽內且延伸於基板單元的上表面與下表面之間。在封裝之後，於單體化切割時令接地元件露出側向之連接面，再將電磁干擾防護體電性連接接地元件之連接面，藉由接地元件提供一電性路徑以將電磁干擾防護體上的電磁放射放電至接地端。利用此方法，接地元件與電磁干擾防護體之結合面積雖然增加了，但接地元件之設計、製作與切割製成步驟複雜而繁瑣，而增加了製造成本與時間。
有鑒於此，本發明之主要目的係在於提供一種全罩式屏蔽至接地銲球之晶片封裝構造，令在封膠體表面之全罩式屏蔽層跳過基板之接地線路而直接連接至接地銲球，藉以改善封裝構造之電性效能。
本發明之次一目的係在於提供一種全罩式屏蔽至接地銲球之晶片封裝構造，確保全罩式屏蔽層的接地連接，又不需要改變基板之線路結構。
本發明的目的及解決其技術問題是採用以下技術方案來實現的。本發明揭示一種全罩式屏蔽至接地銲球之晶片封裝構造，包含一基板、至少一晶片、一封膠體、複數個銲球、一電磁干擾屏蔽層以及一底面導線。該基板係具有一上表面、一下表面與複數個側邊，該基板之該下表面係設有複數個接球墊與一銲罩層，該些接球墊係包含至少一接地墊。該晶片係設置於該基板上且電性連接至該基板。該封膠體係形成於該基板之該上表面，以包覆該晶片。該些銲球係接合至該基板之該些接球墊，該些銲球係包含至少一位於該接地墊之接地銲球。該電磁干擾屏蔽層係包覆該封膠體之一頂面與四周側面，更延伸至該基板之該些側邊。該底面導線係形成於該銲罩層上，該底面導線係由該基板鄰近該接地墊之其中一側邊連接該電磁干擾屏蔽層至該接地銲球，以提供電磁干擾屏蔽。
本發明的目的及解決其技術問題還可採用以下技術措施進一步實現。
在前述的晶片封裝構造中，該電磁干擾屏蔽層係可為表面塗佈之導電漆層。
在前述的晶片封裝構造中，該基板係可不具有延伸至該些側邊之接地線路。
在前述的晶片封裝構造中，該底面導線之一端係可局部覆蓋該接地墊，以供該接地銲球之接合。
在前述的晶片封裝構造中，該晶片之一主動面係可貼附至該基板之該上表面，該基板係可更具有一貫穿槽孔，以顯露該晶片複數個位於該主動面之銲墊。
在前述的晶片封裝構造中，可另包含複數個穿過該貫穿槽孔之電性連接元件，以電性連接該些銲墊至該基板。
在前述的晶片封裝構造中，該些電性連接元件係可為打線形成之銲線。
由以上技術方案可以看出，本發明之全罩式屏蔽至接地銲球之晶片封裝構造，具有以下優點與功效：
一、可藉由電磁干擾屏蔽層與底面導線之特殊組合關係作為其中之一技術手段，利用電磁干擾屏蔽層包覆封膠體之頂面與四周側面，更延伸至基板之側邊，再利用在銲罩層表面之底面導線連接至接地銲球，令在封膠體表面之全罩式屏蔽層跳過基板之接地線路而直接連接至接地銲球，藉以改善封裝構造之電性效能。
二、可藉由電磁干擾屏蔽層與底面導線之特殊組合關係作為其中之一技術手段，能從晶片封裝構造外部形成接地之底面導線，確保全罩式屏蔽層的接地連接又不需要改變基板之線路結構。
以下將配合所附圖示詳細說明本發明之實施例，然應注意的是，該些圖示均為簡化之示意圖，僅以示意方法來說明本發明之基本架構或實施方法，故僅顯示與本案有關之元件與組合關係，圖中所顯示之元件並非以實際實施之數目、形狀、尺寸做等比例繪製，某些尺寸比例與其他相關尺寸比例或已誇張或是簡化處理，以提供更清楚的描述。實際實施之數目、形狀及尺寸比例為一種選置性之設計，詳細之元件佈局可能更為複雜。
依據本發明之第一具體實施例，一種全罩式屏蔽至接地銲球之晶片封裝構造舉例說明於第1、2圖之截面示意圖與第3圖之局部底面示意圖。該晶片封裝構造100主要包含一基板110、至少一晶片120、一封膠體130、複數個銲球140、一電磁干擾屏蔽層150以及一底面導線160。在本實施例第1圖中，雖以窗口型球柵陣列封裝型態為例，但不受局限地，本發明亦可運用在其它已知的球柵陣列封裝架構或是覆晶封裝架構。
請參閱第1圖所示，該基板110係用以提供電性連接並作為該晶片封裝構造100之晶片載體，通常是印刷電路板，或可為陶瓷載板、電路薄膜或是一鋸切型態封裝之無外接腳式導線架。該基板110係具有一上表面111、一下表面112與複數個側邊113，該上表面111係為晶片設置面，並作為被該封膠體130覆蓋之表面，而該下表面112係為顯露於該封膠體130之外且相對於該上表面111之外表面，作為該些銲球140的安裝面。該基板110係可為複數個一體形成之一基板條(substrate strip)，後續再予以單體化切割以製成複數個晶片封裝構造。經切割後之該基板110係具有複數個經單體化切割為顯露之側邊113，通常為四面連接該上表面111之周邊至該下表面112之周邊，而使該基板110為矩形或正方形。在本實施例中，該基板110係可不具有延伸至該些側邊113之接地線路，故該基板110內部為原有金屬線路層之結構。較佳地，該基板110可選用一種僅具有單面線路層之電路基板，可省去接地金屬層佈局之複雜度與製程困擾，提高訊號處理高速化，並降低基板之製作成本。
再如第1圖所示，該基板110之該下表面112係設有複數個接球墊114與一銲罩層115，該些接球墊114係包含至少一接地墊116。該銲罩層115係可為一保護線路之絕緣性表面塗層，可稱之為綠漆，或可為其它具防銲特性之表面保護層。在本實施例中，該銲罩層115係形成於該基板110之該下表面112並局部覆蓋該些接球墊114(包含該接地墊116)，能防止線路及基板核心層外露而被污染。該接地墊116係可為虛置墊(dummy pad)而不具有訊號傳遞功能，或者是以接地線路連接至外部印刷電路板之金屬墊。
再如第1圖所示，該晶片120係設置於該基板110上且電性連接至該基板110。該晶片120係可為一基頻晶片(base band chip)或一射頻晶片(RF chip)，可由一晶圓(wafer)分割而出。在本實施例中，該晶片120之一主動面121係可貼附至該基板110之該上表面111，該基板110係可更具有一貫穿槽孔117，以顯露該晶片120複數個位於該主動面121之銲墊122。該貫穿槽孔117係可位於該基板110之中央位置，而該些銲墊122係分佈排列於該晶片120之該主動面121之中央，即中央型銲墊(central pad)。該晶片120係可利用一非液態黏晶層，例如膠帶、B階黏膠(B-stage adhesive)或是晶片貼附物質(Die Attach Material,DAM)，以黏接該晶片120之該主動面121至該基板110之該上表面111。該基板110在該貫穿槽孔117之兩側可設置複數個接指，利用跡線電性連接至該些接球墊114(包含該接地墊116)。此外，在該晶片封裝構造100中可另包含複數個穿過該貫穿槽孔117之電性連接元件170，以電性連接該些銲墊122至該基板110。在本實施例中，該些電性連接元件170係為打線形成之銲線(bonding wires)，可為金線或銅線，係連接該晶片120之該些銲墊122與該基板110之接指。在另一變化實施例中，該些電性連接元件170亦可為基板內部延伸出之引線(lead)。
該封膠體130係形成於該基板110之該上表面111，以包覆該晶片120。具體而言，該封膠體130係可為一環氧模封化合物(Epoxy Molding Compound,EMC)，以轉移成形方式(transfer molding)覆蓋於該基板110之該上表面111。在本實施例中，該封膠體130係可更形成在該基板110之該貫穿槽孔117與部分之該下表面112，以密封該些電性連接元件170，提供適當的絕緣封裝保護，以防止電性短路與塵埃污染。
如第1圖與第2圖之局部放大圖所示，該些銲球140係接合至該基板110之該些接球墊114，該些銲球140係包含至少一位於該接地墊116之接地銲球141。該些銲球140與該接地銲球141係呈柵狀陣列排列於該下表面112，其形成方式例如為：在該基板110之該下表面112上的該些接球墊114(包含該接地墊116)上形成一錫膏(solder paste)或助銲劑(flux)，再在上述錫膏或助銲劑上分別放置具有一定固定球徑的錫球(solder ball)，再經由一迴焊(reflow)製程將上述錫球熔化並焊接於該基板110上，形成該些銲球140以及該接地銲球141。
請再參閱第1圖所示，該電磁干擾屏蔽層150係包覆該封膠體130之一頂面131與四周側面132，更延伸至該基板110之該些側邊113。該電磁干擾屏蔽層150係作為該晶片封裝構造100之電磁防護層(RF shielding)，可形成在該封膠體130表面上，更延伸至該基板110之該些側邊113。詳細而言，該電磁干擾屏蔽層150係可為表面塗佈之導電漆層(conductive coating)，例如銀膠(epoxy paste)，可利用印刷塗佈(coating)、噴塗(spray)等方式將該電磁干擾屏蔽層150形成在該封膠體130表面上與該基板110之該些側邊113上，如此方可以在該封膠體130與該基板110等不同材質表面以一次作業方式形成該電磁干擾屏蔽層150。在其他之變化例中，該電磁干擾屏蔽層150亦可利用浸漬、電鍍(plating)、真空印刷(vacuum printing)、真空沉積(vacuum depositiop)、插入成形(insert molding)或其他可行方法形成。此外，在其他應用例中，該電磁干擾屏蔽層150亦可為一金屬殼體，利用雙面膠層貼附於該封膠體130表面與該基板110之該些側邊113。較佳地，如第1圖所示，該封膠體130之該些四周側面132與該基板110之該些側邊113平齊而不具有凸出端，其係可在模封(molding)之後經同一切割步驟中形成，以利該電磁干擾屏蔽層150之形成。
該底面導線160係形成於該銲罩層115上，該底面導線160係由該基板110鄰近該接地墊116之其中一側邊113連接該電磁干擾屏蔽層150至該接地銲球141，以完成接地線路之連接與提供電磁干擾屏蔽、減少傳輸損耗與串擾(cross talk)現象。具體而言，如第2與3圖所示，該底面導線160係形成於該基板110底部之顯露表面上，除了採用在植球之前(即該些銲球140形成之前)的印刷方法形成該底面導線160，亦可在植球之後利用一金線筆(gold wire pen，圖未繪出)升溫至可使金線成融溶態的溫度，取由該接地銲球141至該電磁干擾屏蔽層150之最短距離，以塗畫方式形成該底面導線160，使該接地銲球141與該電磁干擾屏蔽層150為連結導通。詳細而言，金線筆係可採尖端加熱或放電形式達成，以減少能源消耗。在另一變化實施例中，可將金線筆內塗施物可更換為其他任何金屬材質，例如：鋁、銅等價格較為便宜之材質，以降低製造成本。較佳地，該接地墊116係可設置在鄰近該基板110之任一側邊113，以降低該底面導線160之長度與塗施難度。故本發明係從該晶片封裝構造100之基板外部形成接地連接之底面導線160，確保全罩式電磁干擾屏蔽層150的接地連接又不需要改變該基板110之線路結構。此外，本發明利用該電磁干擾屏蔽層150包覆該封膠體130之該頂面131與四周側面132，更延伸至該基板110之側邊113，再利用該底面導線160連接至該接地銲球141，令在該封膠體130表面之全罩式電磁干擾屏蔽層150跳過該基板110之接地線路而直接連接至接地銲球141，藉以改善該晶片封裝構造100之電性效能，並且對於封裝結構之抗濕性亦有改善之效果。
依據本發明之第二具體實施例，另一種全罩式屏蔽至接地銲球之晶片封裝構造說明於第4與5圖之截面示意圖。該晶片封裝構造200主要包含一基板110、至少一晶片120、一封膠體130、複數個銲球140、一電磁干擾屏蔽層150以及一底面導線160。其中與第一實施例相同的主要元件將以相同符號標示，故可理解亦具有上述之相同作用，在此不再予以贅述。
在本實施例中，如第4圖所示，該晶片120之該主動面121係可朝上設置，該些銲墊122係設置於該晶片120之該主動面121之單一側邊。該晶片120之上方可再往上堆疊更多適當數量之晶片120，達到記憶體容量或是功能的擴充，而成為多晶片封裝構造。再利用該些電性連接元件170連接該些晶片120至該基板110之複數個接指215。該些接指215係設置在該基板110之該上表面111，可並以另一銲罩層216局部覆蓋該些接指215以防止線路及基板核心層外露而被污染。在其他變化例中，下方之晶片120亦可以覆晶方式接合至該基板110。
此外，如第5圖之局部放大圖所示，該底面導線160之一端係可局部覆蓋該接地墊116，以供該接地銲球141之接合。其形成方式係在植球之前先以金線筆塗畫連接由該接地墊116至該電磁干擾屏蔽層150，之後再進行該些銲球140之設置，經由一迴焊(reflow)製程後可將錫球熔化並焊接於該些接球墊114與該接地墊116上，而達到全罩式屏蔽之接地連接，不需要利用習知延伸基板側邊之接地線路。
以上所述，僅是本發明的較佳實施例而已，並非對本發明作任何形式上的限制，雖然本發明已以較佳實施例揭露如上，然而並非用以限定本發明，任何熟悉本項技術者，在不脫離本發明之技術範圍內，所作的任何簡單修改、等效性變化與修飾，均仍屬於本發明的技術範圍內。
100．．．晶片封裝構造
110．．．基板
111．．．上表面
112．．．下表面
113．．．側邊
114．．．接球墊
115．．．銲罩層
116．．．接地墊
117．．．貫穿槽孔
120．．．晶片
121．．．主動面
122．．．銲墊
130．．．封膠體
131．．．頂面
132．．．四周側面
140．．．銲球
141．．．接地銲球
150．．．電磁干擾屏蔽層
160．．．底面導線
170．．．電性連接元件
200．．．晶片封裝構造
215．．．接指
216．．．銲罩層
第1圖：依據本發明之第一具體實施例的一種全罩式屏蔽至接地銲球之晶片封裝構造之截面示意圖。
第2圖：依據本發明之第一具體實施例的全罩式屏蔽至接地銲球之晶片封裝構造之局部放大截面示意圖。
第3圖：依據本發明之第一具體實施例的全罩式屏蔽至接地銲球之晶片封裝構造之局部底面示意圖。
第4圖：依據本發明之第二具體實施例的另一種全罩式屏蔽至接地銲球之晶片封裝構造之截面示意圖。
第5圖：依據本發明之第二具體實施例的全罩式屏蔽至接地銲球之晶片封裝構造之局部放大截面示意圖。
100．．．晶片封裝構造
110．．．基板
111．．．上表面
112．．．下表面
113．．．側邊
114．．．接球墊
115．．．銲罩層
116．．．接地墊
117．．．貫穿槽孔
120．．．晶片
121．．．主動面
122．．．銲墊
130．．．封膠體
131．．．頂面
132．．．四周側面
140．．．銲球
141．．．接地銲球
150．．．電磁干擾屏蔽層
160．．．底面導線
170．．．電性連接元件

Claims (4)

  1. 一種全罩式屏蔽至接地銲球之晶片封裝構造，包含：一基板，係具有一上表面、一下表面與複數個側邊，該基板之該下表面係設有複數個接球墊與一銲罩層，該些接球墊係包含至少一接地墊；至少一晶片，係設置於該基板上且電性連接至該基板；一封膠體，係形成於該基板之該上表面，以包覆該晶片；複數個銲球，係接合至該基板之該些接球墊，該些銲球係包含至少一位於該接地墊之接地銲球；一電磁干擾屏蔽層，係包覆該封膠體之一頂面與四周側面，更延伸至該基板之該些側邊；以及一底面導線，係形成於該銲罩層上，該底面導線係由該基板鄰近該接地墊之其中一側邊連接該電磁干擾屏蔽層至該接地銲球，以提供電磁干擾屏蔽；其中，該電磁干擾屏蔽層係為表面塗佈之導電漆層，該底面導線係為以印刷或塗畫方式形成之非基板線路，並且該底面導線之一端係局部覆蓋該接地墊，以供該接地銲球之接合，以確保該基板不具有延伸至該些側邊之接地線路。
  2. 根據申請專利範圍第1項之全罩式屏蔽至接地銲球之晶片封裝構造，其中該晶片之一主動面係貼附至該基板之該上表面，該基板係更具有一貫穿槽孔， 以顯露該晶片複數個位於該主動面之銲墊。
  3. 根據申請專利範圍第2項之全罩式屏蔽至接地銲球之晶片封裝構造，另包含複數個穿過該貫穿槽孔之電性連接元件，以電性連接該些銲墊至該基板。
  4. 根據申請專利範圍第3項之全罩式屏蔽至接地銲球之晶片封裝構造，其中該些電性連接元件係為打線形成之銲線。
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