TWI452665B - 具防靜電破壞及防電磁波干擾之封裝件及其製法 - Google Patents

具防靜電破壞及防電磁波干擾之封裝件及其製法 Download PDF

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TWI452665B
TWI452665B TW099140955A TW99140955A TWI452665B TW I452665 B TWI452665 B TW I452665B TW 099140955 A TW099140955 A TW 099140955A TW 99140955 A TW99140955 A TW 99140955A TW I452665 B TWI452665 B TW I452665B
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package
electrostatic discharge
substrate
electromagnetic wave
protection pad
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TW201222765A (en
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蔡宗賢
邱志賢
鍾興隆
林建成
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矽品精密工業股份有限公司
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Priority to US12/987,613 priority patent/US9111945B2/en
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Priority to US14/817,624 priority patent/US10062582B2/en

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Description

具防靜電破壞及防電磁波干擾之封裝件及其製法
本發明係有關於一種半導體封裝件及其製法，尤指一種具防靜電破壞及防電磁波干擾之封裝件及其製法。
隨著科技的快速發展，各種新的產品不斷推陳出新，為了滿足消費者方便使用及攜帶容易之需求，現今各式電子產品無不朝向輕、薄、短、小發展；其中，半導體封裝件(Semiconductor Package)係為一種將半導體晶片(chip)電性連接在一係為封裝基板之承載件上，再以係如環氧樹脂之封裝膠體包覆該半導體晶片及承載件，以藉由該封裝膠體保護該半導體晶片及承載件，並避免外界水氣或污染物之侵害，再於該封裝膠體上罩設一係為金屬殼之覆蓋構件；或僅於該半導體晶片及承載件上罩設一係為金屬殼之覆蓋構件，以藉由該覆蓋構件保護該半導體晶片免受外界影響(如靜電放電(ESD)…等)而受損，並藉由該覆蓋構件阻擋內外部之電磁波干擾(Electro-Magnetic Interference,EMI)及電磁相容性(Electro-Magnetic Compatibility,EMC)。
而習知之封裝構件或系統級封裝(System in Package,SiP或System Integrated Package,SIP)之接地系統，係藉由該設於外部之覆蓋構件與其自身之接地結構電性連接，再與系統大地電性連接，藉以防止電磁波之干擾。
第5,166,772號美國專利提出一種具有網狀金屬罩蓋之半導體封裝件。如第1A及1B圖所示，該第5,166,772號美國專利所揭示之半導體封裝件係在基板10上接置一網狀金屬罩蓋(Meshed Metallic Shield)12，將晶片11收納其中，再以封裝膠體13將該網狀金屬罩蓋12及晶片11完全包覆。該半導體封裝件係藉由該網狀金屬罩蓋12之提供，以遮蔽晶片11所產生之電磁波干擾或由外部裝置所產生之電磁波干擾，其中，該網狀金屬罩蓋12係電性連接該基板10之接地線路14。
請參閱第2圖，係為第6,187,613號美國專利所揭示之另一習知半導體封裝件之剖視示意圖。如圖所示，係於基板10上透過凸塊15以覆晶方式接置一晶片11，又於該基板10及晶片11上黏附蓋設一金屬箔16，其中，金屬箔16電性連接至基板10之接地線路上(未圖示)，且於該金屬箔16與基板10之間填充封裝膠體13。該半導體封裝件係藉由該外設於封裝膠體13上的金屬箔16，以遮蔽晶片11所產生之電磁波干擾或由外部裝置所產生之電磁波干擾。
惟，上述之該些封裝件之接地方式，皆係藉由網狀金屬罩蓋或金屬箔電性連接至晶片及主/被動元件之接地線路，當靜電發生並接觸該網狀金屬罩蓋時，則該靜電會沿該接地線路之路徑朝電路板及晶片及主/被動元件傳導，靜電傳導至晶片及主/被動元件時發生靜電釋放，就容易造成晶片及主/被動元件損壞。
再者，該網狀金屬罩蓋或金屬箔連接到系統大地之路徑過長，尤其習知基板/0多於六層線路時，因線路過多致使該接地線路之接地效果降低，使得電荷不易釋放，而更有可能導致該晶片或其它主/被動元件內部損壞。
因此，如何提供一種封裝件，能避免內部之晶片或主/被動元件被靜電破壞，且具有良好的防電磁波干擾之功能，實為一重要課題。
鑑於上述習知技術之種種缺失，本發明揭露一種具防靜電破壞及防電磁波干擾之封裝件，係包括：基板單元，係具有設於該基板單元中之接地結構及輸出/輸入(I/O)結構；至少一半導體元件，係接置於該基板單元表面上並電性連接該接地結構及輸出/輸入結構；封裝膠體，係覆蓋於接置該半導體元件之該基板單元表面及該半導體元件上；以及金屬層，係形成於該封裝膠體外露表面及基板單元之側表面，並與該接地結構電性隔絕。
本發明復提供一種具防靜電破壞及防電磁波干擾之封裝件之製法，係包括：準備一封裝件預製品，係包括：封裝基板，係具有複數基板單元，且各該基板單元具有設於其中之接地結構及輸出/輸入結構；半導體元件，係接置於各該基板單元上並電性連接該接地結構及輸出/輸入結構；封裝膠體，係覆蓋於該接置該半導體元件之封裝基板表面及半導體元件上；沿著各該基板單元邊緣切割該封裝件預製品之封裝膠體及封裝基板以形成複數分離之封裝單元；以及於各該封裝單元之封裝膠體外露表面及基板單元之側表面形成與該接地結構電性隔絕之金屬層。
前述之具防靜電破壞及防電磁波干擾之封裝件之一製法中，該封裝件預製品之製法係包括：提供一封裝基板，係具有複數基板單元，且各該基板單元具有相對之第一表面及第二表面，於該第一表面設有複數第一電性接觸墊及靜電放電防護墊，其中，各該第一電性接觸墊分別電性連接該接地結構及輸出/輸入結構；於各該基板單元之第二表面上接置至少一半導體元件，以電性連接該接地結構及輸出/輸入結構；以及於該封裝基板第二表面及該些半導體元件上覆蓋封裝膠體。
於另一實施態樣中，封裝基板為增層線路，且該封裝件預製品之製法係包括：提供至少一嵌埋於封裝膠體中之半導體元件，該半導體元件具相對之作用面及非作用面，且該半導體元件之作用面外露出該封裝膠體；以及於外露該半導體元件之作用面的封裝膠體表面上形成增層線路，俾使該增層線路作為封裝基板。
依上所述之具防靜電破壞及防電磁波干擾之封裝件及其製法，該基板單元具有相對之第一表面及第二表面，於該第一表面具有複數第一電性接觸墊及靜電放電防護墊，其中，各該第一電性接觸墊分別電性連接該接地結構及輸出/輸入結構；又該半導體元件，係接置於該基板單元之第二表面上，且該封裝膠體係覆蓋於該基板單元之第二表面上。
較佳地，該靜電放電防護墊係於各該基板單元之周圍。於一具體實施例中，該靜電放電防護墊係與該金屬層彼此間隔。
又依上所述之具防靜電破壞及防電磁波干擾之封裝件及其製法，該金屬層電性連接該靜電放電防護墊之另一實施態樣中，各該靜電放電防護墊係由彼此間隔之第一子靜電放電防護墊和第二子靜電放電防護墊所構成，且該第一子靜電放電防護墊係設於該基板單元之第一表面邊緣，並與該基板單元側面齊平。此外，該第一子靜電放電防護墊係與該接地結構電性隔絕。
或者，該至少部份之靜電放電防護墊係設於該第一表面邊緣，並與該基板單元側面齊平以接觸該金屬層。又，設於該第一表面邊緣之靜電放電防護墊可具有缺口，係設於與該基板單元側面齊平的靜電放電防護墊邊緣處。由於設於該第一表面邊緣之靜電放電防護墊與金屬層接觸，則該靜電放電防護墊係與該接地結構電性隔絕。此外，該封裝膠體及基板單元之側表面係為齊平，且復可包括於該基板單元之第一表面上形成連接該金屬層與靜電放電防護墊之導電元件。
如上所述之具防靜電破壞及防電磁波干擾之封裝件及其製法，該基板單元之第二表面復具有複數第二電性接觸墊，且該半導體元件係以打線或覆晶方式電性連接各該第二電性接觸墊。
由上可知，本發明具防靜電破壞及防電磁波干擾之封裝件及其製法，係於各該封裝單元之封裝膠體外露表面及基板單元之側表面形成金屬層，最後，形成連接該金屬層與靜電放電防護墊之的導電元件。俾透過該導電元件接地連通至金屬層以防止電磁波之干擾。具體而言，當封裝件接置於線路基板前，若有靜電發生並接觸到金屬層時，靜電荷不會經由封裝件之接地結構傳導至如晶片之主動或被動元件，使該半導體元件不會受到靜電釋放的影響而得到保護；且當接置於線路基板時，金屬層得藉由導電元件與線路基板之接地系統連接而得提供該半導體元件之電磁波干擾屏障及釋放靜電。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“上”、“一”及“至少一”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
第一實施例
請參閱第3A至3F圖，係為本發明所揭露之一種具防靜電破壞及防電磁波干擾之封裝件之製法。
首先，準備一封裝件預製品，其製法係如第3A至3C圖所示。如第3A及3A’圖所示，提供一封裝基板30，其上劃分有複數縱橫分佈之切割線301以圍設出複數基板單元302，如第3A圖所示；且各該基板單元302具有相對之第一表面302a及第二表面302b及設於該基板單元302中之接地結構及輸出/輸入結構(未圖式)，於該第一表面302a具有複數第一電性接觸墊303及靜電放電防護墊304，其中，第一電性接觸墊303包括接地墊303a及輸出/輸入(I/O)墊303b，各該第一電性接觸墊303分別電性連接該接地結構及輸出/輸入結構，該接地結構及輸出/輸入結構係延伸至該基板單元302之第二表面302b以供電性連接後續接置之半導體元件；又該第二表面302b具有複數第二電性接觸墊305，如第3A’圖所示，且各該第二電性接觸墊305分別電性連接該接地結構及輸出/輸入結構；於此較佳實施例中，該靜電放電防護墊304係於各該基板單元302之周圍，例如靠近基板單元302邊緣之位置或角落，以縮短電性連接路徑，但未延伸至基板單元302邊緣，舉例而言，該靜電放電防護墊304可與基板單元302邊緣相距0.1至1.0mm。此時，該靜電放電防護墊304可為虛墊(Dummy pad)或者與該接地結構電性連接，例如與接地墊303a電性連接，如第3A圖中S所示。
如第3B及3B’圖所示，於各該基板單元302之第二表面302b上接置至少一如晶片之半導體元件31，以電性連接該接地結構及輸出/輸入結構，例如，該半導體元件31以打線方式，如銲線311對應電性連接各該第二電性接觸墊305，如第3B圖所示；或該半導體元件31以覆晶方式，例如藉由銲球312對應電性連接至各該第二電性接觸墊305，如第3B’圖所示。
如第3C圖所示，於該封裝基板30之第二表面302b及該些半導體元件31上覆蓋封裝膠體33，以得到封裝件預製品。
如第3D圖所示，之後，沿著該基板單元302邊緣，即該切割線301切割該封裝件預製品之封裝膠體33及封裝基板30以形成複數分離之封裝單元3，該封裝膠體33及基板單元302之側表面係為齊平。
如第3E及3E’圖所示，於各該封裝單元3之封裝膠體33外露表面及基板單元302之側表面以如濺鍍(sputtering)的方式形成與該接地結構電性隔絕之金屬層34，如銅(Cu)、鎳(Ni)、鐵(Fe)、鋁(Al)、不銹鋼(Sus)等金屬，以藉由該金屬層34提供防電磁波干擾之功能，其中，該靜電放電防護墊304係與該金屬層34彼此間隔，俾使金屬層34與接地結構電性隔絕。從而當封裝件接置於線路基板前，若有靜電發生並接觸到金屬層時，靜電荷不會經由封裝單元3之接地結構傳導至如晶片之主動或被動元件，使該半導體元件不會受到靜電釋放的影響而得到保護。
如第3F圖所示，當封裝單元3要接置於一線路基板36時，可藉由線路基板36上之導電元件35，如銲錫(Solder)，電性連接該金屬層34與靜電放電防護墊304，俾供金屬層34得連接至線路基板36之接地系統，俾使可能發生之靜電荷經由該導電元件35傳導至線路基板36之接地系統，並得以提供該半導體元件之電磁波干擾屏障(EMI Shielding)。
根據前述之製法，本發明復提供一種具防靜電破壞及防電磁波干擾之封裝件，係包括：基板單元302，係具有設於該基板單元302中之接地結構及輸出/輸入結構；至少一半導體元件31，係接置於該基板單元302上並電性連接該接地結構及輸出/輸入結構；封裝膠體33，係覆蓋於該接置該半導體元件31之基板單元302表面及半導體元件31上；以及金屬層34，係形成於該封裝膠體33外露表面及基板單元302之側表面，並與該接地結構電性隔絕。
具體而言，基板單元302係具有相對之第一表面302a及第二表面302b，於該第一表面302a具有複數第一電性接觸墊303及靜電放電防護墊304，其中，第一電性接觸墊303包括接地墊303a及輸出/輸入(I/O)墊303b，各該第一電性接觸墊303分別電性連接該接地結構及輸出/輸入結構；該半導體元件31係接置於該基板單元302之第二表面302b上並電性連接該接地結構及輸出/輸入結構；該封裝膠體33係覆蓋於該基板單元302之第二表面302b及該半導體元件31上。
依上所述，該靜電放電防護墊304係以於各該基板單元302之周圍為佳，例如靠近基板單元302邊緣之位置或角落，並與該金屬層彼此間隔，以縮短電性連接路徑。舉例而言，該靜電放電防護墊304可與基板單元302邊緣相距0.1至1.0mm。該些靜電放電防護墊304之至少一者可為虛墊或者與該基板單元302之接地結構電性連接，例如與接地墊303a電性連接，如第3A圖中S所示。
如上所述之該基板單元302之第二表面302b復具有複數第二電性接觸墊305，該半導體元件31係透過打線方式，如銲線311對應電性連接至各該第二電性接觸墊305，或該半導體元件31以覆晶方式之銲球312對應電性連接至各該第二電性接觸墊305。
第二實施例
當如銲錫之導電元件35無法與如鋁或不銹鋼之金屬層34產生濕潤作用(wetting)時，則如第4A至4C圖所示，係為該靜電放電防護墊304之另一實施態樣；如第4A圖所示，各該靜電放電防護墊304係由彼此間隔之第一子靜電放電防護墊304a和第二子靜電放電防護墊304b所構成，且該第一子靜電放電防護墊304a係設於該第一表面302a邊緣，並與該基板單元302側面齊平。此外，本實施例中，第一子靜電放電防護墊304a和第二子靜電放電防護墊304b彼此相間隔，如第4B圖所示。
如第4B及4C圖所示，在切割該封裝膠體33及封裝基板30及形成金屬層34後，該第一子靜電放電防護墊304a係接觸該金屬層34，此外，該第一子靜電放電防護墊304a係與該接地結構電性隔絕，如第一子靜電放電防護墊304a為虛墊，而該第二子靜電放電防護墊304b除可為虛墊外，亦可選擇與基板單元中之接地結構電性連接。後續封裝單元3要接置於一線路基板36時，藉由導電元件35電性連接第一表面302a之第一子靜電放電防護墊304a和第二子靜電放電防護墊304b上，俾供金屬層34得連接至線路基板36之接地系統，俾使可能發生之靜電荷經由該導電元件35傳導至線路基板36之接地系統，並得以提供該半導體元件之電磁波干擾屏障(EMI Shielding)。
第三實施例
另請參閱第5A及5B圖，係為該靜電放電防護墊304之第二實施例之另一實施態樣。
該至少部份之靜電放電防護墊304係設於該基板單元302第一表面302a邊緣，以於切割步驟之後，令該靜電放電防護墊304與該基板單元302側面齊平以接觸該金屬層34。如第5A圖所例示之形成於第一表面302a邊緣角落之靜電放電防護墊304，在尚未切割該封裝膠體33及封裝基板30時，相鄰基板單元302之靜電放電防護墊304彼此連接。而在形成金屬層34後，該靜電放電防護墊304係接觸該金屬層34。此外，該設於第一表面302a邊緣之靜電放電防護墊304係與該接地結構電性隔絕，例如可為虛墊。
第四實施例
另請參閱第6A及6B圖，係為該靜電放電防護墊304之第三實施例之另一實施態樣。
如第6A圖所例示之形成於第一表面302a邊緣之靜電放電防護墊304，在尚未切割該封裝膠體33及封裝基板30時，相鄰基板單元302之靜電放電防護墊304彼此呈不連續連接。如圖所示，該兩相連接之靜電放電防護墊304具有開口37，係外露出部分第一表面302a。
如第6B圖所示，在切割該封裝膠體33及封裝基板30及形成金屬層34後，設於該第一表面302a邊緣之靜電放電防護墊304具有缺口37’，係設於與該基板單元302側面齊平的靜電放電防護墊304邊緣處。是種在相鄰基板單元302彼此呈不連續連接之靜電放電防護墊304，可避免在施做切割步驟時在基板單元302邊緣產生毛邊(burr)。此外，該設於第一表面302a邊緣之靜電放電防護墊304係與該接地結構電性隔絕，例如可為虛墊。
第五實施例
請參閱第7A至7C圖，係為本發明之具防靜電破壞及防電磁波干擾之封裝件之另一製法。在本實施例中，其製法與第一實施例大致相同，其差異在於該封裝件預製品之製法及封裝基板。
如第7A圖所示，該封裝件預製品之製法係包括；提供至少一嵌埋於封裝膠體33中之半導體元件31，該半導體元件31具相對之作用面31a及非作用面31b，且該半導體元件31之作用面31a外露出該封裝膠體33。具體而言，係可於一表面設有作為封裝膠體33之軟質層的硬質板38上，藉由拾取器(pick-up head)將該半導體元件31黏設於該封裝膠體33上，之後再壓制嵌埋於封裝膠體33中，並令該半導體元件31之作用面31a外露出該封裝膠體33。
如第7B圖所示，於外露該半導體元件31之作用面31a的封裝膠體33表面上形成增層線路30’，俾使該增層線路30’作為封裝基板。具體而言，增層線路30’之製作係可包括於該半導體元件31之作用面31a及封裝膠體33表面上設置介電層306，並利用例如黃光(photo-lithography)製程或雷射製程使該介電層306形成開口以外露出該半導體元件31之電極墊31c，該介電層306係用以供後續之線路層附著其上之種子層(seed layer)。接著，利用重佈線(RDL)技術於該介電層306上形成第一線路層307，並使該部份第一線路層307電性連接至該電極墊31c，部份第一線路層307則可構成與電極墊31c電性隔絕之靜電放電防護墊304，之後，再於該介電層306及第一線路層307上設置第一拒銲層308，並使該第一拒銲層308形成複數開口以外露該第一線路層307之預定部分，各該預定部分即作為前述之第一電性接觸墊303及靜電放電防護墊304。
如第7C圖所示，接著，再如前述製法進行切割步驟以得到複數分離之封裝單元，並於各該封裝單元之封裝膠體33外露表面及基板單元302之側表面形成金屬層34。當然，亦可先移除硬質板38再進行切割步驟及形成金屬層34。
由上述實施例可知，本發明中該封裝基板係為一具有線路之承載板，例如，本實施例中之封裝基板為增層線路(Build-up layer)。當然，封裝基板之實例不限於此，第一實施例中之封裝基板可為印刷電路板或雙順丁烯二酸亞氨(Bismaleimide Triacine,BT)基板。
本發明具防靜電破壞及防電磁波干擾之封裝件及其製法，係於各該封裝單元之封裝膠體外露表面及基板單元之側表面形成金屬層，最後，形成連接該金屬層與靜電放電防護墊之的導電元件。俾透過該導電元件接地連通至金屬層以防止電磁波之干擾。具體而言，當封裝件接置於線路基板前，若有靜電發生並接觸到金屬層時，靜電荷不會經由封裝件之接地結構傳導至如晶片之主動或被動元件，使該半導體元件不會受到靜電釋放的影響而得到保護；且當接置於線路基板時，金屬層得藉由導電元件與線路基板之接地系統連接而得提供該半導體元件之電磁波干擾屏障及釋放靜電。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
10．．．基板
11．．．晶片
12．．．網狀金屬罩蓋
13．．．封裝膠體
14．．．接地線路
15．．．凸塊
16．．．金屬箔
3．．．封裝單元
30．．．封裝基板
30’．．．增層線路
301．．．切割線
302．．．基板單元
302a．．．第一表面
302b．．．第二表面
303．．．第一電性接觸墊
303a．．．接地墊
303b．．．輸出/輸入墊
304．．．靜電放電防護墊
304a．．．第一子靜電放電防護墊
304b．．．第二子靜電放電防護墊
305．．．第二電性接觸墊
31．．．半導體元件
31a．．．作用面
31b．．．非作用面
31c．．．電極墊
311．．．銲線
312．．．銲球
33．．．封裝膠體
34．．．金屬層
35．．．導電元件
36．．．線路基板
37．．．開口
37’．．．缺口
38．．．硬質板
306．．．介電層
307．．．第一線路層
308．．．第一拒銲層
第1A及1B圖係為第5,166,772號美國專利所揭示之半導體封裝件的立體示意圖；
第2圖係為美國專利第6,187,613號所揭露之半導體封裝件之剖視圖；
第3A至3F圖係為本發明之封裝結構及其製法之剖視圖；其中，該第3A圖係為第3A’圖之底視圖；該第3B’圖係為第3B圖之另一實施態樣；該第3E’圖係為第3E圖之底視圖；以及
第4A至4C圖係為本發明中之靜電放電防護墊之第二實施態樣；其中，該第4A圖係封裝基板之底視圖，第4B及4C圖係分別為進行切割步驟後之基板單元剖視圖及以導電元件接置於線路基板之剖視圖；
第5A及5B圖係本發明中之靜電放電防護墊之第三實施態樣，其中，第5A圖係封裝基板之底視圖，第5B圖係基板單元之剖視圖；
第6A及6B圖係本發明中之靜電放電防護墊之第四實施態樣，其中，第6A圖係封裝基板之底視圖，第6B圖係基板單元之底視圖；以及
第7A至7C圖係本發明之封裝結構及其製法之第五實施例之剖視圖。
3．．．封裝單元
302．．．基板單元
302a．．．第一表面
302b．．．第二表面
303．．．第一電性接觸墊
304．．．靜電放電防護墊
305．．．第二電性接觸墊
31．．．半導體元件
311．．．銲線
33．．．封裝膠體
34．．．金屬層
35．．．導電元件
36．．．線路基板

Claims (28)

  1. 一種具防靜電破壞及防電磁波干擾之封裝件，係包括：基板單元，係具有設於該基板單元中之接地結構及輸出/輸入結構；至少一半導體元件，係接置於該基板單元上並電性連接該接地結構及輸出/輸入結構；封裝膠體，係覆蓋於該接置該半導體元件之基板單元表面及半導體元件上；以及金屬層，係形成於該封裝膠體外露表面及基板單元之側表面，並與該接地結構電性隔絕。
  2. 如申請專利範圍第1項所述之具防靜電破壞及防電磁波干擾之封裝件，其中，該基板單元具有相對之第一表面及第二表面，於該第一表面具有複數第一電性接觸墊及靜電放電防護墊，其中，各該第一電性接觸墊分別電性連接該接地結構及輸出/輸入結構；又該半導體元件係接置於該基板單元之第二表面上，且該封裝膠體係覆蓋於該基板單元之第二表面上。
  3. 如申請專利範圍第2項所述之具防靜電破壞及防電磁波干擾之封裝件，其中，該靜電放電防護墊係於各該基板單元之周圍。
  4. 如申請專利範圍第3項所述之具防靜電破壞及防電磁波干擾之封裝件，其中，該靜電放電防護墊係與該接地結構電性連接。
  5. 如申請專利範圍第3項所述之具防靜電破壞及防電磁波干擾之封裝件，其中，該靜電放電防護墊係與該金屬層彼此間隔。
  6. 如申請專利範圍第3項所述之具防靜電破壞及防電磁波干擾之封裝件，其中，各該靜電放電防護墊係由彼此間隔之第一子靜電放電防護墊和第二子靜電放電防護墊所構成，且該第一子靜電放電防護墊係設於該第一表面邊緣，並與該基板單元側面齊平。
  7. 如申請專利範圍第6項所述之具防靜電破壞及防電磁波干擾之封裝件，其中，該第一子靜電放電防護墊係與該接地結構電性隔絕。
  8. 如申請專利範圍第6項所述之具防靜電破壞及防電磁波干擾之封裝件，其中，該第二子靜電放電防護墊係與該接地結構電性連接。
  9. 如申請專利範圍第2項所述之具防靜電破壞及防電磁波干擾之封裝件，其中，該至少部份之靜電放電防護墊係設於該第一表面邊緣，並與該基板單元側面齊平。
  10. 如申請專利範圍第9項所述之具防靜電破壞及防電磁波干擾之封裝件，其中，設於該第一表面邊緣之靜電放電防護墊具有缺口，係設於與該基板單元側面齊平的靜電放電防護墊邊緣處。
  11. 如申請專利範圍第9項所述之具防靜電破壞及防電磁波干擾之封裝件，其中，設於該第一表面邊緣之靜電放電防護墊係與該接地結構電性隔絕。
  12. 如申請專利範圍第1項所述之具防靜電破壞及防電磁波干擾之封裝件，其中，該封裝膠體及基板單元之側表面係為齊平。
  13. 如申請專利範圍第1項所述之具防靜電破壞及防電磁波干擾之封裝件，其中，該金屬層係選自銅、鎳、鐵、鋁或不銹鋼之材質。
  14. 一種具防靜電破壞及防電磁波干擾之封裝件之製法，係包括：準備一封裝件預製品，係包括：封裝基板，係具有複數基板單元，且各該基板單元具有設於其中之接地結構及輸出/輸入結構；半導體元件，係接置於各該基板單元上並電性連接該接地結構及輸出/輸入結構；以及封裝膠體，係覆蓋於該接置該半導體元件之封裝基板表面及半導體元件上；沿著各該基板單元邊緣切割該封裝件預製品之封裝膠體及封裝基板以形成複數分離之封裝單元；以及於各該封裝單元之封裝膠體外露表面及基板單元之側表面形成與該接地結構電性隔絕之金屬層。
  15. 如申請專利範圍第14項所述之具防靜電破壞及防電磁波干擾之封裝件之製法，其中，該封裝件預製品之製法係包括：提供一封裝基板，係具有複數基板單元，且各該基板單元具有相對之第一表面及第二表面，於該第一表面設有複數第一電性接觸墊及靜電放電防護墊，其中，各該第一電性接觸墊分別電性連接該接地結構及輸出/輸入結構；於各該基板單元之第二表面上接置至少一半導體元件，以電性連接該接地結構及輸出/輸入結構；以及於該封裝基板第二表面及該些半導體元件上覆蓋封裝膠體。
  16. 如申請專利範圍第14項所述之具防靜電破壞及防電磁波干擾之封裝件之製法，其中，封裝基板為增層線路，且該封裝件預製品之製法係包括：提供至少一嵌埋於封裝膠體中之半導體元件，該半導體元件具相對之作用面及非作用面，且該半導體元件之作用面外露出該封裝膠體；以及於外露該半導體元件之作用面的封裝膠體表面上形成增層線路，俾使該增層線路作為封裝基板。
  17. 如申請專利範圍第14項所述之具防靜電破壞及防電磁波干擾之封裝件之製法，其中，該基板單元具有相對之第一表面及第二表面，於該第一表面具有複數第一電性接觸墊及靜電放電防護墊，其中，各該第一電性接觸墊分別電性連接該接地結構及輸出/輸入結構；又該半導體元件係接置於該基板單元之第二表面上，且該封裝膠體係覆蓋於該基板單元之第二表面上。
  18. 如申請專利範圍第17項所述之具防靜電破壞及防電磁波干擾之封裝件之製法，其中，該靜電放電防護墊係於各該基板單元之周圍。
  19. 如申請專利範圍第18項所述之具防靜電破壞及防電磁波干擾之封裝件之製法，其中，該靜電放電防護墊係與該金屬層彼此間隔。
  20. 如申請專利範圍第18項所述之具防靜電破壞及防電磁波干擾之封裝件之製法，其中，各該靜電放電防護墊係由彼此間隔之第一子靜電放電防護墊和第二子靜電放電防護墊所構成，且該第一子靜電放電防護墊係設於該基板單元之第一表面邊緣，並與該基板單元側面齊平。
  21. 如申請專利範圍第20項所述之具防靜電破壞及防電磁波干擾之封裝件之製法，其中，該第二子靜電放電防護墊係與該接地結構電性連接。
  22. 如申請專利範圍第20項所述之具防靜電破壞及防電磁波干擾之封裝件之製法，其中，該第一子靜電放電防護墊係與該接地結構電性隔絕。
  23. 如申請專利範圍第17項所述之具防靜電破壞及防電磁波干擾之封裝件之製法，其中，該靜電放電防護墊係與該接地結構電性連接。
  24. 如申請專利範圍第17項所述之具防靜電破壞及防電磁波干擾之封裝件之製法，其中，該至少部份之靜電放電防護墊係設於該第一表面邊緣，並與該基板單元側面齊平。
  25. 如申請專利範圍第24項所述之具防靜電破壞及防電磁波干擾之封裝件之製法，其中，該設於該第一表面邊緣之靜電放電防護墊具有缺口，係設於與該基板單元側面齊平的靜電放電防護墊邊緣處。
  26. 如申請專利範圍第24項所述之具防靜電破壞及防電磁波干擾之封裝件之製法，其中，設於該第一表面邊緣之靜電放電防護墊係與該接地結構電性隔絕。
  27. 如申請專利範圍第14項所述之具防靜電破壞及防電磁波干擾之封裝件之製法，其中，該封裝膠體及基板單元之側表面係為齊平。
  28. 如申請專利範圍第14項所述之具防靜電破壞及防電磁波干擾之封裝件之製法，其中，該金屬層係選自銅、鎳、鐵、鋁或不銹鋼之材質。
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